Hardware implementation of the MultiVic architecture, for deployment on FPGA (Xilinx ZCU102 or VCU128) or Verilator simulation. The architecture is configurable in the number of worker cores and the size of the scratchpad memories.
Examplary hardware architecture, with 4 worker cores and 1 MiB data scratchpads:
Default address ranges for a 2-core configuration:
| Component | Base Address | Size in bytes |
|---|---|---|
| scratchpad management instruction | 0x00000000 | 0x10000 |
| scratchpad management data | 0x00100000 | 0x10000 |
| vicuna 0 instruction | 0x00200000 | 0x4000 |
| vicuna 0 data | 0x00300000 | 0x80000 |
| vicuna 1 instruction | 0x00400000 | 0x4000 |
| vicuna 1 data | 0x00500000 | 0x80000 |
| Component | Base Address | Size |
|---|---|---|
| scratchpad management data | 0x00100000 | 0x10000 |
| uart | 0x80001000 | 0x1000 |
| timer | 0x80002000 | 0x1000 |
| dma register port | 0x90001000 | 0x1000 |
The commands are contained in a justfile. Run just to see a list of options.
The primary commands that you need to know are:
CORE_COUNT=2 just setupThis command sets the project up.
This will:
- Initialize the git submodules.
- Run the preprocessor to generate files like system.sv.
- Generate the xbars.
just buildwill build the project for verilator
just runexecutes the project with verilator. This will pass through parameters, like -t.
To configure the size of the vector registers or the compute units, you can use the provided Makefile.
For example 1024 bit vector registers and 512 bit multiplication unit:
cd submodules/vicuna
make --file config.mk VPROC_CONFIG=legacy VREG_W=2048 VPIPE_W_VMUL=1024Unless otherwise noted, everything in this repository is licensed under the Solderpad Hardware License v2.1, a permissive free software license that is based on the Apache-2.0 license.