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1. Xcelerium-Training Xcelerium-Training Public

   All code, exercises, and tasks from Xcelerium Training 2025 are uploaded here.

   SystemVerilog

2. FPGA-Image-Pipeline-Simulator FPGA-Image-Pipeline-Simulator Public

   Simulation of an FPGA-style image processing pipeline using C++. Models a hardware accelerator workflow for embedded vision systems, inspired by FPGA/SoC design methodologies.

   C++

3. FSM-UART-Serial-Interface FSM-UART-Serial-Interface Public

   A SystemVerilog-based UART (Universal Asynchronous Receiver/Transmitter) module built from scratch using FSM design. Includes baud tick generator, transmitter and receiver FSMs, and simulation test…

   SystemVerilog

4. FSM-XGA-VGA-Controller FSM-XGA-VGA-Controller Public

   🖥️ FSM-based VGA controller in SystemVerilog for XGA (1024×768 @ 60Hz) resolution. Built for DE1-SoC FPGA, with modular HSYNC/VSYNC FSMs and RGB pattern output.

   SystemVerilog