Popular repositories Loading
-
-Image-Edge-Detection-on-FPGA-Sobel-Filter--Verilog
-Image-Edge-Detection-on-FPGA-Sobel-Filter--Verilog PublicThis project implements real-time edge detection on grayscale images using the Sobel filter algorithm, designed in Verilog and simulated in Xilinx Vivado. A sliding 3×3 window is applied to each pi…
Verilog 3
-
Theft-Analysis-Using-AI-and-Computer-Vision
Theft-Analysis-Using-AI-and-Computer-Vision PublicThis project mainly focuses on AI and machine learning using computer vision to analysis different kinds of approach on theft.
Python 1
-
Machine-Learning-Based-Driver-Drowsiness-Detection-System
Machine-Learning-Based-Driver-Drowsiness-Detection-System PublicThis project implements a real-time driver drowsiness detection system using a Raspberry Pi equipped with an OV camera module. The system employs computer vision (OpenCV) and machine learning techn…
Python 1
-
-
High-Speed-Communication-Protocol-in-FPGA-Architecture
High-Speed-Communication-Protocol-in-FPGA-Architecture PublicVHDL
-
Arithmetic-Logic-Unit-ALU-Hardware-Design-on-FPGA
Arithmetic-Logic-Unit-ALU-Hardware-Design-on-FPGA PublicThis project mainly focuses on building an ALU which performs arithmetic and logic functions using verilog and FPGA
Verilog
If the problem persists, check the GitHub status page or contact support.