Here is the basic architecture including instruction memory, register file, ALU, and data memory.
bne: MUX for the PC targetr-type: MUX for result source
Control unit is composed of a main decoder and an ALU decoder.
The truth table of the main decoder is like:
| Instruction | Op | RegWrite | ImmSrc | ALUSrc | MemWrite | ResultSrc | Branch | ALUOp |
|---|---|---|---|---|---|---|---|---|
| lw | 0000011 | 1 | 00 | 1 | 0 | 1 | 0 | 00 |
| sw | 0100011 | 0 | 01 | 1 | # | x | 0 | 00 |
| R-type | 0110011 | 1 | xx | 0 | 0 | 0 | 0 | 10 |
| beq | 1100011 | 0 | 10 | 0 | 0 | x | 1 | 01 |
| addi | 0010011 | 1 | 00 | 1 | 0 | 0 | 0 | 10 |
ALU decoder truth table
| ALUop | funct3 | {op5, funct7_5} | ALUControl | Instruction |
|---|---|---|---|---|
| 00 | x | x | 000(add) | lw, sw |
| 01 | x | x | 001(substract) | beq |
| 10 | 000 | 00, 01, 10 | 000(add) | add |
| 000 | 11 | 001(substract) | sub | |
| 010 | x | 101(set less than) | slt | |
| 110 | x | 011(or) | or | |
| 111 | x | 010(and) | and |
Here is the enhanced data path for jal
ImmSrc including
| ImmSrc | ImmExt | Type | Description |
| 00 | {{20{Instr[31]}}, Instr[31:20]} | I | 12-bit signed immediate |
| 01 | {{20{Instr[31]}}, Instr[31:20]} | S | 12-bit signed immediate |
| 10 | {{20{Instr[31]}}, Instr[31:20]} | B | 13-bit signed immediate |
| 11 | {{20{Instr[31]}}, Instr[31:20]} | J | 21-bit signed immediate |
Here is the abstract view illustrating hazards and solving it with NOPs.
The forwarding also called bypassing.
This unused stage propagating through the pipeline is called a bubble.
stalling a stage is performed by disabling its pipeline register (i.e., the register to the left of a stage) so that the stage’s inputs do not change.
The pipeline register directly after the stalled stage must be cleared (flushed).
Two-way super-scalar processor with data dependencies.
iverilog
The assembly code can be simulated in https://venus.kvakil.me/.
The code is from: S. L. Harris and D. Harris, "Digital Design and RISC-V Computer Architecture Textbook," 2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE), Raleigh, NC, USA, 2021, pp. 1-5, doi: 10.1109/WCAE53984.2021.9707615. This book is highly recommended for beginners in computer architecture. It can be effectively complemented by two authoritative textbooks to enhance your learning experience(Computer Organization and Design THE HARDWARE SOFTWARE INTERFACE, Computer Architecture: A Quantitative Approach). Additionally, you can utilize the provided code to practice debugging a basic CPU, understanding the data flow and hazard handling. For a complete and detailed explanation, readers are encouraged to refer to the original book.