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Dios-001/README.MD

Hi πŸ‘‹, I'm Abhishek Patawari

RTL Design β€’ FPGA β€’ Embedded Systems β€’ Computer Architecture

dios-001


🧠 About Me

  • πŸ”§ Passionate about RTL Design & Digital Systems
  • βš™οΈ Working with Verilog, FPGA (Vivado, Intel Quartus), and Logic Analysis
  • 🧬 Exploring Computer Architecture (OpenRISC, toolchains, embench)
  • πŸ“‘ Building 5G-enabled embedded healthcare systems (Raspberry Pi + sensors)
  • 🐳 Running cross-compilation & hardware workflows inside Docker
  • 🎯 Goal: Become a Chip Design / RTL Engineer

πŸš€ Current Work

  • 🟒 Implementing FSM-based systems (Traffic Controller, Washing Machine) in Verilog
  • 🟒 Ultrasonic Distance Measurement on DE0-Nano + SignalTap Analysis
  • 🟒 OpenRISC toolchain + Embench benchmarking
  • 🟒 Building hardware + software co-design systems

πŸ› οΈ Languages and Tools


πŸ”¬ Areas of Interest

  • 🧩 RTL Design & Verification
  • ⚑ Digital Integrated Circuits
  • 🧠 Computer Architecture
  • πŸ“‘ Embedded & Communication Systems
  • πŸ”— Hardware-Software Co-Design

πŸ“« Contact


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