ChipFlow · robtaylor · Mar 4, 2026 · Mar 4, 2026
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -143,7 +143,7 @@ jobs:
           cargo run --release --features metal --bin jacquard -- sim \
             tests/timing_test/inv_chain_pnr/inv_chain.v \
             tests/timing_test/inv_chain_pnr/inv_chain_stimulus.vcd \
-            tests/timing_test/inv_chain_pnr/loom_timed_output.vcd \
+            tests/timing_test/inv_chain_pnr/jacquard_timed_output.vcd \
             1 \
             --sdf tests/timing_test/inv_chain_pnr/inv_chain_test_ps.sdf \
             --sdf-corner typ \
@@ -158,7 +158,7 @@ jobs:
           path: |
             tests/timing_test/ci_output.vcd
             tests/timing_test/ci_xprop_output.vcd
-            tests/timing_test/inv_chain_pnr/loom_timed_output.vcd
+            tests/timing_test/inv_chain_pnr/jacquard_timed_output.vcd
             metal_timing.txt
             metal_xprop.txt
             metal_timed.txt
@@ -540,7 +540,7 @@ jobs:
             --sdf tests/mcu_soc/data/6_final_stripped.sdf \
             --sdf-corner typ \
             --stimulus-vcd tests/mcu_soc/stimulus.vcd \
-            --timing-vcd tests/mcu_soc/loom_timed_mcu.vcd \
+            --timing-vcd tests/mcu_soc/jacquard_timed_mcu.vcd \
             2>&1 | tee cosim_stimulus.txt
 
       - name: Replay stimulus (non-timed, for CVC comparison)
@@ -550,7 +550,7 @@ jobs:
           cargo run --release --features metal --bin jacquard -- sim \
             tests/mcu_soc/data/6_final.v \
             tests/mcu_soc/stimulus.vcd \
-            tests/mcu_soc/loom_replay_mcu.vcd \
+            tests/mcu_soc/jacquard_replay_mcu.vcd \
             1 \
             --top-module top \
             --max-cycles 10000 \
@@ -589,8 +589,8 @@ jobs:
             metal_mcu_replay.txt
             tests/mcu_soc/sim_config.json
             tests/mcu_soc/stimulus.vcd
-            tests/mcu_soc/loom_replay_mcu.vcd
-            tests/mcu_soc/loom_timed_mcu.vcd
+            tests/mcu_soc/jacquard_replay_mcu.vcd
+            tests/mcu_soc/jacquard_timed_mcu.vcd
 
   # Build documentation (cargo doc + mdbook) and deploy to GitHub Pages
   docs:
@@ -742,9 +742,9 @@ jobs:
             tests/timing_test/inv_chain_pnr/cvc_output.log
             tests/timing_test/inv_chain_pnr/cvc_inv_chain_output.vcd
 
-  # Compare timing results between CVC (event-driven) and Loom (GPU)
+  # Compare timing results between CVC (event-driven) and Jacquard (GPU)
   timing-comparison:
-    name: Timing Comparison (CVC vs Loom)
+    name: Timing Comparison (CVC vs Jacquard)
     runs-on: ubuntu-latest
     needs: [metal, cvc-reference]
     if: always() && needs.metal.result == 'success' && needs.cvc-reference.result == 'success'
@@ -770,7 +770,7 @@ jobs:
           uv run scripts/compare_timing.py \
             --cvc-log cvc-results/tests/timing_test/inv_chain_pnr/cvc_output.log \
             --cvc-vcd cvc-results/tests/timing_test/inv_chain_pnr/cvc_inv_chain_output.vcd \
-            --loom-vcd metal-results/tests/timing_test/inv_chain_pnr/loom_timed_output.vcd \
+            --jacquard-vcd metal-results/tests/timing_test/inv_chain_pnr/jacquard_timed_output.vcd \
             --clock-period-ps 10000 \
             --clock-signal CLK \
             --output-signal Q \
@@ -781,7 +781,7 @@ jobs:
         if: always()
         run: |
           {
-            echo "## Timing Comparison (CVC vs Loom)"
+            echo "## Timing Comparison (CVC vs Jacquard)"
             echo ""
             echo "\`\`\`"
             cat comparison.txt 2>/dev/null || echo "No comparison output"
@@ -894,7 +894,7 @@ jobs:
             tests/mcu_soc/cvc/cvc_sim.log
             tests/mcu_soc/cvc/cvc_output.vcd
 
-  # Compare MCU SoC results between CVC (event-driven) and Loom (GPU)
+  # Compare MCU SoC results between CVC (event-driven) and Jacquard (GPU)
   mcu-soc-comparison:
     name: MCU SoC Functional Comparison
     runs-on: ubuntu-latest
@@ -917,25 +917,25 @@ jobs:
           name: mcu-soc-cvc-results
           path: cvc-results/
 
-      - name: Compare outputs (non-timed Loom vs CVC)
+      - name: Compare outputs (non-timed Jacquard vs CVC)
         run: |
-          LOOM_VCD="metal-results/tests/mcu_soc/loom_replay_mcu.vcd"
+          JACQUARD_VCD="metal-results/tests/mcu_soc/jacquard_replay_mcu.vcd"
           CVC_VCD="cvc-results/cvc_output.vcd"
-          if [ ! -f "$LOOM_VCD" ]; then
-            echo "SKIP: Loom replay VCD not found" | tee mcu_comparison.txt
+          if [ ! -f "$JACQUARD_VCD" ]; then
+            echo "SKIP: Jacquard replay VCD not found" | tee mcu_comparison.txt
             exit 0
           fi
           if [ ! -f "$CVC_VCD" ]; then
             echo "SKIP: CVC output VCD not found (CVC simulation may have failed)" | tee mcu_comparison.txt
             exit 0
           fi
-          LOOM_TIMING_VCD="metal-results/tests/mcu_soc/loom_timed_mcu.vcd"
+          JACQUARD_TIMING_VCD="metal-results/tests/mcu_soc/jacquard_timed_mcu.vcd"
           TIMING_ARGS=""
-          if [ -f "$LOOM_TIMING_VCD" ]; then
-            TIMING_ARGS="--loom-timing-vcd $LOOM_TIMING_VCD"
+          if [ -f "$JACQUARD_TIMING_VCD" ]; then
+            TIMING_ARGS="--jacquard-timing-vcd $JACQUARD_TIMING_VCD"
           fi
           uv run tests/mcu_soc/cvc/compare_simulation.py \
-            "$LOOM_VCD" "$CVC_VCD" \
+            "$JACQUARD_VCD" "$CVC_VCD" \
             --skip-cycles 5 \
             --num-cycles 10000 \
             --skip-bits 0-5 \
@@ -947,7 +947,7 @@ jobs:
         if: always()
         run: |
           {
-            echo "## MCU SoC Simulation Comparison (CVC vs Loom)"
+            echo "## MCU SoC Simulation Comparison (CVC vs Jacquard)"
             echo ""
             echo "\`\`\`"
             cat mcu_comparison.txt 2>/dev/null || echo "No comparison output"

diff --git a/docs/cosim-timing-support.md b/docs/cosim-timing-support.md
@@ -2,17 +2,17 @@
 
 **Status**: Implementation plan for Goal step 8 (final step)
 
-**Objective**: Enable arrival time readback in cosim mode so timing-annotated VCD can be produced without a separate `loom sim` replay. Completes timing validation feature parity with `loom sim`.
+**Objective**: Enable arrival time readback in cosim mode so timing-annotated VCD can be produced without a separate `jacquard sim` replay. Completes timing validation feature parity with `jacquard sim`.
 
 ## Current State
 
-### loom sim ✅ (Complete)
+### jacquard sim ✅ (Complete)
 - Metal: `--timing-vcd` fully functional with arrival time readback
 - CUDA/HIP: In progress (step 7 - kernel FFI bindings)
 - Produces timing-annotated VCD with arrival times for all signals
 - Validated against CVC reference simulator
 
-### loom cosim ❌ (No timing support)
+### jacquard cosim ❌ (No timing support)
 - Supports co-simulation with external testbenches (via Verilog VCD)
 - **Does NOT support** `--timing-vcd` flag currently
 - CPU-GPU synchronized stepping; peripheral models run on CPU
@@ -23,16 +23,16 @@
 **Current workflow** (suboptimal):
 ```bash
 # Step 1: Run cosim to get functional outputs
-loom cosim --input stimulus.vcd --output functional.vcd
+jacquard cosim --input stimulus.vcd --output functional.vcd
 
 # Step 2: Run again with timing to get arrival times (slow!)
-loom sim --input stimulus.vcd --output timed.vcd --sdf design.sdf --timing-vcd
+jacquard sim --input stimulus.vcd --output timed.vcd --sdf design.sdf --timing-vcd
 ```
 
 **Desired workflow** (step 8):
 ```bash
 # Single command produces both functional + timing outputs
-loom cosim --input stimulus.vcd --output timed.vcd \
+jacquard cosim --input stimulus.vcd --output timed.vcd \
     --sdf design.sdf --timing-vcd
 ```
 

diff --git a/docs/simulation-architecture.md b/docs/simulation-architecture.md
@@ -283,15 +283,15 @@ WARN (GATESIM_VCDI_MISSING_PI) Primary input port (HierName(), "reset", None) no
 
 ### 3. No Latch or Asynchronous Sequential Logic Support
 
-**Issue**: Loom only supports edge-triggered D flip-flops (DFFs) as sequential elements. Latch-based designs (SR latches, transparent latches, master-slave latch pairs) and asynchronous sequential logic are not supported.
+**Issue**: Jacquard only supports edge-triggered D flip-flops (DFFs) as sequential elements. Latch-based designs (SR latches, transparent latches, master-slave latch pairs) and asynchronous sequential logic are not supported.
 
 **Impact**: Designs using latches will either:
 - Fail during AIG conversion (unrecognized cell type)
 - Be silently treated as combinational logic (incorrect simulation)
 
 **What this means in practice**:
 - Gate-level netlists must be synthesized to a DFF-only cell library (AIGPDK or SKY130)
-- CVC's built-in test suite (`tests_and_examples/install.test/`) uses NAND-latch flip-flops (e.g., `dfpsetd.v`, `sdfia04.v`) and cannot be used as Loom reference tests
+- CVC's built-in test suite (`tests_and_examples/install.test/`) uses NAND-latch flip-flops (e.g., `dfpsetd.v`, `sdfia04.v`) and cannot be used as Jacquard reference tests
 - Self-timed designs with internal clock generation (e.g., CVC's `das_lfsr` benchmark) are also unsupported
 
 **What would be needed to support latches**:
@@ -304,7 +304,7 @@ WARN (GATESIM_VCDI_MISSING_PI) Primary input port (HierName(), "reset", None) no
 
 **Complexity estimate**: Moderate-to-high. The main challenge is the evaluation model change — DFF-only simulation is a clean "capture at edge" model, while latches require iterative evaluation within clock phases.
 
-**Status**: Not planned. Loom targets synthesis flows that produce DFF-only netlists.
+**Status**: Not planned. Jacquard targets synthesis flows that produce DFF-only netlists.
 
 ### 4. Format String Preservation
 **Issue**: Yosys synthesis may not preserve `gem_format` attributes

diff --git a/docs/timing-simulation.md b/docs/timing-simulation.md
@@ -290,7 +290,7 @@ This is feasible but significantly increases memory pressure and computation.
 
 ## Conservative Timing Model: Sources of Overestimation
 
-Loom's GPU timing is intentionally conservative — it may over-estimate arrival times
+Jacquard's GPU timing is intentionally conservative — it may over-estimate arrival times
 but will never under-estimate them. This is important for setup violation detection:
 false positives are safe, false negatives would miss real bugs.
 
@@ -309,15 +309,15 @@ delay = max(gate_delays[pin].rise_ps, gate_delays[pin].fall_ps)
 
 **Impact**: For the SKY130 inv_chain test (16 inverters), rise delays average ~10ps
 larger than fall delays. In a real inverter chain, transitions alternate (rise→fall→rise),
-so half the cells use the smaller fall delay. Loom uses the larger rise delay for all.
+so half the cells use the smaller fall delay. Jacquard uses the larger rise delay for all.
 
 **Measured**: 80ps overestimate on 1235ps (6.5%) for 16 inverters with ~10ps rise/fall
 asymmetry per cell.
 
 ### Source 2: max wire delay across all input pins
 
 For multi-input cells (AND gates, MUXes), INTERCONNECT delays to different input pins
-may differ significantly. Loom takes the maximum across all input pins:
+may differ significantly. Jacquard takes the maximum across all input pins:
 
 ```rust
 // wire_delays_per_cell: dest_cellid → max(all input wire delays)
@@ -326,7 +326,7 @@ entry.fall_ps = entry.fall_ps.max(ic.delay.fall_ps);
 ```
 
 **Impact**: If an AND gate has input A arriving via a 10ps wire and input B via a
-200ps wire, Loom assigns 200ps to the cell regardless of which input is on the
+200ps wire, Jacquard assigns 200ps to the cell regardless of which input is on the
 critical path. An event-driven simulator would correctly propagate the 10ps arrival
 on input A independently.
 
@@ -336,7 +336,7 @@ delays to multi-input cells.
 
 ### Source 3: max arrival across 32 packed signals per thread
 
-Each thread position holds 32 independent Boolean signals. Loom tracks one arrival
+Each thread position holds 32 independent Boolean signals. Jacquard tracks one arrival
 per thread position (the maximum across all 32 signals):
 
 ```
@@ -373,7 +373,7 @@ The inv_chain design (2 DFFs + 16 SKY130 inverters) was validated against CVC
 
 ```
 CVC:  clk_to_q=350ps  chain=885ps  total=1235ps  (transition-accurate)
-Loom: clk_to_q=350ps  chain=973ps  total=1323ps  (conservative max)
+Jacquard: clk_to_q=350ps  chain=973ps  total=1323ps  (conservative max)
 Difference: 88ps (7.1% overestimate)
 ```
 

diff --git a/docs/timing-validation.md b/docs/timing-validation.md
@@ -24,7 +24,7 @@ GEM's timing simulation (`--timing-vcd` and `--enable-timing` flags) must be val
 ```bash
 # Example: MCU SoC functional comparison
 uv run tests/mcu_soc/cvc/compare_outputs.py \
-    loom_output.vcd cvc_output.vcd \
+    jacquard_output.vcd cvc_output.vcd \
     --skip-cycles 5  # Skip first 5 cycles (reset/initialization)
 ```
 
@@ -75,7 +75,7 @@ cargo run -r --features metal --bin jacquard -- sim \
 ```
 
 **Expected results**:
-- Loom Q arrival ≈ CVC total_delay (within ±5%)
+- Jacquard Q arrival ≈ CVC total_delay (within ±5%)
 - Both simulators show monotonic delay increase with each inverter stage
 
 ### MCU SoC post-layout (Complex Case)
@@ -95,11 +95,11 @@ uv run tests/mcu_soc/cvc/strip_sdf_checks.py \
     tests/mcu_soc/data/6_final.sdf \
     tests/mcu_soc/data/6_final_stripped.sdf
 
-# 2. Generate Loom timing VCD
+# 2. Generate Jacquard timing VCD
 cargo run -r --features metal --bin jacquard -- sim \
     tests/mcu_soc/data/6_final.v \
     tests/mcu_soc/stimulus.vcd \
-    tests/mcu_soc/loom_timed_mcu.vcd 1 \
+    tests/mcu_soc/jacquard_timed_mcu.vcd 1 \
     --sdf tests/mcu_soc/data/6_final_stripped.sdf \
     --sdf-corner typ \
     --timing-vcd \
@@ -114,14 +114,14 @@ cvc64 +typdelays tests/mcu_soc/cvc/tb_cvc.v \
 
 # 4. Compare functional outputs
 uv run tests/mcu_soc/cvc/compare_outputs.py \
-    tests/mcu_soc/loom_timed_mcu.vcd \
+    tests/mcu_soc/jacquard_timed_mcu.vcd \
     tests/mcu_soc/cvc/cvc_output.vcd \
     --skip-cycles 5
 ```
 
 **Expected results**:
 - Functional output: Exact match (or documented difference with explanation)
-- Arrival times: Loom values ≥ CVC due to conservative path accumulation
+- Arrival times: Jacquard values ≥ CVC due to conservative path accumulation
 - CI: Comparison completes without errors
 
 ### Pre-layout Library Timing
@@ -151,19 +151,19 @@ python3 gen_liberty_sdf.py logic_cone.v
 cvc64 +typdelays tb_inv_chain.v inv_chain.v 2>&1 | tee cvc.log
 ./cvcsim
 
-# Run Loom GPU simulation
+# Run Jacquard GPU simulation
 cargo run -r --features metal --bin jacquard -- sim \
-    inv_chain.v stimulus.vcd loom_output.vcd 1 \
+    inv_chain.v stimulus.vcd jacquard_output.vcd 1 \
     --sdf inv_chain.sdf \
     --timing-vcd
 
 # Compare outputs
-uv run ../../mcu_soc/cvc/compare_outputs.py loom_output.vcd cvc_output.vcd
+uv run ../../mcu_soc/cvc/compare_outputs.py jacquard_output.vcd cvc_output.vcd
 ```
 
 **Expected results**:
 - Functional output: Exact match (logic correctness)
-- Arrival times: Loom ≥ CVC (conservative accumulation expected)
+- Arrival times: Jacquard ≥ CVC (conservative accumulation expected)
 - No SDF parsing errors or malformed delays
 
 **Purpose**: Pre-layout tests catch timing issues early without P&R turnaround (30+ min). Library-only delays provide floor (lower bound); post-layout adds routing parasitics for final validation.
@@ -174,9 +174,9 @@ uv run ../../mcu_soc/cvc/compare_outputs.py loom_output.vcd cvc_output.vcd
 
 The main CI pipeline (`.github/workflows/ci.yml`) includes:
 
-1. **mcu-soc-metal job**: Generates Loom timing VCD
+1. **mcu-soc-metal job**: Generates Jacquard timing VCD
    - Includes SDF stripping step (strip_sdf_checks.py)
-   - Produces loom_timed_mcu.vcd with arrival time annotations
+   - Produces jacquard_timed_mcu.vcd with arrival time annotations
 
 2. **mcu-soc-cvc job**: Generates CVC reference output
    - Uses stripped SDF (6_final_nocheck.sdf)
@@ -237,7 +237,7 @@ Post-layout designs include routing delays and P&R context:
 
 **Why**: Boomerang architecture evaluates in hierarchical stages. To know Q arrival, you sum delays from all stages.
 
-**Mitigation**: Compare Loom Q arrival against CVC RESULT: total_delay (if available), or accept that arrival times differ but functional output matches.
+**Mitigation**: Compare Jacquard Q arrival against CVC RESULT: total_delay (if available), or accept that arrival times differ but functional output matches.
 
 ### 2. SDF Parser Robustness
 
@@ -274,7 +274,7 @@ Post-layout designs include routing delays and P&R context:
    - Compare first 5-10 cycles after reset
    - Verify reset logic is synchronized
 
-4. **Compare against Loom non-timed version**:
+4. **Compare against Jacquard non-timed version**:
    ```bash
    # Run without timing VCD
    cargo run -r --features metal --bin jacquard -- sim \

diff --git a/scripts/chipflow_harness/README.md b/scripts/chipflow_harness/README.md
@@ -5,7 +5,7 @@ VCD stimulus generator for ChipFlow post-synthesis simulation using GEM.
 ## Overview
 
 This tool converts ChipFlow's `input.json` test format into VCD waveforms suitable
-for gate-level simulation with Loom.
+for gate-level simulation with Jacquard.
 
 ## Installation
 
@@ -122,7 +122,7 @@ uv run --extra dev pytest tests/ -v
                                              │
                                              ▼
 ┌─────────────┐    ┌─────────────┐    ┌─────────────┐
-│ netlist.v   │───►│  loom sim   │───►│ events.json │
+│ netlist.v   │───►│ jacquard sim│───►│ events.json │
 │             │    │  / cosim    │    │             │
 └─────────────┘    └─────────────┘    └─────────────┘
 ```