Remove unary operators from wrapper for parser compat#47
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The structural Verilog parser (sverilogparse) doesn't support unary operators (~, !) in assign statements. The OEB inversion in the openframe_project_wrapper wrapper caused parse failures when loom tried to map the rebuilt netlist. Since the wrapper is not simulated (sim uses --top-module top), we pass through the $oe signal directly without inversion. Co-developed-by: Claude Code v2.1.44 (claude-opus-4-6)
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Summary
~(bitwise NOT) operators fromwrap_openframe.py's OEB assign statementssverilogparse) doesn't support unary operators in assigns--top-module top), so the polarity change doesn't affect simulationContext
PR #44 (auto-rebuild of MCU SoC test data) failed the
mcu-soc-metalCI job because the parser couldn't handleassign gpio_oeb[0] = ~\io$soc_flash_clk$oe ;. The existing netlist on main has a minimal wrapper without GPIO mapping logic, so this was never an issue before.Test plan
mcu-soc-metalCI passes with the new netlist