Update MCU SoC post-P&R test data#44

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Commits on Feb 27, 2026

Add GPU arrival time readback for timing-aware VCD output
robtaylor
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Document latch-based design limitation and support requirements
robtaylor
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Fix timing arrival unit tests and make write_output_vcd_timed generic
robtaylor
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Fix Metal kernel double-buffer bug reading gate_delay from wrong stage
robtaylor
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Fix compiler warnings in gem lib (unused variables, dead assignments)
robtaylor
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Add CVC reference testbench and timing VCD comparison tools
robtaylor
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Add Docker-based CVC reference simulation for local timing validation
robtaylor
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Document conservative timing model and CVC validation results
robtaylor
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Add multi-depth synthetic test for timing-aware bit packing
robtaylor
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Fix SDF extraction to prefer post-PnR over pre-PnR timing
robtaylor
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Update MCU SoC test data from librelane rebuild

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