Micore
A MIPS pipelined processor designed using Chisel.

To perform ChiselTest, use the command sbt "testOnly PipelineTest" (note: uncomment the Debug section in Core.scala).

For simulation in Vivado, import the following five source files: Core.sv, Display.sv, Memory.sv, Regfile.sv, and Top.sv, along with the constraint file micore.xdc. A simulation test file testbench.sv is also provided.

The display module and constraint file is based on the Xilinx Basys3 development board.