UC Davis Senior Design Project. Configurable TPU for matrix multiplication. Uses DE1-SoC, Intel Quartus project.
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Brmanzo/FPGA-Based-TPU
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TPU designed on DE1-SoC FPGA for 4096x4096 sparse MM and convolution for UC Davis Senior Design 2023 with Austin York, Gurkirat Dhillon, and Kent Cassidy.
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