UART Safety Controller ASIC — Synthesis, STA & CDC/RDC Signoff

Phase 2 implementation repository for the UART Safety Controller ASIC. This repo takes the functionally verified RTL into SKY130 HD synthesis, OpenSTA timing analysis, multi-corner closure, reset/CDC/RDC review, and implementation-readiness reporting.

Executive Summary

This repository documents the synthesis, static timing analysis, timing-closure, and CDC/RDC review phase for the UART Safety Controller ASIC. The design is a safety-aware UART communication controller with SPI-configurable registers, watchdog supervision, CRC-8 tracking, sticky fault capture, safe-state control, interrupt generation, and reset synchronization.

The Phase 2 objective is implementation readiness before physical design: prove that the RTL synthesizes cleanly into SKY130 HD standard cells, is constrained with meaningful SDC, closes pre-layout timing at 100 MHz across TT/SS/FF corners, and has reviewed clock/reset-domain behavior.

Scope	Status
RTL regression	PASS
SKY130 synthesis	PASS
OpenSTA single-corner timing	PASS
OpenSTA multi-corner timing	PASS
CDC/RDC review	Complete
100 MHz pre-layout timing	Closed

Project Highlights

• 843 SKY130 standard cells
• 10,242.3232 µm² total cell area
• 100 MHz target achieved
• Multi-corner STA closed (TT/SS/FF)
• Worst SS setup slack +0.9095 ns
• Worst FF hold slack +0.1227 ns
• CDC/RDC review completed
• Physical-design ready handoff

Design Specifications

Item	Specification
Project	UART Safety Controller ASIC
Top module	uart_safety_controller_top
RTL language	Verilog
Target PDK/library	SKY130 HD standard-cell Liberty
Synthesis tool	Yosys 0.52
STA tool	OpenSTA 2.0.17
Clock target	100 MHz
Clock period	10.00 ns
Register access	SPI-configurable register bank
UART datapath	UART TX/RX
Data width	8-bit
Parity support	No parity, even parity, odd parity through parity_mode[1:0]
Safety features	Watchdog timeout, sticky fault latch, safe-state control, interrupt generation
Data protection	CRC-8 update path for received UART data
CDC/RDC features	UART RX synchronizer, SPI SCLK/CSn synchronization, reset synchronizer
Final Phase 2 status	RTL regression clean, synthesis clean, TT/SS/FF timing closed

Key Results

The final reports show a closed pre-layout ASIC implementation point for the current RTL and constraints.

Metric	Result
Technology	SKY130 HD standard-cell library
Top module	uart_safety_controller_top
Clock target	100 MHz
Clock period	10.00 ns
Standard Cells	843 cells
Cell Area	10242.323200 µm²
Corners analyzed	TT, SS, FF
TT WNS/TNS	0.00 / 0.00 ns
SS WNS/TNS	0.00 / 0.00 ns
FF WNS/TNS	0.00 / 0.00 ns
Worst SS setup slack	+0.9095 ns
Worst FF hold slack	+0.1227 ns

Proof artifacts:

Result	Report file
Final synthesis cells and area	reports/synthesis/yosys_sky130_synth.log
Corner summary	reports/timing/multi_corner_summary.md
SS setup path	reports/timing/ss/setup_timing.rpt
FF hold path	reports/timing/ff/hold_timing.rpt
WNS/TNS by corner	reports/timing/*/wns.rpt, reports/timing/*/tns.rpt
CDC/RDC review	reports/cdc_rdc_summary.md

These are pre-layout timing results. Placement, routing, extracted parasitics, clock-tree synthesis, and post-route timing closure remain physical-design tasks.

Relationship to RTL Repository

The previous repository, uart-safety-controller-asic, contains the RTL design and functional verification work. This repository, uart-safety-controller-synthesis-sta, focuses on the implementation phase: synthesis, mapped netlists, SDC constraints, OpenSTA reports, timing closure, and CDC/RDC review.

ASIC Implementation Flow

Verified RTL
  -> RTL regression
  -> Yosys synthesis
  -> SKY130 mapping
  -> Gate-level netlist
  -> OpenSTA-compatible netlist
  -> SDC constraints
  -> OpenSTA
  -> Multi-corner STA
  -> Timing closure
  -> CDC/RDC review
  -> Final Phase 2 signoff

Repository Structure

.
|-- config/                 Project configuration
|-- constraints/            SDC timing constraints
|-- docs/                   Supporting documentation
|-- gls/                    Gate-level simulation workspace
|-- images/                 README diagrams and report screenshots
|-- openlane/               OpenLane configuration for physical-design handoff
|-- python/                 Flow automation and multi-corner STA scripts
|-- reports/
|   |-- cdc_rdc_summary.md  CDC/RDC review summary
|   |-- lint/               RTL quality reports
|   |-- synthesis/          Yosys logs and generated mapped netlists
|   `-- timing/             OpenSTA setup, hold, WNS, TNS and corner reports
|-- rtl/                    Synthesizable Verilog RTL
|-- scripts/                Regression and helper scripts
|-- sim/                    Simulation output products
|-- sta/                    STA workspace
|-- tb/                     RTL testbenches
|-- tcl/                    OpenSTA Tcl scripts
`-- yosys/                  Yosys synthesis, lint and check scripts

Functional Regression

The integrated RTL regression is run before synthesis and timing analysis:

./scripts/run_rtl_sim.sh

The system test covers reset behavior, SPI CTRL writes, baud-divider configuration, UART TX activity, watchdog timeout generation, sticky fault behavior, IRQ assertion, and safe-state response.

Expected terminal result:

ALL UART Safety Controller SYSTEM TESTS PASSED

Synthesis

Synthesis is performed with Yosys 0.52 using the SKY130 HD Liberty file. The flow reads the RTL modules, checks uart_safety_controller_top, lowers behavioral RTL, maps sequential cells with dfflibmap, optimizes combinational logic with ABC, and emits SKY130 technology-mapped Verilog.

Primary synthesis stages:

Stage	Purpose
RTL read-in	Load synthesizable Verilog modules
Hierarchy check	Verify top-level module and module connectivity
Generic synthesis	Convert behavioral RTL into generic logic
DFF mapping	Map inferred sequential elements into SKY130-supported flops
ABC mapping	Optimize and map combinational logic into SKY130 cells
Mapped netlist	Produce SKY130 technology-mapped gate-level netlist
STA netlist	Produce split-net OpenSTA-compatible Verilog

Generated netlists:

File	Description
reports/synthesis/uart_safety_controller_sky130.v	SKY130 technology-mapped gate-level netlist
reports/synthesis/uart_safety_controller_sky130_sta.v	OpenSTA-compatible netlist generated with split nets/ports

An OpenSTA-compatible split-net netlist is generated for timing analysis to avoid parser limitations in older OpenSTA builds. This is a tool-compatibility artifact; the RTL source remains the golden design input.

Final mapped synthesis metrics from reports/synthesis/yosys_sky130_synth.log:

Metric	Result
Top-level mapped cells	843
Top-level mapped area	10242.323200 µm²
Watchdog mapped cells	95
Watchdog mapped area	877.091200 µm²

Representative mapped SKY130 cells:

Cell	Count
sky130_fd_sc_hd__dfrtp_1	191
sky130_fd_sc_hd__mux2_1	79
sky130_fd_sc_hd__o21ai_0	60
sky130_fd_sc_hd__nor2_1	59
sky130_fd_sc_hd__nand2_1	58
sky130_fd_sc_hd__a21oi_1	45
sky130_fd_sc_hd__edfxtp_1	32
sky130_fd_sc_hd__nand3_1	26
sky130_fd_sc_hd__a31oi_1	23
sky130_fd_sc_hd__clkinv_1	20

Static Timing Analysis

STA is performed with OpenSTA 2.0.17. The timing script is implemented in Tcl and driven across process corners by Python:

tcl/sta_corner.tcl
python/run_multi_corner_sta.py

The STA flow reads the SKY130 Liberty file for each corner, loads reports/synthesis/uart_safety_controller_sky130_sta.v, links uart_safety_controller_top, reads constraints/uart_safety_controller.sdc, and emits setup, hold, WNS, TNS and clock reports.

SDC Overview

Constraint	Value / Purpose
Primary clock	clk, 10.000 ns period
Target frequency	100 MHz
Setup uncertainty	0.20 ns
Hold uncertainty	0.10 ns
Clock transition	0.05 ns
Input delay	2.0 ns on external input ports
Output delay	2.0 ns on output ports
Reset exceptions	External reset, reset synchronizer release, async reset/set pins

Reset-related exceptions prevent reset distribution and reset release infrastructure from being analyzed as ordinary single-cycle functional data timing. The reset network remains structurally present in the netlist; it is constrained according to intent.

Multi-Corner Timing Results

Corner	PVT	WNS	TNS	Critical Path	Slack	Status
TT	Typical, 25°C, 1.80 V	0.00 ns	0.00 ns	No violations	N/A	PASS
SS	Slow, 100°C, 1.40 V	0.00 ns	0.00 ns	u_watchdog/_157_ -> u_watchdog/_164_	+0.9095 ns setup	PASS
FF	Fast, −40°C, 1.95 V	0.00 ns	0.00 ns	u_reset_sync/_0_ -> u_reset_sync/_1_	+0.1227 ns hold	PASS

Terminal-style summary:

Representative SS setup report excerpt:

Startpoint: u_watchdog/_157_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: u_watchdog/_164_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

data arrival time                                    8.2818
data required time                                   9.1913
slack (MET)                                          0.9095

Representative FF hold report excerpt:

Startpoint: u_reset_sync/_0_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: u_reset_sync/_1_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

data arrival time                                    0.2032
data required time                                   0.0805
slack (MET)                                          0.1227

Timing Closure

1. Initial SS Setup Failure

After reset synchronization and reset-path constraints were corrected, the slow-slow corner exposed a real functional setup violation in the watchdog counter logic. The failing path was inside the watchdog block and was not a reset-distribution artifact. The path involved a wide counter decision cone feeding another watchdog register, with SS delay too large for the 10.00 ns clock after setup uncertainty.

2. Baud Generator RTL Optimization

The baud generator was reviewed for avoidable wide comparison logic. The implementation was simplified so the synthesis tool had a cleaner counter/tick structure to map into SKY130 cells. This reduced unnecessary timing pressure and kept the baud path from becoming the dominant timing limiter.

3. Reset Synchronizer and Constraint Debug

Reset release was originally visible in setup reports because the synchronized reset net was being timed like ordinary data. OpenSTA object-name matching was debugged at the mapped-netlist level, and the constraints were updated to target the actual reset synchronizer objects and asynchronous reset/set pins reported by OpenSTA. This is a proper STA constraint for reset intent, not a workaround for functional data timing.

4. Watchdog Timing Closure

The remaining SS setup issue was closed by optimizing the watchdog counter structure. The final mapped watchdog uses 95 cells and reports a clean worst SS setup path:

u_watchdog/_157_ -> u_watchdog/_164_
slack (MET) 0.9095 ns

The area overhead required to close timing was modest.

Implementation point	Cells	Area
Baseline after reset constraints	828	10162.2464 µm²
Final watchdog-optimized design	843	10242.3232 µm²
Increase	+15	+80.0768 µm²

5. Final Timing Closure Result

The design has successfully completed RTL implementation and pre-layout timing signoff. The synthesized SKY130 netlist closes timing across TT, SS, and FF operating corners and is ready to enter physical design, including floorplanning, placement, clock-tree synthesis, routing, parasitic extraction, and post-route timing analysis.

CDC/RDC Review

The design has one primary internal clock, clk, constrained at 100 MHz. External asynchronous inputs are synchronized before use where required.

Signal	Source	Handling	Status
ui_in[0]	UART RX input	2-flop synchronizer in rx_synchronizer	Reviewed
ui_in[1]	SPI SCLK	3-stage synchronizer in spi_reg_if	Reviewed
ui_in[3]	SPI CSn	3-stage synchronizer in spi_reg_if	Reviewed
ui_in[2]	SPI MOSI	Sampled relative to synchronized SPI SCLK edge	Reviewed
rst_n	External reset	reset_sync for synchronized release	Reviewed

The CDC/RDC review is summarized in reports/cdc_rdc_summary.md. The review confirms that the UART RX input, SPI control inputs, and reset release behavior are explicitly handled before timing signoff.

Lessons Learned

This phase showed why timing closure has to separate real functional failures from constraint noise. Reset-release paths initially dominated STA, but those paths represented reset distribution intent rather than a functional single-cycle data path. Once constrained correctly, OpenSTA exposed the real SS limiter in the watchdog counter logic.

It also showed the value of small RTL changes guided by reports. The final timing closure did not require a broad rewrite; it required identifying the real critical cone, restructuring the watchdog logic, and accepting a small area increase to gain reliable 100 MHz margin.

Finally, report reproducibility matters. The synthesis log, per-corner STA reports, WNS/TNS files, and CDC/RDC summary make the result reviewable without relying on screenshots alone.

Reproducing The Flow

Run RTL regression:

./scripts/run_rtl_sim.sh

Run synthesis:

yosys -s yosys/synth.ys

Run multi-corner STA:

python3 python/run_multi_corner_sta.py

Review final reports:

cat reports/timing/multi_corner_summary.md
cat reports/timing/ss/setup_timing.rpt
cat reports/timing/ff/hold_timing.rpt
cat reports/cdc_rdc_summary.md

Current Limitations

This repository closes pre-layout timing only. The design still needs physical implementation, post-placement timing, clock-tree synthesis, routing, parasitic extraction, post-route STA, and physical verification before tapeout-level signoff.

Final Phase 2 Signoff

Check	Evidence	Status
RTL regression	scripts/run_rtl_sim.sh, simulation output	PASS
SKY130 synthesis	reports/synthesis/yosys_sky130_synth.log	PASS
Cell count and area captured	843 cells, 10242.323200 µm²	PASS
TT timing	reports/timing/tt/*	PASS
SS setup timing	reports/timing/ss/setup_timing.rpt, +0.9095 ns	PASS
FF hold timing	reports/timing/ff/hold_timing.rpt, +0.1227 ns	PASS
Multi-corner WNS/TNS	TT/SS/FF all 0.00/0.00 ns	PASS
Reset constraint intent	SDC reset exceptions and reset synchronizer reports	PASS
CDC/RDC review	reports/cdc_rdc_summary.md	PASS

The design is ready for the next implementation stage: physical design and post-route timing closure.