Design and Verification of a Parameterized Modular ALU Architecture in Verilog HDL

Abstract

This project presents the design and verification of a scalable Arithmetic Logic Unit (ALU) architecture implemented in Verilog HDL. The ALU is built using modular arithmetic, logic, comparison, and shift units controlled by a decoder-based enable structure.

The design supports signed arithmetic operations, registered outputs, active-low reset, and parameterized datapath widths. Functional verification was performed using a custom Verilog testbench in ModelSim Intel FPGA Edition 2020.1.

1. Introduction

Arithmetic Logic Units are important datapath blocks in digital processors, embedded systems, DSP systems, and hardware accelerators. They perform arithmetic, logical, comparison, and shifting operations required by many digital systems.

This project implements a modular 16-bit ALU in Verilog HDL. The main goal was to practice hierarchical RTL design by separating the ALU into smaller functional units and connecting them through a top-level module.

The design objectives were:

• Build a modular RTL hierarchy.
• Use parameterized datapath widths.
• Support signed arithmetic operations.
• Register outputs using clocked logic.
• Use a decoder to enable one functional unit at a time.
• Verify the design using a Verilog testbench.

2. Project Structure

Scalable-Parameterized-ALU-RTL/
|-- rtl/
|   |-- decoder_unit.v
|   |-- logic_unit.v
|   |-- cmp_unit.v
|   |-- shift_unit.v
|   |-- arith_unit.v
|   `-- ALU_TOP.v
|
|-- tb/
|   `-- ALU_TOP_tb.v
|
|-- images/
|   |-- alu_architecture.svg
|   |-- modelsim_waveform.png
|   `-- modelsim_transcript.png
|
|-- docs/
|   |-- ALU_design.mpf
|   |-- ALU_design.cr.mti
|   `-- alu_testbench_transcript.txt
|
`-- README.md

3. System Architecture

The top-level module is ALU_TOP. It receives two signed 16-bit operands, a 4-bit operation select signal, clock, and reset. The opcode is split into two parts:

• ALU_FUNC[3:2] selects the functional unit.
• ALU_FUNC[1:0] selects the operation inside that unit.

The decoder generates one enable signal at a time:

• ARITH_ENABLE
• LOGIC_ENABLE
• CMP_ENABLE
• SHIFT_ENABLE

4. Opcode Map

ALU_FUNC	Unit	Operation
0000	Arithmetic	Addition: A + B
0001	Arithmetic	Subtraction: A - B
0010	Arithmetic	Multiplication: A * B
0011	Arithmetic	Division: A / B
0100	Logic	AND: A & B
0101	Logic	OR: `A
0110	Logic	NAND: ~(A & B)
0111	Logic	NOR: `~(A
1000	Comparison	NOP / zero result
1001	Comparison	Equal comparison
1010	Comparison	Greater-than comparison
1011	Comparison	Less-than comparison
1100	Shift	Shift A right by 1
1101	Shift	Shift A left by 1
1110	Shift	Shift B right by 1
1111	Shift	Shift B left by 1

5. RTL Design Methodology

Arithmetic Unit

The arith_unit module supports signed addition, subtraction, multiplication, and division. The arithmetic output is 32 bits wide so that multiplication results from 16-bit operands are not immediately truncated. Division-by-zero protection is included by returning zero when B == 0.

Logic Unit

The logic_unit module performs AND, OR, NAND, and NOR operations on operands A and B.

Comparison Unit

The cmp_unit module generates encoded comparison outputs:

Output	Meaning
0	No match or NOP
1	A == B
2	A > B
3	A < B

Shift Unit

The shift_unit module supports single-bit left and right shift operations on both operands.

Registered Outputs

Each functional unit uses positive-edge-triggered sequential logic with an asynchronous active-low reset. When reset is active, the output and flag registers are cleared to zero.

6. Top-Level Interface

Signal	Direction	Width	Description
A	Input	16 signed	Operand A
B	Input	16 signed	Operand B
ALU_FUNC	Input	4	Operation select
CLK	Input	1	Clock
RST_N	Input	1	Active-low reset
ARITH_OUT	Output	32 signed	Arithmetic result
ARITH_FLAG	Output	1	Arithmetic unit flag
LOGIC_OUT	Output	16	Logic result
LOGIC_FLAG	Output	1	Logic unit flag
CMP_OUT	Output	16	Comparison result
CMP_FLAG	Output	1	Comparison unit flag
SHIFT_OUT	Output	16	Shift result
SHIFT_FLAG	Output	1	Shift unit flag

Default parameters:

Parameter	Value	Description
IN_WIDTH	16	Operand width
ARITH_OUT_WIDTH	32	Arithmetic output width
OUT_WIDTH	16	Logic, comparison, and shift output width

7. Verification Methodology

Functional verification was performed using tb/ALU_TOP_tb.v in ModelSim. The testbench includes clock generation, reset sequencing, directed input stimulus, and transcript-based result checking using $display.

The clock period is 10 us, which gives a 100 kHz clock frequency. The high duration is 6 us and the low duration is 4 us.

The testbench covers:

• Reset behavior
• Signed addition
• Signed subtraction
• Signed multiplication
• Signed division
• Logic operations
• Comparison operations
• Shift operations
• Output flag behavior

8. Running the Simulation

From the project root:

vlib work
vlog -work work rtl/decoder_unit.v rtl/arith_unit.v rtl/logic_unit.v rtl/cmp_unit.v rtl/shift_unit.v rtl/ALU_TOP.v tb/ALU_TOP_tb.v
vsim work.ALU_TOP_tb
run -all

Command-line simulation:

vsim -c work.ALU_TOP_tb -do "run -all; quit -f"

9. Results

The design was simulated in ModelSim Intel FPGA Edition 2020.1 using directed test cases from ALU_TOP_tb. The waveform confirms registered output behavior for the arithmetic unit, while the transcript shows the full testbench output for arithmetic, logic, comparison, and shift operations.

Simulation summary:

Errors: 0, Warnings: 0
Top level module: ALU_TOP_tb

The full simulation transcript is available here:

docs/alu_testbench_transcript.txt

10. Future Improvements

Future improvements include:

• Carry, zero, negative, and overflow flags.
• Arithmetic right shift support.
• A single shared output bus.
• Self-checking SystemVerilog testbench.
• FPGA synthesis and timing reports.
• Basic assertion-based verification.

11. Skills and Tools

• Verilog HDL
• Modular RTL design
• Parameterized hardware design
• Testbench development
• ModelSim Intel FPGA Edition 2020.1
• Git and GitHub

12. Conclusion

This project completed the RTL design and simulation of a parameterized modular ALU in Verilog HDL. The ALU was organized into separate functional units, integrated through ALU_TOP, and verified using a directed testbench in ModelSim.