Design and Verification of an 8×16 Register File Using Verilog HDL

Project Overview

This project implements and verifies an 8×16 Register File using Verilog HDL.

The register file supports:

• Write operations
• Read operations
• Asynchronous active-low reset
• Parameterized RTL design
• Functional verification using a Verilog testbench
• Waveform generation using VCD

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Features

• 8 registers
• 16-bit data width
• 3-bit addressing
• Positive edge-triggered operations
• Asynchronous active-low reset
• Parameterized design for scalability
• Waveform generation with register_file.vcd

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Project Structure

Register_File_Design/
├── rtl/
│   └── register_file.v
├── tb/
│   └── register_file_tb.v
├── work/
├── register_file.vcd
├── Register_File.mpf
├── Register_File.cr.mti
├── README.md
└── .gitignore

RTL Design Specifications

Parameter	Value
Register Count	8
Register Width	16 bits
Address Width	3 bits
Clock Edge	Positive edge
Reset Type	Asynchronous active-low

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Supported Operations

Write Operation

Data is written into the selected register when:

• WrEn = 1
• RdEn = 0

Read Operation

Data is read from the selected register when:

• RdEn = 1
• WrEn = 0

Reset Behavior

When reset is asserted:

• RST = 0
• All internal registers are cleared to 0
• RdData is cleared to 0

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Testbench Verification

The testbench verifies:

• Reset functionality
• Write operation
• Read operation
• Multiple register accesses
• Waveform generation

Test Cases

Test Case	Description
Write Test 1	Write data to register 2
Read Test 1	Read data from register 2
Write Test 2	Write data to register 3
Read Test 2	Read data from register 3

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Simulation Tools

Recommended tools:

• Icarus Verilog
• GTKWave
• ModelSim / QuestaSim

Compile and Run with Icarus Verilog

cd "c:\BRA FAMOUS\PROGRAMMING\Verilog\Verilog_codes\Register_File_Design"
iverilog -o register_file_tb rtl/register_file.v tb/register_file_tb.v
vvp register_file_tb

Open Waveform with GTKWave

gtkwave register_file.vcd

Compile and Run with ModelSim / QuestaSim

cd "c:\BRA FAMOUS\PROGRAMMING\Verilog\Verilog_codes\Register_File_Design"
vsim -c -do "vlib work; vlog rtl/register_file.v tb/register_file_tb.v; vsim register_file_tb -do \"run -all; quit\""

If you prefer interactive simulation:

cd "c:\BRA FAMOUS\PROGRAMMING\Verilog\Verilog_codes\Register_File_Design"
vsim -do "vlib work; vlog rtl/register_file.v tb/register_file_tb.v; vsim register_file_tb"
run -all
view wave -position end

Open in Quartus

1. Open Register_File.mpf in Quartus.
2. Add rtl/register_file.v and tb/register_file_tb.v to the project.
3. Launch the simulation toolchain if configured.

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Expected Output

Write Test 1: Address=010, WrData=0000000000000110
Read Test 1: Address=010, RdData=0000000000000110

Write Test 2: Address=011, WrData=0000000001101110
Read Test 2: Address=011, RdData=0000000001101110

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Results

The simulation output and waveform behavior for the register file are shown below.

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Concepts Demonstrated

• Sequential logic design
• Register file architecture
• Verilog RTL coding
• Testbench development
• Functional verification
• Waveform analysis

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Future Improvements

• Add synchronous read option
• Implement dual-port register file
• Add invalid operation detection
• Add SystemVerilog assertions
• Build a UVM-based verification environment