A custom-built 6-bit CPU featuring a 3-bit opcode ISA, XOR & NOT ALU operations, 3-register architecture, 7-word RAM, and support for register, immediate, and branching modes (JLE). Includes full ISA design, ROM module mapping, and Logisim circuit for the CPU implementation.
This repository contains the complete implementation of a custom 6-bit CPU designed using a simplified Instruction Set Architecture (ISA), ROM module, and Logisim-based circuit. The project demonstrates the fundamentals of CPU architecture, control logic, instruction encoding, and memory organization.
🖥 Files Included
• ISA-Design & ROM Module (1703100).pdf — Full ISA specification and ROM table.
• 6 bit CPU-DESIGN.circ — Logisim circuit implementing the CPU.
- Install Logisim Evolution.
- Open the file: 6 bit CPU-DESIGN.circ
- Load the ROM table using the values provided in the PDF.
- Run the CPU step-by-step or continuously to observe execution.
📚 Learning Outcomes This project demonstrates: • CPU datapath design • ALU operation handling • Register transfer logic • Instruction encoding/decoding • ROM-based microprogramming • Conditional branching (JLE)