Skip to content
View Axat-Gadhwal's full-sized avatar
👾
Coding
👾
Coding

Achievements

Achievement: YOLOAchievement: Pull SharkAchievement: Quickdraw

Achievements

Achievement: YOLOAchievement: Pull SharkAchievement: Quickdraw

Block or report Axat-Gadhwal

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Axat-Gadhwal/README.md

Screenshot 2025-04-16 113427

Hi 👋, I'm Axat Gadhwal

A passionate student learning about FPGA, RISC-V and Semiconductor field.

axatgadhwal

axat gadhwal

Blogs posts

Connect with me:

www.vlsisysytemdesign.com axat gadhwal axat gadhwal axat gadhwal quality pixels quality pixels www.vlsisystemdesign.com

Languages and Tools:

android arduino blender c cplusplus css3 git html5 illustrator javascript oracle photoshop python unity unreal

Contributions:

A Big Thanks to all the Contributors for your various contributions..

Support:

axatgadhwal



Pinned Loading

  1. Dcdc-Level3-Axat-Gadhwal Dcdc-Level3-Axat-Gadhwal Public

    This repo is created by Axat Gadhwal of grade 7th of APS Varanasi.

    1

  2. VSD-Squadron-FM-Research-Internship VSD-Squadron-FM-Research-Internship Public

    This repo is created by Axat Gadhwal of grade 7th of APS Varanasi.

    Verilog 1