Clarify error phase plane units#59
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Summary
unit_modetoanalyze_error_phase_planefor normalized full-scale, voltage, and code displaysADC Input Level (FS, 0-1)/Residual (uFS)in the normalized residual phase-plane exampleNotes
unit_mode="auto"keeps the legacy range heuristic, but replaces the misleading "Signal Amplitude" label with ADC input/output level wording.Validation
uv run --with pytest pytest tests/unit/aout/test_analyze_error_phase_plane.py tests/integration/test_user_guide_skill_examples.py -quv run python src/adctoolbox/examples/04_debug_analog/exp_a42_analyze_error_phase_plane.py