I build silicon from RTL to GDSII β specializing in ASIC physical design, FPGA implementation and AI accelerator architecture on open-source EDA flows.
- ASIC Physical Design β Full PnR on SKY130 using OpenLane2 + OpenROAD, DRC/LVS clean
- FPGA Acceleration β Systolic array AI accelerator on ZCU104 Zynq UltraScale+
| Project | Stack | Status |
|---|---|---|
| pe-asic-sky130 | OpenLane2 Β· OpenROAD Β· SKY130 Β· OpenSTA | β GDS + Timing Clean |
| systolic-array-fpga-zcu104 | Vivado Β· Zynq Β· SystemVerilog | β Post-Impl Simulation |
