dev(timer): timer tests cleanup and rework

docs/bsa/arm_bsa_testcase_checklist.md

@@ -630,11 +630,11 @@ The checklist provides information about:
       <td>L1</td>
       <td>B_TIME_02</td>
       <td>B_TIME_02</td>
-      <td>407</td>
-      <td>Check System Counter Frequency</td>
-      <td>Yes</td>
-      <td>Yes</td>
-      <td>No</td>
+      <td>Not Covered</td>
+      <td></td>
+      <td></td>
+      <td></td>
+      <td></td>
       <td></td>
     </tr>
     <tr>

docs/sbsa/arm_sbsa_testcase_checklist.md

@@ -474,11 +474,11 @@ The checklist provides information about:
       <td>L5</td>
       <td>S_L5TI_01</td>
       <td>S_L5TI_01</td>
-      <td>Not Covered</td>
-      <td></td>
-      <td></td>
-      <td></td>
-      <td></td>
+      <td>406</td>
+      <td>Check OS visible counter reports 1GHz</td>
+      <td>Yes</td>
+      <td>Yes</td>
+      <td>No</td>
       <td></td>
     </tr>
     <tr>
@@ -3266,11 +3266,11 @@ The checklist provides information about:
       <td>Version 8.0</td>
       <td>S_L8TI_01</td>
       <td>S_L8TI_01</td>
-      <td>406</td>
-      <td>Check Minimum Counter Frequency 50MHz</td>
-      <td>Yes</td>
-      <td>Yes</td>
-      <td>No</td>
+      <td>Not Covered</td>
+      <td></td>
+      <td></td>
+      <td></td>
+      <td></td>
       <td></td>
     </tr>
     <tr>

docs/vbsa/arm_vbsa_architecture_compliance_test_scenario.md

@@ -176,8 +176,7 @@ Purpose: capture ACS scenario outlines for each VBSA rule. Each section:
 ### V_L1TM_02 — Check Virt and Phy counter min freq
 **Rationale**: Virtual Counter (CNTVCT_EL0) = Physical counter (CNTPCT_EL0) - Virtual offset (CNTVOFF_EL2). As the offset is a constant provided by the hypervisor, the virtual counter advances at the same effective frequency as the physical counter.
 
-**Scenario**: Execute the same test used to validate B_TIME_02, which verifies physical counter runs at atleast 10MHz.
-- see section 2.6 in [BSA ACS Scenario Document](../bsa/arm_bsa_architecture_compliance_test_scenario.pdf#page18&search=B_TIME_02)
+**Rationale for not implementing** - The base frequency should be obtained from the CNTFID registers, which are implemented in Secure space. At present, ACS does not provide a mechanism for accessing Secure registers from Non-secure (NS) space.
 
 ---
 

docs/vbsa/arm_vbsa_testcase_checklist.md

@@ -347,10 +347,10 @@ The checklist provides information about:
       <td>L1</td>
       <td><a href="arm_vbsa_architecture_compliance_test_scenario.md#v_l1tm_02--check-virt-and-phy-counter-min-freq">V_L1TM_02</td>
       <td></td>
-      <td>402</td>
-      <td>Check Virt and Phy counter min freq</td>
-      <td>✅</td>
-      <td>❌</td>
+      <td>Not Covered</td>
+      <td></td>
+      <td></td>
+      <td></td>
       <td>Related rules from other specifications: B_TIME_02 (BSA)</td>
     </tr>
     <tr>

pal/baremetal/target/RDN2/src/pal_sbsa.c

@@ -32,6 +32,19 @@ extern const PLATFORM_OVERRIDE_MEMORY_INFO_TABLE  platform_mem_cfg;
 extern const PCIE_INFO_TABLE                      platform_pcie_cfg;
 extern const WD_INFO_TABLE                        platform_wd_cfg;
 
+/** Timer API **/
+/**
+  @brief  Platform defined method to read time in microseconds from an independent timer source
+
+  @return PAL_STATUS_NOT_IMPLEMENTED - API not implemented, Other values - Success
+**/
+uint64_t
+pal_get_platform_time_us(void)
+{
+  pal_warn_not_implemented(__func__);
+  return PAL_STATUS_NOT_IMPLEMENTED;
+}
+
 /** SMMU API's **/
 /**
   @brief  Platform defined method to check if CATU is behind an ETR device

pal/baremetal/target/RDV3/src/pal_sbsa.c

@@ -32,6 +32,19 @@ extern const PLATFORM_OVERRIDE_MEMORY_INFO_TABLE  platform_mem_cfg;
 extern const PCIE_INFO_TABLE                      platform_pcie_cfg;
 extern const WD_INFO_TABLE                        platform_wd_cfg;
 
+/** Timer API **/
+/**
+  @brief  Platform defined method to read time in microseconds from an independent timer source
+
+  @return PAL_STATUS_NOT_IMPLEMENTED - API not implemented, Other values - Success
+**/
+uint64_t
+pal_get_platform_time_us(void)
+{
+  pal_warn_not_implemented(__func__);
+  return PAL_STATUS_NOT_IMPLEMENTED;
+}
+
 /** SMMU API's **/
 /**
   @brief  Platform defined method to check if CATU is behind an ETR device

pal/baremetal/target/RDV3CFG1/src/pal_sbsa.c

@@ -32,6 +32,19 @@ extern const PLATFORM_OVERRIDE_MEMORY_INFO_TABLE  platform_mem_cfg;
 extern const PCIE_INFO_TABLE                      platform_pcie_cfg;
 extern const WD_INFO_TABLE                        platform_wd_cfg;
 
+/** Timer API **/
+/**
+  @brief  Platform defined method to read time in microseconds from an independent timer source
+
+  @return PAL_STATUS_NOT_IMPLEMENTED - API not implemented, Other values - Success
+**/
+uint64_t
+pal_get_platform_time_us(void)
+{
+  pal_warn_not_implemented(__func__);
+  return PAL_STATUS_NOT_IMPLEMENTED;
+}
+
 /** SMMU API's **/
 /**
   @brief  Platform defined method to check if CATU is behind an ETR device

pal/uefi_acpi/src/pal_timer_wd.c

@@ -17,6 +17,7 @@
 
 #include <Library/UefiLib.h>
 #include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
 #include <Library/BaseLib.h>
 #include <Library/BaseMemoryLib.h>
 
@@ -31,6 +32,27 @@ static EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE *gGtdtHdr;
 UINT64
 pal_get_gtdt_ptr();
 
+UINT64
+pal_get_platform_time_us (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  EFI_TIME Time;
+  UINT64 TimeUs;
+
+  Status = gRT->GetTime(&Time, NULL);
+  if (EFI_ERROR(Status)) {
+    pal_print_msg(ACS_PRINT_WARN, " GetTime failed: %x\n", Status);
+    return ~0ULL;
+  }
+
+  TimeUs = (((UINT64)Time.Hour * 60 + Time.Minute) * 60 + Time.Second) * 1000000ULL;
+  TimeUs += (UINT64)Time.Nanosecond / 1000ULL;
+
+  return TimeUs;
+}
+
 /**
   @brief This API overrides the timer specified by TimerTable
          Note: Information about only one timer can be mentioned as an Override

pal/uefi_dt/src/pal_timer_wd.c

@@ -17,6 +17,7 @@
 
 #include <Library/UefiLib.h>
 #include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
 #include <Library/BaseLib.h>
 #include <Library/BaseMemoryLib.h>
 
@@ -48,6 +49,27 @@ static char wd_dt_arr[][WD_COMPATIBLE_STR_LEN] = {
 UINT64
 pal_get_gtdt_ptr();
 
+UINT64
+pal_get_platform_time_us (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  EFI_TIME Time;
+  UINT64 TimeUs;
+
+  Status = gRT->GetTime(&Time, NULL);
+  if (EFI_ERROR(Status)) {
+    pal_print_msg(ACS_PRINT_WARN, " GetTime failed: %x\n", Status);
+    return ~0ULL;
+  }
+
+  TimeUs = (((UINT64)Time.Hour * 60 + Time.Minute) * 60 + Time.Second) * 1000000ULL;
+  TimeUs += (UINT64)Time.Nanosecond / 1000ULL;
+
+  return TimeUs;
+}
+
 /**
   @brief This API overrides the timer specified by TimerTable
          Note: Information about only one timer can be mentioned as an Override

test_pool/timer/t001.c

@@ -22,10 +22,6 @@
 #define TEST_RULE  "B_TIME_01"
 #define TEST_DESC  "Check for Generic System Counter      "
 
-#define TEST_NUM1   (ACS_TIMER_TEST_NUM_BASE + 7)
-#define TEST_RULE1  "B_TIME_02"
-#define TEST_DESC1  "Check System Counter Frequency        "
-
 /* This test checks for presence of Generic System Counter */
 static
 void
@@ -49,46 +45,6 @@ payload_check_system_counter_presence()
   }
 }
 
-/* This test checks if Generic System Counter frequency is greater than 10Mhz */
-static
-void
-payload_check_system_timer_freq()
-{
-  uint64_t counter_freq, print_freq = 0;
-  uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-  uint32_t print_mhz = 0;
-
-  /* Read CNTFRQ_EL0 register for counter frequency */
-  counter_freq = val_timer_get_info(TIMER_INFO_CNTFREQ, 0);
-
-  /* Convert frequency into MHz or KHz unit */
-  print_freq = counter_freq/1000;
-  if (print_freq > 1000) {
-      print_freq = print_freq/1000;
-      print_mhz = 1;
-  }
-
-  /* Print counter frequency in DEBUG verbosity */
-  if (print_mhz)
-      val_print(DEBUG, "\n       Counter frequency is %ld MHz", print_freq);
-  else
-      val_print(DEBUG, "\n       Counter frequency is %ld KHz", print_freq);
-
-  /* Check if Generic system counter frequency is greater than 10MHz */
-  if (counter_freq > 10*1000*1000) {
-      val_set_status(index, RESULT_PASS);
-      return;
-  }
-
-  /* If 10Mhz check fails, print frequency in ERROR verbosity */
-  if (print_mhz)
-      val_print(ERROR, "\n       Counter frequency is %ld MHz", print_freq);
-  else
-      val_print(ERROR, "\n       Counter frequency is %ld KHz", print_freq);
-
-  val_set_status(index, RESULT_FAIL(1));
-}
-
 uint32_t
 t001_entry(uint32_t num_pe)
 {
@@ -109,24 +65,3 @@ t001_entry(uint32_t num_pe)
 
   return status;
 }
-
-uint32_t
-t007_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This Timer test is run on single processor
-
-  val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__);
-  status = val_initialize_test(TEST_NUM1, TEST_DESC1, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM1, num_pe, payload_check_system_timer_freq, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM1, num_pe, TEST_RULE1);
-
-  val_report_status(0, ACS_END(TEST_NUM1), NULL);
-
-  return status;
-}