From 908acb360abe7e758a7c2ed59f5d7943470cd09c Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Mon, 1 Feb 2021 18:18:45 +0800 Subject: [PATCH 01/27] add serial-boot for vc709 board, add configs for vc709 prototyping. new file: src/main/resources/vc709/uartboot/Makefile new file: src/main/resources/vc709/uartboot/Makefile-back new file: src/main/resources/vc709/uartboot/common.h new file: src/main/resources/vc709/uartboot/crc16.c new file: src/main/resources/vc709/uartboot/crc16.o new file: src/main/resources/vc709/uartboot/gpoi.c new file: src/main/resources/vc709/uartboot/head.S new file: src/main/resources/vc709/uartboot/hello.c new file: src/main/resources/vc709/uartboot/include/bits.h new file: src/main/resources/vc709/uartboot/include/const.h new file: src/main/resources/vc709/uartboot/include/crc16.h new file: src/main/resources/vc709/uartboot/include/devices/clint.h new file: src/main/resources/vc709/uartboot/include/devices/gpio.h new file: src/main/resources/vc709/uartboot/include/devices/plic.h new file: src/main/resources/vc709/uartboot/include/devices/spi.h new file: src/main/resources/vc709/uartboot/include/devices/uart.h new file: src/main/resources/vc709/uartboot/include/kprintf.h new file: src/main/resources/vc709/uartboot/include/platform.h new file: src/main/resources/vc709/uartboot/include/riscv_test_defaults.h new file: src/main/resources/vc709/uartboot/include/sections.h new file: src/main/resources/vc709/uartboot/include/serial.h new file: src/main/resources/vc709/uartboot/include/smp.h new file: src/main/resources/vc709/uartboot/kprintf.c new file: src/main/resources/vc709/uartboot/linker/bootrom.elf.lds new file: src/main/resources/vc709/uartboot/linker/memory.lds new file: src/main/resources/vc709/uartboot/plic.c new file: src/main/resources/vc709/uartboot/sd.c new file: src/main/resources/vc709/uartboot/serial.c new file: src/main/resources/vc709/uartboot/uart.c new file: src/main/resources/vc709/uartsend/Makefile new file: src/main/resources/vc709/uartsend/serial new file: src/main/resources/vc709/uartsend/serial.c new file: src/main/resources/vc709/uartsend/serial.o new file: src/main/scala/vc709/Configs.scala new file: src/main/scala/vc709/CustomOverlays.scala new file: src/main/scala/vc709/TestHarness.scala modified: Makefile --- .../main/resources/vc709/uartboot/Makefile | 42 +++ .../resources/vc709/uartboot/Makefile-back | 72 +++++ .../main/resources/vc709/uartboot/common.h | 9 + .../src/main/resources/vc709/uartboot/crc16.c | 26 ++ .../src/main/resources/vc709/uartboot/crc16.o | Bin 0 -> 1752 bytes fpga/src/main/resources/vc709/uartboot/gpoi.c | 9 + fpga/src/main/resources/vc709/uartboot/head.S | 21 ++ .../src/main/resources/vc709/uartboot/hello.c | 14 + .../resources/vc709/uartboot/include/bits.h | 36 +++ .../resources/vc709/uartboot/include/const.h | 18 ++ .../resources/vc709/uartboot/include/crc16.h | 18 ++ .../vc709/uartboot/include/devices/clint.h | 14 + .../vc709/uartboot/include/devices/gpio.h | 32 ++ .../vc709/uartboot/include/devices/plic.h | 39 +++ .../vc709/uartboot/include/devices/spi.h | 79 +++++ .../vc709/uartboot/include/devices/uart.h | 36 +++ .../vc709/uartboot/include/kprintf.h | 76 +++++ .../vc709/uartboot/include/platform.h | 107 +++++++ .../uartboot/include/riscv_test_defaults.h | 81 +++++ .../vc709/uartboot/include/sections.h | 17 + .../resources/vc709/uartboot/include/serial.h | 32 ++ .../resources/vc709/uartboot/include/smp.h | 142 +++++++++ .../main/resources/vc709/uartboot/kprintf.c | 145 +++++++++ .../vc709/uartboot/linker/bootrom.elf.lds | 79 +++++ .../vc709/uartboot/linker/memory.lds | 14 + fpga/src/main/resources/vc709/uartboot/plic.c | 11 + fpga/src/main/resources/vc709/uartboot/sd.c | 221 +++++++++++++ .../main/resources/vc709/uartboot/serial.c | 73 +++++ fpga/src/main/resources/vc709/uartboot/uart.c | 57 ++++ .../main/resources/vc709/uartsend/Makefile | 9 + fpga/src/main/resources/vc709/uartsend/serial | Bin 0 -> 18344 bytes .../main/resources/vc709/uartsend/serial.c | 294 ++++++++++++++++++ .../main/resources/vc709/uartsend/serial.o | Bin 0 -> 9128 bytes fpga/src/main/scala/vc709/Configs.scala | 74 +++++ .../src/main/scala/vc709/CustomOverlays.scala | 89 ++++++ fpga/src/main/scala/vc709/TestHarness.scala | 134 ++++++++ 36 files changed, 2120 insertions(+) create mode 100644 fpga/src/main/resources/vc709/uartboot/Makefile create mode 100644 fpga/src/main/resources/vc709/uartboot/Makefile-back create mode 100644 fpga/src/main/resources/vc709/uartboot/common.h create mode 100644 fpga/src/main/resources/vc709/uartboot/crc16.c create mode 100644 fpga/src/main/resources/vc709/uartboot/crc16.o create mode 100644 fpga/src/main/resources/vc709/uartboot/gpoi.c create mode 100644 fpga/src/main/resources/vc709/uartboot/head.S create mode 100644 fpga/src/main/resources/vc709/uartboot/hello.c create mode 100644 fpga/src/main/resources/vc709/uartboot/include/bits.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/const.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/crc16.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/devices/clint.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/devices/gpio.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/devices/plic.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/devices/spi.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/devices/uart.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/kprintf.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/platform.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/riscv_test_defaults.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/sections.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/serial.h create mode 100644 fpga/src/main/resources/vc709/uartboot/include/smp.h create mode 100644 fpga/src/main/resources/vc709/uartboot/kprintf.c create mode 100644 fpga/src/main/resources/vc709/uartboot/linker/bootrom.elf.lds create mode 100644 fpga/src/main/resources/vc709/uartboot/linker/memory.lds create mode 100644 fpga/src/main/resources/vc709/uartboot/plic.c create mode 100644 fpga/src/main/resources/vc709/uartboot/sd.c create mode 100644 fpga/src/main/resources/vc709/uartboot/serial.c create mode 100644 fpga/src/main/resources/vc709/uartboot/uart.c create mode 100644 fpga/src/main/resources/vc709/uartsend/Makefile create mode 100644 fpga/src/main/resources/vc709/uartsend/serial create mode 100644 fpga/src/main/resources/vc709/uartsend/serial.c create mode 100644 fpga/src/main/resources/vc709/uartsend/serial.o create mode 100644 fpga/src/main/scala/vc709/Configs.scala create mode 100644 fpga/src/main/scala/vc709/CustomOverlays.scala create mode 100644 fpga/src/main/scala/vc709/TestHarness.scala diff --git a/fpga/src/main/resources/vc709/uartboot/Makefile b/fpga/src/main/resources/vc709/uartboot/Makefile new file mode 100644 index 0000000000..794dac7dd2 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/Makefile @@ -0,0 +1,42 @@ +# RISCV environment variable must be set +ROOT_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) +BUILD_DIR := $(ROOT_DIR)/build + +CC=$(RISCV)/bin/riscv64-unknown-elf-gcc +OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy +OBJDUMP=$(RISCV)/bin/riscv64-unknown-elf-objdump +CFLAGS=-march=rv64ima -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles +CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0 +CFLAGS+= -I $(ROOT_DIR)/include -I. +LFLAGS=-static -nostdlib -L $(ROOT_DIR)/linker -T bootrom.elf.lds + +PBUS_CLK ?= 1000000 # default to 1MHz but really should be overridden + +default: elf bin dump + +elf := $(BUILD_DIR)/bootrom.elf +$(elf): head.S crc16.c kprintf.c serial.c + mkdir -p $(BUILD_DIR) + $(CC) $(CFLAGS) -DTL_CLK="$(PBUS_CLK)UL" $(LFLAGS) -o $@ head.S crc16.c kprintf.c serial.c + +.PHONY: elf +elf: $(elf) + +bin := $(BUILD_DIR)/bootrom.bin +$(bin): $(elf) + mkdir -p $(BUILD_DIR) + $(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@ + +.PHONY: bin +bin: $(bin) + +dump := $(BUILD_DIR)/bootrom.dump +$(dump): $(elf) + $(OBJDUMP) -D -S $< > $@ + +.PHONY: dump +dump: $(dump) + +.PHONY: clean +clean:: + rm -rf $(BUILD_DIR) diff --git a/fpga/src/main/resources/vc709/uartboot/Makefile-back b/fpga/src/main/resources/vc709/uartboot/Makefile-back new file mode 100644 index 0000000000..47694a0ef5 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/Makefile-back @@ -0,0 +1,72 @@ +# RISCV environment variable must be set + +CC=$(RISCV)/bin/riscv64-unknown-elf-gcc +OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy +CFLAGS=-march=rv64imac -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles +CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0 +CFLAGS+= -I $(BOOTROM_DIR)/include -I. +LFLAGS=-static -nostdlib -L $(BOOTROM_DIR)/linker -T bootrom.elf.lds + +dts := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts +dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb +clk := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).tl_clock.h + +## device tree +$(clk): $(dts) + awk '/tlclk {/ && !f{f=1; next}; f && match($$0, /^.*clock-frequency.*<(.*)>.*/, arr) { print "#define TL_CLK " arr[1] "UL"}' $< > $@.tmp + mv $@.tmp $@ + +$(dtb): $(dts) + dtc -I dts -O dtb -o $@ $< + +.PHONY: dtb +dtb: $(dtb) + +## uart_boot +elf := $(BUILD_DIR)/bootrom.elf +$(elf): $(dtb) head.S crc16.c kprintf.c serial.c $(clk) + $(CC) $(CFLAGS) -include $(clk) -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ head.S crc16.c kprintf.c serial.c + +## sd_boot +# elf := $(BUILD_DIR)/bootrom.elf +# $(elf): $(dtb) head.S kprintf.c sd.c $(clk) + # $(CC) $(CFLAGS) -include $(clk) -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ head.S sd.c kprintf.c + +.PHONY: elf +elf: $(elf) + +bin := $(BUILD_DIR)/bootrom.bin +$(bin): $(elf) + $(OBJCOPY) -O binary $< $@ + +.PHONY: bin +bin: $(bin) + +hex := $(BUILD_DIR)/bootrom.hex +$(hex): $(bin) + od -t x4 -An -w4 -v $< > $@ + +.PHONY: hex +hex: $(hex) + +# # Berkeley Boot Loader (BBL) +# elf := $(RISCV)/riscv64-unknown-elf/bin/bbl +# bin := $(BUILD_DIR)/bootrom.bin +# $(bin): $(elf) +# $(OBJCOPY) -O binary $< $@ + +# hex := $(BUILD_DIR)/bootrom.hex +# $(hex): $(bin) +# od -t x4 -An -w4 -v $< > $@ + +# Finally +romgen := $(BUILD_DIR)/rom.v +$(romgen): $(hex) + $(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@ + +.PHONY: romgen +romgen: $(romgen) + +.PHONY: clean +clean:: + rm -rf $(hex) $(elf) diff --git a/fpga/src/main/resources/vc709/uartboot/common.h b/fpga/src/main/resources/vc709/uartboot/common.h new file mode 100644 index 0000000000..4f71e103a8 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/common.h @@ -0,0 +1,9 @@ +#ifndef _SDBOOT_COMMON_H +#define _SDBOOT_COMMON_H + +#ifndef PAYLOAD_DEST + #define PAYLOAD_DEST MEMORY_MEM_ADDR +#endif + + +#endif diff --git a/fpga/src/main/resources/vc709/uartboot/crc16.c b/fpga/src/main/resources/vc709/uartboot/crc16.c new file mode 100644 index 0000000000..7534375e24 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/crc16.c @@ -0,0 +1,26 @@ +/* + * @,@Author: ,: your name + * @,@Date: ,: 1970-01-01 08:00:00 + * @,@LastEditTime: ,: 2021-01-30 11:48:26 + * @,@LastEditors: ,: Please set LastEditors + * @,@Description: ,: In User Settings Edit + * @,@FilePath: ,: /freedom/bootrom/sdboot/crc16.h + */ +#include "include/crc16.h" + +inline uint16_t crc16_round(uint16_t crc, uint8_t data) { + crc = (uint8_t)(crc >> 8) | (crc << 8); + crc ^= data; + crc ^= (uint8_t)(crc >> 4) & 0xf; + crc ^= crc << 12; + crc ^= (crc & 0xff) << 5; + return crc; +} + +uint16_t crc16(uint8_t *q) { + uint16_t crc = 0; + for (int i = 0; i < CRC16_LEN; i++) { + crc = crc16_round(crc, *q++); + } + return crc; +} \ No newline at end of file diff --git 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a/fpga/src/main/resources/vc709/uartboot/gpoi.c b/fpga/src/main/resources/vc709/uartboot/gpoi.c new file mode 100644 index 0000000000..14783690f7 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/gpoi.c @@ -0,0 +1,9 @@ +/* + * @,@Author: ,: your name + * @,@Date: ,: 1970-01-01 08:00:00 + * @,@LastEditTime: ,: 2021-01-15 19:06:26 + * @,@LastEditors: ,: Please set LastEditors + * @,@Description: ,: In User Settings Edit + * @,@FilePath: ,: /freedom/bootrom/sdboot/gpoi.c + */ +#include "gpio.h" \ No newline at end of file diff --git a/fpga/src/main/resources/vc709/uartboot/head.S b/fpga/src/main/resources/vc709/uartboot/head.S new file mode 100644 index 0000000000..14fa740476 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/head.S @@ -0,0 +1,21 @@ +// See LICENSE for license details. +#include +#include +#include "common.h" + + .section .text.init + .option norvc + .globl _prog_start +_prog_start: + smp_pause(s1, s2) + li sp, (PAYLOAD_DEST + 0x7fff000) + call main + smp_resume(s1, s2) + csrr a0, mhartid + la a1, dtb + li s1, PAYLOAD_DEST + jr s1 + + .section .rodata +dtb: + .incbin DEVICE_TREE diff --git a/fpga/src/main/resources/vc709/uartboot/hello.c b/fpga/src/main/resources/vc709/uartboot/hello.c new file mode 100644 index 0000000000..7e718ea256 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/hello.c @@ -0,0 +1,14 @@ +#include +#include "./include/platform.h" +#include "./include/common.h" + +#define DEBUG +#include "kprintf.h" + +#define MAX_CORES 8 + +int main(void) +{ + kputs("this is hello\n"); + return 0; +} diff --git a/fpga/src/main/resources/vc709/uartboot/include/bits.h b/fpga/src/main/resources/vc709/uartboot/include/bits.h new file mode 100644 index 0000000000..bfe656feb0 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/bits.h @@ -0,0 +1,36 @@ +// See LICENSE for license details. +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#if __riscv_xlen == 64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/fpga/src/main/resources/vc709/uartboot/include/const.h b/fpga/src/main/resources/vc709/uartboot/include/const.h new file mode 100644 index 0000000000..8dcffbb064 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/const.h @@ -0,0 +1,18 @@ +// See LICENSE for license details. +/* Derived from */ + +#ifndef _SIFIVE_CONST_H +#define _SIFIVE_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _SIFIVE_CONST_H */ diff --git a/fpga/src/main/resources/vc709/uartboot/include/crc16.h b/fpga/src/main/resources/vc709/uartboot/include/crc16.h new file mode 100644 index 0000000000..8c84748f70 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/crc16.h @@ -0,0 +1,18 @@ +/* + * @,@Author: ,: your name + * @,@Date: ,: 1970-01-01 08:00:00 + * @,@LastEditTime: ,: 2021-01-30 12:11:45 + * @,@LastEditors: ,: Please set LastEditors + * @,@Description: ,: In User Settings Edit + * @,@FilePath: ,: /freedom/bootrom/sdboot/include/crc16.h + */ +#include + +#define CRC16_BITS 12 +#define CRC16_LEN 4096 +#define NUM_BLOCKS 1024 +#define NAK 0x15 +#define ACK 0x06 + +uint16_t crc16_round(uint16_t crc, uint8_t data); +uint16_t crc16(uint8_t *q); \ No newline at end of file diff --git a/fpga/src/main/resources/vc709/uartboot/include/devices/clint.h b/fpga/src/main/resources/vc709/uartboot/include/devices/clint.h new file mode 100644 index 0000000000..c2b05baeda --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/devices/clint.h @@ -0,0 +1,14 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_CLINT_H +#define _SIFIVE_CLINT_H + + +#define CLINT_MSIP 0x0000 +#define CLINT_MSIP_size 0x4 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIMECMP_size 0x8 +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIME_size 0x8 + +#endif /* _SIFIVE_CLINT_H */ diff --git a/fpga/src/main/resources/vc709/uartboot/include/devices/gpio.h b/fpga/src/main/resources/vc709/uartboot/include/devices/gpio.h new file mode 100644 index 0000000000..8ff5cb5d34 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/devices/gpio.h @@ -0,0 +1,32 @@ +/* + * @,@Author: ,: your name + * @,@Date: ,: 1970-01-01 08:00:00 + * @,@LastEditTime: ,: 2021-01-15 20:05:40 + * @,@LastEditors: ,: Please set LastEditors + * @,@Description: ,: In User Settings Edit + * @,@FilePath: ,: /freedom/mnt/D/Ubuntu/projects/freedom/bootrom/sdboot/include/devices/gpio.h + */ +// See LICENSE for license details. + +#ifndef _SIFIVE_GPIO_H +#define _SIFIVE_GPIO_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#endif /* _SIFIVE_GPIO_H */ diff --git a/fpga/src/main/resources/vc709/uartboot/include/devices/plic.h b/fpga/src/main/resources/vc709/uartboot/include/devices/plic.h new file mode 100644 index 0000000000..feb7f199c3 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/devices/plic.h @@ -0,0 +1,39 @@ +/* + * @,@Author: ,: your name + * @,@Date: ,: 1970-01-01 08:00:00 + * @,@LastEditTime: ,: 2021-01-26 13:14:09 + * @,@LastEditors: ,: Please set LastEditors + * @,@Description: ,: In User Settings Edit + * @,@FilePath: ,: /freedom/mnt/D/Ubuntu/projects/freedom/bootrom/sdboot/include/devices/plic.h + */ +// See LICENSE for license details. + +#ifndef PLIC_H +#define PLIC_H + +#include "../const.h" + +// 32 bits per source +#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 +// 1 bit per source (1 address) +#define PLIC_PENDING_OFFSET _AC(0x1000,UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +//0x80 per target +#define PLIC_ENABLE_OFFSET _AC(0x2000,UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + + +#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) +#define PLIC_CLAIM_OFFSET _AC(0x200004,UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#define PLIC_MAX_SOURCE 1023 +#define PLIC_SOURCE_MASK 0x3FF + +#define PLIC_MAX_TARGET 15871 +#define PLIC_TARGET_MASK 0x3FFF + +#endif /* PLIC_H */ diff --git a/fpga/src/main/resources/vc709/uartboot/include/devices/spi.h b/fpga/src/main/resources/vc709/uartboot/include/devices/spi.h new file mode 100644 index 0000000000..7118572abc --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/devices/spi.h @@ -0,0 +1,79 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_SPI_H +#define _SIFIVE_SPI_H + +/* Register offsets */ + +#define SPI_REG_SCKDIV 0x00 +#define SPI_REG_SCKMODE 0x04 +#define SPI_REG_CSID 0x10 +#define SPI_REG_CSDEF 0x14 +#define SPI_REG_CSMODE 0x18 + +#define SPI_REG_DCSSCK 0x28 +#define SPI_REG_DSCKCS 0x2a +#define SPI_REG_DINTERCS 0x2c +#define SPI_REG_DINTERXFR 0x2e + +#define SPI_REG_FMT 0x40 +#define SPI_REG_TXFIFO 0x48 +#define SPI_REG_RXFIFO 0x4c +#define SPI_REG_TXCTRL 0x50 +#define SPI_REG_RXCTRL 0x54 + +#define SPI_REG_FCTRL 0x60 +#define SPI_REG_FFMT 0x64 + +#define SPI_REG_IE 0x70 +#define SPI_REG_IP 0x74 + +/* Fields */ + +#define SPI_SCK_POL 0x1 +#define SPI_SCK_PHA 0x2 + +#define SPI_FMT_PROTO(x) ((x) & 0x3) +#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) +#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) +#define SPI_FMT_LEN(x) (((x) & 0xf) << 16) + +/* TXCTRL register */ +#define SPI_TXWM(x) ((x) & 0xffff) +/* RXCTRL register */ +#define SPI_RXWM(x) ((x) & 0xffff) + +#define SPI_IP_TXWM 0x1 +#define SPI_IP_RXWM 0x2 + +#define SPI_FCTRL_EN 0x1 + +#define SPI_INSN_CMD_EN 0x1 +#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) +#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) +#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) +#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) +#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) +#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) +#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) + +#define SPI_TXFIFO_FULL (1 << 31) +#define SPI_RXFIFO_EMPTY (1 << 31) + +/* Values */ + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + +#endif /* _SIFIVE_SPI_H */ diff --git a/fpga/src/main/resources/vc709/uartboot/include/devices/uart.h b/fpga/src/main/resources/vc709/uartboot/include/devices/uart.h new file mode 100644 index 0000000000..f7ce659b87 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/devices/uart.h @@ -0,0 +1,36 @@ +/* + * @,@Author: ,: your name + * @,@Date: ,: 1970-01-01 08:00:00 + * @,@LastEditTime: ,: 2021-01-24 11:08:33 + * @,@LastEditors: ,: Please set LastEditors + * @,@Description: ,: In User Settings Edit + * @,@FilePath: ,: /freedom/bootrom/sdboot/include/devices/uart.h + */ +// See LICENSE for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXNSTOP 0x2 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ \ No newline at end of file diff --git a/fpga/src/main/resources/vc709/uartboot/include/kprintf.h b/fpga/src/main/resources/vc709/uartboot/include/kprintf.h new file mode 100644 index 0000000000..c2b4f7b4bf --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/kprintf.h @@ -0,0 +1,76 @@ +/* + * @,@Author: ,: your name + * @,@Date: ,: 1970-01-01 08:00:00 + * @,@LastEditTime: ,: 2021-01-26 13:18:40 + * @,@LastEditors: ,: Please set LastEditors + * @,@Description: ,: In User Settings Edit + * @,@FilePath: ,: /freedom/mnt/D/Ubuntu/projects/freedom/bootrom/sdboot/kprintf.h + */ +// See LICENSE for license details. +#ifndef _SDBOOT_KPRINTF_H +#define _SDBOOT_KPRINTF_H + +#include + +#include "platform.h" + +#define REG32(p, i) ((p)[(i) >> 2]) + +#ifndef UART_CTRL_ADDR + #ifndef UART_NUM + #define UART_NUM 0 + #endif + + #define _CONCAT3(A, B, C) A ## B ## C + #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) + #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) +#endif +static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); + +static inline void kputc(char c) +{ + volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); +#ifdef __riscv_atomic + int32_t r; + do { + __asm__ __volatile__ ( + "amoor.w %0, %2, %1\n" + : "=r" (r), "+A" (*tx) + : "r" (c)); + } while (r < 0); +#else + while ((int32_t)(*tx) < 0); + *tx = c; +#endif +} + +static inline char kgetc() +{ + int32_t val = -1; + volatile uint32_t *rx = ®32(uart, UART_REG_RXFIFO); + + while (val < 0) { + val = *rx; + } + + return val & 0xff; +} + + +extern void kputs(const char *); +extern void kprintf(const char *, ...); + +extern void kgets(char *); + +extern void kread(char *s, int count); +extern void kwrite(char *s, int count); + +#ifdef DEBUG +#define dprintf(s, ...) kprintf((s), ##__VA_ARGS__) +#define dputs(s) kputs((s)) +#else +#define dprintf(s, ...) do { } while (0) +#define dputs(s) do { } while (0) +#endif + +#endif /* _SDBOOT_KPRINTF_H */ diff --git a/fpga/src/main/resources/vc709/uartboot/include/platform.h b/fpga/src/main/resources/vc709/uartboot/include/platform.h new file mode 100644 index 0000000000..e1549cf65e --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/platform.h @@ -0,0 +1,107 @@ +/* + * @,@Author: ,: your name + * @,@Date: ,: 1970-01-01 08:00:00 + * @,@LastEditTime: ,: 2021-01-23 21:51:27 + * @,@LastEditors: ,: your name + * @,@Description: ,: In User Settings Edit + * @,@FilePath: ,: /freedom/mnt/D/Ubuntu/projects/freedom/bootrom/sdboot/include/platform.h + */ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +#include "const.h" +#include "riscv_test_defaults.h" +#include "devices/clint.h" +#include "devices/gpio.h" +#include "devices/plic.h" +#include "devices/spi.h" +#include "devices/uart.h" + + // Some things missing from the official encoding.h +#if __riscv_xlen == 32 + #define MCAUSE_INT 0x80000000UL + #define MCAUSE_CAUSE 0x7FFFFFFFUL +#else + #define MCAUSE_INT 0x8000000000000000UL + #define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL +#endif + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// CPU info +#define NUM_CORES 1 +#define GLOBAL_INT_SIZE 15 +#define GLOBAL_INT_MAX_PRIORITY 7 + +// Memory map +#define AXI_PCIE_HOST_1_00_A_CTRL_ADDR _AC(0x50000000,UL) +#define AXI_PCIE_HOST_1_00_A_CTRL_SIZE _AC(0x4000000,UL) +#define CLINT_CTRL_ADDR _AC(0x2000000,UL) +#define CLINT_CTRL_SIZE _AC(0x10000,UL) +#define DEBUG_CTRL_ADDR _AC(0x0,UL) +#define DEBUG_CTRL_SIZE _AC(0x1000,UL) +#define ERROR_MEM_ADDR _AC(0x3000,UL) +#define ERROR_MEM_SIZE _AC(0x1000,UL) +#define GPIO_CTRL_ADDR _AC(0x64002000,UL) +#define GPIO_CTRL_SIZE _AC(0x1000,UL) +#define MASKROM_MEM_ADDR _AC(0x10000,UL) +#define MASKROM_MEM_SIZE _AC(0x2000,UL) +#define MEMORY_MEM_ADDR _AC(0x80000000,UL) +#define MEMORY_MEM_SIZE _AC(0x40000000,UL) +#define PLIC_CTRL_ADDR _AC(0xc000000,UL) +#define PLIC_CTRL_SIZE _AC(0x4000000,UL) +#define SPI_CTRL_ADDR _AC(0x64001000,UL) +#define SPI_CTRL_SIZE _AC(0x1000,UL) +#define TEST_CTRL_ADDR _AC(0x4000,UL) +#define TEST_CTRL_SIZE _AC(0x1000,UL) +#define UART_CTRL_ADDR _AC(0x64000000,UL) +#define UART_CTRL_SIZE _AC(0x1000,UL) + +// IOF masks + + +// Interrupt numbers +#define UART_INT_BASE 1 +#define SPI_INT_BASE 2 +#define GPIO_INT_BASE 3 +#define AXI_PCIE_HOST_1_00_A_INT_BASE 7 + +// Helper functions +#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i))) +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) +#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i))) +// Bulk set bits in `reg` to either 0 or 1. +// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7 +// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7 +#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); } +#define AXI_PCIE_HOST_1_00_A_REG(offset) _REG32(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define DEBUG_REG(offset) _REG32(DEBUG_CTRL_ADDR, offset) +#define ERROR_REG(offset) _REG32(ERROR_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define MASKROM_REG(offset) _REG32(MASKROM_CTRL_ADDR, offset) +#define MEMORY_REG(offset) _REG32(MEMORY_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define SPI_REG(offset) _REG32(SPI_CTRL_ADDR, offset) +#define TEST_REG(offset) _REG32(TEST_CTRL_ADDR, offset) +#define UART_REG(offset) _REG32(UART_CTRL_ADDR, offset) +#define AXI_PCIE_HOST_1_00_A_REG64(offset) _REG64(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset) +#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset) +#define DEBUG_REG64(offset) _REG64(DEBUG_CTRL_ADDR, offset) +#define ERROR_REG64(offset) _REG64(ERROR_CTRL_ADDR, offset) +#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset) +#define MASKROM_REG64(offset) _REG64(MASKROM_CTRL_ADDR, offset) +#define MEMORY_REG64(offset) _REG64(MEMORY_CTRL_ADDR, offset) +#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset) +#define SPI_REG64(offset) _REG64(SPI_CTRL_ADDR, offset) +#define TEST_REG64(offset) _REG64(TEST_CTRL_ADDR, offset) +#define UART_REG64(offset) _REG64(UART_CTRL_ADDR, offset) + +// Misc + + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/fpga/src/main/resources/vc709/uartboot/include/riscv_test_defaults.h b/fpga/src/main/resources/vc709/uartboot/include/riscv_test_defaults.h new file mode 100644 index 0000000000..a2dea3d4ad --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/riscv_test_defaults.h @@ -0,0 +1,81 @@ +// See LICENSE for license details. +#ifndef _RISCV_TEST_DEFAULTS_H +#define _RISCV_TEST_DEFAULTS_H + +#define TESTNUM x28 +#define TESTBASE 0x4000 + +#define RVTEST_RV32U \ + .macro init; \ + .endm + +#define RVTEST_RV64U \ + .macro init; \ + .endm + +#define RVTEST_RV32UF \ + .macro init; \ + /* If FPU exists, initialize FCSR. */ \ + csrr t0, misa; \ + andi t0, t0, 1 << ('F' - 'A'); \ + beqz t0, 1f; \ + /* Enable FPU if it exists. */ \ + li t0, MSTATUS_FS; \ + csrs mstatus, t0; \ + fssr x0; \ +1: ; \ + .endm + +#define RVTEST_RV64UF \ + .macro init; \ + /* If FPU exists, initialize FCSR. */ \ + csrr t0, misa; \ + andi t0, t0, 1 << ('F' - 'A'); \ + beqz t0, 1f; \ + /* Enable FPU if it exists. */ \ + li t0, MSTATUS_FS; \ + csrs mstatus, t0; \ + fssr x0; \ +1: ; \ + .endm + +#define RVTEST_CODE_BEGIN \ + .section .text.init; \ + .globl _prog_start; \ +_prog_start: \ + init; + +#define RVTEST_CODE_END \ + unimp + +#define RVTEST_PASS \ + fence; \ + li t0, TESTBASE; \ + li t1, 0x5555; \ + sw t1, 0(t0); \ +1: \ + j 1b; + +#define RVTEST_FAIL \ + li t0, TESTBASE; \ + li t1, 0x3333; \ + slli a0, a0, 16; \ + add a0, a0, t1; \ + sw a0, 0(t0); \ +1: \ + j 1b; + +#define EXTRA_DATA + +#define RVTEST_DATA_BEGIN \ + EXTRA_DATA \ + .align 4; .global begin_signature; begin_signature: + +#define RVTEST_DATA_END \ + _msg_init: .asciz "RUN\r\n"; \ + _msg_pass: .asciz "PASS"; \ + _msg_fail: .asciz "FAIL "; \ + _msg_end: .asciz "\r\n"; \ + .align 4; .global end_signature; end_signature: + +#endif /* _RISCV_TEST_DEFAULTS_H */ diff --git a/fpga/src/main/resources/vc709/uartboot/include/sections.h b/fpga/src/main/resources/vc709/uartboot/include/sections.h new file mode 100644 index 0000000000..6e1f0518bc --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/sections.h @@ -0,0 +1,17 @@ +// See LICENSE for license details. +#ifndef _SECTIONS_H +#define _SECTIONS_H + +extern unsigned char _rom[]; +extern unsigned char _rom_end[]; + +extern unsigned char _ram[]; +extern unsigned char _ram_end[]; + +extern unsigned char _ftext[]; +extern unsigned char _etext[]; +extern unsigned char _fbss[]; +extern unsigned char _ebss[]; +extern unsigned char _end[]; + +#endif /* _SECTIONS_H */ diff --git a/fpga/src/main/resources/vc709/uartboot/include/serial.h b/fpga/src/main/resources/vc709/uartboot/include/serial.h new file mode 100644 index 0000000000..c0f36e0c37 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/serial.h @@ -0,0 +1,32 @@ +/* + * @,@Author: ,: your name + * @,@Date: ,: 1970-01-01 08:00:00 + * @,@LastEditTime: ,: 2021-01-30 11:45:36 + * @,@LastEditors: ,: Please set LastEditors + * @,@Description: ,: In User Settings Edit + * @,@FilePath: ,: /freedom/bootrom/sdboot/include/serial_boot.h + */ + +#ifndef __SERIAL_BOOT_ +#define __SERIAL_BOOT_ + +#include +#include "platform.h" +#include "crc16.h" +#include "kprintf.h" + +#define MAX_CORES 4 + +typedef enum _cmd_t +{ + UART_CMD_TRANSFER, + UART_CMD_END +} cmd_t; + +typedef struct _package_t +{ + uint8_t *addr; + long len; +} package_t; + +#endif \ No newline at end of file diff --git a/fpga/src/main/resources/vc709/uartboot/include/smp.h b/fpga/src/main/resources/vc709/uartboot/include/smp.h new file mode 100644 index 0000000000..145ceb37f4 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/include/smp.h @@ -0,0 +1,142 @@ +#ifndef SIFIVE_SMP +#define SIFIVE_SMP +#include "platform.h" + +// The maximum number of HARTs this code supports +#ifndef MAX_HARTS +#define MAX_HARTS 32 +#endif +#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4) +#define CLINT1_END_HART_IPI CLINT1_CTRL_ADDR + (MAX_HARTS*4) + +// The hart that non-SMP tests should run on +#ifndef NONSMP_HART +#define NONSMP_HART 0 +#endif + +/* If your test cannot handle multiple-threads, use this: + * smp_disable(reg1) + */ +#define smp_disable(reg1, reg2) \ + csrr reg1, mhartid ;\ + li reg2, NONSMP_HART ;\ + beq reg1, reg2, hart0_entry ;\ +42: ;\ + wfi ;\ + j 42b ;\ +hart0_entry: + +/* If your test needs to temporarily block multiple-threads, do this: + * smp_pause(reg1, reg2) + * ... single-threaded work ... + * smp_resume(reg1, reg2) + * ... multi-threaded work ... + */ + +#define smp_pause(reg1, reg2) \ + li reg2, 0x8 ;\ + csrw mie, reg2 ;\ + li reg1, NONSMP_HART ;\ + csrr reg2, mhartid ;\ + bne reg1, reg2, 42f + +#ifdef CLINT1_CTRL_ADDR +// If a second CLINT exists, then make sure we: +// 1) Trigger a software interrupt on all harts of both CLINTs. +// 2) Locate your own hart's software interrupt pending register and clear it. +// 3) Wait for all harts on both CLINTs to clear their software interrupt +// pending register. +// WARNING: This code makes these assumptions, which are only true for Fadu as +// of now: +// 1) hart0 uses CLINT0 at offset 0 +// 2) hart2 uses CLINT1 at offset 0 +// 3) hart3 uses CLINT1 at offset 1 +// 4) There are no other harts or CLINTs in the system. +#define smp_resume(reg1, reg2) \ + /* Trigger software interrupt on CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ + /* Trigger software interrupt on CLINT1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT1_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ + /* Wait to receive software interrupt */ \ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + /* Clear own software interrupt bit */ \ + csrr reg2, mhartid ;\ + bnez reg2, 41f; \ + /* hart0 case: Use CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ + j 42f; \ +41: \ + /* hart 2, 3 case: Use CLINT1 and remap hart IDs to 0 and 1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ + addi reg2, reg2, -2; \ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ; \ +42: \ + /* Wait for all software interrupt bits to be cleared on CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b; \ + /* Wait for all software interrupt bits to be cleared on CLINT1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT1_END_HART_IPI ;\ + blt reg1, reg2, 41b; \ + /* End smp_resume() */ + +#else + +#define smp_resume(reg1, reg2) \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + li reg1, CLINT_CTRL_ADDR ;\ + csrr reg2, mhartid ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b + +#endif /* ifdef CLINT1_CTRL_ADDR */ + +#endif diff --git a/fpga/src/main/resources/vc709/uartboot/kprintf.c b/fpga/src/main/resources/vc709/uartboot/kprintf.c new file mode 100644 index 0000000000..9dec7a7a04 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/kprintf.c @@ -0,0 +1,145 @@ +// See LICENSE for license details. +#include +#include +#include + +#include "kprintf.h" + +static inline void _kputs(const char *s) +{ + char c; + for (; (c = *s) != '\0'; s++) + kputc(c); +} + +static inline void _kgets(char *s) +{ + for (; (*s = kgetc()) != '\n'; s++); + *s = '\0'; +} + +void kread(char *s, int count) +{ + char *p = s; + for (int i = 0; i < count; i++) { + *p++ = kgetc(); + } +} + +void kwrite(char *s, int count) +{ + char *p = s; + for (int i = 0; i < count; i++) { + kputc(*p++); + } +} + +void kputs(const char *s) +{ + _kputs(s); + kputc('\n'); +} + +void kgets(char *s){ + _kgets(s); +} + +void _escape_char(const char c){ + switch (c) { + case 'a': + kputc('\n'); + break; + case 'b': + kputc('\n'); + break; + case 'f': + kputc('\n'); + break; + case 'n': + kputc('\n'); + break; + case 'r': + kputc('\n'); + break; + case 't': + kputc('\n'); + break; + case 'v': + kputc('\n'); + break; + case '\\': + kputc('\n'); + break; + case '\'': + kputc('\''); + break; + case '"': + kputc('"'); + break; + case '?': + kputc('?'); + break; + case '0': + kputc('\0'); + break; + default: + break; + } +} + +void kprintf(const char *fmt, ...) +{ + va_list vl; + bool is_format, is_long, is_char; + char c; + + va_start(vl, fmt); + is_format = false; + is_long = false; + is_char = false; + while ((c = *fmt++) != '\0') { + if (is_format) { + switch (c) { + case 'l': + is_long = true; + continue; + case 'h': + is_char = true; + continue; + case 'x': { + unsigned long n; + long i; + if (is_long) { + n = va_arg(vl, unsigned long); + i = (sizeof(unsigned long) << 3) - 4; + } else { + n = va_arg(vl, unsigned int); + i = is_char ? 4 : (sizeof(unsigned int) << 3) - 4; + } + for (; i >= 0; i -= 4) { + long d; + d = (n >> i) & 0xF; + kputc(d < 10 ? '0' + d : 'a' + d - 10); + } + break; + } + case 's': + _kputs(va_arg(vl, const char *)); + break; + case 'c': + kputc(va_arg(vl, int)); + break; + } + is_format = false; + is_long = false; + is_char = false; + } else if (c == '%') { + is_format = true; + } else if (c == '\\') { + _escape_char(*(fmt++)); + } else { + kputc(c); + } + } + va_end(vl); +} diff --git a/fpga/src/main/resources/vc709/uartboot/linker/bootrom.elf.lds b/fpga/src/main/resources/vc709/uartboot/linker/bootrom.elf.lds new file mode 100644 index 0000000000..deb76da9fd --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/linker/bootrom.elf.lds @@ -0,0 +1,79 @@ +OUTPUT_ARCH("riscv") +ENTRY(_prog_start) + +INCLUDE memory.lds + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + PROVIDE(_ram = ORIGIN(memory_mem)); + PROVIDE(_ram_end = _ram + LENGTH(memory_mem)); + + .text ALIGN((ORIGIN(maskrom_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(maskrom_mem) + 0x0), 8)) { + PROVIDE(_ftext = .); + *(.text.init) + *(.text.unlikely .text.unlikely.*) + *(.text .text.* .gnu.linkonce.t.*) + PROVIDE(_etext = .); + . += 0x40; /* to create a gap between .text and .data b/c ifetch can fetch ahead from .data */ + } >maskrom_mem :text + + .eh_frame ALIGN((ADDR(.text) + SIZEOF(.text)), 8) : AT(ALIGN((LOADADDR(.text) + SIZEOF(.text)), 8)) { + *(.eh_frame) + } >maskrom_mem :text + + .rodata ALIGN((ADDR(.eh_frame) + SIZEOF(.eh_frame)), 8) : AT(ALIGN((LOADADDR(.eh_frame) + SIZEOF(.eh_frame)), 8)) ALIGN_WITH_INPUT { + *(.rodata .rodata.* .gnu.linkonce.r.*) + } >maskrom_mem :data + + .srodata ALIGN((ADDR(.rodata) + SIZEOF(.rodata)), 8) : AT(ALIGN((LOADADDR(.rodata) + SIZEOF(.rodata)), 8)) ALIGN_WITH_INPUT { + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata.*) + } >maskrom_mem :data + + .data ALIGN((ADDR(.srodata) + SIZEOF(.srodata)), 8) : AT(ALIGN((LOADADDR(.srodata) + SIZEOF(.srodata)), 8)) ALIGN_WITH_INPUT { + *(.data .data.* .gnu.linkonce.d.*) + *(.tohost) /* TODO: Support sections that aren't explicitly listed in this linker script */ + } >maskrom_mem :data + + .sdata ALIGN((ADDR(.data) + SIZEOF(.data)), 8) : AT(ALIGN((LOADADDR(.data) + SIZEOF(.data)), 8)) ALIGN_WITH_INPUT { + *(.sdata .sdata.* .gnu.linkonce.s.*) + } >maskrom_mem :data + + PROVIDE(_data = ADDR(.rodata)); + PROVIDE(_data_lma = LOADADDR(.rodata)); + PROVIDE(_edata = .); + + .bss ALIGN((ORIGIN(memory_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(memory_mem) + 0x0), 8)) ALIGN(8) { + PROVIDE(_fbss = .); + PROVIDE(__global_pointer$ = . + 0x7C0); + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(8); + PROVIDE(_ebss = .); + } >memory_mem :bss + + PROVIDE(_end = .); + + /* + * heap_stack_region_usable_end: (ORIGIN(memory_mem) + LENGTH(memory_mem)) + * heap_stack_min_size: 4096 + * heap_stack_max_size: 1048576 + */ + PROVIDE(_sp = ALIGN(MIN((ORIGIN(memory_mem) + LENGTH(memory_mem)), _ebss + 1048576) - 7, 8)); + PROVIDE(_heap_end = _sp - 2048); + + /* This section is a noop and is only used for the ASSERT */ + .stack : { + ASSERT(_sp >= (_ebss + 4096), "Error: No room left for the heap and stack"); + } +} diff --git a/fpga/src/main/resources/vc709/uartboot/linker/memory.lds b/fpga/src/main/resources/vc709/uartboot/linker/memory.lds new file mode 100644 index 0000000000..7f6cfc9194 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/linker/memory.lds @@ -0,0 +1,14 @@ +MEMORY +{ + debug_ctrl (rwx) : ORIGIN = 0x0, LENGTH = 0x1000 + error_mem (rw) : ORIGIN = 0x3000, LENGTH = 0x1000 + test_ctrl (rw) : ORIGIN = 0x4000, LENGTH = 0x1000 + maskrom_mem (rx) : ORIGIN = 0x10000, LENGTH = 0x2000 + clint_ctrl (rw) : ORIGIN = 0x2000000, LENGTH = 0x10000 + plic_ctrl (rw) : ORIGIN = 0xc000000, LENGTH = 0x4000000 + axi_pcie_host_1_00_a_ctrl (rw) : ORIGIN = 0x50000000, LENGTH = 0x4000000 + uart_ctrl (rw) : ORIGIN = 0x54000000, LENGTH = 0x1000 + spi_ctrl (rw) : ORIGIN = 0x54001000, LENGTH = 0x1000 + gpio_ctrl (rw) : ORIGIN = 0x54002000, LENGTH = 0x1000 + memory_mem (rwx) : ORIGIN = 0x80000000, LENGTH = 0x40000000 +} diff --git a/fpga/src/main/resources/vc709/uartboot/plic.c b/fpga/src/main/resources/vc709/uartboot/plic.c new file mode 100644 index 0000000000..8ab278fd4f --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/plic.c @@ -0,0 +1,11 @@ +/* + * @,@Author: ,: your name + * @,@Date: ,: 1970-01-01 08:00:00 + * @,@LastEditTime: ,: 2021-01-22 09:12:20 + * @,@LastEditors: ,: Please set LastEditors + * @,@Description: ,: In User Settings Edit + * @,@FilePath: ,: /freedom/bootrom/sdboot/plic.c + */ +#include + + diff --git a/fpga/src/main/resources/vc709/uartboot/sd.c b/fpga/src/main/resources/vc709/uartboot/sd.c new file mode 100644 index 0000000000..0e882572ca --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/sd.c @@ -0,0 +1,221 @@ +// See LICENSE for license details. +#include + +#include "include/platform.h" +#include "common.h" +#include "crc16.h" + +#define DEBUG +#include "kprintf.h" + +#define MAX_CORES 8 + +#define PAYLOAD_SIZE (26 << 11) + +#ifndef TL_CLK +#error Must define TL_CLK +#endif + +#define F_CLK TL_CLK + +static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR); + +static inline uint8_t spi_xfer(uint8_t d) +{ + int32_t r; + + REG32(spi, SPI_REG_TXFIFO) = d; + do { + r = REG32(spi, SPI_REG_RXFIFO); + } while (r < 0); + return r; +} + +static inline uint8_t sd_dummy(void) +{ + return spi_xfer(0xFF); +} + +static uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) +{ + unsigned long n; + uint8_t r; + + REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_HOLD; + sd_dummy(); + spi_xfer(cmd); + spi_xfer(arg >> 24); + spi_xfer(arg >> 16); + spi_xfer(arg >> 8); + spi_xfer(arg); + spi_xfer(crc); + + n = 1000; + do { + r = sd_dummy(); + if (!(r & 0x80)) { + dprintf("sd:cmd: %hx\r\n", r); + goto done; + } + } while (--n > 0); + kputs("sd_cmd: timeout"); +done: + return r; +} + +static inline void sd_cmd_end(void) +{ + sd_dummy(); + REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_AUTO; +} + + +static void sd_poweron(void) +{ + long i; + REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL); + REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF; + for (i = 10; i > 0; i--) { + sd_dummy(); + } + REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_AUTO; +} + +static int sd_cmd0(void) +{ + int rc; + dputs("CMD0"); + rc = (sd_cmd(0x40, 0, 0x95) != 0x01); + sd_cmd_end(); + return rc; +} + +static int sd_cmd8(void) +{ + int rc; + dputs("CMD8"); + rc = (sd_cmd(0x48, 0x000001AA, 0x87) != 0x01); + sd_dummy(); /* command version; reserved */ + sd_dummy(); /* reserved */ + rc |= ((sd_dummy() & 0xF) != 0x1); /* voltage */ + rc |= (sd_dummy() != 0xAA); /* check pattern */ + sd_cmd_end(); + return rc; +} + +static void sd_cmd55(void) +{ + sd_cmd(0x77, 0, 0x65); + sd_cmd_end(); +} + +static int sd_acmd41(void) +{ + uint8_t r; + dputs("ACMD41"); + do { + sd_cmd55(); + r = sd_cmd(0x69, 0x40000000, 0x77); /* HCS = 1 */ + } while (r == 0x01); + return (r != 0x00); +} + +static int sd_cmd58(void) +{ + int rc; + dputs("CMD58"); + rc = (sd_cmd(0x7A, 0, 0xFD) != 0x00); + rc |= ((sd_dummy() & 0x80) != 0x80); /* Power up status */ + sd_dummy(); + sd_dummy(); + sd_dummy(); + sd_cmd_end(); + return rc; +} + +static int sd_cmd16(void) +{ + int rc; + dputs("CMD16"); + rc = (sd_cmd(0x50, 0x200, 0x15) != 0x00); + sd_cmd_end(); + return rc; +} + +#define SPIN_SHIFT 6 +#define SPIN_UPDATE(i) (!((i) & ((1 << SPIN_SHIFT)-1))) +#define SPIN_INDEX(i) (((i) >> SPIN_SHIFT) & 0x3) + +static const char spinner[] = { '-', '/', '|', '\\' }; + +static int copy(void) +{ + volatile uint8_t *p = (void *)(PAYLOAD_DEST); + long i = PAYLOAD_SIZE; + int rc = 0; + + dputs("CMD18"); + kprintf("LOADING"); + + REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL); + if (sd_cmd(0x52, 0, 0xE1) != 0x00) { + sd_cmd_end(); + return 1; + } + do { + volatile uint8_t *q = p; + + // transfer data + while (sd_dummy() != 0xFE); + for (int i = 0; i < 512; i++) { + uint8_t x = sd_dummy(); + *p++ = x; + } + + // crc16 512-bytes + crc = crc16(q); + + // expected crc16 + uint16_t crc_exp = ((uint16_t)sd_dummy() << 8); + crc_exp |= sd_dummy(); + + if (crc != crc_exp) { + kputs("\b- CRC mismatch "); + rc = 1; + break; + } + + if (SPIN_UPDATE(i)) { + kputc('\b'); + kputc(spinner[SPIN_INDEX(i)]); + } + } while (--i > 0); + sd_cmd_end(); + + sd_cmd(0x4C, 0, 0x01); + sd_cmd_end(); + kputs("\b "); + return rc; +} + +int main(void) +{ + REG32(uart, UART_REG_TXCTRL) = UART_TXEN; + + kputs("INIT"); + sd_poweron(); + if (sd_cmd0() || + sd_cmd8() || + sd_acmd41() || + sd_cmd58() || + sd_cmd16() || + copy()) { + kputs("ERROR"); + return 1; + } + + kputs("BOOT"); + + __asm__ __volatile__ ("fence.i" : : : "memory"); + return 0; +} diff --git a/fpga/src/main/resources/vc709/uartboot/serial.c b/fpga/src/main/resources/vc709/uartboot/serial.c new file mode 100644 index 0000000000..912f53f1d5 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/serial.c @@ -0,0 +1,73 @@ +/* + * @,@Author: ,: your name + * @,@Date: ,: 1970-01-01 08:00:00 + * @,@LastEditTime: ,: 2021-01-29 22:34:27 + * @,@LastEditors: ,: Please set LastEditors + * @,@Description: ,: In User Settings Edit + * @,@FilePath: ,: /freedom/bootrom/sdboot/serial.c + */ + +#include "./include/serial.h" + +static int read_block(uint8_t *q) +{ + int retry = -1; + char cmd = NAK; + + uint16_t crc_exp; + do { + retry++; + uint8_t *p = q; + // receive file and crc + kread((char *)p, CRC16_LEN); + kread((char *)&crc_exp, 2); + // ACK/NAK + cmd = ((crc16(p) == crc_exp) ? ACK : NAK); + kwrite(&cmd, 1); + } while (cmd != ACK); + + return retry; +} + +static int read(uint8_t *addr, long len) +{ + uint8_t *p = addr; + int retry = 0; + int n_blocks = len >> CRC16_BITS; + n_blocks += (((len % CRC16_LEN) == 0)? 0 : 1); + for (int i = 0; i < n_blocks; i++, p += CRC16_LEN) { + retry += read_block(p); + } + return retry; +} + +static void session(void) +{ + cmd_t cmd; + while (cmd != UART_CMD_END) { + kread((char *)&cmd, sizeof(cmd_t)); + if (cmd == UART_CMD_TRANSFER) { + package_t package; + kread((char*)&package, sizeof(package_t)); + read(package.addr, package.len); + } + } +} + +int main(void) +{ + REG32(uart, UART_REG_TXCTRL) = UART_TXEN; + REG32(uart, UART_REG_RXCTRL) = UART_RXEN; + + kputs("BOOT INIT"); + + session(); + + kputs("BOOT END"); + + REG32(uart, UART_REG_TXCTRL) &= ~UART_TXEN; + REG32(uart, UART_REG_RXCTRL) &= ~UART_RXEN; + + __asm__ __volatile__ ("fence.i" : : : "memory"); + return 0; +} diff --git a/fpga/src/main/resources/vc709/uartboot/uart.c b/fpga/src/main/resources/vc709/uartboot/uart.c new file mode 100644 index 0000000000..96c47dbc56 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/uart.c @@ -0,0 +1,57 @@ +/* + * @,@Author: ,: your name + * @,@Date: ,: 1970-01-01 08:00:00 + * @,@LastEditTime: ,: 2021-01-24 11:27:59 + * @,@LastEditors: ,: Please set LastEditors + * @,@Description: ,: In User Settings Edit + * @,@FilePath: ,: /freedom/bootrom/sdboot/uart.c + */ +// See LICENSE for license details. +#include + +#include "./include/platform.h" +#include "common.h" + +#define DEBUG +#include "kprintf.h" + +#define is_num(c) ((c>='0')&&(c<='9')) +#define is_lower(c) ((c>='a')&&(c<='z')) +#define is_upper(c) ((c>='A')&&(c<='Z')) +#define is_alpha(c) (is_lower(c)||is_upper(c)) + +static int strcmp(const char *p, const char *q) { + // equal + for( ; *p == *q; ++p, ++q) + if(*p == '\0') + return (0); + // not equal + return (*(unsigned char *)p < *(unsigned char *)q) ? -1 : +1; +} + +static int stoi(char *p) { + int val = 0; + if (*p == '0' && *(p+1) == 'x') { + p += 2; + for ( ; *p != '\0'; p++) { + if (is_num(*p)) { + val = (val << 4) + (*p - '0'); + } else if (is_lower(*p)) { + val = (val << 4) + (*p - 'a' + 10); + } else if (is_upper(*p)) { + val = (val << 4) + (*p - 'A' + 10); + } else { + break; + } + } + } else { + for ( ; *p != '\0'; p++) { + if (is_num(*p)) { + val = val * 10 + (*p - '0'); + } else { + break; + } + } + } + return val; +} \ No newline at end of file diff --git a/fpga/src/main/resources/vc709/uartsend/Makefile b/fpga/src/main/resources/vc709/uartsend/Makefile new file mode 100644 index 0000000000..5fdd604dd5 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartsend/Makefile @@ -0,0 +1,9 @@ +build: + CC=gcc + $(CC) -c ./uartboot/crc16.c -o ./uartboot/crc16.o + $(CC) -c serial.c -o serial.o + $(CC) -o serial serial.o ./uartboot/crc16.o + +clean: + rm serial.o ./uartboot/crc16.o + rm serial diff --git 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+#include +#include +#include +#include //文件控制定义 +#include //终端控制定义 +#include +#include +#include +#include +#include + +#include "./uartboot/include/serial.h" + +#define DEVICE "/dev/ttyUSB1" +#define S_TIMEOUT 1 + +int serial_fd = 0; + +//打开串口并初始化设置 +int init_serial(char *device) +{ + serial_fd = open(device, O_RDWR | O_NOCTTY | O_NDELAY); + if (serial_fd < 0) { + perror("open"); + return -1; + } + + //串口主要设置结构体termios + struct termios options; + + /**1. tcgetattr函数用于获取与终端相关的参数。 + *参数fd为终端的文件描述符，返回的结果保存在termios结构体中 + */ + + tcgetattr(serial_fd, &options); + /**2. 修改所获得的参数*/ + options.c_cflag |= (CLOCAL | CREAD); //设置控制模式状态，本地连接，接收使能 + options.c_cflag &= ~CSIZE; //字符长度，设置数据位之前一定要屏掉这个位 + options.c_cflag &= ~CRTSCTS; //无硬件流控 + options.c_cflag |= CS8; //8位数据长度 + options.c_cflag &= ~CSTOPB; //1位停止位 + options.c_iflag |= IGNPAR; //无奇偶检验位 + options.c_oflag = 0; //输出模式 + options.c_lflag = 0; //不激活终端模式 + cfsetospeed(&options, B115200); //设置波特率 + + /**3. 设置新属性，TCSANOW：所有改变立即生效*/ + tcflush(serial_fd, TCIFLUSH); //溢出数据可以接收，但不读 + tcsetattr(serial_fd, TCSANOW, &options); + + return 0; +} + +/** +*串口发送数据 +*@fd:串口描述符 +*@data:待发送数据 +*@datalen:数据长度 +*/ +unsigned int total_send = 0 ; +int uart_send(int fd, uint8_t *data, int datalen) +{ + int len = 0; + len = write(fd, data, datalen);//实际写入的长度 + if(len == datalen) { + total_send += len; + return len; + } else { + tcflush(fd, TCOFLUSH);//TCOFLUSH刷新写入的数据但不传送 + return -1; + } + return 0; +} + +/** +*串口接收数据 +*要求启动后，在pc端发送ascii文件 +*/ +unsigned int total_length = 0 ; +int uart_recv(int fd, uint8_t *data, int datalen) +{ + int len=0, ret = 0; + fd_set fs_read; + struct timeval tv_timeout; + + FD_ZERO(&fs_read); + FD_SET(fd, &fs_read); + +#ifdef S_TIMEOUT + tv_timeout.tv_sec = (10*20/115200+2); + tv_timeout.tv_usec = 0; + ret = select(fd+1, &fs_read, NULL, NULL, NULL); +#elif + ret = select(fd+1, &fs_read, NULL, NULL, tv_timeout); +#endif + + //如果返回0，代表在描述符状态改变前已超过timeout时间,错误返回-1 + + if (FD_ISSET(fd, &fs_read)) { + len = read(fd, data, datalen); + total_length += len ; + return len; + } else { + perror("select"); + return -1; + } + + return 0; +} + +void readline(char *p) +{ + char *q = p; + do { + uart_recv(serial_fd, (uint8_t *)q, sizeof(uint8_t)); + } while (*q++ != '\n'); + *q = '\0'; +} + +void write_cmd(cmd_t cmd) +{ + uart_send(serial_fd, (uint8_t *)&cmd, sizeof(cmd)); +} + +size_t write_block(int serial_fd, char *buf) +{ + size_t retry = -1; + char cmd = NAK; + + // calculate crc + uint16_t crc_exp = crc16((uint8_t *)buf); + do { + retry++; + // send file and crc + uart_send(serial_fd, (uint8_t *)buf, CRC16_LEN); + uart_send(serial_fd, (uint8_t *)&crc_exp, 2); + // ACK/NAK + uart_recv(serial_fd, (uint8_t *)&cmd, sizeof(char)); + } while (cmd != ACK); + + return retry; +} + +char bar[101]; + +void update_progress(char *bar, uint8_t p){ + + bar[p] = '#'; + bar[p + 1] = '\0'; + + printf("send blocks: [%-100s][%3d%%]\r", bar, p); +} + +size_t write_batch(int serial_id, char *buf, size_t num_blocks){ + + size_t retry = 0; + + for (size_t i = 0; i < num_blocks; i++) { + retry += write_block(serial_fd, buf + i * CRC16_LEN); + update_progress(bar, i * 100 / num_blocks); + } + + printf("\n"); + + return retry; +} + +void write_header(uint8_t *addr, long len) +{ + // send metadata + package_t package; + package.addr = addr; + package.len = len; + + uart_send(serial_fd, (uint8_t *)&package, sizeof(package)); +} + +void write_file(FILE *fd) +{ + // send file + size_t n_blocks = 0; + size_t n_bytes = 0; + size_t size; + size_t retry = 0; + + char *buf = (char *)malloc(sizeof(char) * CRC16_LEN * NUM_BLOCKS); + + do { + size = fread(buf, CRC16_LEN, NUM_BLOCKS, fd); + if (size == -1) { + perror("read"); + exit(1); + } + if (size > 0) { + retry += write_batch(serial_fd, buf, size); + n_blocks += size; + n_bytes += size * CRC16_LEN; + printf("send %5ld blocks, retry %5ld times.\n", size, retry); + } + } while (size != 0); + + if (size == 0) { + memset(buf, 0, CRC16_LEN * NUM_BLOCKS); + fseek(fd, CRC16_LEN * n_blocks, SEEK_SET); + size = fread(buf, sizeof(char), CRC16_LEN, fd); + if (size == -1) { + perror("read"); + exit(1); + } + if (size > 0) { + retry += write_block(serial_fd, buf); + n_blocks += 1; + n_bytes += size; + printf("send %ld bytes, retry %ld times.\n", size, retry); + } + } + free(buf); + + printf("send %ld blocks, %ld bytes, retry %ld times in total\n", n_blocks, n_bytes, retry); +} + +int send_file(char *address, char *filename) +{ + FILE *fd = fopen(filename, "r"); + + if (fd == NULL) { + printf("open file failed.\n"); + perror("open"); + return -1; + } + + printf("open file successfully.\n"); + + // get file len + long len; + fseek(fd, 0L, SEEK_END); + len = ftell(fd); + fseek(fd, 0L, SEEK_SET); + + printf("file len: %ld\n", len); + + // parse address + uint8_t *addr; + sscanf(address, "%p", &addr); + printf("start transfer at addr[%p].\n", addr); + + // send cmd, header and file + write_cmd(UART_CMD_TRANSFER); + write_header(addr, len); + write_file(fd); + + fclose(fd); + + return 0; +} + +char msg[256]; + +int main(int argc, char *argv[]) +{ + for (int i = 0; i < argc; i++) + printf("argv[%d]: %s\n", i, argv[i]); + + // init connection + if (init_serial(argv[1]) != 0) { + printf("open serial failed.\n"); + exit(-1); + } + printf("open serial successfully.\n"); + + if (argc == 4) { + // ./serial tty, address, filename + send_file(argv[2], argv[3]); + printf("transfer finished.\n"); + } else if (argc == 3) { + // read message + printf("reading message.\n"); + readline(msg); + printf("%s\n", msg); + } else { + // ./serial tty + write_cmd(UART_CMD_END); + while (1) { + readline(msg); + printf("%s", msg); + } + } + + close(serial_fd); + + return 0; +} diff --git a/fpga/src/main/resources/vc709/uartsend/serial.o b/fpga/src/main/resources/vc709/uartsend/serial.o new file mode 100644 index 0000000000000000000000000000000000000000..45d6b8949e9685486b9b00ed3c1c61675d0cf10e GIT binary patch literal 9128 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freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} +import freechips.rocketchip.tile.{XLen} + +import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} +import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} + +import sifive.fpgashells.shell.{DesignKey} +import sifive.fpgashells.shell.xilinx.{VC709ShellPMOD, VC709DDRSize} + +import testchipip.{SerialTLKey} + +import chipyard.{BuildSystem, ExtTLMem} +import chipyard.fpga.vcu118.{WithUARTIOPassthrough, WithSPIIOPassthrough, WithTLIOPassthrough} + +class WithDefaultPeripherals extends Config((site, here, up) => { + case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) +}) + +class WithSystemModifications extends Config((site, here, up) => { + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) + case DTSTimebase => BigInt(1000000) + case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => + // invoke makefile for uart boot + val freqMHz = site(FPGAFrequencyKey).toInt * 1000000 + val make = s"make -C fpga/src/main/resources/vc709/uartboot PBUS_CLK=${freqMHz} bin" + require (make.! == 0, "Failed to build bootrom") + p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc709/uartboot/build/bootrom.bin") + } + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC709DDRSize)))) // set extmem to DDR size + case SerialTLKey => None // remove serialized tl port +}) + +// DOC include start: AbstractVC709 and Rocket +class WithVC709Tweaks extends Config( + new WithUART ++ + new WithDDRMem ++ + new WithUARTIOPassthrough ++ + new WithTLIOPassthrough ++ + new WithDefaultPeripherals ++ + new chipyard.config.WithTLBackingMemory ++ // use TL backing memory + new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size + new chipyard.config.WithNoDebug ++ // remove debug module + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) + +class RocketVC709Config extends Config( + new WithVC709Tweaks ++ + new chipyard.RocketConfig) +// DOC include end: AbstractVC709 and Rocket + +class BoomVC709Config extends Config( + new WithFPGAFrequency(50) ++ + new WithVC709Tweaks ++ + new chipyard.MegaBoomConfig) + +class WithFPGAFrequency(MHz: Double) extends Config((site, here, up) => { + case FPGAFrequencyKey => MHz +}) + +class WithFPGAFreq25MHz extends WithFPGAFrequency(25) +class WithFPGAFreq50MHz extends WithFPGAFrequency(50) +class WithFPGAFreq75MHz extends WithFPGAFrequency(75) +class WithFPGAFreq100MHz extends WithFPGAFrequency(100) +class WithFPGAFreq25MHz extends WithDevKitFrequency(125) +class WithFPGAFreq150MHz extends WithDevKitFrequency(150) +class WithFPGAFreq200MHz extends WithDevKitFrequency(200) diff --git a/fpga/src/main/scala/vc709/CustomOverlays.scala b/fpga/src/main/scala/vc709/CustomOverlays.scala new file mode 100644 index 0000000000..2c9b6a2c19 --- /dev/null +++ b/fpga/src/main/scala/vc709/CustomOverlays.scala @@ -0,0 +1,89 @@ +package chipyard.fpga.vc709 + +import chisel3._ + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} + +import sifive.fpgashells.shell._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.clocks._ +import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVC709MIGPads, XilinxVC709MIGParams, XilinxVC709MIG} + +case object VC709DDR3Size extends Field[BigInt](0x100000000L) // 4GB +class DualDDR3VC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput) + extends DDRPlacedOverlay[XilinxVC709MIGPads](name, designInput, shellInput) +{ + val size = p(VC709DDR3Size) + + val migParams = XilinxVC709MIGParams(address = AddressSet.misaligned(di.baseAddress, size)) + val mig = LazyModule(new XilinxVC709MIG(migParams)) + val ioNode = BundleBridgeSource(() => mig.module.io.cloneType) + val topIONode = shell { ioNode.makeSink() } + val ddrUI = shell { ClockSourceNode(freqMHz = 200) } + val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } + areset := designInput.wrangler := ddrUI + + // since this uses a separate clk/rst need to put an async crossing + val asyncSink = LazyModule(new TLAsyncCrossingSink()) + val migClkRstNode = BundleBridgeSource(() => new Bundle { + val clock = Output(Clock()) + val reset = Output(Bool()) + }) + val topMigClkRstIONode = shell { migClkRstNode.makeSink() } + + def overlayOutput = DDROverlayOutput(ddr = mig.node) + def ioFactory = new XilinxVC709MIGPads(size) + + InModuleBody { + ioNode.bundle <> mig.module.io + + // setup async crossing + asyncSink.module.clock := migClkRstNode.bundle.clock + asyncSink.module.reset := migClkRstNode.bundle.reset + } + + shell { InModuleBody { + require (shell.sys_clock.get.isDefined, "Use of DDRVC709Overlay depends on SysClockVC709PlacedOverlay") + val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0) + val (ui, _) = ddrUI.out(0) + val (ar, _) = areset.in(0) + + // connect the async fifo sync to sys_clock + topMigClkRstIONode.bundle.clock := sys.clock + topMigClkRstIONode.bundle.reset := sys.reset + + val port = topIONode.bundle.port + io <> port + // This is modified for vc709 + ui.clock := port.ui_clk + ui.reset := !port.mmcm_locked || port.ui_clk_sync_rst + port.sys_clk_i = sys.clock.asUInt + port.sys_rst = sys.reset // pllReset + port.aresetn := !ar.reset + + // The pins for Dual DDR3 on vc709 board are emitted in the following order: + // addr[0->15], ba[0-2], ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt, dm[0->7], dq[0->63], dqs_n[0->7], dqs_p[0->7] + val allddrpins = Seq( + "AN19", "AR19", "AP20", "AP17", "AP18", "AJ18", "AN16", "AM16", "AK18", "AK19", "AM17", "AM18", "AL17", "AK17", "AM19", "AL19", // addr[0->15] + "AR17", "AR18", "AN18", // ba[0->2] + "AV19", "AT20", "AU19", "BB19", "AT17", "AU17", "AW17", "AV16", "AT16", // ctrl: ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt + "AT22", "AL22", "AU24", "BB23", "BB12", "AV15", "AK12", "AP13", // dm [0->7] + "AN24", "AM24", "AR22", "AR23", "AN23", "AM23", "AN21", "AP21", "AK23", "AJ23", "AL21", "AM21", "AJ21", "AJ20", "AK20", "AL20", // dq[0->15] + "AW22", "AW23", "AW21", "AV21", "AU23", "AV23", "AR24", "AT24", "BB24", "BA24", "AY23", "AY24", "AY25", "BA25", "BB21", "BA21", // dq[16->31] + "AY14", "AW15", "BB14", "BB13", "AW12", "AY13", "AY12", "BA12", "AU12", "AU13", "AT12", "AU14", "AV13", "AW13", "AT15", "AR15", // dq[32->47] + "AL15", "AJ15", "AK14", "AJ12", "AJ16", "AL16", "AJ13", "AK13", "AR14", "AT14", "AM12", "AP11", "AM13", "AN13", "AM11", "AN11", // dq[48->63] + "AP22", "AK22", "AU21", "BB22", "BA14", "AR12", "AL14", "AN14", // dqs_n[0->7] + "AP23", "AJ22", "AT21", "BA22", "BA15", "AP12", "AK15", "AN15") // dqs_p[0->7] + + (IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } + } } + + shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) +} +class DualDDR3VC709ShellPlacer(shell: VC709Shell, val shellInput: DDRShellInput)(implicit val valName: ValName) + extends DDRShellPlacer[VC709Shell] { + def place(designInput: DDRDesignInput) = new DualDDR3VC709PlacedOverlay(shell, valName.name, designInput, shellInput) +} \ No newline at end of file diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala new file mode 100644 index 0000000000..90afada3c1 --- /dev/null +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -0,0 +1,134 @@ +package chipyard.fpga.vc709 + +import chisel3._ +import chisel3.experimental.{IO} + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.tilelink._ + +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell._ +import sifive.fpgashells.clocks._ + +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.gpio._ + +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort} +import chipyard.iobinders.{HasIOBinders} +import chipyard.harness.{ApplyHarnessBinders} + +case object FPGAFrequencyKey extends Field[Double](100.0) + +class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709Shell { + + def dp = designParameters + +// Now we removed jtag, cjtag, pcie-fmc, pcie-edge + // val pmod_is_sdio = p(VC709ShellPMOD) == "SDIO" + // val jtag_location = Some(if (pmod_is_sdio) "FMC_J2" else "PMOD_J52") + + // Order matters; ddr depends on sys_clock + // val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput(location = jtag_location))) + // val cjtag = Overlay(cJTAGDebugOverlayKey, new cJTAGDebugVC709ShellPlacer(this, cJTAGDebugShellInput())) + // val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVC709ShellPlacer(this, JTAGDebugBScanShellInput())) + // val fmc = Overlay(PCIeOverlayKey, new PCIeVC709FMCShellPlacer(this, PCIeShellInput())) + // val edge = Overlay(PCIeOverlayKey, new PCIeVC709EdgeShellPlacer(this, PCIeShellInput())) + + val uart = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC709ShellPlacer(this, UARTShellInput(index = 0)))) + val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput())) + val pcie = Overlay(PCIeOverlayKey, new PCIeVC709ShellPlacer(this, PCIeShellInput())) + val ddr1 = Overlay(DDROverlayKey, new DualDDR3VC709ShellPlacer(this, DDRShellInput())) + + val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") + +// DOC include start: ClockOverlay + // place all clocks in the shell + require(dp(ClockInputOverlayKey).size >= 1) + val sysClkNode = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()).overlayOutput.node + + /*** Connect/Generate clocks ***/ + + // connect to the PLL that will generate multiple clocks + val harnessSysPLL = dp(PLLFactoryKey)() + harnessSysPLL := sysClkNode + + // create and connect to the dutClock + val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + val dutWrangler = LazyModule(new ResetWrangler) + val dutGroup = ClockGroup() + dutClock := dutWrangler.node := dutGroup := harnessSysPLL +// DOC include end: ClockOverlay + + /*** UART ***/ + +// DOC include start: UartOverlay + // 1st UART goes to the VC709 dedicated UART + + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) + dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) +// DOC include end: UartOverlay + + /*** DDR ***/ + + val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr + + // connect 1 mem. channel to the FPGA DDR + val inParams = topDesign match { case td: ChipTop => + td.lazySystem match { case lsys: CanHaveMasterTLMemPort => + lsys.memTLNode.edges.in(0) + } + } + val ddrClient = TLClientNode(Seq(inParams.master)) + ddrNode := ddrClient + + // module implementation + override lazy val module = new VC709FPGATestHarnessImp(this) +} + +class VC709FPGATestHarnessImp(_outer: VC709FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { + + val VC709Outer = _outer + + val reset = IO(Input(Bool())) + _outer.xdc.addPackagePin(reset, "AV40") + _outer.xdc.addIOStandard(reset, "LVCMOS18") + + val resetIBUF = Module(new IBUF) + resetIBUF.io.I := reset + + val sysclk: Clock = _outer.sysClkNode.out.head._1.clock + + val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) + _outer.sdc.addAsyncPath(Seq(powerOnReset)) + + // val ereset: Bool = _outer.chiplink.get() match { + // case Some(x: ChipLinkVC709PlacedOverlay) => !x.ereset_n + // case _ => false.B + // } + + _outer.pllReset := (resetIBUF.io.O || powerOnReset || false.B) + + // reset setup + val hReset = Wire(Reset()) + hReset := _outer.dutClock.in.head._1.reset + + val harnessClock = _outer.dutClock.in.head._1.clock + val harnessReset = WireInit(hReset) + val dutReset = hReset.asAsyncReset + val success = false.B + + childClock := harnessClock + childReset := harnessReset + + // harness binders are non-lazy + _outer.topDesign match { case d: HasTestHarnessFunctions => + d.harnessFunctions.foreach(_(this)) + } + _outer.topDesign match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) + } +} From 7888b11dba41af32aaa940c298524983a9a4cd6c Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Mon, 1 Feb 2021 23:38:49 +0800 Subject: [PATCH 02/27] update support for vc709 --- fpga/Makefile | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/fpga/Makefile b/fpga/Makefile index 1437d8bc76..6bbb6d6ca1 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -59,6 +59,20 @@ ifeq ($(SUB_PROJECT),arty) FPGA_BRAND ?= xilinx endif +ifeq ($(SUB_PROJECT),vc709) + SBT_PROJECT ?= fpga_platforms + MODEL ?= VC709FPGATestHarness + VLOG_MODEL ?= VC709FPGATestHarness + MODEL_PACKAGE ?= chipyard.fpga.vc709 + CONFIG ?= BoomVC709Config + CONFIG_PACKAGE ?= chipyard.fpga.vc709 + GENERATOR_PACKAGE ?= chipyard + TB ?= none # unused + TOP ?= ChipTop + BOARD ?= vc709 + FPGA_BRAND ?= xilinx +endif + include $(base_dir)/variables.mk # default variables to build the arty example From 98bb00f183f7e66c28bdc26cc615feeb1b3adebc Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Tue, 2 Feb 2021 00:03:21 +0800 Subject: [PATCH 03/27] add support for vc709 modified: fpga/src/main/scala/vc709/Configs.scala modified: fpga/src/main/scala/vc709/TestHarness.scala modified: fpga/fpga-shells (new commits, modified content) modified: generators/rocket-chip (new commits) --- fpga/src/main/scala/vc709/Configs.scala | 3 ++- fpga/src/main/scala/vc709/TestHarness.scala | 10 +++++----- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index 7dfe5abb3a..0c0c656e92 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -18,10 +18,11 @@ import sifive.fpgashells.shell.xilinx.{VC709ShellPMOD, VC709DDRSize} import testchipip.{SerialTLKey} import chipyard.{BuildSystem, ExtTLMem} -import chipyard.fpga.vcu118.{WithUARTIOPassthrough, WithSPIIOPassthrough, WithTLIOPassthrough} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) + // case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L))) + // case VC709ShellPMOD => "SDIO" }) class WithSystemModifications extends Config((site, here, up) => { diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala index 90afada3c1..7b440529ce 100644 --- a/fpga/src/main/scala/vc709/TestHarness.scala +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -39,7 +39,7 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She // val edge = Overlay(PCIeOverlayKey, new PCIeVC709EdgeShellPlacer(this, PCIeShellInput())) val uart = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC709ShellPlacer(this, UARTShellInput(index = 0)))) - val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput())) + // val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput())) val pcie = Overlay(PCIeOverlayKey, new PCIeVC709ShellPlacer(this, PCIeShellInput())) val ddr1 = Overlay(DDROverlayKey, new DualDDR3VC709ShellPlacer(this, DDRShellInput())) @@ -105,10 +105,10 @@ class VC709FPGATestHarnessImp(_outer: VC709FPGATestHarness) extends LazyRawModul val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) _outer.sdc.addAsyncPath(Seq(powerOnReset)) - // val ereset: Bool = _outer.chiplink.get() match { - // case Some(x: ChipLinkVC709PlacedOverlay) => !x.ereset_n - // case _ => false.B - // } + val ereset: Bool = _outer.chiplink.get() match { + case Some(x: ChipLinkVC709PlacedOverlay) => !x.ereset_n + case _ => false.B + } _outer.pllReset := (resetIBUF.io.O || powerOnReset || false.B) From e6f4528fa3327e1f5c5035d411e5cf35ae8b4e25 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Tue, 2 Feb 2021 13:14:35 +0800 Subject: [PATCH 04/27] update support for vc709 --- fpga/src/main/scala/vc709/Configs.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index 0c0c656e92..6810822c1e 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -19,6 +19,8 @@ import testchipip.{SerialTLKey} import chipyard.{BuildSystem, ExtTLMem} +import chipyard.fpga.vcu118.{WithUARTIOPassthrough, WithTLIOPassthrough} + class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) // case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L))) From aed1f14924c8227997722ba0a889314a80855933 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Wed, 3 Feb 2021 11:31:14 +0800 Subject: [PATCH 05/27] add support for vc709 board modified: src/main/resources/vc709/uartboot/head.S modified: src/main/resources/vc709/uartboot/linker/bootrom.elf.lds modified: src/main/resources/vc709/uartboot/linker/memory.lds modified: src/main/scala/vc709/Configs.scala modified: src/main/scala/vc709/CustomOverlays.scala modified: src/main/scala/vc709/TestHarness.scala --- fpga/Makefile | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/fpga/Makefile b/fpga/Makefile index 6bbb6d6ca1..5450643f2d 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -85,6 +85,7 @@ default: $(mcs) # misc. directories ######################################################################################### fpga_dir := $(base_dir)/fpga/fpga-shells/$(FPGA_BRAND) +fpga_board_script_dir := $(fpga_dir)/$(BOARD)/tcl fpga_common_script_dir := $(fpga_dir)/common/tcl ######################################################################################### @@ -134,6 +135,16 @@ debug-bitstream: $(build_dir)/obj/post_synth.dcp $(build_dir)/debug_obj \ $(fpga_common_script_dir) +MCS_FILE := $(build_dir)/obj/$(MODEL).mcs +$(MCS_FILE): $(BIT_FILE) + cd $(build_dir); vivado \ + -nojournal -mode batch \ + -source $(fpga_common_script_dir)/write_cfgmem.tcl \ + -tclargs $(BOARD) $@ $^ \ + +.PHONY: mcs +mcs: $(MCS_FILE) + ######################################################################################### # general cleanup rules ######################################################################################### From 9ea9c18b23d2064ad374a0859c7add4c7aaca6ca Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Fri, 5 Feb 2021 18:36:15 +0800 Subject: [PATCH 06/27] add support for dual memory channels modified: src/main/scala/vc709/Configs.scala modified: src/main/scala/vc709/CustomOverlays.scala new file: src/main/scala/vc709/HarnessBinders.scala modified: src/main/scala/vc709/TestHarness.scala modified: Makefile deleted: src/main/resources/vc709/uartboot/crc16.o modified: src/main/resources/vc709/uartboot/head.S modified: src/main/resources/vc709/uartboot/linker/bootrom.elf.lds modified: src/main/resources/vc709/uartboot/linker/memory.lds --- fpga/src/main/scala/vc709/Configs.scala | 23 ++---- .../src/main/scala/vc709/CustomOverlays.scala | 76 ++++++------------- .../src/main/scala/vc709/HarnessBinders.scala | 41 ++++++++++ fpga/src/main/scala/vc709/TestHarness.scala | 66 ++++++++++------ 4 files changed, 112 insertions(+), 94 deletions(-) create mode 100644 fpga/src/main/scala/vc709/HarnessBinders.scala diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index 6810822c1e..ed467d8dc6 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -13,13 +13,14 @@ import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} -import sifive.fpgashells.shell.xilinx.{VC709ShellPMOD, VC709DDRSize} +import sifive.fpgashells.shell.xilinx.{VC709DDR3Size} import testchipip.{SerialTLKey} -import chipyard.{BuildSystem, ExtTLMem} +import chipyard.{BuildSystem, ExtTLMem} + +import chipyard.fpga.vcu118.{WithUARTIOPassthrough, WithTLIOPassthrough, WithFPGAFrequency} -import chipyard.fpga.vcu118.{WithUARTIOPassthrough, WithTLIOPassthrough} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) @@ -37,7 +38,7 @@ class WithSystemModifications extends Config((site, here, up) => { require (make.! == 0, "Failed to build bootrom") p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc709/uartboot/build/bootrom.bin") } - case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC709DDRSize)))) // set extmem to DDR size + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC709DDR3Size)))) // set extmem to DDR size case SerialTLKey => None // remove serialized tl port }) @@ -62,16 +63,4 @@ class RocketVC709Config extends Config( class BoomVC709Config extends Config( new WithFPGAFrequency(50) ++ new WithVC709Tweaks ++ - new chipyard.MegaBoomConfig) - -class WithFPGAFrequency(MHz: Double) extends Config((site, here, up) => { - case FPGAFrequencyKey => MHz -}) - -class WithFPGAFreq25MHz extends WithFPGAFrequency(25) -class WithFPGAFreq50MHz extends WithFPGAFrequency(50) -class WithFPGAFreq75MHz extends WithFPGAFrequency(75) -class WithFPGAFreq100MHz extends WithFPGAFrequency(100) -class WithFPGAFreq25MHz extends WithDevKitFrequency(125) -class WithFPGAFreq150MHz extends WithDevKitFrequency(150) -class WithFPGAFreq200MHz extends WithDevKitFrequency(200) + new chipyard.DualSmallBoomConfig) \ No newline at end of file diff --git a/fpga/src/main/scala/vc709/CustomOverlays.scala b/fpga/src/main/scala/vc709/CustomOverlays.scala index 2c9b6a2c19..650f5562de 100644 --- a/fpga/src/main/scala/vc709/CustomOverlays.scala +++ b/fpga/src/main/scala/vc709/CustomOverlays.scala @@ -10,60 +10,31 @@ import sifive.fpgashells.shell._ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.clocks._ -import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVC709MIGPads, XilinxVC709MIGParams, XilinxVC709MIG} +import sifive.fpgashells.devices.xilinx.xilinxvc709mig.{XilinxVC709MIGPads, XilinxVC709MIGParams, XilinxVC709MIG} -case object VC709DDR3Size extends Field[BigInt](0x100000000L) // 4GB -class DualDDR3VC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput) - extends DDRPlacedOverlay[XilinxVC709MIGPads](name, designInput, shellInput) +class MemClockVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput) + extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput) { - val size = p(VC709DDR3Size) - - val migParams = XilinxVC709MIGParams(address = AddressSet.misaligned(di.baseAddress, size)) - val mig = LazyModule(new XilinxVC709MIG(migParams)) - val ioNode = BundleBridgeSource(() => mig.module.io.cloneType) - val topIONode = shell { ioNode.makeSink() } - val ddrUI = shell { ClockSourceNode(freqMHz = 200) } - val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } - areset := designInput.wrangler := ddrUI - - // since this uses a separate clk/rst need to put an async crossing - val asyncSink = LazyModule(new TLAsyncCrossingSink()) - val migClkRstNode = BundleBridgeSource(() => new Bundle { - val clock = Output(Clock()) - val reset = Output(Bool()) - }) - val topMigClkRstIONode = shell { migClkRstNode.makeSink() } - - def overlayOutput = DDROverlayOutput(ddr = mig.node) - def ioFactory = new XilinxVC709MIGPads(size) - - InModuleBody { - ioNode.bundle <> mig.module.io - - // setup async crossing - asyncSink.module.clock := migClkRstNode.bundle.clock - asyncSink.module.reset := migClkRstNode.bundle.reset - } + val node = shell { ClockSourceNode(freqMHz = 233.3333, jitterPS = 50)(ValName(name)) } shell { InModuleBody { - require (shell.sys_clock.get.isDefined, "Use of DDRVC709Overlay depends on SysClockVC709PlacedOverlay") - val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0) - val (ui, _) = ddrUI.out(0) - val (ar, _) = areset.in(0) - - // connect the async fifo sync to sys_clock - topMigClkRstIONode.bundle.clock := sys.clock - topMigClkRstIONode.bundle.reset := sys.reset - - val port = topIONode.bundle.port - io <> port - // This is modified for vc709 - ui.clock := port.ui_clk - ui.reset := !port.mmcm_locked || port.ui_clk_sync_rst - port.sys_clk_i = sys.clock.asUInt - port.sys_rst = sys.reset // pllReset - port.aresetn := !ar.reset + shell.xdc.addPackagePin(io.p, "AY18") + shell.xdc.addPackagePin(io.n, "AY17") + shell.xdc.addIOStandard(io.p, "DIFF_SSTL15_DCI") + shell.xdc.addIOStandard(io.n, "DIFF_SSTL15_DCI") + } } +} +class MemClockVC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: ClockInputShellInput)(implicit val valName: ValName) + extends ClockInputShellPlacer[VC709ShellBasicOverlays] +{ + def place(designInput: ClockInputDesignInput) = new MemClockVC709PlacedOverlay(shell, valName.name, designInput, shellInput) +} +// case object VC709DDR3Size extends Field[BigInt](0x100000000L) // 4GB +class DualDDR3VC709PlacedOverlay(val shell: VC709FPGATestHarness, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput) + extends DDR3XilinxPlacedOverlay(shell, name, designInput, shellInput) +{ + shell { InModuleBody { // The pins for Dual DDR3 on vc709 board are emitted in the following order: // addr[0->15], ba[0-2], ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt, dm[0->7], dq[0->63], dqs_n[0->7], dqs_p[0->7] val allddrpins = Seq( @@ -78,12 +49,13 @@ class DualDDR3VC709PlacedOverlay(val shell: VC709Shell, name: String, val design "AP22", "AK22", "AU21", "BB22", "BA14", "AR12", "AL14", "AN14", // dqs_n[0->7] "AP23", "AJ22", "AT21", "BA22", "BA15", "AP12", "AK15", "AN15") // dqs_p[0->7] + IOPin.of(io).foreach { shell.xdc.addPackagePin(_, "") } (IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } } } - shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) + shell.sdc.addGroup(clocks = Seq("ui_clk1"), pins = Seq(mig.island.module.blackbox.io.ui_clk)) } -class DualDDR3VC709ShellPlacer(shell: VC709Shell, val shellInput: DDRShellInput)(implicit val valName: ValName) - extends DDRShellPlacer[VC709Shell] { +class DualDDR3VC709ShellPlacer(shell: VC709FPGATestHarness, val shellInput: DDRShellInput)(implicit val valName: ValName) + extends DDRShellPlacer[VC709FPGATestHarness] { def place(designInput: DDRDesignInput) = new DualDDR3VC709PlacedOverlay(shell, valName.name, designInput, shellInput) } \ No newline at end of file diff --git a/fpga/src/main/scala/vc709/HarnessBinders.scala b/fpga/src/main/scala/vc709/HarnessBinders.scala new file mode 100644 index 0000000000..c62e322a29 --- /dev/null +++ b/fpga/src/main/scala/vc709/HarnessBinders.scala @@ -0,0 +1,41 @@ +package chipyard.fpga.vc709 + +import chisel3._ +import chisel3.experimental.{BaseModule} + +import freechips.rocketchip.diplomacy.{NodeHandlePair} +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + +import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} +import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} + +import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} +import chipyard.harness.{OverrideHarnessBinder} + +/*** UART ***/ +class WithUART extends OverrideHarnessBinder({ + (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + th match { case vc709th: VC709FPGATestHarnessImp => { + // println("WithUART:ports.size = " + ports.size) + val io_uart_bb_s = vc709th.vc709Outer.io_uart_bb_s + (io_uart_bb_s zip ports).map { case (io_uart_bb, port) => io_uart_bb.bundle <> port } + } } + } +}) + +/*** Experimental DDR ***/ +class WithDDRMem extends OverrideHarnessBinder({ + (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { + th match { case vc709th: VC709FPGATestHarnessImp => { + require(ports.size > 0, "There must be at least one port.") // all ports go to the TL mem + + (vc709th.vc709Outer.ddrClients zip ports).map({ case (ddrClient, port) => + val bundles = ddrClient.out.map(_._1) + val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType))) + bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } + ddrClientBundle <> port + }) + } } + } +}) diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala index 7b440529ce..2dd8f1c44f 100644 --- a/fpga/src/main/scala/vc709/TestHarness.scala +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -23,25 +23,17 @@ import chipyard.harness.{ApplyHarnessBinders} case object FPGAFrequencyKey extends Field[Double](100.0) -class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709Shell { +class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709ShellBasicOverlays { def dp = designParameters -// Now we removed jtag, cjtag, pcie-fmc, pcie-edge - // val pmod_is_sdio = p(VC709ShellPMOD) == "SDIO" - // val jtag_location = Some(if (pmod_is_sdio) "FMC_J2" else "PMOD_J52") - // Order matters; ddr depends on sys_clock - // val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput(location = jtag_location))) // val cjtag = Overlay(cJTAGDebugOverlayKey, new cJTAGDebugVC709ShellPlacer(this, cJTAGDebugShellInput())) // val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVC709ShellPlacer(this, JTAGDebugBScanShellInput())) // val fmc = Overlay(PCIeOverlayKey, new PCIeVC709FMCShellPlacer(this, PCIeShellInput())) // val edge = Overlay(PCIeOverlayKey, new PCIeVC709EdgeShellPlacer(this, PCIeShellInput())) - - val uart = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC709ShellPlacer(this, UARTShellInput(index = 0)))) - // val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput())) - val pcie = Overlay(PCIeOverlayKey, new PCIeVC709ShellPlacer(this, PCIeShellInput())) - val ddr1 = Overlay(DDROverlayKey, new DualDDR3VC709ShellPlacer(this, DDRShellInput())) + // val mem_clock = Overlay(ClockInputOverlayKey, new MemClockVC709ShellPlacer(this, ClockInputShellInput())) + // val ddr1 = Overlay(DDROverlayKey, new DualDDR3VC709ShellPlacer(this, DDRShellInput())) val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") @@ -66,24 +58,48 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She /*** UART ***/ // DOC include start: UartOverlay - // 1st UART goes to the VC709 dedicated UART - - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) - dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) + // All UART goes to the VC709 dedicated UART + val io_uart_bb_s = (dp(UARTOverlayKey) zip dp(PeripheryUARTKey)).map { + case (uartOverlayKey, peripheryUARTKey) => + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(peripheryUARTKey))) + uartOverlayKey.place(UARTDesignInput(io_uart_bb)) + io_uart_bb + } // DOC include end: UartOverlay /*** DDR ***/ - - val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr - - // connect 1 mem. channel to the FPGA DDR - val inParams = topDesign match { case td: ChipTop => - td.lazySystem match { case lsys: CanHaveMasterTLMemPort => - lsys.memTLNode.edges.in(0) +// DOC include start: DDR3Overlay + val ddrDesignInput = DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL) + // connect all mem. channels to the FPGA DDR + val (ddrNodes, ddrClients) = topDesign match { + case td: ChipTop => td.lazySystem match { + case lsys: CanHaveMasterTLMemPort => { + (dp(DDROverlayKey) zip lsys.memTLNode.edges.in).map { case (ddrOverlayKey, inParams) => + val ddrNode = ddrOverlayKey.place(ddrDesignInput).overlayOutput.ddr + val ddrClient = TLClientNode(Seq(inParams.master)) + ddrNode := ddrClient + (ddrNode, ddrClient) + }.unzip + } } } - val ddrClient = TLClientNode(Seq(inParams.master)) - ddrNode := ddrClient + println("ddrNodes: " + ddrNodes.toString()) + println("ddrClients: " + ddrClients.toString()) +// DOC include end: DDR3Overlay + + /*** PCIe ***/ + // hook the first PCIe the board has + // dp(PCIeOverlayKey) foreach { case key => { + // val pcies = key.place(PCIeDesignInput(wrangler=dutWrangler.node, corePLL=harnessSysPLL)).overlayOutput + // pcies match { case (pcieNode, pcieInt) => { + // val pciename = Some(s"pcie_$i") + // sbus.fromMaster(pciename) { pcieNode } + // sbus.toFixedWidthSlave(pciename) { pcieNode } + // ibus.fromSync := pcieInt + // println(pciename) + // } } + // } + // } // module implementation override lazy val module = new VC709FPGATestHarnessImp(this) @@ -91,7 +107,7 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She class VC709FPGATestHarnessImp(_outer: VC709FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { - val VC709Outer = _outer + val vc709Outer = _outer val reset = IO(Input(Bool())) _outer.xdc.addPackagePin(reset, "AV40") From a09bb6f7ef73304fc7ffc40dbfbce2bbb9f5b74a Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Thu, 4 Mar 2021 16:02:28 +0800 Subject: [PATCH 07/27] support DDR3 dual memory channels for vc709 --- fpga/Makefile | 2 +- fpga/src/main/resources/vc709/uartboot/head.S | 12 +-- .../vc709/uartboot/linker/bootrom.elf.lds | 23 ++--- .../vc709/uartboot/linker/memory.lds | 13 +-- fpga/src/main/scala/vc709/Configs.scala | 4 +- .../src/main/scala/vc709/CustomOverlays.scala | 50 +++++++---- .../src/main/scala/vc709/HarnessBinders.scala | 16 ++-- fpga/src/main/scala/vc709/TestHarness.scala | 83 ++++++++++--------- 8 files changed, 106 insertions(+), 97 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index 5450643f2d..f820355b7b 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -64,7 +64,7 @@ ifeq ($(SUB_PROJECT),vc709) MODEL ?= VC709FPGATestHarness VLOG_MODEL ?= VC709FPGATestHarness MODEL_PACKAGE ?= chipyard.fpga.vc709 - CONFIG ?= BoomVC709Config + CONFIG ?= RocketVC709Config CONFIG_PACKAGE ?= chipyard.fpga.vc709 GENERATOR_PACKAGE ?= chipyard TB ?= none # unused diff --git a/fpga/src/main/resources/vc709/uartboot/head.S b/fpga/src/main/resources/vc709/uartboot/head.S index 14fa740476..c6653f7ceb 100644 --- a/fpga/src/main/resources/vc709/uartboot/head.S +++ b/fpga/src/main/resources/vc709/uartboot/head.S @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #include #include #include "common.h" @@ -8,14 +8,14 @@ .globl _prog_start _prog_start: smp_pause(s1, s2) - li sp, (PAYLOAD_DEST + 0x7fff000) + li sp, (PAYLOAD_DEST + 0xffff000) call main smp_resume(s1, s2) - csrr a0, mhartid - la a1, dtb + csrr a0, mhartid // hartid for next level bootloader + la a1, dtb // dtb address for next level bootloader li s1, PAYLOAD_DEST jr s1 - .section .rodata + .section .dtb + .align 3 dtb: - .incbin DEVICE_TREE diff --git a/fpga/src/main/resources/vc709/uartboot/linker/bootrom.elf.lds b/fpga/src/main/resources/vc709/uartboot/linker/bootrom.elf.lds index deb76da9fd..6843436fae 100644 --- a/fpga/src/main/resources/vc709/uartboot/linker/bootrom.elf.lds +++ b/fpga/src/main/resources/vc709/uartboot/linker/bootrom.elf.lds @@ -15,39 +15,40 @@ SECTIONS PROVIDE(_ram = ORIGIN(memory_mem)); PROVIDE(_ram_end = _ram + LENGTH(memory_mem)); - .text ALIGN((ORIGIN(maskrom_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(maskrom_mem) + 0x0), 8)) { + .text ALIGN((ORIGIN(bootrom_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(bootrom_mem) + 0x0), 8)) { PROVIDE(_ftext = .); *(.text.init) *(.text.unlikely .text.unlikely.*) *(.text .text.* .gnu.linkonce.t.*) PROVIDE(_etext = .); . += 0x40; /* to create a gap between .text and .data b/c ifetch can fetch ahead from .data */ - } >maskrom_mem :text + } >bootrom_mem :text .eh_frame ALIGN((ADDR(.text) + SIZEOF(.text)), 8) : AT(ALIGN((LOADADDR(.text) + SIZEOF(.text)), 8)) { *(.eh_frame) - } >maskrom_mem :text + } >bootrom_mem :text - .rodata ALIGN((ADDR(.eh_frame) + SIZEOF(.eh_frame)), 8) : AT(ALIGN((LOADADDR(.eh_frame) + SIZEOF(.eh_frame)), 8)) ALIGN_WITH_INPUT { - *(.rodata .rodata.* .gnu.linkonce.r.*) - } >maskrom_mem :data - - .srodata ALIGN((ADDR(.rodata) + SIZEOF(.rodata)), 8) : AT(ALIGN((LOADADDR(.rodata) + SIZEOF(.rodata)), 8)) ALIGN_WITH_INPUT { + .srodata ALIGN((ADDR(.eh_frame) + SIZEOF(.eh_frame)), 8) : AT(ALIGN((LOADADDR(.eh_frame) + SIZEOF(.eh_frame)), 8)) ALIGN_WITH_INPUT { *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata.*) - } >maskrom_mem :data + } >bootrom_mem :data .data ALIGN((ADDR(.srodata) + SIZEOF(.srodata)), 8) : AT(ALIGN((LOADADDR(.srodata) + SIZEOF(.srodata)), 8)) ALIGN_WITH_INPUT { *(.data .data.* .gnu.linkonce.d.*) *(.tohost) /* TODO: Support sections that aren't explicitly listed in this linker script */ - } >maskrom_mem :data + } >bootrom_mem :data .sdata ALIGN((ADDR(.data) + SIZEOF(.data)), 8) : AT(ALIGN((LOADADDR(.data) + SIZEOF(.data)), 8)) ALIGN_WITH_INPUT { *(.sdata .sdata.* .gnu.linkonce.s.*) - } >maskrom_mem :data + } >bootrom_mem :data + + .rodata ALIGN((ADDR(.sdata) + SIZEOF(.sdata)), 8) : AT(ALIGN((LOADADDR(.sdata) + SIZEOF(.sdata)), 8)) ALIGN_WITH_INPUT { + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.dtb) /* Must be last if this code is added to RC's BootROM */ + } >bootrom_mem :data PROVIDE(_data = ADDR(.rodata)); PROVIDE(_data_lma = LOADADDR(.rodata)); diff --git a/fpga/src/main/resources/vc709/uartboot/linker/memory.lds b/fpga/src/main/resources/vc709/uartboot/linker/memory.lds index 7f6cfc9194..65737bb3c0 100644 --- a/fpga/src/main/resources/vc709/uartboot/linker/memory.lds +++ b/fpga/src/main/resources/vc709/uartboot/linker/memory.lds @@ -1,14 +1,5 @@ MEMORY { - debug_ctrl (rwx) : ORIGIN = 0x0, LENGTH = 0x1000 - error_mem (rw) : ORIGIN = 0x3000, LENGTH = 0x1000 - test_ctrl (rw) : ORIGIN = 0x4000, LENGTH = 0x1000 - maskrom_mem (rx) : ORIGIN = 0x10000, LENGTH = 0x2000 - clint_ctrl (rw) : ORIGIN = 0x2000000, LENGTH = 0x10000 - plic_ctrl (rw) : ORIGIN = 0xc000000, LENGTH = 0x4000000 - axi_pcie_host_1_00_a_ctrl (rw) : ORIGIN = 0x50000000, LENGTH = 0x4000000 - uart_ctrl (rw) : ORIGIN = 0x54000000, LENGTH = 0x1000 - spi_ctrl (rw) : ORIGIN = 0x54001000, LENGTH = 0x1000 - gpio_ctrl (rw) : ORIGIN = 0x54002000, LENGTH = 0x1000 + bootrom_mem (rx) : ORIGIN = 0x10000, LENGTH = 0x2000 memory_mem (rwx) : ORIGIN = 0x80000000, LENGTH = 0x40000000 -} +} \ No newline at end of file diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index ed467d8dc6..dadb09c3c2 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -53,7 +53,7 @@ class WithVC709Tweaks extends Config( new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) + new freechips.rocketchip.subsystem.WithNMemoryChannels(2)) class RocketVC709Config extends Config( new WithVC709Tweaks ++ @@ -63,4 +63,4 @@ class RocketVC709Config extends Config( class BoomVC709Config extends Config( new WithFPGAFrequency(50) ++ new WithVC709Tweaks ++ - new chipyard.DualSmallBoomConfig) \ No newline at end of file + new chipyard.DualSmallBoomConfig) diff --git a/fpga/src/main/scala/vc709/CustomOverlays.scala b/fpga/src/main/scala/vc709/CustomOverlays.scala index 650f5562de..e44d59b1c2 100644 --- a/fpga/src/main/scala/vc709/CustomOverlays.scala +++ b/fpga/src/main/scala/vc709/CustomOverlays.scala @@ -34,26 +34,42 @@ class MemClockVC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: C class DualDDR3VC709PlacedOverlay(val shell: VC709FPGATestHarness, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput) extends DDR3XilinxPlacedOverlay(shell, name, designInput, shellInput) { + // since this uses a separate clk/rst need to put an async crossing + val asyncSink = LazyModule(new TLAsyncCrossingSink()) + val migClkRstNode = BundleBridgeSource(() => new Bundle { + val clock = Output(Clock()) + val reset = Output(Bool()) + }) + val topMigClkRstIONode = shell { migClkRstNode.makeSink() } + + InModuleBody { + // setup async crossing + asyncSink.module.clock := migClkRstNode.bundle.clock + asyncSink.module.reset := migClkRstNode.bundle.reset + } + shell { InModuleBody { - // The pins for Dual DDR3 on vc709 board are emitted in the following order: - // addr[0->15], ba[0-2], ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt, dm[0->7], dq[0->63], dqs_n[0->7], dqs_p[0->7] - val allddrpins = Seq( - "AN19", "AR19", "AP20", "AP17", "AP18", "AJ18", "AN16", "AM16", "AK18", "AK19", "AM17", "AM18", "AL17", "AK17", "AM19", "AL19", // addr[0->15] - "AR17", "AR18", "AN18", // ba[0->2] - "AV19", "AT20", "AU19", "BB19", "AT17", "AU17", "AW17", "AV16", "AT16", // ctrl: ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt - "AT22", "AL22", "AU24", "BB23", "BB12", "AV15", "AK12", "AP13", // dm [0->7] - "AN24", "AM24", "AR22", "AR23", "AN23", "AM23", "AN21", "AP21", "AK23", "AJ23", "AL21", "AM21", "AJ21", "AJ20", "AK20", "AL20", // dq[0->15] - "AW22", "AW23", "AW21", "AV21", "AU23", "AV23", "AR24", "AT24", "BB24", "BA24", "AY23", "AY24", "AY25", "BA25", "BB21", "BA21", // dq[16->31] - "AY14", "AW15", "BB14", "BB13", "AW12", "AY13", "AY12", "BA12", "AU12", "AU13", "AT12", "AU14", "AV13", "AW13", "AT15", "AR15", // dq[32->47] - "AL15", "AJ15", "AK14", "AJ12", "AJ16", "AL16", "AJ13", "AK13", "AR14", "AT14", "AM12", "AP11", "AM13", "AN13", "AM11", "AN11", // dq[48->63] - "AP22", "AK22", "AU21", "BB22", "BA14", "AR12", "AL14", "AN14", // dqs_n[0->7] - "AP23", "AJ22", "AT21", "BA22", "BA15", "AP12", "AK15", "AN15") // dqs_p[0->7] - - IOPin.of(io).foreach { shell.xdc.addPackagePin(_, "") } - (IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } + require (shell.mem_clock.get.isDefined, "Use of DualDDR3VC709PlacedOverlay depends on MemClockVC709PlacedOverlay") + + val (sys, _) = shell.mem_clock.get.get.overlayOutput.node.out(0) + val (ui, _) = ddrUI.out(0) + val (ar, _) = areset.in(0) + + // connect the async fifo sync to sys_clock + topMigClkRstIONode.bundle.clock := sys.clock + topMigClkRstIONode.bundle.reset := sys.reset + + val port = topIONode.bundle.port + io <> port + // This is modified for vc709 + ui.clock := port.ui_clk + ui.reset := !port.mmcm_locked || port.ui_clk_sync_rst + port.sys_clk_i := sys.clock.asUInt + port.sys_rst := sys.reset // pllReset + port.aresetn := !ar.reset } } - shell.sdc.addGroup(clocks = Seq("ui_clk1"), pins = Seq(mig.island.module.blackbox.io.ui_clk)) + shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) } class DualDDR3VC709ShellPlacer(shell: VC709FPGATestHarness, val shellInput: DDRShellInput)(implicit val valName: ValName) extends DDRShellPlacer[VC709FPGATestHarness] { diff --git a/fpga/src/main/scala/vc709/HarnessBinders.scala b/fpga/src/main/scala/vc709/HarnessBinders.scala index c62e322a29..726b09ed3b 100644 --- a/fpga/src/main/scala/vc709/HarnessBinders.scala +++ b/fpga/src/main/scala/vc709/HarnessBinders.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} +import sifive.fpgashells.devices.xilinx.xilinxvc709pciex1.{HasSystemXilinxVC709PCIeX1ModuleImp, XilinxVC709PCIeX1IO} import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} import chipyard.harness.{OverrideHarnessBinder} @@ -17,7 +18,6 @@ import chipyard.harness.{OverrideHarnessBinder} class WithUART extends OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { th match { case vc709th: VC709FPGATestHarnessImp => { - // println("WithUART:ports.size = " + ports.size) val io_uart_bb_s = vc709th.vc709Outer.io_uart_bb_s (io_uart_bb_s zip ports).map { case (io_uart_bb, port) => io_uart_bb.bundle <> port } } } @@ -29,13 +29,13 @@ class WithDDRMem extends OverrideHarnessBinder({ (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { th match { case vc709th: VC709FPGATestHarnessImp => { require(ports.size > 0, "There must be at least one port.") // all ports go to the TL mem - - (vc709th.vc709Outer.ddrClients zip ports).map({ case (ddrClient, port) => + // connect each ddrClient to port + (ports zip vc709th.vc709Outer.ddrClients).map { case (port, ddrClient) => val bundles = ddrClient.out.map(_._1) - val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType))) - bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } - ddrClientBundle <> port - }) + val wire = Wire(new HeterogeneousBag(bundles.map(_.cloneType))) + (bundles zip wire) foreach { case (bundle, io) => bundle <> io } + wire <> port + } } } } -}) +}) \ No newline at end of file diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala index 2dd8f1c44f..86630c9418 100644 --- a/fpga/src/main/scala/vc709/TestHarness.scala +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -7,6 +7,7 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx._ @@ -17,7 +18,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.gpio._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, DigitalTop, ChipyardSystem, ExtTLMem, CanHaveMasterTLMemPort} import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders} @@ -28,31 +29,36 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She def dp = designParameters // Order matters; ddr depends on sys_clock - // val cjtag = Overlay(cJTAGDebugOverlayKey, new cJTAGDebugVC709ShellPlacer(this, cJTAGDebugShellInput())) - // val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVC709ShellPlacer(this, JTAGDebugBScanShellInput())) - // val fmc = Overlay(PCIeOverlayKey, new PCIeVC709FMCShellPlacer(this, PCIeShellInput())) - // val edge = Overlay(PCIeOverlayKey, new PCIeVC709EdgeShellPlacer(this, PCIeShellInput())) - // val mem_clock = Overlay(ClockInputOverlayKey, new MemClockVC709ShellPlacer(this, ClockInputShellInput())) - // val ddr1 = Overlay(DDROverlayKey, new DualDDR3VC709ShellPlacer(this, DDRShellInput())) + val mem_clock = Overlay(ClockInputOverlayKey, new MemClockVC709ShellPlacer(this, ClockInputShellInput())) + val ddr1 = Overlay(DDROverlayKey, new DualDDR3VC709ShellPlacer(this, DDRShellInput())) val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") // DOC include start: ClockOverlay - // place all clocks in the shell - require(dp(ClockInputOverlayKey).size >= 1) - val sysClkNode = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()).overlayOutput.node - + require(dp(ClockInputOverlayKey).size > 0, "There must be at least one sysclk.") /*** Connect/Generate clocks ***/ + // place all clocks in the shell, and connect to the PLL that will generate + // multiple clocks, finally create and connect to the clockSinkNode - // connect to the PLL that will generate multiple clocks + /*** The first clock goes to the system and the first DDR ***/ + val sysClkNode = dp(ClockInputOverlayKey).head.place(ClockInputDesignInput()).overlayOutput.node val harnessSysPLL = dp(PLLFactoryKey)() - harnessSysPLL := sysClkNode - - // create and connect to the dutClock val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) val dutWrangler = LazyModule(new ResetWrangler) val dutGroup = ClockGroup() - dutClock := dutWrangler.node := dutGroup := harnessSysPLL + + // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLL <-- ClockSourceNode + dutClock := dutWrangler.node := dutGroup := harnessSysPLL := sysClkNode + + /*** The second clock goes to the second DDR ***/ + val memClkNode = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node + val harnessMemPLL = dp(PLLFactoryKey)() + val memClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + val memWrangler = LazyModule(new ResetWrangler) + val memGroup = ClockGroup() + + // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLL <-- ClockSourceNode + memClock := memWrangler.node := memGroup := harnessMemPLL := memClkNode // DOC include end: ClockOverlay /*** UART ***/ @@ -69,36 +75,31 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She /*** DDR ***/ // DOC include start: DDR3Overlay - val ddrDesignInput = DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL) - // connect all mem. channels to the FPGA DDR - val (ddrNodes, ddrClients) = topDesign match { - case td: ChipTop => td.lazySystem match { - case lsys: CanHaveMasterTLMemPort => { - (dp(DDROverlayKey) zip lsys.memTLNode.edges.in).map { case (ddrOverlayKey, inParams) => - val ddrNode = ddrOverlayKey.place(ddrDesignInput).overlayOutput.ddr - val ddrClient = TLClientNode(Seq(inParams.master)) - ddrNode := ddrClient - (ddrNode, ddrClient) - }.unzip + + // The first DDR3 uses sys_clock, while the second DDR3 uses mem_clock + var ddrDesignInputs = Seq( + DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL), + DDRDesignInput(dp(ExtTLMem).get.master.base, memWrangler.node, harnessMemPLL) + ) + val ddrNodes = (dp(DDROverlayKey) zip ddrDesignInputs).map { case (ddrOverlayKey, ddrDesignInput) => + ddrOverlayKey.place(ddrDesignInput).overlayOutput.ddr + } + + // DDRNode <--- TLClientNode[Master] ---> in-edge ---> TLNode[Slave] + val ddrClients = topDesign match { case td: ChipTop => + td.lazySystem match { case lsys: CanHaveMasterTLMemPort => + (ddrNodes zip lsys.memTLNode.edges.in).map { case (node, edge) => + val ddrClient = TLClientNode(Seq(edge.master)) + node := ddrClient + ddrClient } } } - println("ddrNodes: " + ddrNodes.toString()) - println("ddrClients: " + ddrClients.toString()) // DOC include end: DDR3Overlay - /*** PCIe ***/ - // hook the first PCIe the board has - // dp(PCIeOverlayKey) foreach { case key => { - // val pcies = key.place(PCIeDesignInput(wrangler=dutWrangler.node, corePLL=harnessSysPLL)).overlayOutput - // pcies match { case (pcieNode, pcieInt) => { - // val pciename = Some(s"pcie_$i") - // sbus.fromMaster(pciename) { pcieNode } - // sbus.toFixedWidthSlave(pciename) { pcieNode } - // ibus.fromSync := pcieInt - // println(pciename) - // } } - // } + // println("#PCIeOverlayKey = " + p(PCIeOverlayKey).size) + // val pcies = p(PCIeOverlayKey).zipWithIndex.map { case (key, i) => + // key.place(PCIeDesignInput(wrangler=dutWrangler.node, corePLL=harnessSysPLL)).overlayOutput // } // module implementation From 18c2da2122b01184be093c1f6123f2deac3d15e1 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Fri, 5 Mar 2021 13:51:44 +0800 Subject: [PATCH 08/27] update support for dual memory channels --- fpga/src/main/scala/vc709/Configs.scala | 2 +- fpga/src/main/scala/vc709/DigitalTop.scala | 57 ++++++++++++++++++++++ 2 files changed, 58 insertions(+), 1 deletion(-) create mode 100644 fpga/src/main/scala/vc709/DigitalTop.scala diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index dadb09c3c2..05f8927931 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -61,6 +61,6 @@ class RocketVC709Config extends Config( // DOC include end: AbstractVC709 and Rocket class BoomVC709Config extends Config( - new WithFPGAFrequency(50) ++ + new WithFPGAFrequency(25) ++ new WithVC709Tweaks ++ new chipyard.DualSmallBoomConfig) diff --git a/fpga/src/main/scala/vc709/DigitalTop.scala b/fpga/src/main/scala/vc709/DigitalTop.scala new file mode 100644 index 0000000000..a86476001a --- /dev/null +++ b/fpga/src/main/scala/vc709/DigitalTop.scala @@ -0,0 +1,57 @@ +package chipyard.fpga.vc709 + +import chisel3._ + +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ + +import chipyard.{DigitalTop, DigitalTopModule} + +// ------------------------------------ +// VC709 DigitalTop +// ------------------------------------ + +class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop + // with sifive.blocks.devices.i2c.HasPeripheryI2C + // with testchipip.HasPeripheryTSIHostWidget +{ + + /*** PCIe ***/ + // println("#PCIeOverlayKey = " + p(PCIeOverlayKey).size) + // topDesign match { case td: ChipTop => + // td.lazySystem match { case lsys: BaseSubsystem => + // println("BaseSubsystem: " + lsys.toString()) + // p(PCIeOverlayKey).zipWithIndex.map { case (key, i) => + // val overlayOutput = key.place(PCIeDesignInput(wrangler=dutWrangler.node, corePLL=harnessSysPLL)).overlayOutput + // val (pcieNode: TLNode, intNode: IntOutwardNode) = (overlayOutput.pcieNode, overlayOutput.intNode) + // val (slaveTLNode: TLIdentityNode, masterTLNode: TLAsyncSinkNode) = (pcieNode.inward, pcieNode.outward) + // lsys.fbus match { case fbus: FrontBus => + // fbus.coupleFrom(s"master_named_pcie${i}"){ bus => + // (bus + // :=* TLFIFOFixer(TLFIFOFixer.all) + // :=* masterTLNode) + // } + // } + // lsys.pbus match { case pbus: PeripheryBus => + // pbus.coupleTo(s"slave_named_pcie${i}"){ bus => + // println("pbus: " + bus.toString()) + // (slaveTLNode + // :*= TLWidthWidget(pbus.beatBytes) + // :*= bus) + // } + // } + // lsys.ibus match { case ibus: InterruptBusWrapper => + // ibus.fromSync := intNode + // } + // } + // } + // } + override lazy val module = new VC709DigitalTopModule(this) +} + +class VC709DigitalTopModule[+L <: VC709DigitalTop](l: L) extends DigitalTopModule(l) + // with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp From 83e6b658793baede1147a30fb04522d9f1319fcf Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Mon, 8 Mar 2021 15:52:17 +0800 Subject: [PATCH 09/27] support PCIeX8 for vc709 --- fpga/src/main/scala/vc709/Configs.scala | 8 ++- fpga/src/main/scala/vc709/DigitalTop.scala | 62 ++++++++++----------- fpga/src/main/scala/vc709/TestHarness.scala | 21 ++----- fpga/src/main/scala/vcu118/Configs.scala | 2 +- 4 files changed, 42 insertions(+), 51 deletions(-) diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index 05f8927931..9e1614cf14 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -17,7 +17,7 @@ import sifive.fpgashells.shell.xilinx.{VC709DDR3Size} import testchipip.{SerialTLKey} -import chipyard.{BuildSystem, ExtTLMem} +import chipyard.{BuildTop, BuildSystem, ExtTLMem} import chipyard.fpga.vcu118.{WithUARTIOPassthrough, WithTLIOPassthrough, WithFPGAFrequency} @@ -55,12 +55,18 @@ class WithVC709Tweaks extends Config( new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(2)) +class WithVC709System extends Config((site, here, up) => { + case BuildSystem => (p: Parameters) => new VC709DigitalTop()(p) +}) + class RocketVC709Config extends Config( + new WithVC709System ++ new WithVC709Tweaks ++ new chipyard.RocketConfig) // DOC include end: AbstractVC709 and Rocket class BoomVC709Config extends Config( new WithFPGAFrequency(25) ++ + new WithVC709System ++ new WithVC709Tweaks ++ new chipyard.DualSmallBoomConfig) diff --git a/fpga/src/main/scala/vc709/DigitalTop.scala b/fpga/src/main/scala/vc709/DigitalTop.scala index a86476001a..fa721ccf91 100644 --- a/fpga/src/main/scala/vc709/DigitalTop.scala +++ b/fpga/src/main/scala/vc709/DigitalTop.scala @@ -8,50 +8,44 @@ import freechips.rocketchip.config.Parameters import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ import chipyard.{DigitalTop, DigitalTopModule} +import sifive.fpgashells.shell._ +import sifive.fpgashells.clocks._ + // ------------------------------------ // VC709 DigitalTop // ------------------------------------ class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop - // with sifive.blocks.devices.i2c.HasPeripheryI2C - // with testchipip.HasPeripheryTSIHostWidget { + def dp = p + + /*** The second clock goes to the second DDR ***/ + val memClkNode = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node + val harnessMemPLL = dp(PLLFactoryKey)() + val memClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + val memWrangler = LazyModule(new ResetWrangler) + val memGroup = ClockGroup() + + // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLL <-- ClockSourceNode + memClock := memWrangler.node := memGroup := harnessMemPLL := memClkNode + + + /*** PCIe dutWrangler.node, harnessSysPLL ***/ + println("#PCIeOverlayKey = " + p(PCIeOverlayKey).size) + p(PCIeOverlayKey).zipWithIndex.map { case (key, i) => + val overlayOutput = key.place(PCIeDesignInput(wrangler=memWrangler.node, corePLL=harnessMemPLL)).overlayOutput + val (pcieNode: TLNode, intNode: IntOutwardNode) = (overlayOutput.pcieNode, overlayOutput.intNode) + val (slaveTLNode: TLIdentityNode, masterTLNode: TLAsyncSinkNode) = (pcieNode.inward, pcieNode.outward) + fbus.coupleFrom(s"master_named_pcie${i}"){ _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* masterTLNode } + pbus.coupleTo(s"slave_named_pcie${i}"){ slaveTLNode :*= TLWidthWidget(pbus.beatBytes) :*= _ } + ibus.fromSync := intNode + } - /*** PCIe ***/ - // println("#PCIeOverlayKey = " + p(PCIeOverlayKey).size) - // topDesign match { case td: ChipTop => - // td.lazySystem match { case lsys: BaseSubsystem => - // println("BaseSubsystem: " + lsys.toString()) - // p(PCIeOverlayKey).zipWithIndex.map { case (key, i) => - // val overlayOutput = key.place(PCIeDesignInput(wrangler=dutWrangler.node, corePLL=harnessSysPLL)).overlayOutput - // val (pcieNode: TLNode, intNode: IntOutwardNode) = (overlayOutput.pcieNode, overlayOutput.intNode) - // val (slaveTLNode: TLIdentityNode, masterTLNode: TLAsyncSinkNode) = (pcieNode.inward, pcieNode.outward) - // lsys.fbus match { case fbus: FrontBus => - // fbus.coupleFrom(s"master_named_pcie${i}"){ bus => - // (bus - // :=* TLFIFOFixer(TLFIFOFixer.all) - // :=* masterTLNode) - // } - // } - // lsys.pbus match { case pbus: PeripheryBus => - // pbus.coupleTo(s"slave_named_pcie${i}"){ bus => - // println("pbus: " + bus.toString()) - // (slaveTLNode - // :*= TLWidthWidget(pbus.beatBytes) - // :*= bus) - // } - // } - // lsys.ibus match { case ibus: InterruptBusWrapper => - // ibus.fromSync := intNode - // } - // } - // } - // } override lazy val module = new VC709DigitalTopModule(this) } -class VC709DigitalTopModule[+L <: VC709DigitalTop](l: L) extends DigitalTopModule(l) - // with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp +class VC709DigitalTopModule[+L <: VC709DigitalTop](l: L) extends DigitalTopModule(l) \ No newline at end of file diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala index 86630c9418..f60c8fff2a 100644 --- a/fpga/src/main/scala/vc709/TestHarness.scala +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -36,6 +36,7 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She // DOC include start: ClockOverlay require(dp(ClockInputOverlayKey).size > 0, "There must be at least one sysclk.") + println("#ClockInputOverlayKey = " + dp(ClockInputOverlayKey).size) /*** Connect/Generate clocks ***/ // place all clocks in the shell, and connect to the PLL that will generate // multiple clocks, finally create and connect to the clockSinkNode @@ -49,16 +50,11 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLL <-- ClockSourceNode dutClock := dutWrangler.node := dutGroup := harnessSysPLL := sysClkNode - - /*** The second clock goes to the second DDR ***/ - val memClkNode = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node - val harnessMemPLL = dp(PLLFactoryKey)() - val memClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) - val memWrangler = LazyModule(new ResetWrangler) - val memGroup = ClockGroup() - - // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLL <-- ClockSourceNode - memClock := memWrangler.node := memGroup := harnessMemPLL := memClkNode + val (memWrangler, harnessMemPLL) = topDesign match { case td: ChipTop => + td.lazySystem match { case lsys: VC709DigitalTop => + (lsys.memWrangler, lsys.harnessMemPLL) + } + } // DOC include end: ClockOverlay /*** UART ***/ @@ -97,11 +93,6 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She } // DOC include end: DDR3Overlay - // println("#PCIeOverlayKey = " + p(PCIeOverlayKey).size) - // val pcies = p(PCIeOverlayKey).zipWithIndex.map { case (key, i) => - // key.place(PCIeDesignInput(wrangler=dutWrangler.node, corePLL=harnessSysPLL)).overlayOutput - // } - // module implementation override lazy val module = new VC709FPGATestHarnessImp(this) } diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 8b17aa98e6..fa1999799b 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -52,7 +52,7 @@ class WithVCU118Tweaks extends Config( new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) + new freechips.rocketchip.subsystem.WithNMemoryChannels(2)) class RocketVCU118Config extends Config( new WithVCU118Tweaks ++ From 82b20a8ba49986dac3d90da5cc0e1ee366e27cc8 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Tue, 9 Mar 2021 13:10:15 +0800 Subject: [PATCH 10/27] update PCIeX8 support for vc709 --- .../src/main/resources/vc709/uartboot/crc16.o | Bin 1752 -> 0 bytes fpga/src/main/scala/vc709/Configs.scala | 4 +- fpga/src/main/scala/vc709/DigitalTop.scala | 41 +++++++++--------- fpga/src/main/scala/vc709/TestHarness.scala | 41 +++++++++++------- 4 files changed, 48 insertions(+), 38 deletions(-) delete mode 100644 fpga/src/main/resources/vc709/uartboot/crc16.o diff --git a/fpga/src/main/resources/vc709/uartboot/crc16.o b/fpga/src/main/resources/vc709/uartboot/crc16.o deleted file mode 100644 index 845b7118eafeda2b24009a6c1e57f231b510cc0b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1752 zcmbu8&ui0g6u@8FZtJu&RVEB3+KW2TeQ8w`hiIV06&WHzz{}X$E_LAAjx?1`*oG9u zAc9B#l1^`}I}~p{i02{*1-+=3QUdk8kWBdvzuR|lWlU! zb+uPWp?3Wd^w&DF^^w*oHv+9@Cw3H#70!3g`SJ3BXrHP5n8{c>-9k(41GH3|w)p*G z=C#_*ym=^PEUhcoL9Vy4Rp0tzwYn65d+OIzTY9l$4`hH{$NT937Srj4#GIC^mdtA6 z7Q4oh^QoIvXPMf)nq7c4o?(RRyGGGSFzjCtg!QS zql{Kz7(WUfKJgch9~2;A=hQ|Wlej!Jv`^=3ke%jSterEV)Vz^T-C%iFuNdWOY0b6C z3Gl&H&X-Vad*DifbDS5=%oBxMf{T8@D%(Xfn?r3Hu3i_Gp>JfFsc)IU*0N?6Sguk5 zmM<5JdI?#nZ0Zc}#(c%h=AZKQlTwv!8s$yhFt>p@74-F$f{`ui-d_I4NMJJE1^=WJ zWF((m<-Ps?{49Ft9xGmiYjpTw&2WAUHRXy43x0uf|IM2AH{x~t_zJK2ulXt7KgsJ0 zCHh|$fNRlT=mq4$9uB=51OsC4Bcs1z_-;`hh36+|F(l&r1j?a7q5k|;p8r?`a_!Gw zMjkZ39xo`)h2}@OB45les5iBG&-+KYK8}q3D}O#Q|LhP!gZHQVH7vZGhfbmult0Je Kh8O7?{`^1Fo5jBX diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index 9e1614cf14..e10fdee015 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -53,7 +53,7 @@ class WithVC709Tweaks extends Config( new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(2)) + new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) class WithVC709System extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => new VC709DigitalTop()(p) @@ -66,7 +66,7 @@ class RocketVC709Config extends Config( // DOC include end: AbstractVC709 and Rocket class BoomVC709Config extends Config( - new WithFPGAFrequency(25) ++ + new WithFPGAFrequency(10) ++ new WithVC709System ++ new WithVC709Tweaks ++ new chipyard.DualSmallBoomConfig) diff --git a/fpga/src/main/scala/vc709/DigitalTop.scala b/fpga/src/main/scala/vc709/DigitalTop.scala index fa721ccf91..98c71320b5 100644 --- a/fpga/src/main/scala/vc709/DigitalTop.scala +++ b/fpga/src/main/scala/vc709/DigitalTop.scala @@ -23,27 +23,26 @@ class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop { def dp = p - /*** The second clock goes to the second DDR ***/ - val memClkNode = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node - val harnessMemPLL = dp(PLLFactoryKey)() - val memClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) - val memWrangler = LazyModule(new ResetWrangler) - val memGroup = ClockGroup() - - // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLL <-- ClockSourceNode - memClock := memWrangler.node := memGroup := harnessMemPLL := memClkNode - - - /*** PCIe dutWrangler.node, harnessSysPLL ***/ - println("#PCIeOverlayKey = " + p(PCIeOverlayKey).size) - p(PCIeOverlayKey).zipWithIndex.map { case (key, i) => - val overlayOutput = key.place(PCIeDesignInput(wrangler=memWrangler.node, corePLL=harnessMemPLL)).overlayOutput - val (pcieNode: TLNode, intNode: IntOutwardNode) = (overlayOutput.pcieNode, overlayOutput.intNode) - val (slaveTLNode: TLIdentityNode, masterTLNode: TLAsyncSinkNode) = (pcieNode.inward, pcieNode.outward) - fbus.coupleFrom(s"master_named_pcie${i}"){ _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* masterTLNode } - pbus.coupleTo(s"slave_named_pcie${i}"){ slaveTLNode :*= TLWidthWidget(pbus.beatBytes) :*= _ } - ibus.fromSync := intNode - } + // /*** The second clock goes to the second DDR ***/ + // val memClkNode = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node + // val harnessMemPLL = dp(PLLFactoryKey)() + // val memGroup = ClockGroup() + // val memWrangler = LazyModule(new ResetWrangler) + // val memClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + + // // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLLNode <-- ClockSourceNode + // memClock := memWrangler.node := memGroup := harnessMemPLL := memClkNode + + // /*** PCIe dutWrangler.node, harnessSysPLL ***/ + // println("#PCIeOverlayKey = " + p(PCIeOverlayKey).size) + // p(PCIeOverlayKey).zipWithIndex.map { case (key, i) => + // val overlayOutput = key.place(PCIeDesignInput(wrangler=memWrangler.node, corePLL=harnessMemPLL)).overlayOutput + // val (pcieNode: TLNode, intNode: IntOutwardNode) = (overlayOutput.pcieNode, overlayOutput.intNode) + // val (slaveTLNode: TLIdentityNode, masterTLNode: TLAsyncSinkNode) = (pcieNode.inward, pcieNode.outward) + // fbus.coupleFrom(s"master_named_pcie${i}"){ _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* masterTLNode } + // pbus.coupleTo(s"slave_named_pcie${i}"){ slaveTLNode :*= TLWidthWidget(pbus.beatBytes) :*= _ } + // ibus.fromSync := intNode + // } override lazy val module = new VC709DigitalTopModule(this) } diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala index f60c8fff2a..94942f5bf4 100644 --- a/fpga/src/main/scala/vc709/TestHarness.scala +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -30,7 +30,7 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She // Order matters; ddr depends on sys_clock val mem_clock = Overlay(ClockInputOverlayKey, new MemClockVC709ShellPlacer(this, ClockInputShellInput())) - val ddr1 = Overlay(DDROverlayKey, new DualDDR3VC709ShellPlacer(this, DDRShellInput())) + // val ddr1 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") @@ -44,17 +44,22 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She /*** The first clock goes to the system and the first DDR ***/ val sysClkNode = dp(ClockInputOverlayKey).head.place(ClockInputDesignInput()).overlayOutput.node val harnessSysPLL = dp(PLLFactoryKey)() - val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) - val dutWrangler = LazyModule(new ResetWrangler) val dutGroup = ClockGroup() - - // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLL <-- ClockSourceNode + val dutWrangler = LazyModule(new ResetWrangler) + val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLLNode <-- ClockSourceNode dutClock := dutWrangler.node := dutGroup := harnessSysPLL := sysClkNode - val (memWrangler, harnessMemPLL) = topDesign match { case td: ChipTop => - td.lazySystem match { case lsys: VC709DigitalTop => - (lsys.memWrangler, lsys.harnessMemPLL) - } - } + + // val (sysClkNode, dutClock, dutWrangler, harnessSysPLL) = topDesign match { case td: ChipTop => + // td.lazySystem match { case lsys: VC709DigitalTop => + // (lsys.dutClock, lsys.dutWrangler, lsys.harnessSysPLL, lsys.sysClkNode) + // } + // } + // val (memWrangler, harnessMemPLL) = topDesign match { case td: ChipTop => + // td.lazySystem match { case lsys: VC709DigitalTop => + // (lsys.memWrangler, lsys.harnessMemPLL) + // } + // } // DOC include end: ClockOverlay /*** UART ***/ @@ -73,11 +78,17 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She // DOC include start: DDR3Overlay // The first DDR3 uses sys_clock, while the second DDR3 uses mem_clock - var ddrDesignInputs = Seq( - DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL), - DDRDesignInput(dp(ExtTLMem).get.master.base, memWrangler.node, harnessMemPLL) - ) - val ddrNodes = (dp(DDROverlayKey) zip ddrDesignInputs).map { case (ddrOverlayKey, ddrDesignInput) => + // var ddrDesignInputs = Seq( + // DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL), + // DDRDesignInput(dp(ExtTLMem).get.master.base, memWrangler.node, harnessMemPLL) + // ) + // val ddrNodes = (dp(DDROverlayKey) zip ddrDesignInputs).map { case (ddrOverlayKey, ddrDesignInput) => + // ddrOverlayKey.place(ddrDesignInput).overlayOutput.ddr + // } + + // All DDR3s use the same clock + var ddrDesignInput = DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL) + val ddrNodes = dp(DDROverlayKey).zipWithIndex.map { case (ddrOverlayKey, i) => ddrOverlayKey.place(ddrDesignInput).overlayOutput.ddr } From 44e91e50fa164cfa1b8eb1ccb4a6c0887f4d82ca Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Wed, 10 Mar 2021 08:56:45 +0800 Subject: [PATCH 11/27] update support for dual memory channels and PCIe X8 --- fpga/src/main/scala/vc709/Configs.scala | 4 +- .../src/main/scala/vc709/CustomOverlays.scala | 5 ++- fpga/src/main/scala/vc709/DigitalTop.scala | 38 +++++++++---------- fpga/src/main/scala/vc709/TestHarness.scala | 29 ++++---------- 4 files changed, 32 insertions(+), 44 deletions(-) diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index e10fdee015..9e1614cf14 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -53,7 +53,7 @@ class WithVC709Tweaks extends Config( new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) + new freechips.rocketchip.subsystem.WithNMemoryChannels(2)) class WithVC709System extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => new VC709DigitalTop()(p) @@ -66,7 +66,7 @@ class RocketVC709Config extends Config( // DOC include end: AbstractVC709 and Rocket class BoomVC709Config extends Config( - new WithFPGAFrequency(10) ++ + new WithFPGAFrequency(25) ++ new WithVC709System ++ new WithVC709Tweaks ++ new chipyard.DualSmallBoomConfig) diff --git a/fpga/src/main/scala/vc709/CustomOverlays.scala b/fpga/src/main/scala/vc709/CustomOverlays.scala index e44d59b1c2..8c7cee7f19 100644 --- a/fpga/src/main/scala/vc709/CustomOverlays.scala +++ b/fpga/src/main/scala/vc709/CustomOverlays.scala @@ -30,7 +30,7 @@ class MemClockVC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: C def place(designInput: ClockInputDesignInput) = new MemClockVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } -// case object VC709DDR3Size extends Field[BigInt](0x100000000L) // 4GB +case object VC709DDR3Size extends Field[BigInt](0x100000000L) // 4GB class DualDDR3VC709PlacedOverlay(val shell: VC709FPGATestHarness, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput) extends DDR3XilinxPlacedOverlay(shell, name, designInput, shellInput) { @@ -69,7 +69,8 @@ class DualDDR3VC709PlacedOverlay(val shell: VC709FPGATestHarness, name: String, port.aresetn := !ar.reset } } - shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) + shell.sdc.addGroup(clocks = Seq("clk_pll_i")) + // shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) } class DualDDR3VC709ShellPlacer(shell: VC709FPGATestHarness, val shellInput: DDRShellInput)(implicit val valName: ValName) extends DDRShellPlacer[VC709FPGATestHarness] { diff --git a/fpga/src/main/scala/vc709/DigitalTop.scala b/fpga/src/main/scala/vc709/DigitalTop.scala index 98c71320b5..a3e94c5a75 100644 --- a/fpga/src/main/scala/vc709/DigitalTop.scala +++ b/fpga/src/main/scala/vc709/DigitalTop.scala @@ -23,26 +23,26 @@ class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop { def dp = p - // /*** The second clock goes to the second DDR ***/ - // val memClkNode = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node - // val harnessMemPLL = dp(PLLFactoryKey)() - // val memGroup = ClockGroup() - // val memWrangler = LazyModule(new ResetWrangler) - // val memClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + /*** The second clock goes to the second DDR ***/ + val memClkNode = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node + val harnessMemPLL = dp(PLLFactoryKey)() + val memGroup = ClockGroup() + val memWrangler = LazyModule(new ResetWrangler) + val memClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) - // // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLLNode <-- ClockSourceNode - // memClock := memWrangler.node := memGroup := harnessMemPLL := memClkNode - - // /*** PCIe dutWrangler.node, harnessSysPLL ***/ - // println("#PCIeOverlayKey = " + p(PCIeOverlayKey).size) - // p(PCIeOverlayKey).zipWithIndex.map { case (key, i) => - // val overlayOutput = key.place(PCIeDesignInput(wrangler=memWrangler.node, corePLL=harnessMemPLL)).overlayOutput - // val (pcieNode: TLNode, intNode: IntOutwardNode) = (overlayOutput.pcieNode, overlayOutput.intNode) - // val (slaveTLNode: TLIdentityNode, masterTLNode: TLAsyncSinkNode) = (pcieNode.inward, pcieNode.outward) - // fbus.coupleFrom(s"master_named_pcie${i}"){ _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* masterTLNode } - // pbus.coupleTo(s"slave_named_pcie${i}"){ slaveTLNode :*= TLWidthWidget(pbus.beatBytes) :*= _ } - // ibus.fromSync := intNode - // } + // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLLNode <-- ClockSourceNode + memClock := memWrangler.node := memGroup := harnessMemPLL := memClkNode + + /*** PCIe dutWrangler.node, harnessSysPLL ***/ + println("#PCIeOverlayKey = " + p(PCIeOverlayKey).size) + p(PCIeOverlayKey).zipWithIndex.map { case (key, i) => + val overlayOutput = key.place(PCIeDesignInput(wrangler=memWrangler.node, corePLL=harnessMemPLL)).overlayOutput + val (pcieNode: TLNode, intNode: IntOutwardNode) = (overlayOutput.pcieNode, overlayOutput.intNode) + val (slaveTLNode: TLIdentityNode, masterTLNode: TLAsyncSinkNode) = (pcieNode.inward, pcieNode.outward) + fbus.coupleFrom(s"master_named_pcie${i}"){ _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* masterTLNode } + pbus.coupleTo(s"slave_named_pcie${i}"){ slaveTLNode :*= TLWidthWidget(pbus.beatBytes) :*= _ } + ibus.fromSync := intNode + } override lazy val module = new VC709DigitalTopModule(this) } diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala index 94942f5bf4..7d1ed27744 100644 --- a/fpga/src/main/scala/vc709/TestHarness.scala +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -22,7 +22,7 @@ import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders} -case object FPGAFrequencyKey extends Field[Double](100.0) +case object FPGAFrequencyKey extends Field[Double](50.0) class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709ShellBasicOverlays { @@ -30,11 +30,12 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She // Order matters; ddr depends on sys_clock val mem_clock = Overlay(ClockInputOverlayKey, new MemClockVC709ShellPlacer(this, ClockInputShellInput())) - // val ddr1 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) + val ddr1 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") // DOC include start: ClockOverlay + require(dp(ClockInputOverlayKey).size > 0, "There must be at least one sysclk.") println("#ClockInputOverlayKey = " + dp(ClockInputOverlayKey).size) /*** Connect/Generate clocks ***/ @@ -50,21 +51,12 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLLNode <-- ClockSourceNode dutClock := dutWrangler.node := dutGroup := harnessSysPLL := sysClkNode - // val (sysClkNode, dutClock, dutWrangler, harnessSysPLL) = topDesign match { case td: ChipTop => - // td.lazySystem match { case lsys: VC709DigitalTop => - // (lsys.dutClock, lsys.dutWrangler, lsys.harnessSysPLL, lsys.sysClkNode) - // } - // } - // val (memWrangler, harnessMemPLL) = topDesign match { case td: ChipTop => - // td.lazySystem match { case lsys: VC709DigitalTop => - // (lsys.memWrangler, lsys.harnessMemPLL) - // } - // } // DOC include end: ClockOverlay /*** UART ***/ // DOC include start: UartOverlay + // All UART goes to the VC709 dedicated UART val io_uart_bb_s = (dp(UARTOverlayKey) zip dp(PeripheryUARTKey)).map { case (uartOverlayKey, peripheryUARTKey) => @@ -72,21 +64,15 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She uartOverlayKey.place(UARTDesignInput(io_uart_bb)) io_uart_bb } + // DOC include end: UartOverlay /*** DDR ***/ -// DOC include start: DDR3Overlay - // The first DDR3 uses sys_clock, while the second DDR3 uses mem_clock - // var ddrDesignInputs = Seq( - // DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL), - // DDRDesignInput(dp(ExtTLMem).get.master.base, memWrangler.node, harnessMemPLL) - // ) - // val ddrNodes = (dp(DDROverlayKey) zip ddrDesignInputs).map { case (ddrOverlayKey, ddrDesignInput) => - // ddrOverlayKey.place(ddrDesignInput).overlayOutput.ddr - // } +// DOC include start: DDR3Overlay // All DDR3s use the same clock + println("#DDROverlayKey = " + dp(DDROverlayKey).size) var ddrDesignInput = DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL) val ddrNodes = dp(DDROverlayKey).zipWithIndex.map { case (ddrOverlayKey, i) => ddrOverlayKey.place(ddrDesignInput).overlayOutput.ddr @@ -102,6 +88,7 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She } } } + // DOC include end: DDR3Overlay // module implementation From 550628a58583cfde24820b075d86c726e52439b9 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Thu, 11 Mar 2021 14:34:09 +0800 Subject: [PATCH 12/27] update Makefile --- fpga/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/Makefile b/fpga/Makefile index f820355b7b..16576eef80 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -150,4 +150,4 @@ mcs: $(MCS_FILE) ######################################################################################### .PHONY: clean clean: - rm -rf $(gen_dir) + rm -rf $(build_dir) From 498b97837ee74175f91a9fad98eb60b0b5776139 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Thu, 11 Mar 2021 14:35:39 +0800 Subject: [PATCH 13/27] update Makefile of uartsend --- fpga/src/main/resources/vc709/uartsend/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/src/main/resources/vc709/uartsend/Makefile b/fpga/src/main/resources/vc709/uartsend/Makefile index 5fdd604dd5..a598850707 100644 --- a/fpga/src/main/resources/vc709/uartsend/Makefile +++ b/fpga/src/main/resources/vc709/uartsend/Makefile @@ -1,9 +1,9 @@ build: CC=gcc - $(CC) -c ./uartboot/crc16.c -o ./uartboot/crc16.o + $(CC) -c ../uartboot/crc16.c -o ../uartboot/crc16.o $(CC) -c serial.c -o serial.o - $(CC) -o serial serial.o ./uartboot/crc16.o + $(CC) -o serial serial.o ../uartboot/crc16.o clean: - rm serial.o ./uartboot/crc16.o + rm serial.o ../uartboot/crc16.o rm serial From 5134387ebd9c1faa1fb8acc13ea594de22edb2fa Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Sat, 13 Mar 2021 16:40:50 +0800 Subject: [PATCH 14/27] update support for vc709 board --- .../main/resources/vc709/uartboot/Makefile.mk | 72 +++++++++++++++++++ fpga/src/main/resources/vc709/uartboot/plic.c | 8 --- .../main/resources/vc709/uartboot/serial.c | 9 --- fpga/src/main/resources/vc709/uartboot/uart.c | 9 +-- .../main/resources/vc709/uartsend/serial.c | 2 +- fpga/src/main/scala/vc709/Configs.scala | 28 +++++--- fpga/src/main/scala/vc709/DigitalTop.scala | 3 +- fpga/src/main/scala/vc709/TestHarness.scala | 19 +++-- 8 files changed, 103 insertions(+), 47 deletions(-) create mode 100644 fpga/src/main/resources/vc709/uartboot/Makefile.mk diff --git a/fpga/src/main/resources/vc709/uartboot/Makefile.mk b/fpga/src/main/resources/vc709/uartboot/Makefile.mk new file mode 100644 index 0000000000..47694a0ef5 --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/Makefile.mk @@ -0,0 +1,72 @@ +# RISCV environment variable must be set + +CC=$(RISCV)/bin/riscv64-unknown-elf-gcc +OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy +CFLAGS=-march=rv64imac -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles +CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0 +CFLAGS+= -I $(BOOTROM_DIR)/include -I. +LFLAGS=-static -nostdlib -L $(BOOTROM_DIR)/linker -T bootrom.elf.lds + +dts := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts +dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb +clk := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).tl_clock.h + +## device tree +$(clk): $(dts) + awk '/tlclk {/ && !f{f=1; next}; f && match($$0, /^.*clock-frequency.*<(.*)>.*/, arr) { print "#define TL_CLK " arr[1] "UL"}' $< > $@.tmp + mv $@.tmp $@ + +$(dtb): $(dts) + dtc -I dts -O dtb -o $@ $< + +.PHONY: dtb +dtb: $(dtb) + +## uart_boot +elf := $(BUILD_DIR)/bootrom.elf +$(elf): $(dtb) head.S crc16.c kprintf.c serial.c $(clk) + $(CC) $(CFLAGS) -include $(clk) -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ head.S crc16.c kprintf.c serial.c + +## sd_boot +# elf := $(BUILD_DIR)/bootrom.elf +# $(elf): $(dtb) head.S kprintf.c sd.c $(clk) + # $(CC) $(CFLAGS) -include $(clk) -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ head.S sd.c kprintf.c + +.PHONY: elf +elf: $(elf) + +bin := $(BUILD_DIR)/bootrom.bin +$(bin): $(elf) + $(OBJCOPY) -O binary $< $@ + +.PHONY: bin +bin: $(bin) + +hex := $(BUILD_DIR)/bootrom.hex +$(hex): $(bin) + od -t x4 -An -w4 -v $< > $@ + +.PHONY: hex +hex: $(hex) + +# # Berkeley Boot Loader (BBL) +# elf := $(RISCV)/riscv64-unknown-elf/bin/bbl +# bin := $(BUILD_DIR)/bootrom.bin +# $(bin): $(elf) +# $(OBJCOPY) -O binary $< $@ + +# hex := $(BUILD_DIR)/bootrom.hex +# $(hex): $(bin) +# od -t x4 -An -w4 -v $< > $@ + +# Finally +romgen := $(BUILD_DIR)/rom.v +$(romgen): $(hex) + $(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@ + +.PHONY: romgen +romgen: $(romgen) + +.PHONY: clean +clean:: + rm -rf $(hex) $(elf) diff --git a/fpga/src/main/resources/vc709/uartboot/plic.c b/fpga/src/main/resources/vc709/uartboot/plic.c index 8ab278fd4f..91156eb1a1 100644 --- a/fpga/src/main/resources/vc709/uartboot/plic.c +++ b/fpga/src/main/resources/vc709/uartboot/plic.c @@ -1,11 +1,3 @@ -/* - * @,@Author: ,: your name - * @,@Date: ,: 1970-01-01 08:00:00 - * @,@LastEditTime: ,: 2021-01-22 09:12:20 - * @,@LastEditors: ,: Please set LastEditors - * @,@Description: ,: In User Settings Edit - * @,@FilePath: ,: /freedom/bootrom/sdboot/plic.c - */ #include diff --git a/fpga/src/main/resources/vc709/uartboot/serial.c b/fpga/src/main/resources/vc709/uartboot/serial.c index 912f53f1d5..0752b886f6 100644 --- a/fpga/src/main/resources/vc709/uartboot/serial.c +++ b/fpga/src/main/resources/vc709/uartboot/serial.c @@ -1,12 +1,3 @@ -/* - * @,@Author: ,: your name - * @,@Date: ,: 1970-01-01 08:00:00 - * @,@LastEditTime: ,: 2021-01-29 22:34:27 - * @,@LastEditors: ,: Please set LastEditors - * @,@Description: ,: In User Settings Edit - * @,@FilePath: ,: /freedom/bootrom/sdboot/serial.c - */ - #include "./include/serial.h" static int read_block(uint8_t *q) diff --git a/fpga/src/main/resources/vc709/uartboot/uart.c b/fpga/src/main/resources/vc709/uartboot/uart.c index 96c47dbc56..a6f505f69f 100644 --- a/fpga/src/main/resources/vc709/uartboot/uart.c +++ b/fpga/src/main/resources/vc709/uartboot/uart.c @@ -1,11 +1,3 @@ -/* - * @,@Author: ,: your name - * @,@Date: ,: 1970-01-01 08:00:00 - * @,@LastEditTime: ,: 2021-01-24 11:27:59 - * @,@LastEditors: ,: Please set LastEditors - * @,@Description: ,: In User Settings Edit - * @,@FilePath: ,: /freedom/bootrom/sdboot/uart.c - */ // See LICENSE for license details. #include @@ -13,6 +5,7 @@ #include "common.h" #define DEBUG + #include "kprintf.h" #define is_num(c) ((c>='0')&&(c<='9')) diff --git a/fpga/src/main/resources/vc709/uartsend/serial.c b/fpga/src/main/resources/vc709/uartsend/serial.c index 08e1838c29..fe7b4846aa 100644 --- a/fpga/src/main/resources/vc709/uartsend/serial.c +++ b/fpga/src/main/resources/vc709/uartsend/serial.c @@ -11,7 +11,7 @@ #include #include -#include "./uartboot/include/serial.h" +#include "../uartboot/include/serial.h" #define DEVICE "/dev/ttyUSB1" #define S_TIMEOUT 1 diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index 9e1614cf14..d9fddef434 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -3,8 +3,8 @@ package chipyard.fpga.vc709 import sys.process._ import freechips.rocketchip.config.{Config, Parameters} -import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} -import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} +import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem, WithJtagDTM} +import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG, JtagDTMKey, JtagDTMConfig} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} import freechips.rocketchip.tile.{XLen} @@ -24,13 +24,16 @@ import chipyard.fpga.vcu118.{WithUARTIOPassthrough, WithTLIOPassthrough, WithFPG class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) - // case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L))) - // case VC709ShellPMOD => "SDIO" }) class WithSystemModifications extends Config((site, here, up) => { case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) case DTSTimebase => BigInt(1000000) + // case JtagDTMKey => new JtagDTMConfig( + // idcodeVersion = 2, + // idcodePartNum = 0x000, + // idcodeManufId = 0x489, + // debugIdleCycles = 5) case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => // invoke makefile for uart boot val freqMHz = site(FPGAFrequencyKey).toInt * 1000000 @@ -49,11 +52,12 @@ class WithVC709Tweaks extends Config( new WithUARTIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ - new chipyard.config.WithTLBackingMemory ++ // use TL backing memory + new WithJtagDTM ++ new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size - new chipyard.config.WithNoDebug ++ // remove debug module + new chipyard.config.WithTLBackingMemory ++ // use TL backing memory + // new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(2)) + new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) class WithVC709System extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => new VC709DigitalTop()(p) @@ -62,11 +66,15 @@ class WithVC709System extends Config((site, here, up) => { class RocketVC709Config extends Config( new WithVC709System ++ new WithVC709Tweaks ++ - new chipyard.RocketConfig) + new chipyard.QuadRocketConfig) // DOC include end: AbstractVC709 and Rocket +class QuadSmallBoomConfig extends Config( + new boom.common.WithNSmallBooms(4) ++ // 4 boom cores + new chipyard.config.AbstractConfig) + class BoomVC709Config extends Config( - new WithFPGAFrequency(25) ++ + new WithFPGAFrequency(50) ++ new WithVC709System ++ new WithVC709Tweaks ++ - new chipyard.DualSmallBoomConfig) + new QuadSmallBoomConfig) diff --git a/fpga/src/main/scala/vc709/DigitalTop.scala b/fpga/src/main/scala/vc709/DigitalTop.scala index a3e94c5a75..139ff59ee3 100644 --- a/fpga/src/main/scala/vc709/DigitalTop.scala +++ b/fpga/src/main/scala/vc709/DigitalTop.scala @@ -20,6 +20,8 @@ import sifive.fpgashells.clocks._ // ------------------------------------ class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop + with freechips.rocketchip.subsystem.CanHaveMasterTLMMIOPort + with freechips.rocketchip.subsystem.CanHaveSlaveTLPort { def dp = p @@ -34,7 +36,6 @@ class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop memClock := memWrangler.node := memGroup := harnessMemPLL := memClkNode /*** PCIe dutWrangler.node, harnessSysPLL ***/ - println("#PCIeOverlayKey = " + p(PCIeOverlayKey).size) p(PCIeOverlayKey).zipWithIndex.map { case (key, i) => val overlayOutput = key.place(PCIeDesignInput(wrangler=memWrangler.node, corePLL=harnessMemPLL)).overlayOutput val (pcieNode: TLNode, intNode: IntOutwardNode) = (overlayOutput.pcieNode, overlayOutput.intNode) diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala index 7d1ed27744..c5f4e8d81b 100644 --- a/fpga/src/main/scala/vc709/TestHarness.scala +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -30,14 +30,13 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She // Order matters; ddr depends on sys_clock val mem_clock = Overlay(ClockInputOverlayKey, new MemClockVC709ShellPlacer(this, ClockInputShellInput())) - val ddr1 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) + // val ddr1 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") // DOC include start: ClockOverlay require(dp(ClockInputOverlayKey).size > 0, "There must be at least one sysclk.") - println("#ClockInputOverlayKey = " + dp(ClockInputOverlayKey).size) /*** Connect/Generate clocks ***/ // place all clocks in the shell, and connect to the PLL that will generate // multiple clocks, finally create and connect to the clockSinkNode @@ -51,6 +50,11 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLLNode <-- ClockSourceNode dutClock := dutWrangler.node := dutGroup := harnessSysPLL := sysClkNode + val (memWrangler, harnessMemPLL) = topDesign match { case td: ChipTop => + td.lazySystem match { case lsys: VC709DigitalTop => + (lsys.memWrangler, lsys.harnessMemPLL) + } + } // DOC include end: ClockOverlay /*** UART ***/ @@ -72,18 +76,13 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She // DOC include start: DDR3Overlay // All DDR3s use the same clock - println("#DDROverlayKey = " + dp(DDROverlayKey).size) var ddrDesignInput = DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL) - val ddrNodes = dp(DDROverlayKey).zipWithIndex.map { case (ddrOverlayKey, i) => - ddrOverlayKey.place(ddrDesignInput).overlayOutput.ddr - } - - // DDRNode <--- TLClientNode[Master] ---> in-edge ---> TLNode[Slave] val ddrClients = topDesign match { case td: ChipTop => td.lazySystem match { case lsys: CanHaveMasterTLMemPort => - (ddrNodes zip lsys.memTLNode.edges.in).map { case (node, edge) => + (dp(DDROverlayKey) zip lsys.memTLNode.edges.in).map { case (ddrOverlayKey, edge) => + val ddtNode = ddrOverlayKey.place(ddrDesignInput).overlayOutput.ddr val ddrClient = TLClientNode(Seq(edge.master)) - node := ddrClient + ddtNode := ddrClient ddrClient } } From 33e001a5c6610816f0baff53b79b74b99a0b24d7 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Sat, 13 Mar 2021 16:45:30 +0800 Subject: [PATCH 15/27] update support for vc709 --- fpga/src/main/scala/vc709/Configs.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index d9fddef434..ff9f7b71db 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -52,10 +52,10 @@ class WithVC709Tweaks extends Config( new WithUARTIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ - new WithJtagDTM ++ + // new WithJtagDTM ++ new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size new chipyard.config.WithTLBackingMemory ++ // use TL backing memory - // new chipyard.config.WithNoDebug ++ // remove debug module + new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) From 4554b85a71af8b4bc3374789fce82e289eae9573 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Sat, 13 Mar 2021 16:46:08 +0800 Subject: [PATCH 16/27] add README.md --- fpga/README.md | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 fpga/README.md diff --git a/fpga/README.md b/fpga/README.md new file mode 100644 index 0000000000..f1cdb3ee4b --- /dev/null +++ b/fpga/README.md @@ -0,0 +1,45 @@ +# Guide + + +``` +$ export RISCV_LINUX=~/riscv-linux +$ export BUILDS=$(RISCV_LINUX)/builds +$ export OPENSBI=$(RISCV_LINUX)/opensbi +$ export LINUX=$(RISCV_LINUX)/linux +$ export CHIPYARD=~/chipyard +$ export gen_src=$(CHIPYARD)/fpga/generated-src +$ export RocketVC709Config=chipyard.fpga.vc709.VC709FPGATestHarness.RocketVC709Config +$ export BoomVC709Config=chipyard.fpga.vc709.VC709FPGATestHarness.BoomVC709Config +``` +Build Linux kernel +``` +$ make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- menuconfig +$ make j8 ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- +``` +Convert *.dts files into *.dtb format. +``` +$ cd $RISCV_LINUX/$BUILDS +$ cp -p $gen_src/$RocketVC709Config/$(RocketVC709Config).dts $BUILDS +$ dtc -I dts -O dtb -o $(RocketVC709Config).dtb $(RocketVC709Config).dts +$ cp -p $gen_src/$BoomVC709Config/$(BoomVC709Config).dts $BUILDS +$ dtc -I dts -O dtb -o $(BoomVC709Config).dtb $(BoomVC709Config).dts +``` +Build Open SBI for RocketVC709Config. +``` +make PLATFORM=generic CROSS_COMPILE=riscv64-unknown-linux-gnu- PLATFORM_RISCV_XLEN=64 FW_PAYLOAD=y FW_PAYLOAD_PATH=~/riscv-linux/linux/arch/riscv/boot/Image FW_FDT_PATH=$BUILDS/$(RocketVC709Config).dtb clean +make PLATFORM=generic CROSS_COMPILE=riscv64-unknown-linux-gnu- PLATFORM_RISCV_XLEN=64 FW_PAYLOAD=y FW_PAYLOAD_PATH=~/riscv-linux/linux/arch/riscv/boot/Image FW_FDT_PATH=$BUILDS/$(RocketVC709Config).dtb install +``` +Build Open SBI for BoomVC709Config. +``` +make PLATFORM=generic CROSS_COMPILE=riscv64-unknown-linux-gnu- PLATFORM_RISCV_XLEN=64 FW_PAYLOAD=y FW_PAYLOAD_PATH=~/riscv-linux/linux/arch/riscv/boot/Image FW_FDT_PATH=$BUILDS/$(BoomVC709Config).dtb clean +make PLATFORM=generic CROSS_COMPILE=riscv64-unknown-linux-gnu- PLATFORM_RISCV_XLEN=64 FW_PAYLOAD=y FW_PAYLOAD_PATH=~/riscv-linux/linux/arch/riscv/boot/Image FW_FDT_PATH=$BUILDS/$(BoomVC709Config).dtb install +``` +Find the `ttyUSB*` device. The outputs looks like this: `[79643.136986] usb 1-9: cp210x converter now attached to ttyUSB2`. +``` +$ sudo dmesg | grep tty +``` +Download `fw_payload.bin` to the board, then start up the kernel. +``` +$ sudo ./serial /dev/ttyUSB2 0x80000000 ../opensbi/build/platform/generic/firmware/fw_payload.bin +$ sudo ./serial /dev/ttyUSB2 +``` \ No newline at end of file From c6a02efde818324a4afcc67d280b26a54c8b2099 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Tue, 16 Mar 2021 11:13:20 +0800 Subject: [PATCH 17/27] update Configs.scala --- fpga/src/main/scala/vc709/Configs.scala | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index ff9f7b71db..d3731e7d0e 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -3,8 +3,8 @@ package chipyard.fpga.vc709 import sys.process._ import freechips.rocketchip.config.{Config, Parameters} -import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem, WithJtagDTM} -import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG, JtagDTMKey, JtagDTMConfig} +import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} +import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} import freechips.rocketchip.tile.{XLen} @@ -29,11 +29,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => { class WithSystemModifications extends Config((site, here, up) => { case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) case DTSTimebase => BigInt(1000000) - // case JtagDTMKey => new JtagDTMConfig( - // idcodeVersion = 2, - // idcodePartNum = 0x000, - // idcodeManufId = 0x489, - // debugIdleCycles = 5) case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => // invoke makefile for uart boot val freqMHz = site(FPGAFrequencyKey).toInt * 1000000 @@ -52,7 +47,6 @@ class WithVC709Tweaks extends Config( new WithUARTIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ - // new WithJtagDTM ++ new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size new chipyard.config.WithTLBackingMemory ++ // use TL backing memory new chipyard.config.WithNoDebug ++ // remove debug module From de74a188c95fb94ef1caba28b0db13493d5d67b3 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Wed, 17 Mar 2021 17:08:22 +0800 Subject: [PATCH 18/27] update I2C and PCIe support for vc709 board. --- fpga/README.md | 7 ++++- .../main/resources/vc709/uartsend/serial.c | 11 +------- fpga/src/main/scala/vc709/Configs.scala | 9 +++--- fpga/src/main/scala/vc709/DigitalTop.scala | 6 +++- .../src/main/scala/vc709/HarnessBinders.scala | 12 +++++++- fpga/src/main/scala/vc709/IOBinders.scala | 26 +++++++++++++++++ fpga/src/main/scala/vc709/TestHarness.scala | 28 ++++++++++++++----- 7 files changed, 75 insertions(+), 24 deletions(-) create mode 100644 fpga/src/main/scala/vc709/IOBinders.scala diff --git a/fpga/README.md b/fpga/README.md index f1cdb3ee4b..0e4ea37317 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -14,7 +14,7 @@ $ export BoomVC709Config=chipyard.fpga.vc709.VC709FPGATestHarness.BoomVC709Confi Build Linux kernel ``` $ make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- menuconfig -$ make j8 ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- +$ make -j8 ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- ``` Convert *.dts files into *.dtb format. ``` @@ -42,4 +42,9 @@ Download `fw_payload.bin` to the board, then start up the kernel. ``` $ sudo ./serial /dev/ttyUSB2 0x80000000 ../opensbi/build/platform/generic/firmware/fw_payload.bin $ sudo ./serial /dev/ttyUSB2 +``` + +``` +$ make PLATFORM=generic CROSS_COMPILE=riscv64-unknown-linux-gnu- FW_PAYLOAD_PATH=../linux/arch/riscv/boot/Image install +$ qemu-system-riscv64 -M virt -m 256M -nographic -bios opensbi/build/platform/generic/firmware/fw_jump.bin -kernel ./linux/arch/riscv/boot/Image -drive file=./rootfs.img,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -append "root=/dev/vda rw console=ttyS0" ``` \ No newline at end of file diff --git a/fpga/src/main/resources/vc709/uartsend/serial.c b/fpga/src/main/resources/vc709/uartsend/serial.c index fe7b4846aa..58607101ad 100644 --- a/fpga/src/main/resources/vc709/uartsend/serial.c +++ b/fpga/src/main/resources/vc709/uartsend/serial.c @@ -13,7 +13,7 @@ #include "../uartboot/include/serial.h" -#define DEVICE "/dev/ttyUSB1" +#define DEVICE "/dev/ttyUSB0" #define S_TIMEOUT 1 int serial_fd = 0; @@ -274,18 +274,9 @@ int main(int argc, char *argv[]) // ./serial tty, address, filename send_file(argv[2], argv[3]); printf("transfer finished.\n"); - } else if (argc == 3) { - // read message - printf("reading message.\n"); - readline(msg); - printf("%s\n", msg); } else { // ./serial tty write_cmd(UART_CMD_END); - while (1) { - readline(msg); - printf("%s", msg); - } } close(serial_fd); diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index d3731e7d0e..e93e654aa1 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -9,20 +9,18 @@ import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} import freechips.rocketchip.tile.{XLen} -import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} +import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} -import sifive.fpgashells.shell.xilinx.{VC709DDR3Size} import testchipip.{SerialTLKey} import chipyard.{BuildTop, BuildSystem, ExtTLMem} - import chipyard.fpga.vcu118.{WithUARTIOPassthrough, WithTLIOPassthrough, WithFPGAFrequency} - class WithDefaultPeripherals extends Config((site, here, up) => { + case PeripheryI2CKey => List(I2CParams(address = BigInt(0x60000000L))) case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) }) @@ -42,14 +40,17 @@ class WithSystemModifications extends Config((site, here, up) => { // DOC include start: AbstractVC709 and Rocket class WithVC709Tweaks extends Config( + new WithI2C ++ new WithUART ++ new WithDDRMem ++ + new WithI2CIOPassthrough ++ new WithUARTIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size new chipyard.config.WithTLBackingMemory ++ // use TL backing memory new chipyard.config.WithNoDebug ++ // remove debug module + new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) diff --git a/fpga/src/main/scala/vc709/DigitalTop.scala b/fpga/src/main/scala/vc709/DigitalTop.scala index 139ff59ee3..8544e3d5c1 100644 --- a/fpga/src/main/scala/vc709/DigitalTop.scala +++ b/fpga/src/main/scala/vc709/DigitalTop.scala @@ -19,7 +19,9 @@ import sifive.fpgashells.clocks._ // VC709 DigitalTop // ------------------------------------ +// DOC include start: VC709DigitalTop class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop + with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with freechips.rocketchip.subsystem.CanHaveMasterTLMMIOPort with freechips.rocketchip.subsystem.CanHaveSlaveTLPort { @@ -48,4 +50,6 @@ class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop override lazy val module = new VC709DigitalTopModule(this) } -class VC709DigitalTopModule[+L <: VC709DigitalTop](l: L) extends DigitalTopModule(l) \ No newline at end of file +class VC709DigitalTopModule[+L <: VC709DigitalTop](l: L) extends DigitalTopModule(l) + with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp +// DOC include end: VC709DigitalTop \ No newline at end of file diff --git a/fpga/src/main/scala/vc709/HarnessBinders.scala b/fpga/src/main/scala/vc709/HarnessBinders.scala index 726b09ed3b..4587a5ce56 100644 --- a/fpga/src/main/scala/vc709/HarnessBinders.scala +++ b/fpga/src/main/scala/vc709/HarnessBinders.scala @@ -7,13 +7,23 @@ import freechips.rocketchip.diplomacy.{NodeHandlePair} import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.tilelink.{TLBundle} +import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} -import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} import sifive.fpgashells.devices.xilinx.xilinxvc709pciex1.{HasSystemXilinxVC709PCIeX1ModuleImp, XilinxVC709PCIeX1IO} import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} import chipyard.harness.{OverrideHarnessBinder} +/*** I2C ***/ +class WithI2C extends OverrideHarnessBinder({ + (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => { + th match { case vc709th: VC709FPGATestHarnessImp => { + val io_i2c_bb_s = vc709th.vc709Outer.io_i2c_bb_s + (io_i2c_bb_s zip ports).map { case (io_i2c_bb, port) => io_i2c_bb.bundle <> port } + } } + } +}) + /*** UART ***/ class WithUART extends OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { diff --git a/fpga/src/main/scala/vc709/IOBinders.scala b/fpga/src/main/scala/vc709/IOBinders.scala new file mode 100644 index 0000000000..64cd6b91fe --- /dev/null +++ b/fpga/src/main/scala/vc709/IOBinders.scala @@ -0,0 +1,26 @@ +package chipyard.fpga.vc709 + +import chisel3._ +import chisel3.experimental.{IO, DataMirror} + +import freechips.rocketchip.diplomacy.{ResourceBinding, Resource, ResourceAddress, InModuleBody} +import freechips.rocketchip.subsystem.{BaseSubsystem} +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + +import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp} +import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice} +import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} + +import chipyard.{CanHaveMasterTLMemPort} +import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} + +class WithI2CIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryI2CModuleImp) => { + val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") } + (io_i2c_pins_temp zip system.i2c).map { case (io, sysio) => + io <> sysio + } + (io_i2c_pins_temp, Nil) + } +}) \ No newline at end of file diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala index c5f4e8d81b..052de49643 100644 --- a/fpga/src/main/scala/vc709/TestHarness.scala +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -14,11 +14,11 @@ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell._ import sifive.fpgashells.clocks._ +import sifive.blocks.devices.i2c._ import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ import sifive.blocks.devices.gpio._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, DigitalTop, ChipyardSystem, ExtTLMem, CanHaveMasterTLMemPort} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort} import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders} @@ -57,15 +57,29 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She } // DOC include end: ClockOverlay + /*** I2C ***/ + +// DOC include start: I2COverlay + + // All I2C goes to the VC709 dedicated I2C + val io_i2c_bb_s = dp(I2COverlayKey).zipWithIndex.map { + case (i2cOverlay, i) => + val io_i2c_bb = BundleBridgeSource(() => (new I2CPort())) + i2cOverlay.place(I2CDesignInput(io_i2c_bb)) + io_i2c_bb + } + +// DOC include end: I2COverlay + /*** UART ***/ // DOC include start: UartOverlay // All UART goes to the VC709 dedicated UART val io_uart_bb_s = (dp(UARTOverlayKey) zip dp(PeripheryUARTKey)).map { - case (uartOverlayKey, peripheryUARTKey) => - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(peripheryUARTKey))) - uartOverlayKey.place(UARTDesignInput(io_uart_bb)) + case (uartOverlay, uartParams) => + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(uartParams))) + uartOverlay.place(UARTDesignInput(io_uart_bb)) io_uart_bb } @@ -79,8 +93,8 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She var ddrDesignInput = DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL) val ddrClients = topDesign match { case td: ChipTop => td.lazySystem match { case lsys: CanHaveMasterTLMemPort => - (dp(DDROverlayKey) zip lsys.memTLNode.edges.in).map { case (ddrOverlayKey, edge) => - val ddtNode = ddrOverlayKey.place(ddrDesignInput).overlayOutput.ddr + (dp(DDROverlayKey) zip lsys.memTLNode.edges.in).map { case (ddrOverlay, edge) => + val ddtNode = ddrOverlay.place(ddrDesignInput).overlayOutput.ddr val ddrClient = TLClientNode(Seq(edge.master)) ddtNode := ddrClient ddrClient From 36c7d1e984e19bcce0a757ce86264dbfa3236a84 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Wed, 17 Mar 2021 17:17:19 +0800 Subject: [PATCH 19/27] remove unnecessary files --- .../resources/vc709/uartboot/Makefile-back | 72 ------------------ fpga/src/main/resources/vc709/uartsend/serial | Bin 18344 -> 0 bytes .../main/resources/vc709/uartsend/serial.o | Bin 9128 -> 0 bytes 3 files changed, 72 deletions(-) delete mode 100644 fpga/src/main/resources/vc709/uartboot/Makefile-back delete mode 100644 fpga/src/main/resources/vc709/uartsend/serial delete mode 100644 fpga/src/main/resources/vc709/uartsend/serial.o diff --git a/fpga/src/main/resources/vc709/uartboot/Makefile-back b/fpga/src/main/resources/vc709/uartboot/Makefile-back deleted file mode 100644 index 47694a0ef5..0000000000 --- a/fpga/src/main/resources/vc709/uartboot/Makefile-back +++ /dev/null @@ -1,72 +0,0 @@ -# RISCV environment variable must be set - -CC=$(RISCV)/bin/riscv64-unknown-elf-gcc -OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy -CFLAGS=-march=rv64imac -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles -CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0 -CFLAGS+= -I $(BOOTROM_DIR)/include -I. -LFLAGS=-static -nostdlib -L $(BOOTROM_DIR)/linker -T bootrom.elf.lds - -dts := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts -dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb -clk := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).tl_clock.h - -## device tree -$(clk): $(dts) - awk '/tlclk {/ && !f{f=1; next}; f && match($$0, /^.*clock-frequency.*<(.*)>.*/, arr) { print "#define TL_CLK " arr[1] "UL"}' $< > $@.tmp - mv $@.tmp $@ - -$(dtb): $(dts) - dtc -I dts -O dtb -o $@ $< - -.PHONY: dtb -dtb: $(dtb) - -## uart_boot -elf := $(BUILD_DIR)/bootrom.elf -$(elf): $(dtb) head.S crc16.c kprintf.c serial.c $(clk) - $(CC) $(CFLAGS) -include $(clk) -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ head.S crc16.c kprintf.c serial.c - -## sd_boot -# elf := $(BUILD_DIR)/bootrom.elf -# $(elf): $(dtb) head.S kprintf.c sd.c $(clk) - # $(CC) $(CFLAGS) -include $(clk) -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ head.S sd.c kprintf.c - -.PHONY: elf -elf: $(elf) - -bin := $(BUILD_DIR)/bootrom.bin -$(bin): $(elf) - $(OBJCOPY) -O binary $< $@ - -.PHONY: bin -bin: $(bin) - -hex := $(BUILD_DIR)/bootrom.hex -$(hex): $(bin) - od -t x4 -An -w4 -v $< > $@ - -.PHONY: hex -hex: $(hex) - -# # Berkeley Boot Loader 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fpga/src/main/scala/vc709/Configs.scala | 2 +- fpga/src/main/scala/vc709/DigitalTop.scala | 2 -- .../src/main/scala/vc709/HarnessBinders.scala | 10 ++++--- fpga/src/main/scala/vc709/TestHarness.scala | 28 +++++-------------- fpga/src/main/scala/vcu118/Configs.scala | 2 +- 5 files changed, 15 insertions(+), 29 deletions(-) diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index e93e654aa1..e832df33a6 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -20,8 +20,8 @@ import chipyard.{BuildTop, BuildSystem, ExtTLMem} import chipyard.fpga.vcu118.{WithUARTIOPassthrough, WithTLIOPassthrough, WithFPGAFrequency} class WithDefaultPeripherals extends Config((site, here, up) => { - case PeripheryI2CKey => List(I2CParams(address = BigInt(0x60000000L))) case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) + case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L))) }) class WithSystemModifications extends Config((site, here, up) => { diff --git a/fpga/src/main/scala/vc709/DigitalTop.scala b/fpga/src/main/scala/vc709/DigitalTop.scala index 8544e3d5c1..bb75a014fe 100644 --- a/fpga/src/main/scala/vc709/DigitalTop.scala +++ b/fpga/src/main/scala/vc709/DigitalTop.scala @@ -22,8 +22,6 @@ import sifive.fpgashells.clocks._ // DOC include start: VC709DigitalTop class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C - with freechips.rocketchip.subsystem.CanHaveMasterTLMMIOPort - with freechips.rocketchip.subsystem.CanHaveSlaveTLPort { def dp = p diff --git a/fpga/src/main/scala/vc709/HarnessBinders.scala b/fpga/src/main/scala/vc709/HarnessBinders.scala index 4587a5ce56..f79a4d074d 100644 --- a/fpga/src/main/scala/vc709/HarnessBinders.scala +++ b/fpga/src/main/scala/vc709/HarnessBinders.scala @@ -18,8 +18,9 @@ import chipyard.harness.{OverrideHarnessBinder} class WithI2C extends OverrideHarnessBinder({ (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => { th match { case vc709th: VC709FPGATestHarnessImp => { - val io_i2c_bb_s = vc709th.vc709Outer.io_i2c_bb_s - (io_i2c_bb_s zip ports).map { case (io_i2c_bb, port) => io_i2c_bb.bundle <> port } + require(ports.size == 1) + + vc709th.vc709Outer.io_i2c_bb.bundle <> ports.head } } } }) @@ -28,8 +29,9 @@ class WithI2C extends OverrideHarnessBinder({ class WithUART extends OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { th match { case vc709th: VC709FPGATestHarnessImp => { - val io_uart_bb_s = vc709th.vc709Outer.io_uart_bb_s - (io_uart_bb_s zip ports).map { case (io_uart_bb, port) => io_uart_bb.bundle <> port } + require(ports.size == 1) + + vc709th.vc709Outer.io_uart_bb.bundle <> ports.head } } } }) diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala index 052de49643..9ace0c19d4 100644 --- a/fpga/src/main/scala/vc709/TestHarness.scala +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -59,37 +59,24 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She /*** I2C ***/ -// DOC include start: I2COverlay - - // All I2C goes to the VC709 dedicated I2C - val io_i2c_bb_s = dp(I2COverlayKey).zipWithIndex.map { - case (i2cOverlay, i) => - val io_i2c_bb = BundleBridgeSource(() => (new I2CPort())) - i2cOverlay.place(I2CDesignInput(io_i2c_bb)) - io_i2c_bb - } + // 1st I2C goes to the VC709 dedicated I2C + val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) + dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) -// DOC include end: I2COverlay - /*** UART ***/ // DOC include start: UartOverlay + // 1st UART goes to the VC709 dedicated UART - // All UART goes to the VC709 dedicated UART - val io_uart_bb_s = (dp(UARTOverlayKey) zip dp(PeripheryUARTKey)).map { - case (uartOverlay, uartParams) => - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(uartParams))) - uartOverlay.place(UARTDesignInput(io_uart_bb)) - io_uart_bb - } - + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) + dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) // DOC include end: UartOverlay /*** DDR ***/ // DOC include start: DDR3Overlay - // All DDR3s use the same clock + var ddrDesignInput = DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL) val ddrClients = topDesign match { case td: ChipTop => td.lazySystem match { case lsys: CanHaveMasterTLMemPort => @@ -101,7 +88,6 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She } } } - // DOC include end: DDR3Overlay // module implementation diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index fa1999799b..8b17aa98e6 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -52,7 +52,7 @@ class WithVCU118Tweaks extends Config( new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(2)) + new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) class RocketVCU118Config extends Config( new WithVCU118Tweaks ++ From 8ea6d38885dacc6527295bdf1666b758d8c1f8c0 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Wed, 17 Mar 2021 17:52:38 +0800 Subject: [PATCH 21/27] update support for one DDR3 controller --- fpga/src/main/scala/vc709/TestHarness.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala index 9ace0c19d4..cb2214e291 100644 --- a/fpga/src/main/scala/vc709/TestHarness.scala +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -76,7 +76,7 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She // DOC include start: DDR3Overlay // All DDR3s use the same clock - + var ddrDesignInput = DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL) val ddrClients = topDesign match { case td: ChipTop => td.lazySystem match { case lsys: CanHaveMasterTLMemPort => From 0959757b030ad485c533378f69a62a20a7730534 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Sat, 20 Mar 2021 16:03:06 +0800 Subject: [PATCH 22/27] updata support for GPIO in vc709 --- fpga/src/main/scala/vc709/Configs.scala | 29 ++++++++++---- .../src/main/scala/vc709/CustomOverlays.scala | 22 +++++++++++ fpga/src/main/scala/vc709/DigitalTop.scala | 22 ++++++++++- fpga/src/main/scala/vc709/GPIOs.scala | 38 +++++++++++++++++++ .../src/main/scala/vc709/HarnessBinders.scala | 12 ++++++ fpga/src/main/scala/vc709/TestHarness.scala | 10 +++++ 6 files changed, 124 insertions(+), 9 deletions(-) create mode 100644 fpga/src/main/scala/vc709/GPIOs.scala diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index e832df33a6..a7d5066526 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -3,30 +3,38 @@ package chipyard.fpga.vc709 import sys.process._ import freechips.rocketchip.config.{Config, Parameters} -import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} -import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} -import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} +import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem, WithJtagDTM} +import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG, JtagDTMKey, JtagDTMConfig} +import freechips.rocketchip.devices.tilelink.{DevNullParams, BuiltInErrorDeviceParams, BootROMLocated} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} import freechips.rocketchip.tile.{XLen} import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} +import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} import sifive.fpgashells.shell.{DesignKey} import testchipip.{SerialTLKey} -import chipyard.{BuildTop, BuildSystem, ExtTLMem} +import chipyard.{BuildTop, BuildSystem, ExtTLMem} import chipyard.fpga.vcu118.{WithUARTIOPassthrough, WithTLIOPassthrough, WithFPGAFrequency} +import chipyard.fpga.vcu118.bringup.{WithI2CIOPassthrough, WithGPIOIOPassthrough} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) + case PeripheryGPIOKey => List(GPIOParams(address = BigInt(0x64002000L), width = 21)) case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L))) }) class WithSystemModifications extends Config((site, here, up) => { case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) case DTSTimebase => BigInt(1000000) + // case JtagDTMKey => new JtagDTMConfig ( + // idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai). + // idcodePartNum = 0x000, // Decided to simplify. + // idcodeManufId = 0x489, // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses. + // debugIdleCycles = 5) // Reasonable guess for synchronization case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => // invoke makefile for uart boot val freqMHz = site(FPGAFrequencyKey).toInt * 1000000 @@ -40,17 +48,20 @@ class WithSystemModifications extends Config((site, here, up) => { // DOC include start: AbstractVC709 and Rocket class WithVC709Tweaks extends Config( - new WithI2C ++ new WithUART ++ + new WithI2C ++ + new WithGPIO ++ new WithDDRMem ++ - new WithI2CIOPassthrough ++ new WithUARTIOPassthrough ++ + new WithI2CIOPassthrough ++ + new WithGPIOIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size new chipyard.config.WithTLBackingMemory ++ // use TL backing memory new chipyard.config.WithNoDebug ++ // remove debug module new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink + // new freechips.rocketchip.subsystem.WithJtagDTM ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) @@ -58,10 +69,14 @@ class WithVC709System extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => new VC709DigitalTop()(p) }) +class OctoRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithNBigCores(8) ++ // quad-core (4 RocketTiles) + new chipyard.config.AbstractConfig) + class RocketVC709Config extends Config( new WithVC709System ++ new WithVC709Tweaks ++ - new chipyard.QuadRocketConfig) + new OctoRocketConfig) // DOC include end: AbstractVC709 and Rocket class QuadSmallBoomConfig extends Config( diff --git a/fpga/src/main/scala/vc709/CustomOverlays.scala b/fpga/src/main/scala/vc709/CustomOverlays.scala index 8c7cee7f19..95bae63e06 100644 --- a/fpga/src/main/scala/vc709/CustomOverlays.scala +++ b/fpga/src/main/scala/vc709/CustomOverlays.scala @@ -30,6 +30,28 @@ class MemClockVC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: C def place(designInput: ClockInputDesignInput) = new MemClockVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } +class GPIOVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String]) + extends GPIOXilinxPlacedOverlay(name, designInput, shellInput) +{ + shell { InModuleBody { + require(gpioNames.length == io.gpio.length) + + val packagePinsWithIOStdWithPackageIOs = (gpioNames zip io.gpio).map { case (name, io) => + val (pin, iostd) = GPIOs.pinMapping(name) + (pin, iostd, IOPin(io)) + } + + packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, iostd) + } } + } } +} +class GPIOVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName) + extends GPIOShellPlacer[VC709ShellBasicOverlays] { + def place(designInput: GPIODesignInput) = new GPIOVC709PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) +} + case object VC709DDR3Size extends Field[BigInt](0x100000000L) // 4GB class DualDDR3VC709PlacedOverlay(val shell: VC709FPGATestHarness, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput) extends DDR3XilinxPlacedOverlay(shell, name, designInput, shellInput) diff --git a/fpga/src/main/scala/vc709/DigitalTop.scala b/fpga/src/main/scala/vc709/DigitalTop.scala index bb75a014fe..e22dd6d037 100644 --- a/fpga/src/main/scala/vc709/DigitalTop.scala +++ b/fpga/src/main/scala/vc709/DigitalTop.scala @@ -1,9 +1,11 @@ package chipyard.fpga.vc709 import chisel3._ +import chisel3.util._ -import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.debug._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ @@ -12,9 +14,18 @@ import freechips.rocketchip.interrupts._ import chipyard.{DigitalTop, DigitalTopModule} +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.pinctrl.{BasePin} + import sifive.fpgashells.shell._ import sifive.fpgashells.clocks._ +object PinGen { + def apply(): BasePin = { + new BasePin() + } +} + // ------------------------------------ // VC709 DigitalTop // ------------------------------------ @@ -22,6 +33,7 @@ import sifive.fpgashells.clocks._ // DOC include start: VC709DigitalTop class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C + with freechips.rocketchip.devices.debug.HasPeripheryDebug { def dp = p @@ -34,13 +46,18 @@ class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLLNode <-- ClockSourceNode memClock := memWrangler.node := memGroup := harnessMemPLL := memClkNode + + // Work-around for a kernel bug (command-line ignored if /chosen missing) + val chosen = new DeviceSnippet { + def describe() = Description("chosen", Map()) + } /*** PCIe dutWrangler.node, harnessSysPLL ***/ p(PCIeOverlayKey).zipWithIndex.map { case (key, i) => val overlayOutput = key.place(PCIeDesignInput(wrangler=memWrangler.node, corePLL=harnessMemPLL)).overlayOutput val (pcieNode: TLNode, intNode: IntOutwardNode) = (overlayOutput.pcieNode, overlayOutput.intNode) val (slaveTLNode: TLIdentityNode, masterTLNode: TLAsyncSinkNode) = (pcieNode.inward, pcieNode.outward) - fbus.coupleFrom(s"master_named_pcie${i}"){ _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* masterTLNode } + fbus.coupleFrom(s"master_named_pcie${i}"){ _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* TLBuffer() :=* masterTLNode } pbus.coupleTo(s"slave_named_pcie${i}"){ slaveTLNode :*= TLWidthWidget(pbus.beatBytes) :*= _ } ibus.fromSync := intNode } @@ -50,4 +67,5 @@ class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop class VC709DigitalTopModule[+L <: VC709DigitalTop](l: L) extends DigitalTopModule(l) with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp + with freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp // DOC include end: VC709DigitalTop \ No newline at end of file diff --git a/fpga/src/main/scala/vc709/GPIOs.scala b/fpga/src/main/scala/vc709/GPIOs.scala new file mode 100644 index 0000000000..0dc9950d31 --- /dev/null +++ b/fpga/src/main/scala/vc709/GPIOs.scala @@ -0,0 +1,38 @@ +package chipyard.fpga.vc709 + +import scala.collection.mutable.{LinkedHashMap} + +object GPIOs { + + // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD) + val pinMapping = LinkedHashMap( + // these connect to LEDs and switches on the VC709 (and use 1.8V) + "led0" -> ("AM39", "LVCMOS18"), // 0 + "led1" -> ("AN39", "LVCMOS18"), // 1 + "led2" -> ("AR37", "LVCMOS18"), // 2 + "led3" -> ("AT37", "LVCMOS18"), // 3 + "led4" -> ("AR35", "LVCMOS18"), // 4 + "led5" -> ("AP41", "LVCMOS18"), // 5 + "led6" -> ("AP42", "LVCMOS18"), // 6 + "led7" -> ("AU39", "LVCMOS18"), // 7 + "sw_n" -> ("AR40", "LVCMOS18"), // N + "sw_e" -> ("AU38", "LVCMOS18"), // E + "sw_s" -> ("AP40", "LVCMOS18"), // S + "sw_w" -> ("AW40", "LVCMOS18"), // W + "sw_c" -> ("AV39", "LVCMOS18"), // C + "sw_0" -> ("AV30", "LVCMOS18"), // 0 + "sw_1" -> ("AY33", "LVCMOS18"), // 1 + "sw_2" -> ("BA31", "LVCMOS18"), // 2 + "sw_3" -> ("BA32", "LVCMOS18"), // 3 + "sw_4" -> ("AW30", "LVCMOS18"), // 4 + "sw_5" -> ("AY30", "LVCMOS18"), // 5 + "sw_6" -> ("BA30", "LVCMOS18"), // 6 + "sw_7" -> ("BB31", "LVCMOS18") // 7 + ) + + // return list of names (ordered) + def names: Seq[String] = pinMapping.keys.toSeq + + // return number of GPIOs + def width: Int = pinMapping.size +} diff --git a/fpga/src/main/scala/vc709/HarnessBinders.scala b/fpga/src/main/scala/vc709/HarnessBinders.scala index f79a4d074d..a9053ce8a4 100644 --- a/fpga/src/main/scala/vc709/HarnessBinders.scala +++ b/fpga/src/main/scala/vc709/HarnessBinders.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} +import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} import sifive.fpgashells.devices.xilinx.xilinxvc709pciex1.{HasSystemXilinxVC709PCIeX1ModuleImp, XilinxVC709PCIeX1IO} import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} @@ -36,6 +37,17 @@ class WithUART extends OverrideHarnessBinder({ } }) +/*** GPIO ***/ +class WithGPIO extends OverrideHarnessBinder({ + (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { + th match { case vc709th: VC709FPGATestHarnessImp => { + require(ports.size == 1) + + vc709th.vc709Outer.io_gpio_bb.bundle <> ports.head + } } + } +}) + /*** Experimental DDR ***/ class WithDDRMem extends OverrideHarnessBinder({ (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala index cb2214e291..a8f6eccd94 100644 --- a/fpga/src/main/scala/vc709/TestHarness.scala +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -29,6 +29,7 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She def dp = designParameters // Order matters; ddr depends on sys_clock + val gpio = Overlay(GPIOOverlayKey, new GPIOVC709ShellPlacer(this, GPIOShellInput(), GPIOs.names)) val mem_clock = Overlay(ClockInputOverlayKey, new MemClockVC709ShellPlacer(this, ClockInputShellInput())) // val ddr1 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) @@ -72,6 +73,15 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) // DOC include end: UartOverlay + /*** LEDs / GPIO ***/ +// DOC include start: GPIOOverlay + // 1st GPIO goes to the VC709 dedicated GPIO + + val gpioParams = dp(PeripheryGPIOKey).head + val io_gpio_bb = BundleBridgeSource(() => (new GPIOPortIO(gpioParams))) + dp(GPIOOverlayKey).head.place(GPIODesignInput(gpioParams, io_gpio_bb)) +// DOC include end: GPIOOverlay + /*** DDR ***/ // DOC include start: DDR3Overlay From 52f5f3d49cd141f3a5c3d625b8aa1baa0bc74c6a Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Thu, 25 Mar 2021 20:36:17 +0800 Subject: [PATCH 23/27] update support for vc709 board --- fpga/src/main/scala/vc709/Configs.scala | 8 +------ fpga/src/main/scala/vc709/IOBinders.scala | 26 ----------------------- 2 files changed, 1 insertion(+), 33 deletions(-) delete mode 100644 fpga/src/main/scala/vc709/IOBinders.scala diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index a7d5066526..db526e7eef 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -30,11 +30,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => { class WithSystemModifications extends Config((site, here, up) => { case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) case DTSTimebase => BigInt(1000000) - // case JtagDTMKey => new JtagDTMConfig ( - // idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai). - // idcodePartNum = 0x000, // Decided to simplify. - // idcodeManufId = 0x489, // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses. - // debugIdleCycles = 5) // Reasonable guess for synchronization case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => // invoke makefile for uart boot val freqMHz = site(FPGAFrequencyKey).toInt * 1000000 @@ -61,7 +56,6 @@ class WithVC709Tweaks extends Config( new chipyard.config.WithTLBackingMemory ++ // use TL backing memory new chipyard.config.WithNoDebug ++ // remove debug module new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink - // new freechips.rocketchip.subsystem.WithJtagDTM ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) @@ -70,7 +64,7 @@ class WithVC709System extends Config((site, here, up) => { }) class OctoRocketConfig extends Config( - new freechips.rocketchip.subsystem.WithNBigCores(8) ++ // quad-core (4 RocketTiles) + new freechips.rocketchip.subsystem.WithNBigCores(8) ++ // Octo-core (4 RocketTiles) new chipyard.config.AbstractConfig) class RocketVC709Config extends Config( diff --git a/fpga/src/main/scala/vc709/IOBinders.scala b/fpga/src/main/scala/vc709/IOBinders.scala deleted file mode 100644 index 64cd6b91fe..0000000000 --- a/fpga/src/main/scala/vc709/IOBinders.scala +++ /dev/null @@ -1,26 +0,0 @@ -package chipyard.fpga.vc709 - -import chisel3._ -import chisel3.experimental.{IO, DataMirror} - -import freechips.rocketchip.diplomacy.{ResourceBinding, Resource, ResourceAddress, InModuleBody} -import freechips.rocketchip.subsystem.{BaseSubsystem} -import freechips.rocketchip.util.{HeterogeneousBag} -import freechips.rocketchip.tilelink.{TLBundle} - -import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp} -import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice} -import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} - -import chipyard.{CanHaveMasterTLMemPort} -import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} - -class WithI2CIOPassthrough extends OverrideIOBinder({ - (system: HasPeripheryI2CModuleImp) => { - val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") } - (io_i2c_pins_temp zip system.i2c).map { case (io, sysio) => - io <> sysio - } - (io_i2c_pins_temp, Nil) - } -}) \ No newline at end of file From d97e5d771d793b5a57e840445fe5a3201fca0ae5 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Mon, 29 Mar 2021 13:38:23 +0800 Subject: [PATCH 24/27] Update and rename gpoi.c to gpio.c --- fpga/src/main/resources/vc709/uartboot/gpio.c | 1 + fpga/src/main/resources/vc709/uartboot/gpoi.c | 9 --------- 2 files changed, 1 insertion(+), 9 deletions(-) create mode 100644 fpga/src/main/resources/vc709/uartboot/gpio.c delete mode 100644 fpga/src/main/resources/vc709/uartboot/gpoi.c diff --git a/fpga/src/main/resources/vc709/uartboot/gpio.c b/fpga/src/main/resources/vc709/uartboot/gpio.c new file mode 100644 index 0000000000..159bede78f --- /dev/null +++ b/fpga/src/main/resources/vc709/uartboot/gpio.c @@ -0,0 +1 @@ +#include "gpio.h" diff --git a/fpga/src/main/resources/vc709/uartboot/gpoi.c b/fpga/src/main/resources/vc709/uartboot/gpoi.c deleted file mode 100644 index 14783690f7..0000000000 --- a/fpga/src/main/resources/vc709/uartboot/gpoi.c +++ /dev/null @@ -1,9 +0,0 @@ -/* - * @,@Author: ,: your name - * @,@Date: ,: 1970-01-01 08:00:00 - * @,@LastEditTime: ,: 2021-01-15 19:06:26 - * @,@LastEditors: ,: Please set LastEditors - * @,@Description: ,: In User Settings Edit - * @,@FilePath: ,: /freedom/bootrom/sdboot/gpoi.c - */ -#include "gpio.h" \ No newline at end of file From 49db3be249edc44c0392f79c1fa7131b884490a7 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Mon, 29 Mar 2021 13:49:15 +0800 Subject: [PATCH 25/27] Update Configs.scala WithTLBackingMemory is moved to the front of WithSystemModifications so that the size of ExtMem is updated and in effect. --- fpga/src/main/scala/vc709/Configs.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index db526e7eef..7751313094 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -52,8 +52,8 @@ class WithVC709Tweaks extends Config( new WithGPIOIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ - new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size new chipyard.config.WithTLBackingMemory ++ // use TL backing memory + new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size new chipyard.config.WithNoDebug ++ // remove debug module new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink new freechips.rocketchip.subsystem.WithoutTLMonitors ++ @@ -64,7 +64,7 @@ class WithVC709System extends Config((site, here, up) => { }) class OctoRocketConfig extends Config( - new freechips.rocketchip.subsystem.WithNBigCores(8) ++ // Octo-core (4 RocketTiles) + new freechips.rocketchip.subsystem.WithNBigCores(8) ++ // Octo-core (8 RocketTiles) new chipyard.config.AbstractConfig) class RocketVC709Config extends Config( From a5e2c135f0a40c1e5aed128996350426fd9538f3 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Wed, 31 Mar 2021 20:34:59 +0800 Subject: [PATCH 26/27] update UART support for vc709 --- .../resources/vc709/uartboot/include/crc16.h | 8 --- .../vc709/uartboot/include/devices/gpio.h | 8 --- .../vc709/uartboot/include/devices/plic.h | 8 --- .../vc709/uartboot/include/devices/uart.h | 8 --- .../vc709/uartboot/include/kprintf.h | 8 --- .../vc709/uartboot/include/platform.h | 8 --- .../resources/vc709/uartboot/include/serial.h | 9 ---- fpga/src/main/scala/vc709/Configs.scala | 22 +++------ .../src/main/scala/vc709/CustomOverlays.scala | 4 +- fpga/src/main/scala/vc709/DigitalTop.scala | 49 ++++++++++--------- fpga/src/main/scala/vc709/TestHarness.scala | 9 +--- 11 files changed, 37 insertions(+), 104 deletions(-) diff --git a/fpga/src/main/resources/vc709/uartboot/include/crc16.h b/fpga/src/main/resources/vc709/uartboot/include/crc16.h index 8c84748f70..fb63c02cdd 100644 --- a/fpga/src/main/resources/vc709/uartboot/include/crc16.h +++ b/fpga/src/main/resources/vc709/uartboot/include/crc16.h @@ -1,11 +1,3 @@ -/* - * @,@Author: ,: your name - * @,@Date: ,: 1970-01-01 08:00:00 - * @,@LastEditTime: ,: 2021-01-30 12:11:45 - * @,@LastEditors: ,: Please set LastEditors - * @,@Description: ,: In User Settings Edit - * @,@FilePath: ,: /freedom/bootrom/sdboot/include/crc16.h - */ #include #define CRC16_BITS 12 diff --git a/fpga/src/main/resources/vc709/uartboot/include/devices/gpio.h b/fpga/src/main/resources/vc709/uartboot/include/devices/gpio.h index 8ff5cb5d34..f7f0acb40f 100644 --- a/fpga/src/main/resources/vc709/uartboot/include/devices/gpio.h +++ b/fpga/src/main/resources/vc709/uartboot/include/devices/gpio.h @@ -1,11 +1,3 @@ -/* - * @,@Author: ,: your name - * @,@Date: ,: 1970-01-01 08:00:00 - * @,@LastEditTime: ,: 2021-01-15 20:05:40 - * @,@LastEditors: ,: Please set LastEditors - * @,@Description: ,: In User Settings Edit - * @,@FilePath: ,: /freedom/mnt/D/Ubuntu/projects/freedom/bootrom/sdboot/include/devices/gpio.h - */ // See LICENSE for license details. #ifndef _SIFIVE_GPIO_H diff --git a/fpga/src/main/resources/vc709/uartboot/include/devices/plic.h b/fpga/src/main/resources/vc709/uartboot/include/devices/plic.h index feb7f199c3..5894ebacf3 100644 --- a/fpga/src/main/resources/vc709/uartboot/include/devices/plic.h +++ b/fpga/src/main/resources/vc709/uartboot/include/devices/plic.h @@ -1,11 +1,3 @@ -/* - * @,@Author: ,: your name - * @,@Date: ,: 1970-01-01 08:00:00 - * @,@LastEditTime: ,: 2021-01-26 13:14:09 - * @,@LastEditors: ,: Please set LastEditors - * @,@Description: ,: In User Settings Edit - * @,@FilePath: ,: /freedom/mnt/D/Ubuntu/projects/freedom/bootrom/sdboot/include/devices/plic.h - */ // See LICENSE for license details. #ifndef PLIC_H diff --git a/fpga/src/main/resources/vc709/uartboot/include/devices/uart.h b/fpga/src/main/resources/vc709/uartboot/include/devices/uart.h index f7ce659b87..32d31b6846 100644 --- a/fpga/src/main/resources/vc709/uartboot/include/devices/uart.h +++ b/fpga/src/main/resources/vc709/uartboot/include/devices/uart.h @@ -1,11 +1,3 @@ -/* - * @,@Author: ,: your name - * @,@Date: ,: 1970-01-01 08:00:00 - * @,@LastEditTime: ,: 2021-01-24 11:08:33 - * @,@LastEditors: ,: Please set LastEditors - * @,@Description: ,: In User Settings Edit - * @,@FilePath: ,: /freedom/bootrom/sdboot/include/devices/uart.h - */ // See LICENSE for license details. #ifndef _SIFIVE_UART_H diff --git a/fpga/src/main/resources/vc709/uartboot/include/kprintf.h b/fpga/src/main/resources/vc709/uartboot/include/kprintf.h index c2b4f7b4bf..c3bfb24cc8 100644 --- a/fpga/src/main/resources/vc709/uartboot/include/kprintf.h +++ b/fpga/src/main/resources/vc709/uartboot/include/kprintf.h @@ -1,11 +1,3 @@ -/* - * @,@Author: ,: your name - * @,@Date: ,: 1970-01-01 08:00:00 - * @,@LastEditTime: ,: 2021-01-26 13:18:40 - * @,@LastEditors: ,: Please set LastEditors - * @,@Description: ,: In User Settings Edit - * @,@FilePath: ,: /freedom/mnt/D/Ubuntu/projects/freedom/bootrom/sdboot/kprintf.h - */ // See LICENSE for license details. #ifndef _SDBOOT_KPRINTF_H #define _SDBOOT_KPRINTF_H diff --git a/fpga/src/main/resources/vc709/uartboot/include/platform.h b/fpga/src/main/resources/vc709/uartboot/include/platform.h index e1549cf65e..73052bd94b 100644 --- a/fpga/src/main/resources/vc709/uartboot/include/platform.h +++ b/fpga/src/main/resources/vc709/uartboot/include/platform.h @@ -1,11 +1,3 @@ -/* - * @,@Author: ,: your name - * @,@Date: ,: 1970-01-01 08:00:00 - * @,@LastEditTime: ,: 2021-01-23 21:51:27 - * @,@LastEditors: ,: your name - * @,@Description: ,: In User Settings Edit - * @,@FilePath: ,: /freedom/mnt/D/Ubuntu/projects/freedom/bootrom/sdboot/include/platform.h - */ // See LICENSE for license details. #ifndef _SIFIVE_PLATFORM_H diff --git a/fpga/src/main/resources/vc709/uartboot/include/serial.h b/fpga/src/main/resources/vc709/uartboot/include/serial.h index c0f36e0c37..aa2788299f 100644 --- a/fpga/src/main/resources/vc709/uartboot/include/serial.h +++ b/fpga/src/main/resources/vc709/uartboot/include/serial.h @@ -1,12 +1,3 @@ -/* - * @,@Author: ,: your name - * @,@Date: ,: 1970-01-01 08:00:00 - * @,@LastEditTime: ,: 2021-01-30 11:45:36 - * @,@LastEditors: ,: Please set LastEditors - * @,@Description: ,: In User Settings Edit - * @,@FilePath: ,: /freedom/bootrom/sdboot/include/serial_boot.h - */ - #ifndef __SERIAL_BOOT_ #define __SERIAL_BOOT_ diff --git a/fpga/src/main/scala/vc709/Configs.scala b/fpga/src/main/scala/vc709/Configs.scala index db526e7eef..441f40fe9c 100644 --- a/fpga/src/main/scala/vc709/Configs.scala +++ b/fpga/src/main/scala/vc709/Configs.scala @@ -3,9 +3,8 @@ package chipyard.fpga.vc709 import sys.process._ import freechips.rocketchip.config.{Config, Parameters} -import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem, WithJtagDTM} -import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG, JtagDTMKey, JtagDTMConfig} -import freechips.rocketchip.devices.tilelink.{DevNullParams, BuiltInErrorDeviceParams, BootROMLocated} +import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} +import freechips.rocketchip.devices.tilelink.{BootROMLocated} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} import freechips.rocketchip.tile.{XLen} @@ -14,7 +13,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} import sifive.fpgashells.shell.{DesignKey} - +import sifive.fpgashells.shell.xilinx.{VC709DDR3Size} import testchipip.{SerialTLKey} import chipyard.{BuildTop, BuildSystem, ExtTLMem} @@ -22,7 +21,7 @@ import chipyard.fpga.vcu118.{WithUARTIOPassthrough, WithTLIOPassthrough, WithFPG import chipyard.fpga.vcu118.bringup.{WithI2CIOPassthrough, WithGPIOIOPassthrough} class WithDefaultPeripherals extends Config((site, here, up) => { - case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) + case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L), nTxEntries = 256, nRxEntries = 256)) case PeripheryGPIOKey => List(GPIOParams(address = BigInt(0x64002000L), width = 21)) case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L))) }) @@ -52,10 +51,9 @@ class WithVC709Tweaks extends Config( new WithGPIOIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ - new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size new chipyard.config.WithTLBackingMemory ++ // use TL backing memory + new WithSystemModifications ++ // setup busses, use uart bootrom, setup ext. mem. size new chipyard.config.WithNoDebug ++ // remove debug module - new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) @@ -63,17 +61,13 @@ class WithVC709System extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => new VC709DigitalTop()(p) }) -class OctoRocketConfig extends Config( - new freechips.rocketchip.subsystem.WithNBigCores(8) ++ // Octo-core (4 RocketTiles) - new chipyard.config.AbstractConfig) - class RocketVC709Config extends Config( new WithVC709System ++ new WithVC709Tweaks ++ - new OctoRocketConfig) + new chipyard.RocketConfig) // DOC include end: AbstractVC709 and Rocket -class QuadSmallBoomConfig extends Config( +class SmallLargeBoomConfig extends Config( new boom.common.WithNSmallBooms(4) ++ // 4 boom cores new chipyard.config.AbstractConfig) @@ -81,4 +75,4 @@ class BoomVC709Config extends Config( new WithFPGAFrequency(50) ++ new WithVC709System ++ new WithVC709Tweaks ++ - new QuadSmallBoomConfig) + new SmallLargeBoomConfig) diff --git a/fpga/src/main/scala/vc709/CustomOverlays.scala b/fpga/src/main/scala/vc709/CustomOverlays.scala index 95bae63e06..5081310ad1 100644 --- a/fpga/src/main/scala/vc709/CustomOverlays.scala +++ b/fpga/src/main/scala/vc709/CustomOverlays.scala @@ -52,7 +52,6 @@ class GPIOVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: G def place(designInput: GPIODesignInput) = new GPIOVC709PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) } -case object VC709DDR3Size extends Field[BigInt](0x100000000L) // 4GB class DualDDR3VC709PlacedOverlay(val shell: VC709FPGATestHarness, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput) extends DDR3XilinxPlacedOverlay(shell, name, designInput, shellInput) { @@ -91,8 +90,7 @@ class DualDDR3VC709PlacedOverlay(val shell: VC709FPGATestHarness, name: String, port.aresetn := !ar.reset } } - shell.sdc.addGroup(clocks = Seq("clk_pll_i")) - // shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) + shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) } class DualDDR3VC709ShellPlacer(shell: VC709FPGATestHarness, val shellInput: DDRShellInput)(implicit val valName: ValName) extends DDRShellPlacer[VC709FPGATestHarness] { diff --git a/fpga/src/main/scala/vc709/DigitalTop.scala b/fpga/src/main/scala/vc709/DigitalTop.scala index e22dd6d037..6d87e9dc83 100644 --- a/fpga/src/main/scala/vc709/DigitalTop.scala +++ b/fpga/src/main/scala/vc709/DigitalTop.scala @@ -26,42 +26,45 @@ object PinGen { } } -// ------------------------------------ -// VC709 DigitalTop -// ------------------------------------ - -// DOC include start: VC709DigitalTop -class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop - with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C - with freechips.rocketchip.devices.debug.HasPeripheryDebug -{ - def dp = p - - /*** The second clock goes to the second DDR ***/ - val memClkNode = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node - val harnessMemPLL = dp(PLLFactoryKey)() +trait HasXilinxVC709PCIe { this: BaseSubsystem => + /*** The second clock goes to the PCIe ***/ + val memClkNode = p(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node + val harnessMemPLL = p(PLLFactoryKey)() val memGroup = ClockGroup() val memWrangler = LazyModule(new ResetWrangler) - val memClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + val memClock = ClockSinkNode(freqMHz = p(FPGAFrequencyKey)) - // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLLNode <-- ClockSourceNode memClock := memWrangler.node := memGroup := harnessMemPLL := memClkNode - - // Work-around for a kernel bug (command-line ignored if /chosen missing) - val chosen = new DeviceSnippet { - def describe() = Description("chosen", Map()) - } - /*** PCIe dutWrangler.node, harnessSysPLL ***/ + /*** Instantiate PCIe Module ***/ p(PCIeOverlayKey).zipWithIndex.map { case (key, i) => val overlayOutput = key.place(PCIeDesignInput(wrangler=memWrangler.node, corePLL=harnessMemPLL)).overlayOutput val (pcieNode: TLNode, intNode: IntOutwardNode) = (overlayOutput.pcieNode, overlayOutput.intNode) val (slaveTLNode: TLIdentityNode, masterTLNode: TLAsyncSinkNode) = (pcieNode.inward, pcieNode.outward) - fbus.coupleFrom(s"master_named_pcie${i}"){ _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* TLBuffer() :=* masterTLNode } + fbus.coupleFrom(s"master_named_pcie${i}"){ _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* masterTLNode } pbus.coupleTo(s"slave_named_pcie${i}"){ slaveTLNode :*= TLWidthWidget(pbus.beatBytes) :*= _ } ibus.fromSync := intNode } +} +trait HasChosenNodeInDTS { this: BaseSubsystem => + // Work-around for a kernel bug (command-line ignored if /chosen missing) + val chosen = new DeviceSnippet { + def describe() = Description("chosen", Map()) + } +} + +// ------------------------------------ +// VC709 DigitalTop +// ------------------------------------ + +// DOC include start: VC709DigitalTop +class VC709DigitalTop()(implicit p: Parameters) extends DigitalTop + with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C + with freechips.rocketchip.devices.debug.HasPeripheryDebug + with HasXilinxVC709PCIe + with HasChosenNodeInDTS +{ override lazy val module = new VC709DigitalTopModule(this) } diff --git a/fpga/src/main/scala/vc709/TestHarness.scala b/fpga/src/main/scala/vc709/TestHarness.scala index a8f6eccd94..c41a2f5324 100644 --- a/fpga/src/main/scala/vc709/TestHarness.scala +++ b/fpga/src/main/scala/vc709/TestHarness.scala @@ -29,8 +29,8 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She def dp = designParameters // Order matters; ddr depends on sys_clock - val gpio = Overlay(GPIOOverlayKey, new GPIOVC709ShellPlacer(this, GPIOShellInput(), GPIOs.names)) val mem_clock = Overlay(ClockInputOverlayKey, new MemClockVC709ShellPlacer(this, ClockInputShellInput())) + val gpio = Overlay(GPIOOverlayKey, new GPIOVC709ShellPlacer(this, GPIOShellInput(), GPIOs.names)) // val ddr1 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") @@ -48,14 +48,9 @@ class VC709FPGATestHarness(override implicit val p: Parameters) extends VC709She val dutGroup = ClockGroup() val dutWrangler = LazyModule(new ResetWrangler) val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) - // ClockSinkNode <-- ResetWrangler <-- ClockGroup <-- PLLNode <-- ClockSourceNode + dutClock := dutWrangler.node := dutGroup := harnessSysPLL := sysClkNode - val (memWrangler, harnessMemPLL) = topDesign match { case td: ChipTop => - td.lazySystem match { case lsys: VC709DigitalTop => - (lsys.memWrangler, lsys.harnessMemPLL) - } - } // DOC include end: ClockOverlay /*** I2C ***/ From d26e1c32e8445c42841c9d29e00075aa0f3fbdef Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Wed, 31 Mar 2021 20:50:21 +0800 Subject: [PATCH 27/27] Update platform.h update MEMORY_MEM_SIZE --- fpga/src/main/resources/vc709/uartboot/include/platform.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/resources/vc709/uartboot/include/platform.h b/fpga/src/main/resources/vc709/uartboot/include/platform.h index 73052bd94b..b60fc9b1b1 100644 --- a/fpga/src/main/resources/vc709/uartboot/include/platform.h +++ b/fpga/src/main/resources/vc709/uartboot/include/platform.h @@ -43,7 +43,7 @@ #define MASKROM_MEM_ADDR _AC(0x10000,UL) #define MASKROM_MEM_SIZE _AC(0x2000,UL) #define MEMORY_MEM_ADDR _AC(0x80000000,UL) -#define MEMORY_MEM_SIZE _AC(0x40000000,UL) +#define MEMORY_MEM_SIZE _AC(0x100000000,UL) #define PLIC_CTRL_ADDR _AC(0xc000000,UL) #define PLIC_CTRL_SIZE _AC(0x4000000,UL) #define SPI_CTRL_ADDR _AC(0x64001000,UL)