Target TCL openOCD configuration file for HiFi4

[jorgeventura]

I need the target openOCD configuration file for the DSP core xtensa HiFi4. I figured out that only the manufacturer can provide such file. I am using a very minimal file create just to identify the core but full details I don't have.

Any help will be very appreciated.

Below are the messages from openOCD:

Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : If you need SWD support, flash KT-Link buffer from https://github.com/bharrisau/busblaster
and use dp_busblaster_kt-link.cfg instead
Info : xtensa permissive mode is enabled
--- Config loaded. Running 'init' ---
Warn : [xtensa] Register count MISMATCH: 0 core regs, 0 extended regs; 16 expected
Info : clock speed 1000 kHz
Info : JTAG tap: xtensa.cpu tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Error: XTensa core not configured; is xtensa-core-openocd.cfg missing?
Warn : target xtensa examination failed
Info : starting gdb server for xtensa on 3333
Info : Listening on port 3333 for gdb connections

Additionally the telnet to openOCD:

Open On-Chip Debugger
> scan_chain
scan_chain
TapName Enabled IdCode Expected IrLen IrCap IrMask

---

0 xtensa.cpu Y 0x120034e5 0x120034e5 5 0x01 0x03
0x120134e5
0x209034e5
0x209134e5
0x209234e5
0x209334e5
0x209434e5
0x209534e5
0x209634e5
0x209734e5
0x20a034e5
0x20a134e5
0x20a234e5
0x20a334e5
0x20a434e5
0x20a534e5
0x20a634e5
0x20a734e5
0x20a834e5
0x20b034e5

> targets
targets
TargetName Type Endian TapName State

---

0* xtensa xtensa little xtensa.cpu running