diff --git a/en/key_stone/k1/k1_docs/k1_usermanual/15.High-Speed_Interface_System.md b/en/key_stone/k1/k1_docs/k1_usermanual/15.High-Speed_Interface_System.md index 98c7816..8d7afb8 100644 --- a/en/key_stone/k1/k1_docs/k1_usermanual/15.High-Speed_Interface_System.md +++ b/en/key_stone/k1/k1_docs/k1_usermanual/15.High-Speed_Interface_System.md @@ -273,7 +273,7 @@ The architecture of the USB port set is depicted below, where | --- | --- | --- | --- | --- | | 31:0 | pumon_monitor_ro[63:32] | RO | 0x0 | Debug signal from PUPHY | -#### 17.1.4.15 P_ADDR_RO4 REGISTER +#### 15.1.4.15 P_ADDR_RO4 REGISTER **Offset: 0x48** @@ -444,15 +444,15 @@ The architecture of the USB port set is depicted below, where | 1 | sof_toggle_out | RO | 0x0 | sof_toggle_out signal | | 0 | interrupt | RO | 0x0 | interrupt signal | -## 16.2 PCIe +## 15.2 PCIe -### 16.2.1 Introduction +### 15.2.1 Introduction K1 implements three PCIe Dual-Mode ports which can be configured as either Root Complex (RC) or Endpoint (EP) device. All ports support Gen2 with a data transfer speed of 5GT/s per lane. However, one port supports one lane only and two ports support two lanes each. -### 16.2.2 Features +### 15.2.2 Features - Support for Dual-Mode, programmable as either Complex (RC) or Endpoint (EP) device - Support for all non-optional features of the PCI Express Base Specification - Revision 5.0 - Version 1.0 (limited to Gen2 speed scope) @@ -473,7 +473,7 @@ All ports support Gen2 with a data transfer speed of 5GT/s per lane. However, on - Support for MSI Capability in EP Mode - Support for Integrated MSI Reception Module in RC Mode -### 16.2.3 Functional Description +### 15.2.3 Functional Description The architecture of the PCIe Dual-Mode port set is depicted below. @@ -608,9 +608,9 @@ The embedded DMA controller (EDMA) offloads data transfer tasks from the CPU and - Fetches the channel context (transfer control information) - Executes transfers based on the DMA elements programmed in local memory -## 16.3 EMAC +## 15.3 EMAC -### 16.3.1 Introduction +### 15.3.1 Introduction K1 features a EMAC core which includes the essential protocol requirements for the operation of 10/100/1000 Mbps Ethernet/IEEE 802.3-2012 compliant node. @@ -618,7 +618,7 @@ On the system side, the EMAC core features a 64-bit AXI Master Interface and a 3 The EMAC core can operate at 10 Mbps, 100 Mbps (Fast Ethernet) or 1000 Mbps (Gigabit Ethernet). Additionally, it includes a powerful 64-bit Scatter-Gather DMA to transfer packets between HOST Memory and Internal FIFOs to achieve high performance. -### 16.3.2 Features +### 15.3.2 Features - Capability of handling transmit/receive data encapsulation functions, including Framing (frame boundary delimitation, frame synchronization) and Error Detection (physical medium transmission errors) - Media access management with medium allocation (collision avoidance) and contention resolution (collision handling) in Half-Duplex Mode of operation at speeds of 10/100 Mbps @@ -629,7 +629,7 @@ The EMAC core can operate at 10 Mbps, 100 Mbps (Fast Ethernet) or 1000 Mbps (Gig - Bus mastering on the AXI interface to transfer packets between the HOST memory and the internal FIFOs using 64-bit transfer mode - Automatic transfer of packets between the HOST memory and internal FIFOs (based on descriptors) to minimize CPU overhead -### 16.3.3 Block Diagram +### 15.3.3 Block Diagram The micro-architecture of EMAC unit is depicted below. @@ -649,7 +649,7 @@ A brief description of each module is provided below. - **AXI Master Interface**: This module provides the AXI Master functionality to generate transactions on the AXI Bus. The transactions are generated based on the requests from the Transmit/Receive DMA’s. - **AXI Target Interface**: This module provides the AXI Target functionality to the AXI Host (CPU). This interface is used to access all the DMA/MAC registers in the Registers Module. -### 16.3.4 Programming Model +### 15.3.4 Programming Model The EMAC Core transfers received data frames/packets from the RMII/RGMII interface to the receive buffers in the host memory. Similarly, it transmits data frames/packets from the transmit buffers in the host memory to the RMII/RGMII interface. Descriptors, which reside in the host memory, act as pointers to these buffers. The receive and transmit FIFOs inside the EMAC Core serve as temporary storage for frame transmission and reception. @@ -665,7 +665,7 @@ Below is depicted the descriptor chain structure. In this configuration, each de ![](static/Programming_Model_1.png) -### 16.3.5 Register Description +### 15.3.5 Register Description The EMAC registers are used to control the operation of the EMAC core and to read status/interrupt information from it. The EMAC core decodes all 16 bits of the AHB/AXI (Slave) target address to access the registers. These registers are 32-bit word-aligned and must be accessed using 32-bit aligned addresses only. Reserved fields should be written as zero, and the EMAC core returns a value of zero in those fields. All registers are set to their default values upon reset. diff --git a/en/key_stone/k1/k1_docs/k1_usermanual/16.Low-Speed_Interface_System.md b/en/key_stone/k1/k1_docs/k1_usermanual/16.Low-Speed_Interface_System.md index 6e86f83..59317b0 100644 --- a/en/key_stone/k1/k1_docs/k1_usermanual/16.Low-Speed_Interface_System.md +++ b/en/key_stone/k1/k1_docs/k1_usermanual/16.Low-Speed_Interface_System.md @@ -1079,7 +1079,7 @@ To reset the I2C unit using the **ICR** register, follow these steps: - Clear the ISR register - Clear reset in the ICR -### 17.1.4 Register Description +### 16.1.4 Register Description > **Note.** The base address of I2C registers are tabled below. @@ -1430,9 +1430,9 @@ Software can write '0' to this register to flush the FIFO after an interrupt. | 31:4 | RSVD | R | 0 | Reserved for future use | | 3:0 | DATA | R/W | 0x0 | This is the location in the TX FIFO where the next entry will be read from by the hardware. | -## 17.2 SPI/I2S +## 16.2 SPI/I2S -### 17.2.1 Introduction +### 16.2.1 Introduction The SPI/I2S is a synchronous serial controller that can be connected to a variety of external Analog-to-Digital converters (ADC), audio and telecommunication codecs and many other devices that use serial protocols for data transfer. The SPI/I2S Controllers directly support the following protocols: @@ -1445,7 +1445,7 @@ The SPI/I2S can be configurate to operate in Master mode (the attached periphera The FIFOs can be loaded or emptied by CPU using programmed I/O (PIO) or DMA burst transfers. -### 17.2.2 Features +### 16.2.2 Features - Directly support for Motorola\* Serial Peripheral Interface (SPI) - The I2S is supported by programming, and data sample sizes can be set to 8, 16, 18 or 32 bits @@ -1456,7 +1456,7 @@ The FIFOs can be loaded or emptied by CPU using programmed I/O (PIO) or DMA burs - Receive-without-Transmit operation - Audio clock control to provide a 4x or 8x output clock to support most standard audio frequencies -### 17.2.3 Functional Description +### 16.2.3 Functional Description Data transfers between an SPI/I2S and memory are initiated by the CPU using programmed I/O (PIO) or DMA bursts. Separate Transmit and Receive FIFOs and serial data paths permit simultaneous transfers in both directions to and from the external peripheral, depending on the protocols chosen. @@ -1726,7 +1726,7 @@ Wait two SS_SCLK cycles before writing new data to the TXFIFO. The SPI/I2S Baud ![](static/SPI-I2S.png) -### 17.2.4 Register Description +### 16.2.4 Register Description > **Note.** The base address of SPI/I2S registers are tabled below. @@ -1932,9 +1932,9 @@ SPI/I2S root counter value write for read request register. | --- | --- | --- | --- | --- | | 31:0 | SSRWOTCVWR | R/W | 0x0 | This register prevents the risk of instability on rwot_counter value reading, it's only valid after SPI/I2S has been enabled Write
0 = No effect Write
1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter | -## 17.3 UART +## 16.3 UART -### 17.3.1 Introduction +### 16.3.1 Introduction The K1 has 10 UARTs (UART 0-9). The UARTs use the same programming model. @@ -1961,7 +1961,7 @@ The supported baud rates of each UART are tabled below. | 3 | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | | 4 | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | -### 17.3.2 Features +### 16.3.2 Features The serial ports are controlled via direct-memory access (DMA) or programmed I/O. The UARTs share the following features: @@ -2003,7 +2003,7 @@ The UARTs are functionally compatible with the 16550A and 16750 industry standar - Auto baud-rate detection - Auto flow -### 17.3.3 Functional Description +### 16.3.3 Functional Description #### Signal Description @@ -2211,7 +2211,7 @@ The recommended baud rates based on divisor values (Divisor Latch High Byte Regi The divisor reset value is 0x0002. Changing the baud rate (writing to registers Divisor Latch Low Byte Register and Divisor Latch High Byte Register) is not permitted while actively transmitting or receiving data. -### 17.3.4 Register Description +### 16.3.4 Register Description > **Note.** > @@ -2518,19 +2518,19 @@ config the baud_newreg_en to use the new address for DLH, DLL, FCR | 1 | BAUD_SYNC_DONE | RWC | 0x0 | baud_sync_done.
1 = the completion of {DLH, DLL } sync to clk_uart domain from clk_apb domain when <baud_newreg_en> is set previously, can be cleared by writing this resiger(0x38) or full baud divisor register(0x34).
0 = default status. | | 0 | BAUD_NEWREG_EN | RW | 0x0 | baud_newreg_en.
0= no influence with the previous config, except the new read access for FCR in offset=0x34.
1= enable another new address access for {DLH, DLL} in offset= 0x30 and FCR in offset=0x34. The previous access for DLH, DLL, FCR are all blocked. | -## 17.4 GPIO +## 16.4 GPIO -### 17.4.1 Introduction +### 16.4.1 Introduction GPIO is used to capture and generate application-specific input and output. All ports of GPIO are brought out via the alternate function muxing. GPIO unit is in charge of GPIO ports control and status check. When programmed as an input, a GPIO port can also serve as an interrupt source. At the assertion of all resets, all GPIO ports are configured as inputs and remain inputs until they are configured either by the boot process or by user software. -### 17.4.2 Features +### 16.4.2 Features - As inputs, they can be programmed to generate an interrupt at a rising edge, a falling edge or both - As outputs, they can be cleared or set individually - As inputs, the values can be read individually -### 17.4.3 Functional Description +### 16.4.3 Functional Description #### Block Diagram @@ -2567,7 +2567,7 @@ Rising-Edge Detect Enable Register and GPIO Falling-Edge Detect Enable Register. The GPIO information described in this section applies only to the GPIO alternate function. Still, it is possible for a system to use the GPIO functions internally and not actually connect to a physical pin. -### 17.4.4 Register Description +### 16.4.4 Register Description > **Note.** The base address of GPIO registers are tabled below. @@ -2724,9 +2724,9 @@ Bit-wise clear of GPIO rising edge detect enable register. | --- | --- | --- | --- | --- | | 31:0 | CFERn | W | 0x0 | Clear GPIO Falling Edge detect enable n (where n = 0 ~ 31)
0: GPIO Falling-Edge Detect Enable Register bit not affected
1: GPIO Falling-Edge Detect Enable Register bit is cleared | -## 17.5 One-Wire Bus Master Interface +## 16.5 One-Wire Bus Master Interface -### 17.5.1 Introduction +### 16.5.1 Introduction The One-Wire Bus Master Interface Controller is responsible for receiving and transmitting data on the One-Wire bus. It fully controls the One-Wire bus using 8-bit commands. The processor interacts with the controller by loading commands, reading and writing data, and configuring interrupt controls through 5 specific registers. @@ -2738,7 +2738,7 @@ The architecture of the One-Wire Bus Master Interface is depicted below. ![](static/One-Wire.png) -### 17.5.2 Functional Description +### 16.5.2 Functional Description #### Signal @@ -2866,7 +2866,7 @@ Ensure that these values are correct (that is, PDR = 0 if there is a slave and P - Wait for TBE interrupt. In the service routine, mask interrupts, clear the W1IER[ETBE] bit. Read the W1INTR[TBE] bit and ensure that it is set - New data, if needed, can be written into the buffer and interrupts should be unmasked -### 17.5.3 Register Description +### 16.5.3 Register Description > **Note.** The base address of 1-Wire Bus Master Registers is 0xD4011800. @@ -2947,19 +2947,19 @@ This register divides the internal reference clock to generate the One-Wire cloc | 4:2 | DIV | RW | 0x0 | Divider.
The One-Wire bus master interface controller uses the output of the prescaler and divides by the DIV value to produce the One-Wire clocks. This clock must be approximately 1 MHz for correct operation. This value must be set to 0x2. | | 1:0 | PRE | RW | 0x0 | Prescaler value.
The One-Wire bus master interface controller uses the input 24-MHz clock and initially divides by this value before outputting to the divider section. This value must be set to 0x3, selecting a prescale of 7. | -## 17.6 IR-RX +## 16.6 IR-RX -### 17.6.1 Introduction +### 16.6.1 Introduction The IR-RX module is capable of receiving infrared signals and transforming the received signals into digital format. Received data can be accessed through FIFO by checking status or configuring interrupt. -### 17.6.2 Features +### 16.6.2 Features - Infrared input signals are transformed into the Run-Length-Code (RLC) format - Configurable signal width threshold for noise detecting - 32 Bytes FIFO for received data storage -### 17.6.3 Functional Description +### 16.6.3 Functional Description The IR-RX module receives infrared signals and transforms the received information into digital format. The input infrared signals are filtered depending on a configurable noise detecting threshold. The transformed data is written into FIFO as the Run-Length-Code (RLC). Software may read the data from FIFO by checking status or configuring interrupt. @@ -2984,7 +2984,7 @@ For example, the following data in RLC format implies that: - 0x06 --\> Logic '0' has sustained for 0x06 working clock cycles. - 0xFF --\> Logic '1' has sustained for 0x7F working clock cycles. -### 17.6.4 Register Description +### 16.6.4 Register Description > **Note.** > @@ -3080,9 +3080,9 @@ For example, the following data in RLC format implies that: | 1 | PEDGE_INT_FLAG | RW1C | 0x0 | This bit is set to 1 if positive edge of the input infrared signal is detected. Interrupt is generated if PEDGE_INT_EN=1. It can be cleared by writing 0x1 to this bit. | | 0 | NEDGE_INT_FLAG | RW1C | 0x0 | This bit is set to 1 if negtive edge of the input infrared signal is detected. Interrupt is generated if NEDGE_INT_EN=1. It can be cleared by writing 0x1 to this bit. | -## 17.7 PWM +## 16.7 PWM -### 17.7.1 Introduction +### 16.7.1 Introduction K1 contains 20 Pulse-Width Modulation (PWM) channels labeled as PWMx where x=[0,19]. @@ -3094,13 +3094,13 @@ The timing of each PWM channel can be set to run continuously or be adjusted dyn The power-saving mode allows stopping the internal clock of a PWM channel (PSCLK_PWM), resulting to a constant high or low state of the output signal of that PWM channel (PWM_OUT), thus saving power when the output signal of that PWM channel is not needed. -### 17.7.2 Features +### 16.7.2 Features - Support for 50% duty-cycle ranging from 198.4Hz to 6.5MHz (additional duty-cycle options depend on the choice of the preferred frequency) - Enhanced period time controlled through 6-bit clock divider and 10-bit period time counter - 15-bit pulse counter control -### 17.7.3 Register Description +### 16.7.3 Register Description > **Note**. The base address of PWMn (n=1, 2, ... , 20) registers is 0xD401A000 with a stride of 0x400.