diff --git a/CODEOWNERS b/.github/CODEOWNERS similarity index 100% rename from CODEOWNERS rename to .github/CODEOWNERS diff --git a/.github/doc-review-agent/README.md b/.github/doc-review-agent/README.md new file mode 100644 index 0000000..f00f0c9 --- /dev/null +++ b/.github/doc-review-agent/README.md @@ -0,0 +1,142 @@ +# Doc Review Agent + +An automated documentation reviewer for the `docs-chip` repository. It runs on every pull request that touches Markdown files under `en/` or `zh/`, posts inline comments directly on the diff, and leaves a summary. A human makes the final merge decision. + +--- + +## How It Works + +``` +PR opened / updated + │ + ▼ +GitHub Actions triggers doc-review.yml + │ + ▼ +agent.py runs two passes: + 1. Rule-based checks (fast, deterministic) + 2. LLM-assisted review (optional, requires OPENAI_API_KEY) + │ + ▼ +Inline comments posted on specific lines +Summary comment posted at PR level + │ + ▼ +Human reviews comments → modifies, ignores, or merges +``` + +The agent only **comments** — it never approves, requests changes, or blocks merge. + +--- + +## File Structure + +``` +.github/ +├── workflows/ +│ └── doc-review.yml # GitHub Actions trigger +└── doc-review-agent/ + ├── agent.py # Main agent script + ├── config.yml # Check toggles and thresholds + └── system_prompt.md # LLM style guide and output rules +``` + +--- + +## Checks + +| Check | Scope | Severity | +|-------|-------|----------| +| YAML frontmatter exists and has required fields | `en/`, `zh/` | Warning | +| Heading levels are not skipped | `en/`, `zh/` | Warning | +| No `TBD` / `TODO` / `FIXME` placeholders | `en/`, `zh/` | Warning | +| Internal Markdown links resolve to existing files | `en/`, `zh/` | Error | +| Images referenced in `![](path)` exist in `static/` | `en/`, `zh/` | Error | +| Code blocks have a language identifier | `en/`, `zh/` | Suggestion | +| Bilingual counterpart file exists (`en/` ↔ `zh/`) | both | Warning | +| Chinese punctuation used in `zh/` files | `zh/` only | Suggestion | +| LLM content review (technical accuracy, style) | `en/`, `zh/` | varies | + +All checks can be toggled individually in `config.yml`. + +--- + +## Setup + +### 1. Secrets and Variables + +In your GitHub repository, go to **Settings → Secrets and variables → Actions** and add: + +| Name | Type | Description | +|------|------|-------------| +| `OPENAI_API_KEY` | Secret | LLM API key. Leave empty to skip LLM review. | +| `OPENAI_BASE_URL` | Secret | Optional. Custom endpoint (e.g., Azure OpenAI). Defaults to `https://api.openai.com/v1`. | +| `OPENAI_MODEL` | Variable | Optional. Model name. Defaults to `gpt-4o`. | + +`GITHUB_TOKEN` is provided automatically by GitHub Actions — no setup needed. + +### 2. Enable the Workflow + +The workflow file is already at `.github/workflows/doc-review.yml`. Push it to `main` and it activates automatically on the next PR. + +### 3. Configure Checks + +Edit `.github/doc-review-agent/config.yml` to enable/disable individual checks or adjust thresholds. + +--- + +## Output Format + +### Inline Comment (English file) + +> `[Warning]` Figure 3 is referenced in the text but not present in the `static/` directory. Add the missing image or update the reference. +> +> `` + +### Inline Comment (Chinese file) + +> `[错误]` 未找到对应的英文文档：`en/key_stone/k1/k1_docs/k1_ds.md`。请创建对应文件或更新语言索引。 +> +> `` + +### PR Summary + +``` +## 📋 Doc Review Summary + +| Severity | Count | +|------------|-------| +| Error | 2 | +| Warning | 3 | +| Suggestion | 1 | + +> Errors indicate missing or incorrect information that should be addressed before merge. +> Warnings and suggestions are advisory — human reviewer makes the final call. +``` + +--- + +## Dismissing False Positives + +All bot comments contain the tag ``. To dismiss: + +- Click **Resolve conversation** on any comment you disagree with. +- The agent will not re-post resolved comments on re-runs. + +To permanently suppress a rule, set it to `enabled: false` in `config.yml`. + +--- + +## Local Testing + +```bash +pip install requests pyyaml + +export GITHUB_TOKEN="ghp_..." +export GITHUB_REPOSITORY="spacemit-com/docs-chip" +export PR_NUMBER="42" +export OPENAI_API_KEY="sk-..." # optional +export GITHUB_WORKSPACE="." + +python .github/doc-review-agent/agent.py +``` diff --git a/.github/doc-review-agent/agent.py b/.github/doc-review-agent/agent.py new file mode 100644 index 0000000..fc10bcc --- /dev/null +++ b/.github/doc-review-agent/agent.py @@ -0,0 +1,471 @@ +""" +Doc Review Agent +================ +Reviews Markdown documentation files in a pull request and posts +inline comments + a summary to GitHub. + +Usage (invoked by GitHub Actions): + python agent.py + +Required environment variables: + GITHUB_TOKEN - GitHub token with pull-request write permission + GITHUB_REPOSITORY - e.g. "spacemit-com/docs-chip" + PR_NUMBER - pull request number + OPENAI_API_KEY - (or compatible LLM key) + OPENAI_BASE_URL - optional, for compatible endpoints + OPENAI_MODEL - model name, e.g. "gpt-4o" +""" + +from __future__ import annotations + +import os +import re +import sys +import json +import yaml +import pathlib +import textwrap +import requests +from dataclasses import dataclass, field +from typing import Literal + +# ─── Configuration ──────────────────────────────────────────────────────────── + +REPO = os.environ["GITHUB_REPOSITORY"] # "owner/repo" +PR_NUMBER = int(os.environ["PR_NUMBER"]) +GITHUB_TOKEN = os.environ["GITHUB_TOKEN"] +LLM_API_KEY = os.environ.get("OPENAI_API_KEY", "") +LLM_BASE_URL = os.environ.get("OPENAI_BASE_URL", "https://api.openai.com/v1") +LLM_MODEL = os.environ.get("OPENAI_MODEL", "gpt-4o") + +CONFIG_PATH = pathlib.Path(__file__).parent / "config.yml" +PROMPT_PATH = pathlib.Path(__file__).parent / "system_prompt.md" +WORKSPACE = pathlib.Path(os.environ.get("GITHUB_WORKSPACE", ".")) + +GH_API = "https://api.github.com" +GH_HEADERS = { + "Authorization": f"Bearer {GITHUB_TOKEN}", + "Accept": "application/vnd.github+json", + "X-GitHub-Api-Version": "2022-11-28", +} + +# ─── Data types ─────────────────────────────────────────────────────────────── + +Severity = Literal["Error", "Warning", "Suggestion", "错误", "警告", "建议"] + +@dataclass +class ReviewComment: + path: str # relative file path + line: int # 1-based line number in the file + body: str # comment text (already formatted) + severity: str # Error / Warning / Suggestion + + +@dataclass +class ReviewResult: + comments: list[ReviewComment] = field(default_factory=list) + errors: int = 0 + warnings: int = 0 + suggestions: int = 0 + + +# ─── GitHub helpers ─────────────────────────────────────────────────────────── + +def gh_get(path: str) -> dict | list: + r = requests.get(f"{GH_API}{path}", headers=GH_HEADERS, timeout=30) + r.raise_for_status() + return r.json() + + +def gh_post(path: str, body: dict) -> dict: + r = requests.post(f"{GH_API}{path}", headers=GH_HEADERS, json=body, timeout=30) + r.raise_for_status() + return r.json() + + +def get_pr_files() -> list[dict]: + """Return list of changed files in the PR (up to 300 files).""" + files = [] + page = 1 + while True: + batch = gh_get(f"/repos/{REPO}/pulls/{PR_NUMBER}/files?per_page=100&page={page}") + if not batch: + break + files.extend(batch) + if len(batch) < 100: + break + page += 1 + return files + + +def get_pr_head_sha() -> str: + pr = gh_get(f"/repos/{REPO}/pulls/{PR_NUMBER}") + return pr["head"]["sha"] + + +def post_review(comments: list[ReviewComment], summary_body: str, commit_sha: str) -> None: + """Post all inline comments + summary as a single PR review.""" + gh_comments = [] + for c in comments: + gh_comments.append({ + "path": c.path, + "line": c.line, + "side": "RIGHT", + "body": c.body, + }) + + payload = { + "commit_id": commit_sha, + "body": summary_body, + "event": "COMMENT", # advisory only — never REQUEST_CHANGES + "comments": gh_comments, + } + gh_post(f"/repos/{REPO}/pulls/{PR_NUMBER}/reviews", payload) + + +# ─── Rule-based checks ──────────────────────────────────────────────────────── + +def is_zh(filepath: str) -> bool: + return filepath.startswith("zh/") + + +def label(sev: str, zh: bool) -> str: + mapping = { + "Error": "错误" if zh else "Error", + "Warning": "警告" if zh else "Warning", + "Suggestion": "建议" if zh else "Suggestion", + } + return f"`[{mapping.get(sev, sev)}]`" + + +def check_frontmatter(content: str, path: str, cfg: dict) -> list[tuple[int, str, str]]: + """Returns list of (line, severity, message).""" + issues = [] + if not content.startswith("---"): + issues.append((1, "Warning", "Missing YAML frontmatter block.")) + return issues + + end = content.find("\n---", 3) + if end == -1: + issues.append((1, "Warning", "Frontmatter block is not closed.")) + return issues + + try: + fm = yaml.safe_load(content[3:end]) + except yaml.YAMLError: + issues.append((1, "Error", "Frontmatter YAML is invalid.")) + return issues + + if not isinstance(fm, dict): + return issues + + for field_name in cfg.get("required_fields", ["title"]): + if field_name not in fm: + issues.append((1, "Warning", f"Frontmatter is missing required field: `{field_name}`.")) + + return issues + + +def check_headings(lines: list[str]) -> list[tuple[int, str, str]]: + issues = [] + prev_level = 0 + for i, line in enumerate(lines, 1): + m = re.match(r'^(#{1,6})\s', line) + if not m: + continue + level = len(m.group(1)) + if prev_level > 0 and level > prev_level + 1: + issues.append((i, "Warning", + f"Heading level jumps from `{'#' * prev_level}` to `{'#' * level}`. " + "Avoid skipping heading levels.")) + prev_level = level + return issues + + +def check_tbd(lines: list[str]) -> list[tuple[int, str, str]]: + issues = [] + pattern = re.compile(r'\b(TBD|TODO|FIXME)\b', re.IGNORECASE) + for i, line in enumerate(lines, 1): + if pattern.search(line): + issues.append((i, "Warning", + f"Found `{pattern.search(line).group()}` placeholder. " + "Remove or replace before publication.")) + return issues + + +def check_images(lines: list[str], file_path: str) -> list[tuple[int, str, str]]: + issues = [] + img_pattern = re.compile(r'!\[.*?\]\(([^)]+)\)') + base_dir = (WORKSPACE / file_path).parent + + for i, line in enumerate(lines, 1): + for m in img_pattern.finditer(line): + img_src = m.group(1) + if img_src.startswith("http"): + continue + img_path = (base_dir / img_src).resolve() + if not img_path.exists(): + issues.append((i, "Error", + f"Image not found: `{img_src}`. " + "Add the file to the `static/` directory or fix the path.")) + return issues + + +def check_links(lines: list[str], file_path: str) -> list[tuple[int, str, str]]: + issues = [] + link_pattern = re.compile(r'\[.*?\]\(([^)#]+)(?:#[^)]*)?\)') + base_dir = (WORKSPACE / file_path).parent + + for i, line in enumerate(lines, 1): + for m in link_pattern.finditer(line): + target = m.group(1).strip() + if target.startswith("http"): + continue + target_path = (base_dir / target).resolve() + if not target_path.exists(): + issues.append((i, "Error", + f"Broken link: `{target}`. " + "Verify the target file exists or update the path.")) + return issues + + +def check_code_blocks(lines: list[str]) -> list[tuple[int, str, str]]: + issues = [] + for i, line in enumerate(lines, 1): + if re.match(r'^```\s*$', line): + issues.append((i, "Suggestion", + "Code block has no language identifier. " + "Specify a language (e.g., ` ```bash `, ` ```c `) for syntax highlighting.")) + return issues + + +def check_chinese_punctuation(lines: list[str], path: str) -> list[tuple[int, str, str]]: + if not is_zh(path): + return [] + issues = [] + # Detect common ASCII punctuation in prose (outside code blocks) + in_code = False + ascii_punct = re.compile(r'(? list[tuple[int, str, str]]: + issues = [] + if file_path.startswith("en/"): + pair = "zh/" + file_path[3:] + elif file_path.startswith("zh/"): + pair = "en/" + file_path[3:] + else: + return issues + + pair_full = WORKSPACE / pair + if not pair_full.exists(): + issues.append((1, "Warning", + f"Bilingual counterpart not found: `{pair}`. " + "Create the corresponding file or update the language index.")) + return issues + + +# ─── LLM-assisted review ───────────────────────────────────────────────────── + +def llm_review(content: str, file_path: str, system_prompt: str) -> list[tuple[int, str, str]]: + """ + Ask the LLM to review the document content. + Returns list of (line, severity, message). + """ + if not LLM_API_KEY: + return [] + + lang_hint = "This file is under zh/ — respond in Chinese." if is_zh(file_path) else \ + "This file is under en/ — respond in English." + + user_msg = textwrap.dedent(f""" + Review the following Markdown file: `{file_path}` + {lang_hint} + + Return your findings as a JSON array. Each item must have: + - "line": integer (1-based line number closest to the issue) + - "severity": "Error" | "Warning" | "Suggestion" (use Chinese equivalents for zh/ files) + - "message": string (formatted per the style guide in your system prompt) + + If there are no issues, return an empty array []. + + ```markdown + {content[:12000]} + ``` + """).strip() + + payload = { + "model": LLM_MODEL, + "messages": [ + {"role": "system", "content": system_prompt}, + {"role": "user", "content": user_msg}, + ], + "temperature": 0.1, + "response_format": {"type": "json_object"}, + } + + try: + r = requests.post( + f"{LLM_BASE_URL}/chat/completions", + headers={"Authorization": f"Bearer {LLM_API_KEY}", "Content-Type": "application/json"}, + json=payload, + timeout=60, + ) + r.raise_for_status() + raw = r.json()["choices"][0]["message"]["content"] + data = json.loads(raw) + items = data if isinstance(data, list) else data.get("issues", data.get("findings", [])) + return [(int(item["line"]), item["severity"], item["message"]) for item in items] + except Exception as e: + print(f" LLM review failed for {file_path}: {e}", file=sys.stderr) + return [] + + +# ─── Main ───────────────────────────────────────────────────────────────────── + +def run_checks(file_path: str, content: str, cfg: dict) -> list[tuple[int, str, str]]: + lines = content.splitlines() + issues: list[tuple[int, str, str]] = [] + + if cfg["checks"]["frontmatter"]["enabled"]: + issues += check_frontmatter(content, file_path, cfg["checks"]["frontmatter"]) + if cfg["checks"]["heading_hierarchy"]["enabled"]: + issues += check_headings(lines) + if cfg["checks"]["technical_style"]["enabled"] and cfg["checks"]["technical_style"]["flag_tbd"]: + issues += check_tbd(lines) + if cfg["checks"]["missing_images"]["enabled"]: + issues += check_images(lines, file_path) + if cfg["checks"]["broken_links"]["enabled"]: + issues += check_links(lines, file_path) + if cfg["checks"]["technical_style"]["enabled"] and cfg["checks"]["technical_style"]["flag_code_block_language"]: + issues += check_code_blocks(lines) + if cfg["checks"]["punctuation"]["enabled"] and cfg["checks"]["punctuation"]["chinese_punctuation_in_zh"]: + issues += check_chinese_punctuation(lines, file_path) + if cfg["checks"]["bilingual_mirror"]["enabled"] and cfg["checks"]["bilingual_mirror"]["flag_missing_pair"]: + issues += check_bilingual_pair(file_path) + + return issues + + +def build_comment_body(sev: str, message: str, zh: bool) -> str: + lbl = label(sev, zh) + return f"{lbl} {message}\n\n" + + +def build_summary(result: ReviewResult, zh: bool) -> str: + bot_tag = "" + if zh: + return textwrap.dedent(f""" + ## 📋 文档审阅摘要 + + | 级别 | 数量 | + |------|------| + | 错误 | {result.errors} | + | 警告 | {result.warnings} | + | 建议 | {result.suggestions} | + + > 错误项表示信息缺失或有误，建议在合并前处理。 + > 警告和建议仅供参考，最终合并决策由人工审阅者决定。 + + {bot_tag} + """).strip() + else: + return textwrap.dedent(f""" + ## 📋 Doc Review Summary + + | Severity | Count | + |------------|-------| + | Error | {result.errors} | + | Warning | {result.warnings} | + | Suggestion | {result.suggestions} | + + > Errors indicate missing or incorrect information that should be addressed before merge. + > Warnings and suggestions are advisory — human reviewer makes the final call. + + {bot_tag} + """).strip() + + +def main() -> None: + cfg = yaml.safe_load(CONFIG_PATH.read_text(encoding="utf-8")) + system_prompt = PROMPT_PATH.read_text(encoding="utf-8") + + pr_files = get_pr_files() + commit_sha = get_pr_head_sha() + + # Filter to Markdown doc files only + include_re = [re.compile(p.replace("**", ".*").replace("*", "[^/]*")) + for p in cfg["include_patterns"]] + exclude_re = [re.compile(p.replace("**", ".*").replace("*", "[^/]*")) + for p in cfg.get("exclude_patterns", [])] + + def is_included(path: str) -> bool: + return (any(r.fullmatch(path) for r in include_re) and + not any(r.fullmatch(path) for r in exclude_re)) + + result = ReviewResult() + all_comments: list[ReviewComment] = [] + has_zh = False + + for f in pr_files: + fpath = f["filename"] + status = f.get("status", "") + + if not is_included(fpath): + continue + if status == "removed": + continue + + print(f"Reviewing: {fpath}") + zh = is_zh(fpath) + if zh: + has_zh = True + + full_path = WORKSPACE / fpath + try: + content = full_path.read_text(encoding="utf-8") + except FileNotFoundError: + print(f" File not found locally, skipping: {fpath}", file=sys.stderr) + continue + + # Rule-based checks + issues = run_checks(fpath, content, cfg) + + # LLM-assisted checks + llm_issues = llm_review(content, fpath, system_prompt) + issues += llm_issues + + for line_no, sev, msg in issues: + body = build_comment_body(sev, msg, zh) + all_comments.append(ReviewComment(path=fpath, line=line_no, body=body, severity=sev)) + + sev_norm = sev.lower() + if sev_norm in ("error", "错误"): + result.errors += 1 + elif sev_norm in ("warning", "警告"): + result.warnings += 1 + else: + result.suggestions += 1 + + summary = build_summary(result, zh=has_zh) + + if all_comments or result.errors + result.warnings + result.suggestions > 0: + print(f"\nPosting review: {result.errors} errors, {result.warnings} warnings, " + f"{result.suggestions} suggestions") + post_review(all_comments, summary, commit_sha) + else: + print("No issues found. Posting clean summary.") + post_review([], summary, commit_sha) + + +if __name__ == "__main__": + main() diff --git a/.github/doc-review-agent/config.yml b/.github/doc-review-agent/config.yml new file mode 100644 index 0000000..8588c7e --- /dev/null +++ b/.github/doc-review-agent/config.yml @@ -0,0 +1,73 @@ +# Doc Review Agent Configuration + +# ─── Scope ──────────────────────────────────────────────────────────────────── +# Only review files matching these patterns +include_patterns: + - "en/**/*.md" + - "zh/**/*.md" + +# Never review these files +exclude_patterns: + - "**/index.md" # index files are auto-generated navigation stubs + +# ─── Checks ─────────────────────────────────────────────────────────────────── +checks: + frontmatter: + enabled: true + required_fields: + - title + # Add sidebar_position if your site framework requires it + # - sidebar_position + + heading_hierarchy: + enabled: true + + empty_file: + enabled: true + min_content_lines: 5 # files with fewer lines are flagged + + broken_links: + enabled: true + check_internal: true + check_anchors: false # anchor checking is best-effort; set true if needed + + missing_images: + enabled: true + + bilingual_mirror: + enabled: true + # Flag if the paired file in the other language is missing + flag_missing_pair: true + # Flag if heading count differs by more than this threshold + heading_count_tolerance: 2 + + technical_style: + enabled: true + flag_tbd: true # flag TBD / TODO / FIXME + flag_missing_units: false # heuristic check; may have false positives + flag_code_block_language: true + + punctuation: + enabled: true + # Enforce Chinese punctuation in zh/ files + chinese_punctuation_in_zh: true + +# ─── Severity overrides ─────────────────────────────────────────────────────── +# Default severities are defined in the agent. Override here if needed. +severity_overrides: + missing_pair_file: "warning" # missing bilingual pair → warning, not error + tbd_in_content: "warning" + missing_code_block_lang: "suggestion" + +# ─── Output ─────────────────────────────────────────────────────────────────── +output: + # Post inline review comments on specific lines + inline_comments: true + # Post a summary comment at the PR level + pr_summary: true + # GitHub status check result when errors are found + # "neutral" = visible but never blocks merge + # "failure" = blocks merge (requires the check to be non-required in branch protection) + status_on_error: "neutral" + # Tag appended to all bot comments for easy identification and bulk-resolve + bot_tag: "" diff --git a/.github/doc-review-agent/system_prompt.md b/.github/doc-review-agent/system_prompt.md new file mode 100644 index 0000000..b20a460 --- /dev/null +++ b/.github/doc-review-agent/system_prompt.md @@ -0,0 +1,163 @@ +# Doc Review Agent — System Prompt + +You are a professional technical documentation reviewer for a semiconductor company. Your role is to review Markdown documentation files submitted via pull requests for the `docs-chip` repository, which covers SoC products (K1, K3, P1, P1S) including datasheets, hardware design guides, user manuals, and SDK guides. + +--- + +## Identity and Role + +- You are a **technical writer reviewer**, not a general-purpose assistant. +- You review documentation only — do not comment on code logic, CI config, or non-doc files. +- Your judgment is advisory. A human makes the final merge decision. + +--- + +## Output Language Rules + +- If the file is under `en/`, respond in **English**. +- If the file is under `zh/`, respond in **Chinese**. +- Never mix review languages within a single comment block. + +--- + +## English Output Style + +**Principles:** +- Use semiconductor industry standard terminology. +- Be concise: one issue, one sentence. No filler phrases. +- Every comment must include a concrete fix suggestion. +- Neutral tone — state facts, not opinions. + +**Comment format:** +``` +`[Severity]` . . [Reference if applicable] +``` + +**Severity labels:** `[Error]` | `[Warning]` | `[Suggestion]` + +**Preferred terminology:** +- SoC, PCIe Gen3, DDR4, LPDDR4X, TDP, GPIO, UART, I²C, SPI, PWM +- power rail, thermal dissipation, boot sequence, register map, memory map +- EVB (Evaluation Board), BOM, schematic, layout guideline, signal integrity +- operating voltage, clock frequency, reset sequence, DMA, interrupt controller + +**Examples:** + +✅ Correct: +> `[Error]` The VDDCORE operating range is missing. Specify the min/typ/max values (e.g., 0.8 V / 0.9 V / 1.0 V) per the datasheet §3.2. + +✅ Correct: +> `[Warning]` Figure 3 is referenced in the text but not present in the `static/` directory. Add the missing image or update the reference. + +❌ Avoid: +> "This section seems incomplete and might confuse readers." + +--- + +## Chinese Output Style + +**原则：** +- 使用半导体行业标准中文术语。 +- 简洁：一个问题，一句话描述清楚。不堆砌形容词。 +- 每条评论必须包含可操作的修改建议。 +- 中立语气，陈述事实，不带主观评价。 + +**评论格式：** +``` +`[级别]` <问题描述>。<修改建议>。[参考来源] +``` + +**级别标签：** `[错误]` | `[警告]` | `[建议]` + +**术语规范：** +- 中文术语：片上系统、存储接口、启动序列、寄存器映射、功耗、热设计、散热方案 +- 英文术语保留原文（不翻译）：SoC、PCIe、DDR4、LPDDR4X、GPIO、UART、I²C、SPI、EVB、BOM +- 单位规范：电压用 V，电流用 mA/A，频率用 MHz/GHz，温度用 °C + +**示例：** + +✅ 正确： +> `[错误]` 未标注 K1 的 VDDCORE 工作电压范围。请补充最小值/典型值/最大值（参见数据手册第 3.2 节）。 + +✅ 正确： +> `[警告]` 正文引用了图 3，但 `static/` 目录中未找到对应图片文件。请添加图片或更新引用。 + +❌ 避免： +> "这里感觉写得不够清楚，建议作者考虑一下是否需要修改。" + +--- + +## What to Check + +### 1. Structure +- Frontmatter: verify required fields exist (`title`, `sidebar_position` or equivalent). +- Heading hierarchy: no skipped levels (e.g., `##` directly after `#`, not `###`). +- File is not empty or placeholder-only. + +### 2. Links and Images +- All internal Markdown links `[text](path)` resolve to existing files. +- All images referenced in `![alt](path)` exist in the `static/` directory. +- No broken anchor links (`#section-id`). + +### 3. Bilingual Consistency (cross-file check) +- The corresponding file in the other language (`en/` ↔ `zh/`) exists. +- Section count (number of `##` headings) matches between language versions. +- Product names and model numbers are consistent: K1, K3, P1, P1S (not k1, K-1, etc.). + +### 4. Technical Content +- Numerical values include units (V, mA, MHz, °C, etc.). +- Tables have headers and consistent column counts. +- Code blocks specify a language identifier (e.g., ` ```bash `, ` ```c `). + +### 5. Style +- No "TBD", "TODO", or "FIXME" in content intended for publication. +- No consecutive blank lines (more than 2). +- Chinese punctuation used in `zh/` files (，。；：""instead of , . ; : ""). + +--- + +## What NOT to Do + +- Do not rewrite content for the author. +- Do not comment on writing style preferences beyond the rules above. +- Do not flag issues in files outside the PR diff. +- Do not approve or request changes at the PR level — only leave comments. +- Do not make assumptions about undocumented hardware specs. + +--- + +## PR Summary Format + +At the end of each review, post a summary comment: + +```markdown +## 📋 Doc Review Summary + +| Severity | Count | +|----------|-------| +| Error | N | +| Warning | N | +| Suggestion | N | + +> Errors indicate missing or incorrect information that should be addressed before merge. +> Warnings and suggestions are advisory — human reviewer makes the final call. + + +``` + +For Chinese PRs, use: + +```markdown +## 📋 文档审阅摘要 + +| 级别 | 数量 | +|------|------| +| 错误 | N | +| 警告 | N | +| 建议 | N | + +> 错误项表示信息缺失或有误，建议在合并前处理。 +> 警告和建议仅供参考，最终合并决策由人工审阅者决定。 + + +``` diff --git a/.github/workflows/doc-review.yml b/.github/workflows/doc-review.yml new file mode 100644 index 0000000..66bf6bb --- /dev/null +++ b/.github/workflows/doc-review.yml @@ -0,0 +1,41 @@ +name: Doc Review + +on: + pull_request: + types: [opened, synchronize, reopened] + paths: + - "en/**/*.md" + - "zh/**/*.md" + +permissions: + pull-requests: write # post review comments + contents: read + +jobs: + review: + name: Review documentation + runs-on: ubuntu-latest + + steps: + - name: Checkout PR + uses: actions/checkout@v4 + with: + fetch-depth: 0 # full history needed for bilingual pair checks + + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: "3.12" + + - name: Install dependencies + run: pip install requests pyyaml + + - name: Run Doc Review Agent + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + GITHUB_REPOSITORY: ${{ github.repository }} + PR_NUMBER: ${{ github.event.pull_request.number }} + OPENAI_API_KEY: ${{ secrets.OPENAI_API_KEY }} + OPENAI_BASE_URL: ${{ secrets.OPENAI_BASE_URL || 'https://api.openai.com/v1' }} + OPENAI_MODEL: ${{ vars.OPENAI_MODEL || 'gpt-4o' }} + run: python .github/doc-review-agent/agent.py diff --git a/en/key_stone/k1/k1_docs/k1_usermanual/10.Memory_&_Storage.md b/en/key_stone/k1/k1_docs/k1_usermanual/10.Memory_&_Storage.md index 93ff265..4201e27 100644 --- a/en/key_stone/k1/k1_docs/k1_usermanual/10.Memory_&_Storage.md +++ b/en/key_stone/k1/k1_docs/k1_usermanual/10.Memory_&_Storage.md @@ -58,22 +58,9 @@ The architecture of the DDR controller interface is depicted below. The DDR Controller supports 4 AXI slave ports with arbitration among them. Details about the port connections to the DDR Controller are tabled below. - - - - - - - - - - - - - - - -
Port0Port1Port2Port3
RISCV X60 Clusters and GPUGMAC0, GMAC1 and
AXI Fabric1 Port		VPU and PCIE PortA/B/CDisplay and ISP
+| Port0 | Port1 | Port2 | Port3 | +| --- | --- | --- | --- | +| RISCV X60 Clusters and GPU | GMAC0, GMAC1 and
AXI Fabric1 Port | VPU and PCIE PortA/B/C | Display and ISP | #### Dynamic Schedulin @@ -284,7 +271,7 @@ The SD/eMMC Host Controller is a hardware block that acts as a host of the SD/eM > - SD AXI master always generates an INCR (AWBURST/ARBURST = 0x1) burst and 8-bytes burst size (AWSIZE/ARSIZE = 0x3) > - SD AXI master bursts are normal, non-secure data accesses (AWPROT/ARPROT = 0x2) > - SD AXI master never generates atomic accesses (AWLOCK/ARLOCK = 0x0) -> - SD AXI slave does not support exclusive, protected or atomic accesses. The response signaling is always “OKAY” (RRESP/BRESP = 0x0) or “DECERR” (RRESP/BRESP = 0x2). The “DECERR” response is signaled if an address is accessed where no registers exist. +> - SD AXI slave does not support exclusive, protected or atomic accesses. The response signaling is always 鈥淥KAY鈥?(RRESP/BRESP = 0x0) or 鈥淒ECERR鈥?(RRESP/BRESP = 0x2). The 鈥淒ECERR鈥?response is signaled if an address is accessed where no registers exist. ### 10.5.3 Functional Description @@ -302,7 +289,7 @@ To be highlighted: - AXI Master - AHB Slave is used for configuring registers and handling read/write operations in PIO mode - AHB Master manages data transmission in SDMA/ADMA mode -- A 128 × 64-bit FIFO stores up to two 512-byte packets for data buffering +- A 128 脳 64-bit FIFO stores up to two 512-byte packets for data buffering - Configuration registers synchronize with the SD/eMMC clock domain via a synchronizer to configure the clock, data width, etc. - Card insertion/removal is detected through GPIO, triggering an interrupt to notify the CPU @@ -398,4593 +385,868 @@ If an error occurs in SPI mode, then the \ field in the Error Interrup The base addresses of SD/eMMC Host Controller Registers are tabled below. - - - - - - - - - - - - - - - - - - - -
NameAddress
SD1_BASE(SD Card)0xD4280000
SD2_BASE(SDIO)0xD4280800
SD3_BASE(eMMC)0xD4281000
+| Name | Address | +| --- | --- | +| SD1_BASE(SD Card) | 0xD4280000 | +| SD2_BASE(SDIO) | 0xD4280800 | +| SD3_BASE(eMMC) | 0xD4281000 | #### SD_SYS_ADDR REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31:16DMA_ADDR_HR/W0x0000- DMA Address High: contains 16 MSb of DMA system buffer starting byte address.
- This register is used with the Auto Cmd 23 to set a 32-bit block count value to the argument of cmd23. This register holds the upper 16bits of the cmd23 argument.
15:0DMA_ADDR_LR/W0x0000- DMA Address Low: contains 16 LSb of DMA system buffer starting byte address.
- This register is used with the Auto Cmd 23 to set a 32-bit block count value to the argument of cmd23. This register holds the lower 16bits of the cmd23 argument.
+**Offset: 0x0** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | DMA_ADDR_H | R/W | 0x0000 | - DMA Address High: contains 16 MSb of DMA system buffer starting byte address.
- This register is used with the Auto Cmd 23 to set a 32-bit block count value to the argument of cmd23. This register holds the upper 16bits of the cmd23 argument. | +| 15:0 | DMA_ADDR_L | R/W | 0x0000 | - DMA Address Low: contains 16 LSb of DMA system buffer starting byte address.
- This register is used with the Auto Cmd 23 to set a 32-bit block count value to the argument of cmd23. This register holds the lower 16bits of the cmd23 argument. | #### SD_BLOCK_SIZE_CNT REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31:16BLOCK_COUNTR/W0x0000Block Count
The Host Controller decrements the block count after each block transfer.
0x1 = 1 block
...
0xFFFF = 65535 blocks
The current value of block count is reflected in the Current Block Count Register.
15RSVDR0Reserved for future use
14:12HOST_DMA_BDRYR/W0x0Host DMA Buffer Boundary
This field specifies the host memory buffer boundary.
If this boundary is crossed, an interrupt (dma_int) is generated.
This interrupt is reflected in <Tx Ready> field of the Normal Interrupt Status Register.
0x0: 4 KB
0x1: 8 KB
0x2: 16 KB
0x3: 32 KB
0x4: 64 KB
0x5: 128 KB
0x6: 256 KB
0x7: 512 KB
11:0BLOCK_SIZER/W0x000Block Size
+**Offset: 0x4** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | BLOCK_COUNT | R/W | 0x0000 | Block Count
The Host Controller decrements the block count after each block transfer.
0x1 = 1 block
...
0xFFFF = 65535 blocks
The current value of block count is reflected in the Current Block Count Register. | +| 15 | RSVD | R | 0 | Reserved for future use | +| 14:12 | HOST_DMA_BDRY | R/W | 0x0 | Host DMA Buffer Boundary
This field specifies the host memory buffer boundary.
If this boundary is crossed, an interrupt (dma_int) is generated.
This interrupt is reflected in field of the Normal Interrupt Status Register.
0x0: 4 KB
0x1: 8 KB
0x2: 16 KB
0x3: 32 KB
0x4: 64 KB
0x5: 128 KB
0x6: 256 KB
0x7: 512 KB | +| 11:0 | BLOCK_SIZE | R/W | 0x000 | Block Size | #### SD_ARG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8
BitsFieldTypeResetDescription
31:16ARG_HR/W0x0000Argument High 16 MSb of Command Argument
This value is inserted into 48 bits command token bits[39:24].
15:0ARG_LR/W0x0000Argument Low 16 LSb of Command Argument
This value is inserted into 48 bits command token bits[23:8].
+**Offset: 0x8** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | ARG_H | R/W | 0x0000 | Argument High 16 MSb of Command Argument
This value is inserted into 48 bits command token bits[39:24]. | +| 15:0 | ARG_L | R/W | 0x0000 | Argument Low 16 LSb of Command Argument
This value is inserted into 48 bits command token bits[23:8]. | #### SD_TRANSFER_MODE_CMD REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC
BitsFieldTypeResetDescription
31:30RSVDR0Reserved for future use
29:24CMD_INDEXR/W0x00Command Index
These bits will be inserted into Command token bits[45:40]
23:22CMD_TYPER/W0x0Command Type
0x0: Normal command
0x1: Suspend command
0x2: Resume command
0x3: Abort command
21DATA_PRESENTR/W0x0Data Present
1: Indicates that data is present and will be transferred using the MMC1_DAT[3:0] line.
0: Commands using only MMC1_CMD lines or commands with no data transfer but using busy signal on MMC1_DAT[0] line (for example, CMD 38)
20CMD_INDEX_CHK_ENR/W0x0Command Index Check Enable
1: The Host Controller checks the index field in the response to ensure it matches the command index.
- If there is a mismatch, it is reported as a Command Index Error.
19CMD_CRC_CHK_ENR/W0x0Command CRC Check Enable
1: Host controller checks the CRC field in response.
- If an error is detected, it is reported as a command CRC error. The number of bits checked by the CRC field value changes according to the length of response.
18RSVDR0Reserved for future use
17:16RESP_TYPER/W0x0Response Type Select for SD/SD in SPI Modes For SD mode:
0x0: No response
0x1: Response length is 136 bits
0x2: Response length is 48 bits
0x3: Response length is 48 bits and check busy after response CRC field for R3 and R4 is expected to be all 1 bits. CRC Check should be disabled for these response types.
For SD in SPI mode:
0x0: Response length is 8 bits
0x1: Response length is 16 bits
0x2: Response length is 40 bits
0x3: Reserved
15:6RSVDR0Reserved for future use
5MULTI_BLK_SELR/W0x0Multiple Block Select
This bit should be set to 1 only when multiple blocks are to be transferred.
4TO_HOST_DIRR/W0x0Data Transfer Direction Select
This bit defines the direction of the MMC1_DAT[3:0] line data transfer.
1: Transfer data from the SD card to the SD Host Controller,
0: Used for all other commands.
3:2AUTO_CMD_ENR/W0x0Auto CMD Enable
This field determines use of auto command functions.
0x0: Auto Command disabled
0x1: Auto CMD12 Enable
0x2: Auto CMD23 Enable
0x3: Reserved
1BLK_CNT_ENR/W0x0Block Count Enable
This bit validates the value in the Block Count Register.
0DMA_ENR/W0x0DMA Enable
If Programmed Input/Output (PIO) mode is required, this bit should be reset to 0.
+**Offset: 0xC** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | RSVD | R | 0 | Reserved for future use | +| 29:24 | CMD_INDEX | R/W | 0x00 | Command Index
These bits will be inserted into Command token bits[45:40] | +| 23:22 | CMD_TYPE | R/W | 0x0 | Command Type
0x0: Normal command
0x1: Suspend command
0x2: Resume command
0x3: Abort command | +| 21 | DATA_PRESENT | R/W | 0x0 | Data Present
1: Indicates that data is present and will be transferred using the MMC1_DAT[3:0] line.
0: Commands using only MMC1_CMD lines or commands with no data transfer but using busy signal on MMC1_DAT[0] line (for example, CMD 38) | +| 20 | CMD_INDEX_CHK_EN | R/W | 0x0 | Command Index Check Enable
1: The Host Controller checks the index field in the response to ensure it matches the command index.
- If there is a mismatch, it is reported as a Command Index Error. | +| 19 | CMD_CRC_CHK_EN | R/W | 0x0 | Command CRC Check Enable
1: Host controller checks the CRC field in response.
- If an error is detected, it is reported as a command CRC error. The number of bits checked by the CRC field value changes according to the length of response. | +| 18 | RSVD | R | 0 | Reserved for future use | +| 17:16 | RESP_TYPE | R/W | 0x0 | Response Type Select for SD/SD in SPI Modes For SD mode:
0x0: No response
0x1: Response length is 136 bits
0x2: Response length is 48 bits
0x3: Response length is 48 bits and check busy after response CRC field for R3 and R4 is expected to be all 1 bits. CRC Check should be disabled for these response types.
For SD in SPI mode:
0x0: Response length is 8 bits
0x1: Response length is 16 bits
0x2: Response length is 40 bits
0x3: Reserved | +| 15:6 | RSVD | R | 0 | Reserved for future use | +| 5 | MULTI_BLK_SEL | R/W | 0x0 | Multiple Block Select
This bit should be set to 1 only when multiple blocks are to be transferred. | +| 4 | TO_HOST_DIR | R/W | 0x0 | Data Transfer Direction Select
This bit defines the direction of the MMC1_DAT[3:0] line data transfer.
1: Transfer data from the SD card to the SD Host Controller,
0: Used for all other commands. | +| 3:2 | AUTO_CMD_EN | R/W | 0x0 | Auto CMD Enable
This field determines use of auto command functions.
0x0: Auto Command disabled
0x1: Auto CMD12 Enable
0x2: Auto CMD23 Enable
0x3: Reserved | +| 1 | BLK_CNT_EN | R/W | 0x0 | Block Count Enable
This bit validates the value in the Block Count Register. | +| 0 | DMA_EN | R/W | 0x0 | DMA Enable
If Programmed Input/Output (PIO) mode is required, this bit should be reset to 0. | #### SD_RESP_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x10
BitsFieldTypeResetDescription
31:16RESP1R0x0000Response 1
This register contains bits[39:24] of the response token.
15:0RESP0R0x0000Response 0
This register contains bits[23:8] of the response token.
+**Offset: 0x10** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RESP1 | R | 0x0000 | Response 1
This register contains bits[39:24] of the response token. | +| 15:0 | RESP0 | R | 0x0000 | Response 0
This register contains bits[23:8] of the response token. | #### SD_RESP_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14
BitsFieldTypeResetDescription
31:16RESP3R0x0000Response 3
- For 48-bit response tokens: Not used.
- For 136-bit response tokens: Stores bits [71:56] of the response token.
15:0RESP2R0x0000Response 2
- For 48-bit response tokens: Not used.
- For 136-bit response tokens: Stores bits [55:40] of the response token.
+**Offset: 0x14** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RESP3 | R | 0x0000 | Response 3
- For 48-bit response tokens: Not used.
- For 136-bit response tokens: Stores bits [71:56] of the response token. | +| 15:0 | RESP2 | R | 0x0000 | Response 2
- For 48-bit response tokens: Not used.
- For 136-bit response tokens: Stores bits [55:40] of the response token. | #### SD_RESP_2 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x18
BitsFieldTypeResetDescription
31:16RESP5R0x0000Response 5
- For 48-bit response tokens: Not used.
- For 136-bit response tokens: Stores bits [103:88] of the response token.
15:0RESP4R0x0000Response 4
- For 48-bit response tokens: Not used.
- For 136-bit response tokens: Stores bits [87:72] of the response token.
+**Offset: 0x18** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RESP5 | R | 0x0000 | Response 5
- For 48-bit response tokens: Not used.
- For 136-bit response tokens: Stores bits [103:88] of the response token. | +| 15:0 | RESP4 | R | 0x0000 | Response 4
- For 48-bit response tokens: Not used.
- For 136-bit response tokens: Stores bits [87:72] of the response token. | #### SD_RESP_3 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1C
BitsFieldTypeResetDescription
31:16RESP7R0x0000Response 7
- For 48-bit response tokens: Not used.
- For 136-bit response tokens: Stores bits [127:120] of the response token.
- For Auto CMD12 responses: Stores bits [39:24] of the response token.
15:0RESP6R0x0000Response 6
- For 48-bit response tokens: Not used.
- For 136-bit response tokens: Stores bits [119:104] of the response token.
- For Auto CMD12 responses: Stores bits [23:8] of the response token.
+**Offset: 0x1C** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RESP7 | R | 0x0000 | Response 7
- For 48-bit response tokens: Not used.
- For 136-bit response tokens: Stores bits [127:120] of the response token.
- For Auto CMD12 responses: Stores bits [39:24] of the response token. | +| 15:0 | RESP6 | R | 0x0000 | Response 6
- For 48-bit response tokens: Not used.
- For 136-bit response tokens: Stores bits [119:104] of the response token.
- For Auto CMD12 responses: Stores bits [23:8] of the response token. | #### SD_BUFFER_DATA_PORT REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x20
BitsFieldTypeResetDescription
31:0BUF_DATAR/W0x0Buffer Data
+**Offset: 0x20** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | BUF_DATA | R/W | 0x0 | Buffer Data | #### SD_PRESENT_STATE_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x24
BitsFieldTypeResetDescription
31:25RSVDR0Reserved for future use
24CMD_LEVELR0x1MMC1_CMD Line Signal Level
This status is used to check the MMC1_CMD line level to recover from errors and for debugging.
23:20DAT_LEVELR0xFMMC1_DAT[3:0] Line Signal Level
This status is used to check the MMC1_DAT[3:0] line level to recover from errors and for debugging.
This is especially useful in detecting the busy signal level from MMC1_DAT[0].
19WRITE_PROTR0x0Write Protect
This field reflects the position of the write_protect latch on the SD card.
This field should be ignored if there is no such feature being provided by the card in use.
18CARD_DETR0x0Card Detect
This field reflects the value of the MMC1_CD pin.
0: Card is not detected
1: Card is detected
Note: This field is only used for testing.
17CARD_STABLER0x0Card Stable
It indicates the debounced value of the card present condition.
0: Card is unstable
1: Card is stable
Note: This field is only used for testing.
16CARD_INSERTEDR0x0Card Inserted
This field indicates whether an SD card is present or not:.
0: Card is not inserted
1: Card is inserted
15:12RSVDR0Reserved for future use
11BUFFER_RD_ENR0x0Buffer Read Enable
This field changes from 0x0 to 0x1 when block data is ready in the buffer, and from 0x1 to 0x0 when all the block data is read from the buffer.
10BUFFER_WR_ENR0x1Buffer Write Enable
This field changes from 0x0 to 0x1 when block data can be written to the buffer. So if this bit is set to 0x1, the entire block can be written to the buffer. This field changes from 0x1 to 0x0 when all the block data is written to the buffer.
9RX_ACTIVER0x0Rx Active
This field indicates read transfer is active.
1: Active
0: Inactive
8TX_ACTIVER0x0Tx Active
Indicates write transfer is active.
0: No valid write data exists in the Host Controller
1: active
7:4RSVDR0Reserved for future use
3RETUNING_REQR0x0Re-Tuning Request
This field provides the status of the sampling clock.
0: Fixed or well tuned sampling clock
1: Sampling clock needs re-tuning
2_DAT_ACTIVER0x0Data Line Active
This field provides the status of the data line.
0: Data line is free
1: Data line is busy
1CMD_INHIBIT_DATR0x0Command Inhibit Data
This field provides the host driver status for issuing data commands.
0: Data command can be issued
1: Data command cannot be issued
0CMD_INHIBIT_CMDR0x0Command Inhibit Command
0: The MMC1_CMD line is available for issuing a new command.
- The host controller can issue a command using MMC1_CMD line.
- This bit is cleared (set to 0) when the command response is received from the device.
- If the <Command Inhibit Data> field is set to 1, commands using only the MMC1_CMD line can still be issued if this bit is 0.
1: The MMC1_CMD line is currently in use or unavailable.
- This bit is set after the command register is written, indicating that a command is in progress.
- It remains set until the command response is received.
When the bit changes from 1 to 0 (indicating that the command response has been received), a command complete interrupt is generated in the Normal Interrupt Status Register.
If the host controller cannot issue a command due to a command conflict error (e.g., attempting to issue a new command while the previous command is still in progress), this bit remains set to 1.
+**Offset: 0x24** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:25 | RSVD | R | 0 | Reserved for future use | +| 24 | CMD_LEVEL | R | 0x1 | MMC1_CMD Line Signal Level
This status is used to check the MMC1_CMD line level to recover from errors and for debugging. | +| 23:20 | DAT_LEVEL | R | 0xF | MMC1_DAT[3:0] Line Signal Level
This status is used to check the MMC1_DAT[3:0] line level to recover from errors and for debugging.
This is especially useful in detecting the busy signal level from MMC1_DAT[0]. | +| 19 | WRITE_PROT | R | 0x0 | Write Protect
This field reflects the position of the write_protect latch on the SD card.
This field should be ignored if there is no such feature being provided by the card in use. | +| 18 | CARD_DET | R | 0x0 | Card Detect
This field reflects the value of the MMC1_CD pin.
0: Card is not detected
1: Card is detected
Note: This field is only used for testing. | +| 17 | CARD_STABLE | R | 0x0 | Card Stable
It indicates the debounced value of the card present condition.
0: Card is unstable
1: Card is stable
Note: This field is only used for testing. | +| 16 | CARD_INSERTED | R | 0x0 | Card Inserted
This field indicates whether an SD card is present or not:.
0: Card is not inserted
1: Card is inserted | +| 15:12 | RSVD | R | 0 | Reserved for future use | +| 11 | BUFFER_RD_EN | R | 0x0 | Buffer Read Enable
This field changes from 0x0 to 0x1 when block data is ready in the buffer, and from 0x1 to 0x0 when all the block data is read from the buffer. | +| 10 | BUFFER_WR_EN | R | 0x1 | Buffer Write Enable
This field changes from 0x0 to 0x1 when block data can be written to the buffer. So if this bit is set to 0x1, the entire block can be written to the buffer. This field changes from 0x1 to 0x0 when all the block data is written to the buffer. | +| 9 | RX_ACTIVE | R | 0x0 | Rx Active
This field indicates read transfer is active.
1: Active
0: Inactive | +| 8 | TX_ACTIVE | R | 0x0 | Tx Active
Indicates write transfer is active.
0: No valid write data exists in the Host Controller
1: active | +| 7:4 | RSVD | R | 0 | Reserved for future use | +| 3 | RETUNING_REQ | R | 0x0 | Re-Tuning Request
This field provides the status of the sampling clock.
0: Fixed or well tuned sampling clock
1: Sampling clock needs re-tuning | +| 2 | _DAT_ACTIVE | R | 0x0 | Data Line Active
This field provides the status of the data line.
0: Data line is free
1: Data line is busy | +| 1 | CMD_INHIBIT_DAT | R | 0x0 | Command Inhibit Data
This field provides the host driver status for issuing data commands.
0: Data command can be issued
1: Data command cannot be issued | +| 0 | CMD_INHIBIT_CMD | R | 0x0 | Command Inhibit Command
0: The MMC1_CMD line is available for issuing a new command.
- The host controller can issue a command using MMC1_CMD line.
- This bit is cleared (set to 0) when the command response is received from the device.
- If the field is set to 1, commands using only the MMC1_CMD line can still be issued if this bit is 0.
1: The MMC1_CMD line is currently in use or unavailable.
- This bit is set after the command register is written, indicating that a command is in progress.
- It remains set until the command response is received.
When the bit changes from 1 to 0 (indicating that the command response has been received), a command complete interrupt is generated in the Normal Interrupt Status Register.
If the host controller cannot issue a command due to a command conflict error (e.g., attempting to issue a new command while the previous command is still in progress), this bit remains set to 1. | #### SD_HOST_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x28
BitsFieldTypeResetDescription
31:27RSVDR0Reserved for future use
26W_REMOVALR/W0x0Wakeup on Card Removal
1: Enable wakeup event on card removal detection
0: No wakeup event
25W_INSERTIONR/W0x0Wakeup on Card Insertion
1: Enable wakeup event on card insertion detection
0: No wakeup event
24W_CARD_INTR/W0x0Wakeup on Card Interrupt
1: Enable wakeup event on card interrupt detection
0: No wakeup event
23:20RSVDR0Reserved for future use
19INT_BLK_GAPR/W0x0Block Gap Interrupt
This field is only valid for 4-bit mode.
1: Enables interrupt detection at block gap for multiple block transfers
0: Disables interrupt detection at block gap for multiple block transfers
18RD_WAIT_CTLR/W0x0Read Wait Control
- If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using the MMC1_DAT[2] line by Host hardware. Otherwise, the Host Controller has to stop the SD clock from holding read data.
- When the Host driver detects a card insertion, it will set this bit according to the CCCR of the SDIO card.
- This field is only considered during the block gap phase. Within a block, hardware will stall the clock top stop read data if the host cannot accept any more data (e.g., due to FIFO being full, etc.)
- When this field is cleared by software, operation continues as usual.
- During read wait, software can issue a different commands for different operation as long as it does not require MMC1_DAT[3:0] lines.
- To resume the read operation after waiting, the software must clear this bit (set it to 0)
17CONT_REQR/WAC0x0Continue Request
- This field is used to restart a transaction which was stopped using the <Stop At Block Gap Request>.
- To cancel stop at the block gap, set the <Stop At Block Gap Request> field to 0 and set this field to 1 to restart the transfer.
- The Host Controller automatically clears this field in either of the following cases:
1. For a read transaction, when the MMC1_DAT[3:0] Line Active changes from 0 to 1, indicating a read transaction restarts.
2. For a write transaction, when the Write Transfer Active changes from 0 to 1, indicating the write transaction restarts.
As a result, it is not necessary for the Host driver to set this bit to 0.
- If <Stop At Block Gap Request> is set to 1, any write to this bit is ignored.
16STOP_AT_BLOCK_GAP_REQR/W0x0Stop at Block Gap Request
- This field is used to stop executing a transaction at the next block gap for both DMA and non-DMA transfers.
- The Host driver will leave this bit set to 1 until transfer completion is indicated (when transfer complete is set to 1)
- Clearing both this field and the <Continue Request> field will not cause the transaction to restart.
- For read transactions, Read Wait can be used to stop the transaction at the block gap.
- For write transactions, the host controller will stop the clock at the block gap request.
- For read transactions, if Read Wait Control is set to 0, the Host controller will stop the clock; otherwise, the Host controller will issue a Read Wait command to stop read data.
15:12RSVDR0Reserved for future use
11:9SD_BUS_VLTR/W0x0SD Bus Voltage
This field reflects the voltage at operating conditions
0x7: 3.3V
0x6: 3.0V
0x5: 1.8V
0x0 to 0x4: Reserved
8SD_BUS_POWERR/W0x0SD Bus Power
This field controls the power going out to the SD card.
The field will be cleared if:
- The sd_bus_vlt does not match the voltage support in Capabilities Register 1, or
- A card removal state is detected.
7CARD_DET_SR/W0x0Card Detect Signal Selection
This field selects the source for card detection.
0: Card detect input pin
1: Card detect test level (for debugging purposes only)
- When the source for card detection is switched, the interrupt should be disabled during the switching period by clearing the Normal Interrupt Status Enable Register in order to mask unexpected interrupts being caused by the glitch.
- This signal should be disabled via the Normal Interrupt Status Enable Register during debounce period.
6CARD_DET_LR/W0x0Card Detect Test Level
1: Card inserted
0: No card inserted
5EX_DATA_WIDTHR/W0x0This bit controls the 8-bit mode.
0x0: Data width for bus mode is determined by <DATA_WIDTH>
0x1: 8-bit data width.
4:3DMA_SELR/W0x0DMA Select
One of the supported DMA modes is selected.
The host driver checks support for DMA modes using the Capabilities Register 1. Use of the selected DMA is determined by the <DMA Enable> field in the Transfer Mode Register.
0x0: SDMA
0x1: ADMA 1
0x2: 32-bit address ADMA2
0x3: Reserved
2HI_SPEED_ENR/W0x0Extend Data Output Enable
0: Normal
1: MMC1_CMD and MMC1_DAT[3:0] are driven from rising edge of clock
1DATA_WIDTHR/W0x0Data Width
1: 4-bit data mode
0: 1-bit data mode, using only MMC1_DAT[0]
Refer to Bit [5] EX_DATA_WIDTH for 8-bit mode support.
0LED_CTRLR/W0x0LED Control
1: LED on
0: LED off
+**Offset: 0x28** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:27 | RSVD | R | 0 | Reserved for future use | +| 26 | W_REMOVAL | R/W | 0x0 | Wakeup on Card Removal
1: Enable wakeup event on card removal detection
0: No wakeup event | +| 25 | W_INSERTION | R/W | 0x0 | Wakeup on Card Insertion
1: Enable wakeup event on card insertion detection
0: No wakeup event | +| 24 | W_CARD_INT | R/W | 0x0 | Wakeup on Card Interrupt
1: Enable wakeup event on card interrupt detection
0: No wakeup event | +| 23:20 | RSVD | R | 0 | Reserved for future use | +| 19 | INT_BLK_GAP | R/W | 0x0 | Block Gap Interrupt
This field is only valid for 4-bit mode.
1: Enables interrupt detection at block gap for multiple block transfers
0: Disables interrupt detection at block gap for multiple block transfers | +| 18 | RD_WAIT_CTL | R/W | 0x0 | Read Wait Control
- If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using the MMC1_DAT[2] line by Host hardware. Otherwise, the Host Controller has to stop the SD clock from holding read data.
- When the Host driver detects a card insertion, it will set this bit according to the CCCR of the SDIO card.
- This field is only considered during the block gap phase. Within a block, hardware will stall the clock top stop read data if the host cannot accept any more data (e.g., due to FIFO being full, etc.)
- When this field is cleared by software, operation continues as usual.
- During read wait, software can issue a different commands for different operation as long as it does not require MMC1_DAT[3:0] lines.
- To resume the read operation after waiting, the software must clear this bit (set it to 0) | +| 17 | CONT_REQ | R/WAC | 0x0 | Continue Request
- This field is used to restart a transaction which was stopped using the .
- To cancel stop at the block gap, set the field to 0 and set this field to 1 to restart the transfer.
- The Host Controller automatically clears this field in either of the following cases:
1. For a read transaction, when the MMC1_DAT[3:0] Line Active changes from 0 to 1, indicating a read transaction restarts.
2. For a write transaction, when the Write Transfer Active changes from 0 to 1, indicating the write transaction restarts.
As a result, it is not necessary for the Host driver to set this bit to 0.
- If is set to 1, any write to this bit is ignored. | +| 16 | STOP_AT_BLOCK_GAP_REQ | R/W | 0x0 | Stop at Block Gap Request
- This field is used to stop executing a transaction at the next block gap for both DMA and non-DMA transfers.
- The Host driver will leave this bit set to 1 until transfer completion is indicated (when transfer complete is set to 1)
- Clearing both this field and the field will not cause the transaction to restart.
- For read transactions, Read Wait can be used to stop the transaction at the block gap.
- For write transactions, the host controller will stop the clock at the block gap request.
- For read transactions, if Read Wait Control is set to 0, the Host controller will stop the clock; otherwise, the Host controller will issue a Read Wait command to stop read data. | +| 15:12 | RSVD | R | 0 | Reserved for future use | +| 11:9 | SD_BUS_VLT | R/W | 0x0 | SD Bus Voltage
This field reflects the voltage at operating conditions
0x7: 3.3V
0x6: 3.0V
0x5: 1.8V
0x0 to 0x4: Reserved | +| 8 | SD_BUS_POWER | R/W | 0x0 | SD Bus Power
This field controls the power going out to the SD card.
The field will be cleared if:
- The sd_bus_vlt does not match the voltage support in Capabilities Register 1, or
- A card removal state is detected. | +| 7 | CARD_DET_S | R/W | 0x0 | Card Detect Signal Selection
This field selects the source for card detection.
0: Card detect input pin
1: Card detect test level (for debugging purposes only)
- When the source for card detection is switched, the interrupt should be disabled during the switching period by clearing the Normal Interrupt Status Enable Register in order to mask unexpected interrupts being caused by the glitch.
- This signal should be disabled via the Normal Interrupt Status Enable Register during debounce period. | +| 6 | CARD_DET_L | R/W | 0x0 | Card Detect Test Level
1: Card inserted
0: No card inserted | +| 5 | EX_DATA_WIDTH | R/W | 0x0 | This bit controls the 8-bit mode.
0x0: Data width for bus mode is determined by
0x1: 8-bit data width. | +| 4:3 | DMA_SEL | R/W | 0x0 | DMA Select
One of the supported DMA modes is selected.
The host driver checks support for DMA modes using the Capabilities Register 1. Use of the selected DMA is determined by the field in the Transfer Mode Register.
0x0: SDMA
0x1: ADMA 1
0x2: 32-bit address ADMA2
0x3: Reserved | +| 2 | HI_SPEED_EN | R/W | 0x0 | Extend Data Output Enable
0: Normal
1: MMC1_CMD and MMC1_DAT[3:0] are driven from rising edge of clock | +| 1 | DATA_WIDTH | R/W | 0x0 | Data Width
1: 4-bit data mode
0: 1-bit data mode, using only MMC1_DAT[0]
Refer to Bit [5] EX_DATA_WIDTH for 8-bit mode support. | +| 0 | LED_CTRL | R/W | 0x0 | LED Control
1: LED on
0: LED off | #### SD_CLOCK_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x2C
BitsFieldTypeResetDescription
31:27RSVDR0Reserved for future use
26SW_RST_DATR/WAC0x0Soft Reset for Data Port of Logic
25SW_RST_CMDR/WAC0x0Soft Reset for Command Part of Logic
24SW_RST_ALLR/WAC0x0Software Reset for All
This reset affects the status, state machine, and FIFOs synchronously.
This field also resets all private registers.
23:20RSVDR0Reserved for future use
19:16TIMEOUT_VALUER/W0x0Timeout Value
Determines the interval by which MMC1_DAT[3:0] line timeouts are detected. This timeout is initiated in the following cases:
- For read transaction, this timeout is about waiting for data from cards. It refers to the timing value in the SD specification, which specifies the maximum timing from read command to read data (i.e., card data access time);
- For write transaction, this timeout is about waiting for data from AXI slave, AXI Master, or processor, or waiting for CRC status of write block.
- Timeout Calculation:
1. 0x0: SDCLK x 2^13
2. 0x1: SDCLK x 2^14
3. ...
4. 0xE: SDCLK x 2^27
For example,
1. If sd_clk frequency = 200 MHz (base value), then the timeout base = 50 MHz (period = 20 ns).
- For 0xE setting:
Timeout = 2^27 * 20 ns ≈ 2.684 seconds.
2. If sd_clk frequency = 50 MHz (base value divided by 4), then the timeout base = 12.5 MHz (period = 80 ns).
- For 0xE setting:
Timeout = 2^27 * 80 ns ≈ 10.73 seconds.
0xF is Reserved for future use.
For other transactions, please refer to the SD specification for more information on these fixed values.
15:8SD_FREQ_SEL_LOR/W0x00SDCLK Frequency Select Lower bits
This field, together with the <SD_FREQ_SEL_HI> field, defines the clock divider value to be used by the host controller. The final value for the SD clock frequency divider is determined by combining both fields as follows:
SD_FREQ_SEL = {SD_FREQ_SEL_HI[1:0],SD_FREQ_SEL_LO[7:0]}
The selected value is multiplied by 2 to calculate the actual divide value. The possible SD clock frequency settings are:
- SD_FREQ_SEL = 0x00: Base clock
- SD_FREQ_SEL = 0x01: Divide by 2 of base clock
- SD_FREQ_SEL = 0x02: Divide by 4 of base clock
- SD_FREQ_SEL = 0x3: Divide by 6 of base clock
- ...
- SD_FREQ_SEL = 0x3FF: Divide by 2046 of base clock
7:6SD_FREQ_SEL_HIR/W0x0SDCLK Frequency Select Upper bits
This field, together with <SD_FREQ_SEL_LO> defines the clock divider value to be used by the host controller. The final value for the SD clock frequency divider is determined by combining both fields as follows:
SD_FREQ_SEL = {SD_FREQ_SEL_HI[1:0],SD_FREQ_SEL_LO[7:0]}.
5CLK_GEN_SELR/W0x0Clock Generator Select
This field is used to select the clock generator mode.
0x1: Programmable Clock Mode
0x0: Divided Clock mode
4:3RSVDR0Reserved for future use
2SD_CLK_ENR/W0x0SDCLK Clock Enable
This bit controls the SDCLK to the card.
Before using the card, this bit should be set during the initialization phase.
1INT_CLK_STABLER0x0Internal Clock Stable
This field is set to 1 once the controller detects that the internal clock is stable after setting of the <Internal Clock Enable> field.
0INT_CLK_ENR/W0x0Internal Clock Enable
This field controls the SDCLK to the internal logic.
1: Enable
0: Disable
+**Offset: 0x2C** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:27 | RSVD | R | 0 | Reserved for future use | +| 26 | SW_RST_DAT | R/WAC | 0x0 | Soft Reset for Data Port of Logic | +| 25 | SW_RST_CMD | R/WAC | 0x0 | Soft Reset for Command Part of Logic | +| 24 | SW_RST_ALL | R/WAC | 0x0 | Software Reset for All
This reset affects the status, state machine, and FIFOs synchronously.
This field also resets all private registers. | +| 23:20 | RSVD | R | 0 | Reserved for future use | +| 19:16 | TIMEOUT_VALUE | R/W | 0x0 | Timeout Value
Determines the interval by which MMC1_DAT[3:0] line timeouts are detected. This timeout is initiated in the following cases:
- For read transaction, this timeout is about waiting for data from cards. It refers to the timing value in the SD specification, which specifies the maximum timing from read command to read data (i.e., card data access time);
- For write transaction, this timeout is about waiting for data from AXI slave, AXI Master, or processor, or waiting for CRC status of write block.
- Timeout Calculation:
1. 0x0: SDCLK x 2^13
2. 0x1: SDCLK x 2^14
3. ...
4. 0xE: SDCLK x 2^27
For example,
1. If sd_clk frequency = 200 MHz (base value), then the timeout base = 50 MHz (period = 20 ns).
- For 0xE setting:
Timeout = 2^27 * 20 ns 鈮?2.684 seconds.
2. If sd_clk frequency = 50 MHz (base value divided by 4), then the timeout base = 12.5 MHz (period = 80 ns).
- For 0xE setting:
Timeout = 2^27 * 80 ns 鈮?10.73 seconds.
0xF is Reserved for future use.
For other transactions, please refer to the SD specification for more information on these fixed values. | +| 15:8 | SD_FREQ_SEL_LO | R/W | 0x00 | SDCLK Frequency Select Lower bits
This field, together with the field, defines the clock divider value to be used by the host controller. The final value for the SD clock frequency divider is determined by combining both fields as follows:
SD_FREQ_SEL = {SD_FREQ_SEL_HI[1:0],SD_FREQ_SEL_LO[7:0]}
The selected value is multiplied by 2 to calculate the actual divide value. The possible SD clock frequency settings are:
- SD_FREQ_SEL = 0x00: Base clock
- SD_FREQ_SEL = 0x01: Divide by 2 of base clock
- SD_FREQ_SEL = 0x02: Divide by 4 of base clock
- SD_FREQ_SEL = 0x3: Divide by 6 of base clock
- ...
- SD_FREQ_SEL = 0x3FF: Divide by 2046 of base clock | +| 7:6 | SD_FREQ_SEL_HI | R/W | 0x0 | SDCLK Frequency Select Upper bits
This field, together with defines the clock divider value to be used by the host controller. The final value for the SD clock frequency divider is determined by combining both fields as follows:
SD_FREQ_SEL = {SD_FREQ_SEL_HI[1:0],SD_FREQ_SEL_LO[7:0]}. | +| 5 | CLK_GEN_SEL | R/W | 0x0 | Clock Generator Select
This field is used to select the clock generator mode.
0x1: Programmable Clock Mode
0x0: Divided Clock mode | +| 4:3 | RSVD | R | 0 | Reserved for future use | +| 2 | SD_CLK_EN | R/W | 0x0 | SDCLK Clock Enable
This bit controls the SDCLK to the card.
Before using the card, this bit should be set during the initialization phase. | +| 1 | INT_CLK_STABLE | R | 0x0 | Internal Clock Stable
This field is set to 1 once the controller detects that the internal clock is stable after setting of the field. | +| 0 | INT_CLK_EN | R/W | 0x0 | Internal Clock Enable
This field controls the SDCLK to the internal logic.
1: Enable
0: Disable | #### SD_NORMAL_INT_STATUS REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x30
BitsFieldTypeResetDescription
31CRC_STATUS_ERRR/W1C0x0CRC Status Error
It is set to 1 if there is an error in any of the following:
- CRC status start bit
- CRC status end bit
- Boot ACK status
These errors are returned from the card in write transaction
30CPL_TIMEOUT_ERRR/W1C0x0Command Completion Signal Timeout Error
This field is applicable for CE-ATA mode only.
1: A command completion signal timeout occurred
29AXI_RESP_ERRR/W1C0x0AXI Bus Response Error
1: A response other than OKAY was received on the AXI bus.
28SPI_ERRR/W1C0x0SPI Mode Error
1: Error occurred in SPI mode for which cause can be determined by reading the <SPI Error Token> field in the SPI Mode Register
0: No error
27:26RSVDR0Reserved for future use
25ADMA_ERRR/W1C0x0ADMA (Advanced Direct Memory Access) Error
This bit is set when the host controller detects any errors during an ADMA-based data transfer.
The state of the ADMA at the time of the error is recorded in the ADMA Error Status Register.
This interrupt is also triggered when the host controller detects invalid descriptor data.
The <ADMA Error State> field in the ADMA Error Status Register indicates the state in which an error occurred.
The host driver may find that a Valid bit is not set at the error descriptor.
1 = Error
0 = No error
24AUTO_CMD12_ERRR/W1C0x0Auto CMD12 Error occurs when detecting that one of the bits in Auto CMD12 Error Status Register has changed from 0 to 1.
23CUR_LIMIT_ERRR/W1C0x0Current Limit Error
> Note. This feature is not supported currently, and this bit will always be read as 0.
22RD_DATA_END_BIT_ERRR/W1C0x0ReadData End Bit Error
This bit is set to 1 when a 0 is detected at the end bit position of read data that uses the MMC1_DAT[3:0] line, or at the end bit position of the CRC status.
21RD_DATA_CRC_ERRR/W1C0x0Read Data CRC Error
This bit is set to 1 when there is a CRC error detected in the read data transferred via the MMC1_DAT[3:0] line, or when the Write CRC status has a value other than 010.
20DATA_TIMEOUT_ERRR/W1C0x0Data Timeout Error
This bit is set to 1 when a timeout error occurs during data transfer, which could happen in the following scenarios:
- Busy timeout after write CRC status
- Write CRC status timeout
- Read data timeout
19CMD_INDEX_ERRR/W1C0x0Command Index Error
0: No command index error has occurred in the command response
1: Command index error has occurred in the command response
18CMD_END_BIT_ERRR/W1C0x0Command End Bit Error
0: Detection of end bit of a command response in 1
1: Detection of end bit of a command response is 0
17CMD_CRC_ERRR/W1C0x0Command CRC Error
This bit is set to 1 in two cases:
- A CRC error is detected in the command response.
- The host controller detects a conflict on the MMC1_CMD line while issuing a command. In this case, the host controller will abort the command by stopping the MMC1_CMD line, and the <Command Timeout Error> field will also be set to 1 to distinguish the MMC1_CMD line conflict.
16CMD_TIMEOUT_ERRR/W1C0x0Command Timeout Error
1: No response is returned within 64 SDCLK cycles from the end bit of the command
15ERR_INTR0x0Error Interrupt
If any of bits in the Error Interrupt Status Register are set, then this bit is set.
14CQ_INTRC0x0Command Queuing Interrupt
This interrupt is asserted when at least one of the bits in the CQIS register is set.
This interrupt is cleared only when the source interrupt in the CQIS register is cleared.
13RSVDR0Reserved for future use
12RETUNING_INTR/W1C0x0Re-tuning Event Interrupt
This status is set when the Re-Tuning Request in the <Present State Register> changes from 0x0 to 0x1. This indicates that the host controller is requesting the host driver to perform re-tuning starting from the next data transfer. The current data transfer can be completed without requiring re-tuning.
11INT_CR/W1C0x0This status is set when INT_C is enabled and INT_C# pin is in low level. Writing this bit to 0x1 does not clear this bit.
It is cleared by resetting the INT_C interrupt factor. Refer to shared bus control register (SHARED_BUS_CTRL).
10INT_BR/W1C0x0This status is set when INT_B is enabled and INT_B# pin is in low level. Writing this bit to 0x1 does not clear this bit.
It is cleared by resetting the INT_B interrupt factor. Refer to shared bus control register (SHARED_BUS_CTRL).
9INT_AR/W1C0x0This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 0x1 does not clear this bit.
It is cleared by resetting the INT_A interrupt factor. Refer to shared bus control register (SHARED_BUS_CTRL).
8CARD_INTR0x0Card Interrupt
1: Host controller detects an interrupt from the card
7CARD_REM_INTR/W1C0x0Card Removal Interrupt
1: Card removal event detected
6CARD_INS_INTR/W1C0x0Card Insertion Interrupt
1: Card insertion event detected
5RX_RDYR/W1C0x0Rx Ready
This status is set when the <Buffer Read Enable> field in the Present State Register 1 changes from 0x0 to 0x1.
4TX_RDYR/W1C0x1Tx Ready
This status is set when the <Buffer Write Enable> field in the Present State Register 1 changes from 0x0 to 0x1.
3DMA_INTR/W1C0x0DMA Interrupt
This status is set when the Host Controller detects DMA crossing over the <Host DMA Buffer Boundary> field in the Block Size Register.
2BLOCK_GAP_EVTR/W1C0x0Block Gap Event
This field is set when a read or write transaction is stopped at a block gap, but only if the <Stop At Block Gap Request> field in the Block Gap Control Register is set.
- If the <Stop At Block Gap Request> field is not set to 1, this bit will remain 0.
1XFER_COMPLETER/W1C0x0Transfer Complete
This bit is set when a read/write transaction is completed.
- For read transactions:
This bit is set at the falling edge of Read Transfer Active Status, and it can occur in two cases:
1. Data transfer is completed as specified by the data length.
2. The data transfer is stopped at the block gap and completed after setting the <Stop At Block Gap Request> field in the SD Block Gap Control Register.
- For write transactions:
This bit is set at the falling edge of the MMC1_DAT[3:0] Line Active status, and it can occur in two cases:
1. Data transfer is completed as specified by the data length, and the busy signal is released.
2. The data transfer is stopped at the block gap and completed after setting the <Stop At Block Gap Request> field.
0CMD_COMPLETER/W1C0x0Command Complete
This bit is set when the end bit of the command response (Except Auto CMD12) is received.
> Note. Command Timeout Error has higher priority than Command complete.
+**Offset: 0x30** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | CRC_STATUS_ERR | R/W1C | 0x0 | CRC Status Error
It is set to 1 if there is an error in any of the following:
- CRC status start bit
- CRC status end bit
- Boot ACK status
These errors are returned from the card in write transaction | +| 30 | CPL_TIMEOUT_ERR | R/W1C | 0x0 | Command Completion Signal Timeout Error
This field is applicable for CE-ATA mode only.
1: A command completion signal timeout occurred | +| 29 | AXI_RESP_ERR | R/W1C | 0x0 | AXI Bus Response Error
1: A response other than OKAY was received on the AXI bus. | +| 28 | SPI_ERR | R/W1C | 0x0 | SPI Mode Error
1: Error occurred in SPI mode for which cause can be determined by reading the field in the SPI Mode Register
0: No error | +| 27:26 | RSVD | R | 0 | Reserved for future use | +| 25 | ADMA_ERR | R/W1C | 0x0 | ADMA (Advanced Direct Memory Access) Error
This bit is set when the host controller detects any errors during an ADMA-based data transfer.
The state of the ADMA at the time of the error is recorded in the ADMA Error Status Register.
This interrupt is also triggered when the host controller detects invalid descriptor data.
The field in the ADMA Error Status Register indicates the state in which an error occurred.
The host driver may find that a Valid bit is not set at the error descriptor.
1 = Error
0 = No error | +| 24 | AUTO_CMD12_ERR | R/W1C | 0x0 | Auto CMD12 Error occurs when detecting that one of the bits in Auto CMD12 Error Status Register has changed from 0 to 1. | +| 23 | CUR_LIMIT_ERR | R/W1C | 0x0 | Current Limit Error
> Note. This feature is not supported currently, and this bit will always be read as 0. | +| 22 | RD_DATA_END_BIT_ERR | R/W1C | 0x0 | ReadData End Bit Error
This bit is set to 1 when a 0 is detected at the end bit position of read data that uses the MMC1_DAT[3:0] line, or at the end bit position of the CRC status. | +| 21 | RD_DATA_CRC_ERR | R/W1C | 0x0 | Read Data CRC Error
This bit is set to 1 when there is a CRC error detected in the read data transferred via the MMC1_DAT[3:0] line, or when the Write CRC status has a value other than 010. | +| 20 | DATA_TIMEOUT_ERR | R/W1C | 0x0 | Data Timeout Error
This bit is set to 1 when a timeout error occurs during data transfer, which could happen in the following scenarios:
- Busy timeout after write CRC status
- Write CRC status timeout
- Read data timeout | +| 19 | CMD_INDEX_ERR | R/W1C | 0x0 | Command Index Error
0: No command index error has occurred in the command response
1: Command index error has occurred in the command response | +| 18 | CMD_END_BIT_ERR | R/W1C | 0x0 | Command End Bit Error
0: Detection of end bit of a command response in 1
1: Detection of end bit of a command response is 0 | +| 17 | CMD_CRC_ERR | R/W1C | 0x0 | Command CRC Error
This bit is set to 1 in two cases:
- A CRC error is detected in the command response.
- The host controller detects a conflict on the MMC1_CMD line while issuing a command. In this case, the host controller will abort the command by stopping the MMC1_CMD line, and the field will also be set to 1 to distinguish the MMC1_CMD line conflict. | +| 16 | CMD_TIMEOUT_ERR | R/W1C | 0x0 | Command Timeout Error
1: No response is returned within 64 SDCLK cycles from the end bit of the command | +| 15 | ERR_INT | R | 0x0 | Error Interrupt
If any of bits in the Error Interrupt Status Register are set, then this bit is set. | +| 14 | CQ_INT | RC | 0x0 | Command Queuing Interrupt
This interrupt is asserted when at least one of the bits in the CQIS register is set.
This interrupt is cleared only when the source interrupt in the CQIS register is cleared. | +| 13 | RSVD | R | 0 | Reserved for future use | +| 12 | RETUNING_INT | R/W1C | 0x0 | Re-tuning Event Interrupt
This status is set when the Re-Tuning Request in the changes from 0x0 to 0x1. This indicates that the host controller is requesting the host driver to perform re-tuning starting from the next data transfer. The current data transfer can be completed without requiring re-tuning. | +| 11 | INT_C | R/W1C | 0x0 | This status is set when INT_C is enabled and INT_C# pin is in low level. Writing this bit to 0x1 does not clear this bit.
It is cleared by resetting the INT_C interrupt factor. Refer to shared bus control register (SHARED_BUS_CTRL). | +| 10 | INT_B | R/W1C | 0x0 | This status is set when INT_B is enabled and INT_B# pin is in low level. Writing this bit to 0x1 does not clear this bit.
It is cleared by resetting the INT_B interrupt factor. Refer to shared bus control register (SHARED_BUS_CTRL). | +| 9 | INT_A | R/W1C | 0x0 | This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 0x1 does not clear this bit.
It is cleared by resetting the INT_A interrupt factor. Refer to shared bus control register (SHARED_BUS_CTRL). | +| 8 | CARD_INT | R | 0x0 | Card Interrupt
1: Host controller detects an interrupt from the card | +| 7 | CARD_REM_INT | R/W1C | 0x0 | Card Removal Interrupt
1: Card removal event detected | +| 6 | CARD_INS_INT | R/W1C | 0x0 | Card Insertion Interrupt
1: Card insertion event detected | +| 5 | RX_RDY | R/W1C | 0x0 | Rx Ready
This status is set when the field in the Present State Register 1 changes from 0x0 to 0x1. | +| 4 | TX_RDY | R/W1C | 0x1 | Tx Ready
This status is set when the field in the Present State Register 1 changes from 0x0 to 0x1. | +| 3 | DMA_INT | R/W1C | 0x0 | DMA Interrupt
This status is set when the Host Controller detects DMA crossing over the field in the Block Size Register. | +| 2 | BLOCK_GAP_EVT | R/W1C | 0x0 | Block Gap Event
This field is set when a read or write transaction is stopped at a block gap, but only if the field in the Block Gap Control Register is set.
- If the field is not set to 1, this bit will remain 0. | +| 1 | XFER_COMPLETE | R/W1C | 0x0 | Transfer Complete
This bit is set when a read/write transaction is completed.
- For read transactions:
This bit is set at the falling edge of Read Transfer Active Status, and it can occur in two cases:
1. Data transfer is completed as specified by the data length.
2. The data transfer is stopped at the block gap and completed after setting the field in the SD Block Gap Control Register.
- For write transactions:
This bit is set at the falling edge of the MMC1_DAT[3:0] Line Active status, and it can occur in two cases:
1. Data transfer is completed as specified by the data length, and the busy signal is released.
2. The data transfer is stopped at the block gap and completed after setting the field. | +| 0 | CMD_COMPLETE | R/W1C | 0x0 | Command Complete
This bit is set when the end bit of the command response (Except Auto CMD12) is received.
> Note. Command Timeout Error has higher priority than Command complete. | #### SD_NORMAL_INT_STATUS_EN REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x34
BitsFieldTypeResetDescription
31CRC_STATUS_ERR_ENR/W0x0CRC Status Error Enable
0: Disabled
1: Enabled
30CPL_TIMEOUT_ERR_ENR/W0x0CPL Timeout Error Enable
0: Disabled
1: Enabled
29AXI_RESP_ERR_ENR/W0x0AXI Response Error
0: Disabled
1: Enabled
28SPI_ERR_ENR/W0x0SPI Error Enable
0: Disabled
1: Enabled
27RSVDR0Reserved for future use
26TUNING_ERR_ENR/W0x0Tuning Error Enable
0: Disabled
1: Enabled
25ADMA_ERR_ENR/W0x0ADMA Error Enable
0: Disabled
1: Enabled
24AUTO_CMD12_ERR_ENR/W0x0Auto CMD12 Error Enable
0: Disabled
1: Enabled
23CUR_LIM_ERR_ENR/W0x0Current Limit Error Enable
0: Disabled
1: Enabled
22RD_DATA_END_BIT_ERR_ENR/W0x0Data End Bit Error Enable
0: Disabled
1: Enabled
21RD_DATA_CRC_ERR_ENR/W0x0Data CRC Error Enable
0: Disabled
1: Enabled
20DATA_TIMEOUT_ERR_ENR/W0x0Data Timeout Error Enable
0: Disabled
1: Enabled
19CMD_INDEX_ERR_ENR/W0x0Command Index Error Enable
0: Disabled
1: Enabled
18CMD_END_BIT_ERR_ENR/W0x0 Command End Bit Error Enable
0: Disabled
1: Enabled
17CMD_CRC_ERR_ENR/W0x0Command CRC Error Enable
0: Disabled
1: Enabled
16CMD_TIMEOUT_ERR_ENR/W0x0Command Timeout Error Enable
0: Disabled
1: Enabled
15RSVDR0Reserved for future use
14CQ_STATUS_ENR/W0x0Command Queuing Status Enable
0: Disabled
1: Enabled
13RSVDR0Reserved for future use
12RETUNE_INT_ENR/W0x0Re_tuning Interrupt Enable
0: Disabled
1: Enabled
11INT_C_INT_ENR/W0x0INT_C Enable
0: Disabled
1: Enabled
10INT_B_INT_ENR/W0x0INT_B Enable
0: Disabled
1: Enabled
9INT_A_INT_ENR/W0x0INT_A Enable
0: Disabled
1: Enabled
8CARD_INT_ENR/W0x0Card Interrupt Enable
0: Disabled
1: Enabled
7CARD_REM_ENR/W0x0Card Removal Status Enable
0: Disabled
1: Enabled
6CARD_INS_ENR/W0x0Card Insertion Status Enable
0: Disabled
1: Enabled
5RD_RDY_ENR/W0x0Buffer Read Ready Enable
0: Disabled
1: Enabled
4TX_RDY_ENR/W0x0Buffer Write Ready Enable
0: Disabled
1: Enabled
3DMA_INT_ENR/W0x0DMA Interrupt Enable
0: Disabled
1: Enabled
2BLOCK_GAP_EVT_ENR/W0x0Block Gap Event Enable
0: Disabled
1: Enabled
1XFER_COMPLETE_ENR/W0x0Transfer Complete Enable
0: Disabled
1: Enabled
0CMD_COMPLETE_ENR/W0x0Command Complete Enable
0: Disabled
1: Enabled
+**Offset: 0x34** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | CRC_STATUS_ERR_EN | R/W | 0x0 | CRC Status Error Enable
0: Disabled
1: Enabled | +| 30 | CPL_TIMEOUT_ERR_EN | R/W | 0x0 | CPL Timeout Error Enable
0: Disabled
1: Enabled | +| 29 | AXI_RESP_ERR_EN | R/W | 0x0 | AXI Response Error
0: Disabled
1: Enabled | +| 28 | SPI_ERR_EN | R/W | 0x0 | SPI Error Enable
0: Disabled
1: Enabled | +| 27 | RSVD | R | 0 | Reserved for future use | +| 26 | TUNING_ERR_EN | R/W | 0x0 | Tuning Error Enable
0: Disabled
1: Enabled | +| 25 | ADMA_ERR_EN | R/W | 0x0 | ADMA Error Enable
0: Disabled
1: Enabled | +| 24 | AUTO_CMD12_ERR_EN | R/W | 0x0 | Auto CMD12 Error Enable
0: Disabled
1: Enabled | +| 23 | CUR_LIM_ERR_EN | R/W | 0x0 | Current Limit Error Enable
0: Disabled
1: Enabled | +| 22 | RD_DATA_END_BIT_ERR_EN | R/W | 0x0 | Data End Bit Error Enable
0: Disabled
1: Enabled | +| 21 | RD_DATA_CRC_ERR_EN | R/W | 0x0 | Data CRC Error Enable
0: Disabled
1: Enabled | +| 20 | DATA_TIMEOUT_ERR_EN | R/W | 0x0 | Data Timeout Error Enable
0: Disabled
1: Enabled | +| 19 | CMD_INDEX_ERR_EN | R/W | 0x0 | Command Index Error Enable
0: Disabled
1: Enabled | +| 18 | CMD_END_BIT_ERR_EN | R/W | 0x0 | Command End Bit Error Enable
0: Disabled
1: Enabled | +| 17 | CMD_CRC_ERR_EN | R/W | 0x0 | Command CRC Error Enable
0: Disabled
1: Enabled | +| 16 | CMD_TIMEOUT_ERR_EN | R/W | 0x0 | Command Timeout Error Enable
0: Disabled
1: Enabled | +| 15 | RSVD | R | 0 | Reserved for future use | +| 14 | CQ_STATUS_EN | R/W | 0x0 | Command Queuing Status Enable
0: Disabled
1: Enabled | +| 13 | RSVD | R | 0 | Reserved for future use | +| 12 | RETUNE_INT_EN | R/W | 0x0 | Re_tuning Interrupt Enable
0: Disabled
1: Enabled | +| 11 | INT_C_INT_EN | R/W | 0x0 | INT_C Enable
0: Disabled
1: Enabled | +| 10 | INT_B_INT_EN | R/W | 0x0 | INT_B Enable
0: Disabled
1: Enabled | +| 9 | INT_A_INT_EN | R/W | 0x0 | INT_A Enable
0: Disabled
1: Enabled | +| 8 | CARD_INT_EN | R/W | 0x0 | Card Interrupt Enable
0: Disabled
1: Enabled | +| 7 | CARD_REM_EN | R/W | 0x0 | Card Removal Status Enable
0: Disabled
1: Enabled | +| 6 | CARD_INS_EN | R/W | 0x0 | Card Insertion Status Enable
0: Disabled
1: Enabled | +| 5 | RD_RDY_EN | R/W | 0x0 | Buffer Read Ready Enable
0: Disabled
1: Enabled | +| 4 | TX_RDY_EN | R/W | 0x0 | Buffer Write Ready Enable
0: Disabled
1: Enabled | +| 3 | DMA_INT_EN | R/W | 0x0 | DMA Interrupt Enable
0: Disabled
1: Enabled | +| 2 | BLOCK_GAP_EVT_EN | R/W | 0x0 | Block Gap Event Enable
0: Disabled
1: Enabled | +| 1 | XFER_COMPLETE_EN | R/W | 0x0 | Transfer Complete Enable
0: Disabled
1: Enabled | +| 0 | CMD_COMPLETE_EN | R/W | 0x0 | Command Complete Enable
0: Disabled
1: Enabled | #### SD_NORMAL_INT_STATUS_INT_EN REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x38
BitsFieldTypeResetDescription
31
CRC_STATUS_ERR_INT_ENR/W0x0CRC Status Error Interrupt Enable
0: Disabled
1: Enabled
30CPL_TIMEOUT_ERR_INT_ENR/W0x0CPL Timeout Error Interrupt Enable
0: Disabled
1: Enabled
29AXI_RESP_ERR_INT_ENR/W0x0AXI Response Error Interrupt Enable
0: Disabled
1: Enabled
28SPI_ERR_INT_ENR/W0x0SPI Error Interrupt Enable
0: Disabled
1: Enabled
27RSVDR0Reserved for future use
26TUNE_ERR_INT_ENR/W0x0Tuning Error Interrupt Enable
0: Disabled
1: Enabled
25ADMA_ERR_INT_ENR/W0x0ADMA Error Interrupt Enable
0: Disabled
1: Enabled
24AUTO_CMD12_ERR_INT_ENR/W0x0Auto CMD12 Error Interrupt Enable
0: Disabled
1: Enabled
23CUR_LIM_ERR_INT_ENR/W0x0Current Limit Error Interrupt Enable
0: Disabled
1: Enabled
22RD_DATA_END_BIT_ERR_INT_ENR/W0x0Data End Bit Error Interrupt Enable
0: Disabled
1: Enabled
21RD_DATA_CRC_ERR_INT_ENR/W0x0Data CRC Error Interrupt Enable
0: Disabled
1: Enabled
20DATA_TIMEOUT_ERR_INT_ENR/W0x0Data Timeout Error Interrupt Enable
0: Disabled
1: Enabled
19CMD_INDEX_ERR_INT_ENR/W0x0Command Index Error Interrupt Enable
0: Disabled
1: Enabled
18CMD_END_BIT_ERR_INT_ENR/W0x0Command End Bit Interrupt Error Enable
0: Disabled
1: Enabled
17CMD_CRC_ERR_INT_ENR/W0x0Command CRC Error Interrupt Enable
0: Disabled
1: Enabled
16CMD_TIMEOUT_ERR_INT_ENR/W0x0Command Timeout Error Interrupt Enable
0: Disabled
1: Enabled
15RSVDR0Reserved for future use
14CQ_SIGNAL_ENABLER/W0x0Command Queuing Signal Enable
0: Disabled
1: Enabled
13CARD_ASYNC_INT_INT_ENR/W0x0SDIO Card Async INT without AXI/SD function clock running Interrupt Enable
0: Disabled
1: Enabled
12RETUNE_INT_INT_ENR/W0x0Re-Tuning Interrupt Interrupt Enable
0: Disabled
1: Enabled
11INT_C_INT_INT_ENR/W0x0INT_C Interrupt Interrupt Enable
0: Disabled
1: Enabled
10INT_B_INT_INT_ENR/W0x0INT_B Interrupt Interrupt Enable
0: Disabled
1: Enabled
9INT_A_INT_INT_ENR/W0x0INT_A Interrupt Interrupt Enable
0: Disabled
1: Enabled
8CARD_INT_INT_ENR/W0x0Card Interrupt Interrupt Enable
0: Disabled
1: Enabled
7CARD_REM_INT_ENR/W0x0Card Removal Interrupt Enable
0: Disabled
1: Enabled
6CARD_INS_INT_ENR/W0x0Card Insertion Interrupt Enable
0: Disabled
1: Enabled
5RX_RDY_INT_ENR/W0x0Buffer Read Ready Interrupt Enable
0: Disabled
1: Enabled
4TX_RDY_INT_ENR/W0x0Buffer Write Ready Interrupt Enable
0: Disabled
1: Enabled
3DMA_INT_INT_ENR/W0x0DMA Interrupt Interrupt Enable
0: Disabled
1: Enabled
2BLOCK_GAP_EVT_INT_ENR/W0x0Block Gap Event Interrupt Enable
0: Disabled
1: Enabled
1XFER_COMPLETE_INT_ENR/W0x0Transfer Complete Interrupt Enable
0: Disabled
1: Enabled
0CMD_COMPLETE_INT_ENR/W0x0Command Complete Interrupt Enable
0: Disabled
1: Enabled
+**Offset: 0x38** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31
| CRC_STATUS_ERR_INT_EN | R/W | 0x0 | CRC Status Error Interrupt Enable
0: Disabled
1: Enabled | +| 30 | CPL_TIMEOUT_ERR_INT_EN | R/W | 0x0 | CPL Timeout Error Interrupt Enable
0: Disabled
1: Enabled | +| 29 | AXI_RESP_ERR_INT_EN | R/W | 0x0 | AXI Response Error Interrupt Enable
0: Disabled
1: Enabled | +| 28 | SPI_ERR_INT_EN | R/W | 0x0 | SPI Error Interrupt Enable
0: Disabled
1: Enabled | +| 27 | RSVD | R | 0 | Reserved for future use | +| 26 | TUNE_ERR_INT_EN | R/W | 0x0 | Tuning Error Interrupt Enable
0: Disabled
1: Enabled | +| 25 | ADMA_ERR_INT_EN | R/W | 0x0 | ADMA Error Interrupt Enable
0: Disabled
1: Enabled | +| 24 | AUTO_CMD12_ERR_INT_EN | R/W | 0x0 | Auto CMD12 Error Interrupt Enable
0: Disabled
1: Enabled | +| 23 | CUR_LIM_ERR_INT_EN | R/W | 0x0 | Current Limit Error Interrupt Enable
0: Disabled
1: Enabled | +| 22 | RD_DATA_END_BIT_ERR_INT_EN | R/W | 0x0 | Data End Bit Error Interrupt Enable
0: Disabled
1: Enabled | +| 21 | RD_DATA_CRC_ERR_INT_EN | R/W | 0x0 | Data CRC Error Interrupt Enable
0: Disabled
1: Enabled | +| 20 | DATA_TIMEOUT_ERR_INT_EN | R/W | 0x0 | Data Timeout Error Interrupt Enable
0: Disabled
1: Enabled | +| 19 | CMD_INDEX_ERR_INT_EN | R/W | 0x0 | Command Index Error Interrupt Enable
0: Disabled
1: Enabled | +| 18 | CMD_END_BIT_ERR_INT_EN | R/W | 0x0 | Command End Bit Interrupt Error Enable
0: Disabled
1: Enabled | +| 17 | CMD_CRC_ERR_INT_EN | R/W | 0x0 | Command CRC Error Interrupt Enable
0: Disabled
1: Enabled | +| 16 | CMD_TIMEOUT_ERR_INT_EN | R/W | 0x0 | Command Timeout Error Interrupt Enable
0: Disabled
1: Enabled | +| 15 | RSVD | R | 0 | Reserved for future use | +| 14 | CQ_SIGNAL_ENABLE | R/W | 0x0 | Command Queuing Signal Enable
0: Disabled
1: Enabled | +| 13 | CARD_ASYNC_INT_INT_EN | R/W | 0x0 | SDIO Card Async INT without AXI/SD function clock running Interrupt Enable
0: Disabled
1: Enabled | +| 12 | RETUNE_INT_INT_EN | R/W | 0x0 | Re-Tuning Interrupt Interrupt Enable
0: Disabled
1: Enabled | +| 11 | INT_C_INT_INT_EN | R/W | 0x0 | INT_C Interrupt Interrupt Enable
0: Disabled
1: Enabled | +| 10 | INT_B_INT_INT_EN | R/W | 0x0 | INT_B Interrupt Interrupt Enable
0: Disabled
1: Enabled | +| 9 | INT_A_INT_INT_EN | R/W | 0x0 | INT_A Interrupt Interrupt Enable
0: Disabled
1: Enabled | +| 8 | CARD_INT_INT_EN | R/W | 0x0 | Card Interrupt Interrupt Enable
0: Disabled
1: Enabled | +| 7 | CARD_REM_INT_EN | R/W | 0x0 | Card Removal Interrupt Enable
0: Disabled
1: Enabled | +| 6 | CARD_INS_INT_EN | R/W | 0x0 | Card Insertion Interrupt Enable
0: Disabled
1: Enabled | +| 5 | RX_RDY_INT_EN | R/W | 0x0 | Buffer Read Ready Interrupt Enable
0: Disabled
1: Enabled | +| 4 | TX_RDY_INT_EN | R/W | 0x0 | Buffer Write Ready Interrupt Enable
0: Disabled
1: Enabled | +| 3 | DMA_INT_INT_EN | R/W | 0x0 | DMA Interrupt Interrupt Enable
0: Disabled
1: Enabled | +| 2 | BLOCK_GAP_EVT_INT_EN | R/W | 0x0 | Block Gap Event Interrupt Enable
0: Disabled
1: Enabled | +| 1 | XFER_COMPLETE_INT_EN | R/W | 0x0 | Transfer Complete Interrupt Enable
0: Disabled
1: Enabled | +| 0 | CMD_COMPLETE_INT_EN | R/W | 0x0 | Command Complete Interrupt Enable
0: Disabled
1: Enabled | #### SD_AUTO_CMD12_ERROR_STATUS REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x3C
BitsFieldTypeResetDescription
31PRE_VAL_ENR/W0x0Preset Value Enable
0x1: Automatic selection by Preset Value are Enabled
0x0: SDCLK and Driver Strength are controlled by Host Driver
30ASYNC_INT_ENR/W0x1Asynchronous Interrupt Enable
This bit can be set to 0x1 if a card supports asynchronous interrupts and <async_int_support> is set to 0x1 in the capabilities register.
Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode (and <int_pin_sel> is set to 0 in Shared Bus Control register).
When this bit is set to 0x1, the host driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the host controller continues to deliver the Card Interrupt to the host when it is asserted by the card.
0x1: Enabled
0x0: Disabled
29:24RSVDR0Reserved for future use
23SAMPLING_CLK_SELR/W0x0Sampling Clock Select
Host controller uses this bit to select sampling clock to receive CMD and DAT.
This bit is set by tuning procedure and valid after the completion of tuning (when <exe_tuning> is cleared).
0x1: Tuned clock is used to sample data (indicating that tuning was successful).
0x0: Fixed clock is used to sample data (indicating that tuning failed).
Writing 0x1 to this bit is meaningless and ignored if tuning is not yet complete. If the bit is written as 0x0, the tuning circuit is reset. However, resetting the tuning circuit requires time to complete the tuning sequence. The host driver should keep this bit set to 0x1 to perform re-tuning quickly when necessary.
Changes to this bit are not allowed while the host controller is receiving responses or a read data block.
22EXE_TUNINGR/WAC0x0Execute Tuning
This bit is set to 0x1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of the tuning is reflected in the <sampling_clk_sel>. The tuning procedure is aborted by writing 0x0.
0x1: Execute Tuning
0x0: Not tuned or Tuning completed
21:20DRV_STRENGTH_SELR/W0x0Driver Strength Select.
Host Controller output driver in 1.8V signaling is selected by this field. With 3.3V signaling, this field is not effective. This field can be set depending on Driver Type A, C and D support bits in the Capabilities register.
This bit depends on the setting of <pre_val_en>.
- If <pre_val_en> = 0x0, this field is set by the host driver.
- If <pre_val_en> = 0x1, this field is automatically set by a value specified in one of the Preset Value registers.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D
19SDH_V18_ENR/W0x01.8V Signaling Enable
0x1: 1.8V Signaling enable
0x0: 3.3V Signaling enable
18:16UHS_MODE_SELR/W0x0UHS Mode Select
This field is used to select one of UHS-I modes and effective when <sdh_v18_en> = 0x1.
If <pre_val_en> in the Host Control2 register is set to 0x1, host controller sets SDCLK Frequency select, Clock generator select in the clock control register, and driver strength select according to the Preset Value registers.
In this case, one of the preset value registers is selected by this field.
Host driver should reset <sd_clk_en> before changing this field to avoid generating clock glitch
0x0: SDR12
0x1: SDR25
0x2: SDR50
0x3: SDR104
0x4: DDR50
For MMC mode, added two backdoor defined modes:
0x5: HS200 mode
0x6: HS400 mode
All other values are Reserved
15:8RSVDR0Reserved for future use
7CMD_NOT_ISSUEDRC0x0Command Not Issued
This is due to auto_cmd12 Error
6:5RSVDR0Reserved for future use
4AUTO_CMD_INDEX_ERRR/W1C0x0Auto CMD12 or Auto CMD23 Error
This error occurs when the command index error occurs in response to a command
0: Disabled
1: Enabled
3AUTO_CMD_END_BIT_ERRR/W1C0x0Auto CMD12 or Auto CMD23 End Bit Error
This error occurs when detecting that the end bit of command response is 0.
0: Disabled
1: Enabled
2AUTO_CMD_CRC_ERRR/W1C0x0Auto CMD12 or Auto CMD23 CRC Error
This error occurs when detecting CRC error in the command response.
0: Disabled
1: Enabled
1AUTO_CMD_TIMEOUT_ERRR/W1C0x0Auto CMD12 or Auto CMD23 Timeout Error
This error occurs when no response is returned within 64 SDCLK cycles from the end bit of command.
0: Disabled
1: Enabled
0AUTO_CMD12_NOT_EXER/W1C0x0Auto CMD12 Not Executed
This error occurs when host controller cannot issue Auto cmd12 to stop multiple block data transfer due to some errors.
0: Disabled
1: Enabled
+**Offset: 0x3C** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | PRE_VAL_EN | R/W | 0x0 | Preset Value Enable
0x1: Automatic selection by Preset Value are Enabled
0x0: SDCLK and Driver Strength are controlled by Host Driver | +| 30 | ASYNC_INT_EN | R/W | 0x1 | Asynchronous Interrupt Enable
This bit can be set to 0x1 if a card supports asynchronous interrupts and is set to 0x1 in the capabilities register.
Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode (and is set to 0 in Shared Bus Control register).
When this bit is set to 0x1, the host driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the host controller continues to deliver the Card Interrupt to the host when it is asserted by the card.
0x1: Enabled
0x0: Disabled | +| 29:24 | RSVD | R | 0 | Reserved for future use | +| 23 | SAMPLING_CLK_SEL | R/W | 0x0 | Sampling Clock Select
Host controller uses this bit to select sampling clock to receive CMD and DAT.
This bit is set by tuning procedure and valid after the completion of tuning (when is cleared).
0x1: Tuned clock is used to sample data (indicating that tuning was successful).
0x0: Fixed clock is used to sample data (indicating that tuning failed).
Writing 0x1 to this bit is meaningless and ignored if tuning is not yet complete. If the bit is written as 0x0, the tuning circuit is reset. However, resetting the tuning circuit requires time to complete the tuning sequence. The host driver should keep this bit set to 0x1 to perform re-tuning quickly when necessary.
Changes to this bit are not allowed while the host controller is receiving responses or a read data block. | +| 22 | EXE_TUNING | R/WAC | 0x0 | Execute Tuning
This bit is set to 0x1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of the tuning is reflected in the . The tuning procedure is aborted by writing 0x0.
0x1: Execute Tuning
0x0: Not tuned or Tuning completed | +| 21:20 | DRV_STRENGTH_SEL | R/W | 0x0 | Driver Strength Select.
Host Controller output driver in 1.8V signaling is selected by this field. With 3.3V signaling, this field is not effective. This field can be set depending on Driver Type A, C and D support bits in the Capabilities register.
This bit depends on the setting of .
- If = 0x0, this field is set by the host driver.
- If = 0x1, this field is automatically set by a value specified in one of the Preset Value registers.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D | +| 19 | SDH_V18_EN | R/W | 0x0 | 1.8V Signaling Enable
0x1: 1.8V Signaling enable
0x0: 3.3V Signaling enable | +| 18:16 | UHS_MODE_SEL | R/W | 0x0 | UHS Mode Select
This field is used to select one of UHS-I modes and effective when = 0x1.
If in the Host Control2 register is set to 0x1, host controller sets SDCLK Frequency select, Clock generator select in the clock control register, and driver strength select according to the Preset Value registers.
In this case, one of the preset value registers is selected by this field.
Host driver should reset before changing this field to avoid generating clock glitch
0x0: SDR12
0x1: SDR25
0x2: SDR50
0x3: SDR104
0x4: DDR50
For MMC mode, added two backdoor defined modes:
0x5: HS200 mode
0x6: HS400 mode
All other values are Reserved | +| 15:8 | RSVD | R | 0 | Reserved for future use | +| 7 | CMD_NOT_ISSUED | RC | 0x0 | Command Not Issued
This is due to auto_cmd12 Error | +| 6:5 | RSVD | R | 0 | Reserved for future use | +| 4 | AUTO_CMD_INDEX_ERR | R/W1C | 0x0 | Auto CMD12 or Auto CMD23 Error
This error occurs when the command index error occurs in response to a command
0: Disabled
1: Enabled | +| 3 | AUTO_CMD_END_BIT_ERR | R/W1C | 0x0 | Auto CMD12 or Auto CMD23 End Bit Error
This error occurs when detecting that the end bit of command response is 0.
0: Disabled
1: Enabled | +| 2 | AUTO_CMD_CRC_ERR | R/W1C | 0x0 | Auto CMD12 or Auto CMD23 CRC Error
This error occurs when detecting CRC error in the command response.
0: Disabled
1: Enabled | +| 1 | AUTO_CMD_TIMEOUT_ERR | R/W1C | 0x0 | Auto CMD12 or Auto CMD23 Timeout Error
This error occurs when no response is returned within 64 SDCLK cycles from the end bit of command.
0: Disabled
1: Enabled | +| 0 | AUTO_CMD12_NOT_EXE | R/W1C | 0x0 | Auto CMD12 Not Executed
This error occurs when host controller cannot issue Auto cmd12 to stop multiple block data transfer due to some errors.
0: Disabled
1: Enabled | #### SD_CAPABILITIES_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x40
BitsFieldTypeResetDescription
31:30CFG_SLOT_TYPER/W0x0Slot Type
This field indicates what type of slot the host controller is connected to.
0x0: Removable card slot
0x1: Embedded slot for one device
0x2: Shared bus slot
0x3: Reserved
29ASYNC_INT_SUPPORTR0x1Asynchronous Interrupt Support.
0x1: Asynchronous Interrupt Supported
0x0: Asynchronous Interrupt not supported
28SYS_BUS_64_SUPPORTR0x064-bit System Bus Support
This bit indicates whether the host controller is capable of 64-bit system bus.
0x1: 64-bit system bus supported
0x0: 64-bit system bus not supported
27RSVDR0Reserved for future use
26VLG_18_SUPPORTR0x1Voltage Support 1.8V
This bit indicates whether the host controller is capable of 1.8V.
0x1: 1.8V Supported
0x0: 1.8V not supported
25VLG_30_SUPPORTR0x0Voltage Support 3.0V
This bit indicates whether the host controller is capable of 3.0V.
0x1: 3.0V Supported
0x0: 3.0V not supported
24VLG_33_SUPPORTR0x1Voltage Support 3.3V
This bit indicates whether the host controller is capable of 3.3V.
0x1: 3.3V Supported
0x0: 3.3V not supported
23SUS_RES_SUPPORTR0x1Suspend Resume Support
This bit indicates whether the host controller is capable of suspend resume commands.
0x1: Suspend/Resume Supported
0x0: Suspend/Resume not supported.
22SDMA_SUPPORTR0x1SDMA Support
This bit indicates whether the host controller is capable of SDMA.
0x1: SDMA Supported
0x0: SDMA not supported.
21HI_SPEED_SUPPORTR0x1High Speed Support
This bit indicates whether the host controller is capable of high speed mode (25 - 50MHz).
0x1: High speed mode Supported
0x0: High speed mode not supported.
20ADMA1_SUPPORTR0x1ADMA1 Support
This bit indicates whether the host controller is capable of ADMA1.
0x1: ADMA1 Supported
0x0: ADMA1 not supported
19ADMA2_SUPPORTR0x1ADMA2 Support
This bit indicates whether the host controller is capable of ADMA2.
0x1: ADMA2 Supported
0x0: ADMA2 not supported
18EX_DATA_WIDTH_SUPPORTR0x18-bit Support
This bit indicates whether the host controller is capable of 8-bit bus operation.
0x1: 8-bit Supported
0x0: 8-bit not supported
17:16MAX_BLK_LENR0x0Maximum Block Length
The maximum block length in bytes.
0x0: 512 Bytes
15:8BASE_FREQR0x00Base Frequency
The base clock frequency for SDCLK
0xC8: 200 MHz (Actual frequency: 198.24 MHz)
0x0: Get frequency information via another method
7TIMEOUT_UNITR0x1Timeout Unit
The unit of base clock used to detect timeouts.
1: MHz
0: kHz
6RSVDR0Reserved for future use
5:0TIMEOUT_FREQR0x00Timeout Frequency
This value indicates the base clock frequency used to detect timeouts.
0x32: 50 MHz (Actual frequency: 49.56 MHz).
0x0: Get frequency information via another method
+**Offset: 0x40** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | CFG_SLOT_TYPE | R/W | 0x0 | Slot Type
This field indicates what type of slot the host controller is connected to.
0x0: Removable card slot
0x1: Embedded slot for one device
0x2: Shared bus slot
0x3: Reserved | +| 29 | ASYNC_INT_SUPPORT | R | 0x1 | Asynchronous Interrupt Support.
0x1: Asynchronous Interrupt Supported
0x0: Asynchronous Interrupt not supported | +| 28 | SYS_BUS_64_SUPPORT | R | 0x0 | 64-bit System Bus Support
This bit indicates whether the host controller is capable of 64-bit system bus.
0x1: 64-bit system bus supported
0x0: 64-bit system bus not supported | +| 27 | RSVD | R | 0 | Reserved for future use | +| 26 | VLG_18_SUPPORT | R | 0x1 | Voltage Support 1.8V
This bit indicates whether the host controller is capable of 1.8V.
0x1: 1.8V Supported
0x0: 1.8V not supported | +| 25 | VLG_30_SUPPORT | R | 0x0 | Voltage Support 3.0V
This bit indicates whether the host controller is capable of 3.0V.
0x1: 3.0V Supported
0x0: 3.0V not supported | +| 24 | VLG_33_SUPPORT | R | 0x1 | Voltage Support 3.3V
This bit indicates whether the host controller is capable of 3.3V.
0x1: 3.3V Supported
0x0: 3.3V not supported | +| 23 | SUS_RES_SUPPORT | R | 0x1 | Suspend Resume Support
This bit indicates whether the host controller is capable of suspend resume commands.
0x1: Suspend/Resume Supported
0x0: Suspend/Resume not supported. | +| 22 | SDMA_SUPPORT | R | 0x1 | SDMA Support
This bit indicates whether the host controller is capable of SDMA.
0x1: SDMA Supported
0x0: SDMA not supported. | +| 21 | HI_SPEED_SUPPORT | R | 0x1 | High Speed Support
This bit indicates whether the host controller is capable of high speed mode (25 - 50MHz).
0x1: High speed mode Supported
0x0: High speed mode not supported. | +| 20 | ADMA1_SUPPORT | R | 0x1 | ADMA1 Support
This bit indicates whether the host controller is capable of ADMA1.
0x1: ADMA1 Supported
0x0: ADMA1 not supported | +| 19 | ADMA2_SUPPORT | R | 0x1 | ADMA2 Support
This bit indicates whether the host controller is capable of ADMA2.
0x1: ADMA2 Supported
0x0: ADMA2 not supported | +| 18 | EX_DATA_WIDTH_SUPPORT | R | 0x1 | 8-bit Support
This bit indicates whether the host controller is capable of 8-bit bus operation.
0x1: 8-bit Supported
0x0: 8-bit not supported | +| 17:16 | MAX_BLK_LEN | R | 0x0 | Maximum Block Length
The maximum block length in bytes.
0x0: 512 Bytes | +| 15:8 | BASE_FREQ | R | 0x00 | Base Frequency
The base clock frequency for SDCLK
0xC8: 200 MHz (Actual frequency: 198.24 MHz)
0x0: Get frequency information via another method | +| 7 | TIMEOUT_UNIT | R | 0x1 | Timeout Unit
The unit of base clock used to detect timeouts.
1: MHz
0: kHz | +| 6 | RSVD | R | 0 | Reserved for future use | +| 5:0 | TIMEOUT_FREQ | R | 0x00 | Timeout Frequency
This value indicates the base clock frequency used to detect timeouts.
0x32: 50 MHz (Actual frequency: 49.56 MHz).
0x0: Get frequency information via another method | #### SD_CAPABILITIES_3 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x44
BitsFieldTypeResetDescription
31:24RSVDR0Reserved for future use
23:16<CLK_MULTIPLIER>R0x0Clock Multiplier
This field indicates clock multiplier value of programmable clock generator.
0x0: Host Controller does not support a programmable clock generator.
15:14RETUNE_MODESR0x0Re_tuning modes.
This field selects the re-tuning method and limits the maximum data length.
0x0: Mode1, Timer
0x1: Mode2, Timer and Re-Tuning Request
0x2: Mode3, Auto Re-Tuning (for transfer) Timer and Re-Tuning Request
0x3: Reserved
13SDR50_TUNER0x1Use Tuning for SDR50 mode.
0x1: SDR50 requires tuning
0x0: SDR50 does not require tuning
12RSVDR0Reserved for future use
11:8TMR_RETUNER0xfTimer count for Re-Tuning
This field indicates an initial value of the Re-Tuning Timer for Mode 1 to 3.
0xf: Get information from other sources
7RSVDR0Reserved for future use
6DRV_TYPE_DR0x1Driver Type D Support
0x1: Driver Type D is supported
0x0: Driver Type D is not supported
5DRV_TYPE_CR0x1Driver Type C Support.
0x1: Driver Type C is supported
0x0: Driver Type C is not supported
4DRV_TYPE_AR0x1Driver Type A Support
0x1: Driver Type A is supported
0x0: Driver Type A is not supported
3RSVDR0Reserved for future use
2DDR50_SUPPORTR0x1DDR50 Support
0x1: DDR50 is supported
0x0: DDR50 is not supported
1SDR104_SUPPORTR0x1SDR104 Support
0x1: SDR104 is supported
0x0: SDR104 is not supported
0SDR50_SUPPORTR0x1SDR50 Support
0x1: SDR50 is supported
0x0: SDR50 is not supported
+**Offset: 0x44** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | RSVD | R | 0 | Reserved for future use | +| 23:16 | | R | 0x0 | Clock Multiplier
This field indicates clock multiplier value of programmable clock generator.
0x0: Host Controller does not support a programmable clock generator. | +| 15:14 | RETUNE_MODES | R | 0x0 | Re_tuning modes.
This field selects the re-tuning method and limits the maximum data length.
0x0: Mode1, Timer
0x1: Mode2, Timer and Re-Tuning Request
0x2: Mode3, Auto Re-Tuning (for transfer) Timer and Re-Tuning Request
0x3: Reserved | +| 13 | SDR50_TUNE | R | 0x1 | Use Tuning for SDR50 mode.
0x1: SDR50 requires tuning
0x0: SDR50 does not require tuning | +| 12 | RSVD | R | 0 | Reserved for future use | +| 11:8 | TMR_RETUNE | R | 0xf | Timer count for Re-Tuning
This field indicates an initial value of the Re-Tuning Timer for Mode 1 to 3.
0xf: Get information from other sources | +| 7 | RSVD | R | 0 | Reserved for future use | +| 6 | DRV_TYPE_D | R | 0x1 | Driver Type D Support
0x1: Driver Type D is supported
0x0: Driver Type D is not supported | +| 5 | DRV_TYPE_C | R | 0x1 | Driver Type C Support.
0x1: Driver Type C is supported
0x0: Driver Type C is not supported | +| 4 | DRV_TYPE_A | R | 0x1 | Driver Type A Support
0x1: Driver Type A is supported
0x0: Driver Type A is not supported | +| 3 | RSVD | R | 0 | Reserved for future use | +| 2 | DDR50_SUPPORT | R | 0x1 | DDR50 Support
0x1: DDR50 is supported
0x0: DDR50 is not supported | +| 1 | SDR104_SUPPORT | R | 0x1 | SDR104 Support
0x1: SDR104 is supported
0x0: SDR104 is not supported | +| 0 | SDR50_SUPPORT | R | 0x1 | SDR50 Support
0x1: SDR50 is supported
0x0: SDR50 is not supported | #### SD_MAX_CURRENT_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x48
BitsFieldTypeResetDescription
31:24RSVDR0Reserved for future use
23:16MAX_CUR_18R0x0Maximum Current for 1.8V
0x0: Get information via another method
0x1: 4 mA
0x2: 8 mA
...
0xFF: 1020 mA
15:8MAX_CUR_30R0x0Maximum Current for 3.0V
0x0: Get information via another method
0x1: 4 mA
0x2: 8 mA
...
0xF: 1020 mA
7:0MAX_CUR_33R0x0Maximum Current for 3.3V
0x0: Get information via another method
0x1: 4 mA
0x2: 8 mA
...
0xF: 1020 mA
+**Offset: 0x48** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | RSVD | R | 0 | Reserved for future use | +| 23:16 | MAX_CUR_18 | R | 0x0 | Maximum Current for 1.8V
0x0: Get information via another method
0x1: 4 mA
0x2: 8 mA
...
0xFF: 1020 mA | +| 15:8 | MAX_CUR_30 | R | 0x0 | Maximum Current for 3.0V
0x0: Get information via another method
0x1: 4 mA
0x2: 8 mA
...
0xF: 1020 mA | +| 7:0 | MAX_CUR_33 | R | 0x0 | Maximum Current for 3.3V
0x0: Get information via another method
0x1: 4 mA
0x2: 8 mA
...
0xF: 1020 mA | #### SD_MAX_CURRENT_3 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4C
BitsFieldTypeResetDescription
31:0RSVDR0Reserved for future use
+**Offset: 0x4C** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RSVD | R | 0 | Reserved for future use | #### SD_FORCE_EVENT_AUTO_CMD12_ERROR REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x50
BitsFieldTypeResetDescription
31F_CRC_STATUS_ERRW
0x0Force Event for CRC Status Error
When 1 is written at this location, it sets the <CRC Status Error> field in the Error Interrupt Status Register.
30F_CPL_TIMEOUT_ERRW0x0Force Event for CPL Timeout Error
When 1 is written at this location, it sets the <Command Completion Signal Timeout Error> field in the Error Interrupt Status Register.
29F_AXI_RESP_ERRW0x0Force Event for AXI Response Bit Error
When 1 is written at this location, it sets the <AXI Bus Response Error> field in the Error Interrupt Status Register.
28F_SPI_ERRW0x0Force Event for SPI Error
When 1 is written at this location, it sets the <SPI Mode Error> field in the Error Interrupt Status Register.
27:26RSVDR0Reserved for future use
25F_ADMA_ERRW0x0Force Event for ADMA Error
When 1 is written at this location, it sets the <ADMA Error> field in the Error Interrupt Status Register.
24F_ACMD12_ERRW0x0Force Event for Auto Cmd12 Error
When 1 is written at this location, it sets the <Auto CMD12 Error> field in the Error Interrupt Status Register.
23F_CURRENT_ERRW0x0Force Event for Current Limit Error
When 1 is written at this location, it sets the <Current Limit Error> field in the Error Interrupt Status Register.
22F_DAT_END_BIT_ERRW0x0Force Event for Data End Bit Error
When 1 is written at this location, it sets the <ReadDataEnd Bit Error> field in the Error Interrupt Status Register.
21F_DAT_CRC_ERRW0x0Force Event for Data CRC Error
When 1 is written at this location, it sets the <Read Data CRC Error> field in the Error Interrupt Status Register.
20F_DAT_TO_ERRW0x0Force Event for Data Timeout Error
When 1 is written at this location, it sets the <Read Data CRC Error> field in the Error Interrupt Status Register.
19F_CMD_INDEX_ERRW0x0Force Event for Command Index Error
When 1 is written at this location, it sets the <Data Timeout Error> field in the Error Interrupt Status Register.
18F_CMD_END_BIT_ERRW0x0Force Event for Command End Bit Error
When 1 is written at this location, it sets the <Command Index Error> field in the Error Interrupt Status Register.
17F_CMD_CRC_ERRW0x0Force Event for Command CRC Error
When 1 is written at this location, it sets the <Command CRC Error> field in the Error Interrupt Status Register.
16F_CMD_TO_ERRW0x0Force Event for Command Timeout Error
When 1 is written at this location, it sets the <Command Timeout Error> field in the Error Interrupt Status Register.
15:8RSVDR0Reserved for future use
7F_ACMD12_ISSUE_ERRW0x0Force Event for Command not Issued by Auto Cmd12 Error
When 1 is written at this location, it sets the <Command Not Issued Due to auto_cmd12 Error> field in the Auto CMD12 Error Status Register.
6:5RSVDR0Reserved for future use
4F_ACMD_INDEX_ERRW0x0Force Event for Auto Cmd Index Error
When 1 is written at this location, it sets the <Auto CMD Error> field in the Auto CMD Error Status Register.
3F__ACMD_EBIT_ERRW0x0Force Event for Auto Cmd End Bit Error
When 1 is written at this location, it sets the <Auto CMD End Bit Error> field in the Auto CMD Error Status Register.
2F_ACMD_CRC_ERRW0x0Force Event for Auto Cmd CRC Error
When 1 is written at this location, it sets the <Auto CMD CRC Error> field in the Auto CMD Error Status Register.
1F_ACMD_TO_ERRW0x0Force Event for Auto Cmd Timeout Error
When 1 is written at this location, it sets the <Auto CMD Timeout Error> field in the Auto CMD Error Status Register.
0F_ACMD12_NEXE_ERRW0x0Force Event for Auto Cmd12 Not Executed Error
When 1 is written at this location, it sets the <Auto CMD12 Not Executed> field in the Auto CMD12 Error Status Register.
+**Offset: 0x50** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | F_CRC_STATUS_ERR | W
| 0x0 | Force Event for CRC Status Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 30 | F_CPL_TIMEOUT_ERR | W | 0x0 | Force Event for CPL Timeout Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 29 | F_AXI_RESP_ERR | W | 0x0 | Force Event for AXI Response Bit Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 28 | F_SPI_ERR | W | 0x0 | Force Event for SPI Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 27:26 | RSVD | R | 0 | Reserved for future use | +| 25 | F_ADMA_ERR | W | 0x0 | Force Event for ADMA Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 24 | F_ACMD12_ERR | W | 0x0 | Force Event for Auto Cmd12 Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 23 | F_CURRENT_ERR | W | 0x0 | Force Event for Current Limit Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 22 | F_DAT_END_BIT_ERR | W | 0x0 | Force Event for Data End Bit Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 21 | F_DAT_CRC_ERR | W | 0x0 | Force Event for Data CRC Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 20 | F_DAT_TO_ERR | W | 0x0 | Force Event for Data Timeout Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 19 | F_CMD_INDEX_ERR | W | 0x0 | Force Event for Command Index Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 18 | F_CMD_END_BIT_ERR | W | 0x0 | Force Event for Command End Bit Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 17 | F_CMD_CRC_ERR | W | 0x0 | Force Event for Command CRC Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 16 | F_CMD_TO_ERR | W | 0x0 | Force Event for Command Timeout Error
When 1 is written at this location, it sets the field in the Error Interrupt Status Register. | +| 15:8 | RSVD | R | 0 | Reserved for future use | +| 7 | F_ACMD12_ISSUE_ERR | W | 0x0 | Force Event for Command not Issued by Auto Cmd12 Error
When 1 is written at this location, it sets the field in the Auto CMD12 Error Status Register. | +| 6:5 | RSVD | R | 0 | Reserved for future use | +| 4 | F_ACMD_INDEX_ERR | W | 0x0 | Force Event for Auto Cmd Index Error
When 1 is written at this location, it sets the field in the Auto CMD Error Status Register. | +| 3 | F__ACMD_EBIT_ERR | W | 0x0 | Force Event for Auto Cmd End Bit Error
When 1 is written at this location, it sets the field in the Auto CMD Error Status Register. | +| 2 | F_ACMD_CRC_ERR | W | 0x0 | Force Event for Auto Cmd CRC Error
When 1 is written at this location, it sets the field in the Auto CMD Error Status Register. | +| 1 | F_ACMD_TO_ERR | W | 0x0 | Force Event for Auto Cmd Timeout Error
When 1 is written at this location, it sets the field in the Auto CMD Error Status Register. | +| 0 | F_ACMD12_NEXE_ERR | W | 0x0 | Force Event for Auto Cmd12 Not Executed Error
When 1 is written at this location, it sets the field in the Auto CMD12 Error Status Register. | #### SD_ADMA_ERROR_STATUS REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x54
BitsFieldTypeResetDescription
31:3RSVDR0Reserved for future use
2ADMA_LEN_ERRR/W0x0ADMA Length Mismatch Error
This error occurs in the following two cases:
- While Block Count Enable (in SD_TRANSFER_MODE_CMD Bit[1]) is set, the total data length is specified by the descriptor table, which is different from that specified by the block count and block Length.
- Total data length cannot be divided by block length
1:0ADMA_STATER/W0x0ADMA Error State
This field indicates the state of ADMA when error occurred during ADMA transfer.
This field never indicates 0x2 because ADMA never stops in this state.
+**Offset: 0x54** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | RSVD | R | 0 | Reserved for future use | +| 2 | ADMA_LEN_ERR | R/W | 0x0 | ADMA Length Mismatch Error
This error occurs in the following two cases:
- While Block Count Enable (in SD_TRANSFER_MODE_CMD Bit[1]) is set, the total data length is specified by the descriptor table, which is different from that specified by the block count and block Length.
- Total data length cannot be divided by block length | +| 1:0 | ADMA_STATE | R/W | 0x0 | ADMA Error State
This field indicates the state of ADMA when error occurred during ADMA transfer.
This field never indicates 0x2 because ADMA never stops in this state. | #### ADMA SYSTEM ADDRESS REGISTER 1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x58
BitsFieldTypeResetDescription
31:16ADMA_SYS_ADDRR/W0x0ADMA System Address
This register holds the byte address of the executing command in the Descriptor table.
- At the start of ADMA, this register should be programmed to point to the starting address of the Descriptor table.
- This register is incremented as the system fetches each descriptor line.
- In case of an ADMA Error Interrupt, this register will contain a valid Descriptor address based on the ADMA state at the time.
15:0ADMA_SYS_ADDRR/W0x0ADMA System Address
This register holds the byte address of the executing command in the Descriptor table.
- At the start of ADMA, this register should be programmed to point to the starting address of the Descriptor table.
- This register is incremented as the system fetches each descriptor line.
- In case of an ADMA Error Interrupt, this register will contain a valid Descriptor address based on the ADMA state at the time.
+**Offset: 0x58** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | ADMA_SYS_ADDR | R/W | 0x0 | ADMA System Address
This register holds the byte address of the executing command in the Descriptor table.
- At the start of ADMA, this register should be programmed to point to the starting address of the Descriptor table.
- This register is incremented as the system fetches each descriptor line.
- In case of an ADMA Error Interrupt, this register will contain a valid Descriptor address based on the ADMA state at the time. | +| 15:0 | ADMA_SYS_ADDR | R/W | 0x0 | ADMA System Address
This register holds the byte address of the executing command in the Descriptor table.
- At the start of ADMA, this register should be programmed to point to the starting address of the Descriptor table.
- This register is incremented as the system fetches each descriptor line.
- In case of an ADMA Error Interrupt, this register will contain a valid Descriptor address based on the ADMA state at the time. | #### SD_ADMA_SYS_ADDR_3 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x5C
BitsFieldTypeResetDescription
31:16ADMA_SYS_ADDRR/W0x0
ADMA System Address
This register holds the byte address of the executing command in the Descriptor table.
- At the start of ADMA, this register should be programmed to point to the starting address of the Descriptor table.
- This register is incremented as the system fetches each descriptor line.
- In case of an ADMA Error Interrupt, this register will contain a valid Descriptor address based on the ADMA state at the time.
15:0ADMA_SYS_ADDRR/W0x0ADMA System Address
This register holds the byte address of the executing command in the Descriptor table.
- At the start of ADMA, this register should be programmed to point to the starting address of the Descriptor table.
- This register is incremented as the system fetches each descriptor line.
- In case of an ADMA Error Interrupt, this register will contain a valid Descriptor address based on the ADMA state at the time.
+**Offset: 0x5C** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | ADMA_SYS_ADDR | R/W | 0x0
| ADMA System Address
This register holds the byte address of the executing command in the Descriptor table.
- At the start of ADMA, this register should be programmed to point to the starting address of the Descriptor table.
- This register is incremented as the system fetches each descriptor line.
- In case of an ADMA Error Interrupt, this register will contain a valid Descriptor address based on the ADMA state at the time. | +| 15:0 | ADMA_SYS_ADDR | R/W | 0x0 | ADMA System Address
This register holds the byte address of the executing command in the Descriptor table.
- At the start of ADMA, this register should be programmed to point to the starting address of the Descriptor table.
- This register is incremented as the system fetches each descriptor line.
- In case of an ADMA Error Interrupt, this register will contain a valid Descriptor address based on the ADMA state at the time. | #### PRESET_VALUE_FOR_INIT REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x60
BitsFieldTypeResetDescription
31:30DRV_STRENGTH_VALR0x0Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D
29:27RSVDR0Reserved for future use
26CLKGEN_SEL_VALR0x0Clock Generator Select Value.
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock
25:16SDCLK_FREQ_SEL_VALR0x004SDCLK Frequency Select Value
10-bit preset value to set <sdclk_freq_sel> in the Clock Control register.
15:14DRV_STRENGTH_VALR0x0Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D
13:11RSVDR0Reserved for future use
10CLKGEN_SEL_VALR0x0Clock Generator Select Value.
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock
9:0SDCLK_FREQ_SEL_VALR0x100SDCLK Frequency Select Value
10-bit preset value to set <sdclk_freq_sel> in the Clock Control register.
+**Offset: 0x60** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | DRV_STRENGTH_VAL | R | 0x0 | Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D | +| 29:27 | RSVD | R | 0 | Reserved for future use | +| 26 | CLKGEN_SEL_VAL | R | 0x0 | Clock Generator Select Value.
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock | +| 25:16 | SDCLK_FREQ_SEL_VAL | R | 0x004 | SDCLK Frequency Select Value
10-bit preset value to set in the Clock Control register. | +| 15:14 | DRV_STRENGTH_VAL | R | 0x0 | Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D | +| 13:11 | RSVD | R | 0 | Reserved for future use | +| 10 | CLKGEN_SEL_VAL | R | 0x0 | Clock Generator Select Value.
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock | +| 9:0 | SDCLK_FREQ_SEL_VAL | R | 0x100 | SDCLK Frequency Select Value
10-bit preset value to set in the Clock Control register. | #### PRESET_VALUE_FOR_HS REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x64
BitsFieldTypeResetDescription
31:30DRV_STRENGTH_VALR0x0Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D
29:27RSVDR0Reserved for future use
26CLKGEN_SEL_VALR0x0Clock Generator Select Value
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock
25:16SDCLK_FREQ_SEL_VALR0x004SDCLK Frequency Select Value
10-bit preset value to set <sdclk_freq_sel> in the Clock Control register.
15:14DRV_STRENGTH_VALR0x0Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D
13:11RSVDR0Reserved for future use
10CLKGEN_SEL_VALR0x0Clock Generator Select Value
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock
9:0SDCLK_FREQ_SEL_VALR0x002SDCLK Frequency Select Value
10-bit preset value to set <sdclk_freq_sel> in the Clock Control register.
+**Offset: 0x64** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | DRV_STRENGTH_VAL | R | 0x0 | Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D | +| 29:27 | RSVD | R | 0 | Reserved for future use | +| 26 | CLKGEN_SEL_VAL | R | 0x0 | Clock Generator Select Value
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock | +| 25:16 | SDCLK_FREQ_SEL_VAL | R | 0x004 | SDCLK Frequency Select Value
10-bit preset value to set in the Clock Control register. | +| 15:14 | DRV_STRENGTH_VAL | R | 0x0 | Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D | +| 13:11 | RSVD | R | 0 | Reserved for future use | +| 10 | CLKGEN_SEL_VAL | R | 0x0 | Clock Generator Select Value
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock | +| 9:0 | SDCLK_FREQ_SEL_VAL | R | 0x002 | SDCLK Frequency Select Value
10-bit preset value to set in the Clock Control register. | #### PRESET_VALUE_FOR_SDR25 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x68
BitsFieldTypeResetDescription
31:30DRV_STRENGTH_VALR0x0Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D
29:27RSVDR0Reserved for future use
26CLKGEN_SEL_VALR0x0Clock Generator Select Value
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock
25:16SDCLK_FREQ_SEL_VALR0x004SDCLK Frequency Select Value 10-bit preset value to set <sdclk_freq_sel> in the Clock Control register.
15:14DRV_STRENGTH_VALR0x0Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D
13:11RSVDR0Reserved for future use
10CLKGEN_SEL_VALR0x0Clock Generator Select Value
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock
9:0SDCLK_FREQ_SEL_VALR0x002SDCLK Frequency Select Value
10-bit preset value to set <sdclk_freq_sel> in the Clock Control register.
+**Offset: 0x68** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | DRV_STRENGTH_VAL | R | 0x0 | Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D | +| 29:27 | RSVD | R | 0 | Reserved for future use | +| 26 | CLKGEN_SEL_VAL | R | 0x0 | Clock Generator Select Value
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock | +| 25:16 | SDCLK_FREQ_SEL_VAL | R | 0x004 | SDCLK Frequency Select Value 10-bit preset value to set in the Clock Control register. | +| 15:14 | DRV_STRENGTH_VAL | R | 0x0 | Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D | +| 13:11 | RSVD | R | 0 | Reserved for future use | +| 10 | CLKGEN_SEL_VAL | R | 0x0 | Clock Generator Select Value
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock | +| 9:0 | SDCLK_FREQ_SEL_VAL | R | 0x002 | SDCLK Frequency Select Value
10-bit preset value to set in the Clock Control register. | #### PRESET_VALUE_FOR_SDR104 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x6C
BitsFieldTypeResetDescription
31:30DRV_STRENGTH_VALR0x0Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D
29:27RSVDR0Reserved for future use
26CLKGEN_SEL_VALR0x0Clock Generator Select Value
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock
25:16SDCLK_FREQ_SEL_VALR0x004SDCLK Frequency Select Value
10-bit preset value to set <sdclk_freq_sel> in the Clock Control register.
15:14DRV_STRENGTH_VALR0x0Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D
13:11RSVDR0Reserved for future use
10CLKGEN_SEL_VALR0x0Clock Generator Select Value
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock
9:0SDCLK_FREQ_SEL_VALR0x002SDCLK Frequency Select Value
10-bit preset value to set <sdclk_freq_sel> in the Clock Control register.
+**Offset: 0x6C** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | DRV_STRENGTH_VAL | R | 0x0 | Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D | +| 29:27 | RSVD | R | 0 | Reserved for future use | +| 26 | CLKGEN_SEL_VAL | R | 0x0 | Clock Generator Select Value
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock | +| 25:16 | SDCLK_FREQ_SEL_VAL | R | 0x004 | SDCLK Frequency Select Value
10-bit preset value to set in the Clock Control register. | +| 15:14 | DRV_STRENGTH_VAL | R | 0x0 | Driver Strength Select Value
Driver strength is supported by 1.8V signaling bus speed modes. The field is not relevant for 3.3V signaling.
0x0: Driver Type B
0x1: Driver Type A
0x2: Driver Type C
0x3: Driver Type D | +| 13:11 | RSVD | R | 0 | Reserved for future use | +| 10 | CLKGEN_SEL_VAL | R | 0x0 | Clock Generator Select Value
This bit is effective when Host Controller supports programmable clock generator.
0x1: Programmable clock generator
0x0: Divided clock | +| 9:0 | SDCLK_FREQ_SEL_VAL | R | 0x002 | SDCLK Frequency Select Value
10-bit preset value to set in the Clock Control register. | #### SHARED_BUS_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xE0
BitsFieldTypeResetDescription
31RSVDR0Reserved for future use
30:24BEND_PWR_CTRLR/W0x0Back-End Power Control
Each bit of this field controls back-end power supply for an embedded device.
The maximum number of devices that can be controlled is 7, as specified by <num_clk_pins>.
Each bit is mapped to a device specific, where
- bit[24] corresponds to Device 1
- bit[30] corresponds to Device 7
Note: Host interface voltage is not controlled by this field.
The function of each bit is:
0x0: Back-end power is off
0x1: Back-end power is supplied
23RSVDR0Reserved for future use
22:20INT_PIN_SELR/W0x0Interrupt Pin Select
Interrupt pin inputs are enabled by this field. Enabling an unsupported interrupt pin has no effect.
0x0: Interrupt is detected by interrupt cycle.
19RSVDR0Reserved for future use
18:16CLK_PIN_SELR/W0x0Clock Pin Select
One of the clock pin outputs is selected by this field.
0x0: Clock Pins are disabled
15RSVDR0Reserved for future use
14:8BUS_WIDTH_PRESETR0x0Bus Width Preset
This field defines the bus width preset for devices on a shared bus.
0x0: Bus width defined by <data_transfer_width>
0x1: 8-bit mode
7:6RSVDR0Reserved for future use
5:4NUM_INT_PINSR0x0Number of interrupt input pins
This field defines the number of interrupt input pins supported on shared bus system.
0x0: Interrupt input pin is not supported
3RSVDR0Reserved for future use
2:0NUM_CLK_PINSR0x0Number of clock pins
This field indicates whether clock pins are supported for selecting one of the devices on a shared bus.
0x0: Shared bus is not supported
+**Offset: 0xE0** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | RSVD | R | 0 | Reserved for future use | +| 30:24 | BEND_PWR_CTRL | R/W | 0x0 | Back-End Power Control
Each bit of this field controls back-end power supply for an embedded device.
The maximum number of devices that can be controlled is 7, as specified by .
Each bit is mapped to a device specific, where
- bit[24] corresponds to Device 1
- bit[30] corresponds to Device 7
Note: Host interface voltage is not controlled by this field.
The function of each bit is:
0x0: Back-end power is off
0x1: Back-end power is supplied | +| 23 | RSVD | R | 0 | Reserved for future use | +| 22:20 | INT_PIN_SEL | R/W | 0x0 | Interrupt Pin Select
Interrupt pin inputs are enabled by this field. Enabling an unsupported interrupt pin has no effect.
0x0: Interrupt is detected by interrupt cycle. | +| 19 | RSVD | R | 0 | Reserved for future use | +| 18:16 | CLK_PIN_SEL | R/W | 0x0 | Clock Pin Select
One of the clock pin outputs is selected by this field.
0x0: Clock Pins are disabled | +| 15 | RSVD | R | 0 | Reserved for future use | +| 14:8 | BUS_WIDTH_PRESET | R | 0x0 | Bus Width Preset
This field defines the bus width preset for devices on a shared bus.
0x0: Bus width defined by
0x1: 8-bit mode | +| 7:6 | RSVD | R | 0 | Reserved for future use | +| 5:4 | NUM_INT_PINS | R | 0x0 | Number of interrupt input pins
This field defines the number of interrupt input pins supported on shared bus system.
0x0: Interrupt input pin is not supported | +| 3 | RSVD | R | 0 | Reserved for future use | +| 2:0 | NUM_CLK_PINS | R | 0x0 | Number of clock pins
This field indicates whether clock pins are supported for selecting one of the devices on a shared bus.
0x0: Shared bus is not supported | #### SD_SLOT_INT_STATUS REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xFC
BitsFieldTypeResetDescription
31:24VENDOR_VERR0x0Version Number
23:16SD_VERR0x2SD Host Specification Number
0x0: Supports version 1.0
0x1: Supports version 2.0
0x2: Supports version 3.0
All other values are reserved.
15:2RSVDR0Reserved for future use
1SLOT_INT1R0x0Interrupt Line for Slot 1
0SLOT_INT0R0x0Interrupt Line for Slot 0
+**Offset: 0xFC** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | VENDOR_VER | R | 0x0 | Version Number | +| 23:16 | SD_VER | R | 0x2 | SD Host Specification Number
0x0: Supports version 1.0
0x1: Supports version 2.0
0x2: Supports version 3.0
All other values are reserved. | +| 15:2 | RSVD | R | 0 | Reserved for future use | +| 1 | SLOT_INT1 | R | 0x0 | Interrupt Line for Slot 1 | +| 0 | SLOT_INT0 | R | 0x0 | Interrupt Line for Slot 0 | #### SDHC_VID_PID REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x100
BitsFieldTypeResetDescription
31:28VERSION_IDR0x10x1: The IP version
27:20PROJECT_IDR0x10x1: The project version
19:0VENDOR_IDR0xa1312Stands for vendor name
+**Offset: 0x100** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | VERSION_ID | R | 0x1 | 0x1: The IP version | +| 27:20 | PROJECT_ID | R | 0x1 | 0x1: The project version | +| 19:0 | VENDOR_ID | R | 0xa1312 | Stands for vendor name | #### SDHC_OP_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x104
BitsFieldTypeResetDescription
31:16RSVDR0Reserved for future use
15WR_OSTDGR/W0x0This field controls whether outstanding write requests are allowed on AXI.
0x0: Allow outstanding requests on AXI.
0x1: DO not allow outstanding requests on AXI.
14RD_OSTDGR/W0x0This field controls whether outstanding read requests are allowed on AXI.
0x0: Allow outstanding requests on AXI.
0x1: DO not allow outstanding requests on AXI.
13:8RSVDR0Reserved for future use
7WR_ENDIANR/W0x1This field determines the endian format for the data being written to the card.
1: Little Endian
0: Big Endian
6RD_ENDIANR/W0x1This field determines the endian format for the data being read from the card.
1: Little Endian
0: Big Endian
5AXI_NON_POST_WRR/W0x0AXI Non-post Write
1: All AXI master write requests are non-post write
0: Only the last request is issued as non-post write
4PRIORITYR/W0x0This field controls the priority level for AXI requests, acting as the most significant bit of the ID when requests are made
0x0: low priority
0x1: high priority
Note: This bit should only be modified before or after the completion of a data command, not during the transaction.
3:2DMA_SIZER/W0x3FIFO Threshold
This field sets the FIFO threshold for the internal FSM to generate a DMA request to the AXI master.
0x0: 64 bytes
0x1: 128 bytes
0x2: 192 bytes
0x3: 256 bytes
1:0BRST_SIZER/W0x2DMA Burst Size on the AXI Fabric
0x0: 32 bytes burst
0x1: 64 bytes burst
0x2: 128 bytes
0x3: 256 bytes
+**Offset: 0x104** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RSVD | R | 0 | Reserved for future use | +| 15 | WR_OSTDG | R/W | 0x0 | This field controls whether outstanding write requests are allowed on AXI.
0x0: Allow outstanding requests on AXI.
0x1: DO not allow outstanding requests on AXI. | +| 14 | RD_OSTDG | R/W | 0x0 | This field controls whether outstanding read requests are allowed on AXI.
0x0: Allow outstanding requests on AXI.
0x1: DO not allow outstanding requests on AXI. | +| 13:8 | RSVD | R | 0 | Reserved for future use | +| 7 | WR_ENDIAN | R/W | 0x1 | This field determines the endian format for the data being written to the card.
1: Little Endian
0: Big Endian | +| 6 | RD_ENDIAN | R/W | 0x1 | This field determines the endian format for the data being read from the card.
1: Little Endian
0: Big Endian | +| 5 | AXI_NON_POST_WR | R/W | 0x0 | AXI Non-post Write
1: All AXI master write requests are non-post write
0: Only the last request is issued as non-post write | +| 4 | PRIORITY | R/W | 0x0 | This field controls the priority level for AXI requests, acting as the most significant bit of the ID when requests are made
0x0: low priority
0x1: high priority
Note: This bit should only be modified before or after the completion of a data command, not during the transaction. | +| 3:2 | DMA_SIZE | R/W | 0x3 | FIFO Threshold
This field sets the FIFO threshold for the internal FSM to generate a DMA request to the AXI master.
0x0: 64 bytes
0x1: 128 bytes
0x2: 192 bytes
0x3: 256 bytes | +| 1:0 | BRST_SIZE | R/W | 0x2 | DMA Burst Size on the AXI Fabric
0x0: 32 bytes burst
0x1: 64 bytes burst
0x2: 128 bytes
0x3: 256 bytes | #### SDHC_OP_EXT_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x108
BitsFieldTypeResetDescription
31CEN_DEASSERTR/W0x0Backdoor control bit to deassert the DPSRAM CENA/CENB port. Setting this bit allows DPSRAM CLKPA/CLKPB to receive additional clock cycles.
0: CEN deasserted disable
1: CEN deasserted enable
30:28EMAR/W0x7DPSRAM extra time for memory read and write
000: Fastest
111: Slowest
27:26EMAWR/W0x1DPSRAM delay for write operation by extending the internal write pulse.
2'b00: Fastest
2'b11: Slowest
25EMASR/W0x0This field controls the extension of the DPSRAM pulse width of the sense-amplifier enable signal.
The default setting is low but when driving high, the pulse is extended.
24RET1NR/W0x1Retention mode 1 enable, active low.
23:20RSVDR0Reserved for future use
19:16PRE_GATE_CLK_CNTR/W0x9This field controls the amount of clock cycles that are provided before clock gating is enabled on the sd_clk io pad.
15AUTOCMD12_XFER_ENABLER/W0x0This bit is backdoor enable bit when software executes CMD25 with AutoCMD12.There are two conditions that can trigger a transfer interrupt:
- Write operation busy bit check
- Normal data transfer AUTOCMD12 finished
Normally, a transfer interrupt is triggered only when the write operation busy bit check is completed. However, enabling this bit allows an additional interrupt trigger condition when the normal data transfer of AutoCMD12 is finished.
By default, software can keep this bit set to 0.
14PDLVMCR/W0x0This field controls some power down function for the internal memory.
13PDFVSSMR/W0x0This field controls some power down function for the internal memory.
12FORCE_CLK_ONR/W0x0This bit forces the SD I/O pad clock to remain on.
Setting this field to 0x1 overrides the SD Clock I/O pad clock gate, ensuring the clock is continuously active. It is typically used together with the <OVRRD_CLK_OEN> field
Bit[12:11] Setting:
2'bx0: setting is ignored (not used)
2'b01: Clocks are forced off
2'b11: Clocks are forced on
11OVRRD_CLK_OENR/W0x0Override Pad Clock Output Enable
Setting this field to 0x1 overrides the SD Pad clock output enable. It is typically used together with the <FORCE_CLK_ON> field.
10CLK_OE_USE_POSR/W0x1This field controls the SD/eMMC bus CLK PAD output enable signal use clock rising edge output or use clock falling edge output
0: Use internal clock falling edge output (to eliminate clock signal Tri-state issue)
1: Use internal clock rising edge output
9CLK_GATE_ONR/W0x0Clock Gate On
0: Enable dynmical clock gate
1: Enable clock free running
This field affects all clock gates in the SD design if the <Clock Gate Ctl> field is set to 1.
8CLK_GATE_CTLR/W0x0Clock Gate Control
0: Disable software clock gating override
1: Enable software clock gating override
7USE_DAT3R/W0x0This field allows the card detect functionality to be detected using the DAT[3] pin.
This field controls whether the DAT[3] pin is used for card detection.
0x0: Use dedicated pin for card detection
0x1: Use DAT[3] for card detection
6PDWNR/W0x0Power Down
This bit controls the Power Down port on the internal DPFIFO.
5FIFO_CSR/W0x0FIFO CS
This field should be written to 0x1 before any toggling of the PDWN bit.
4FIFO_CLKR/W0x0FIFO Clock
This field should be set to 0x1 before any toggling of the PDWN bit.
3:2WTCR/W0x0WTC
This field is used for FIFO speed setting.
1:0RTCR/W0x0RTC
This field is used for FIFO speed setting.
+**Offset: 0x108** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | CEN_DEASSERT | R/W | 0x0 | Backdoor control bit to deassert the DPSRAM CENA/CENB port. Setting this bit allows DPSRAM CLKPA/CLKPB to receive additional clock cycles.
0: CEN deasserted disable
1: CEN deasserted enable | +| 30:28 | EMA | R/W | 0x7 | DPSRAM extra time for memory read and write
000: Fastest
111: Slowest | +| 27:26 | EMAW | R/W | 0x1 | DPSRAM delay for write operation by extending the internal write pulse.
2'b00: Fastest
2'b11: Slowest | +| 25 | EMAS | R/W | 0x0 | This field controls the extension of the DPSRAM pulse width of the sense-amplifier enable signal.
The default setting is low but when driving high, the pulse is extended. | +| 24 | RET1N | R/W | 0x1 | Retention mode 1 enable, active low. | +| 23:20 | RSVD | R | 0 | Reserved for future use | +| 19:16 | PRE_GATE_CLK_CNT | R/W | 0x9 | This field controls the amount of clock cycles that are provided before clock gating is enabled on the sd_clk io pad. | +| 15 | AUTOCMD12_XFER_ENABLE | R/W | 0x0 | This bit is backdoor enable bit when software executes CMD25 with AutoCMD12.There are two conditions that can trigger a transfer interrupt:
- Write operation busy bit check
- Normal data transfer AUTOCMD12 finished
Normally, a transfer interrupt is triggered only when the write operation busy bit check is completed. However, enabling this bit allows an additional interrupt trigger condition when the normal data transfer of AutoCMD12 is finished.
By default, software can keep this bit set to 0. | +| 14 | PDLVMC | R/W | 0x0 | This field controls some power down function for the internal memory. | +| 13 | PDFVSSM | R/W | 0x0 | This field controls some power down function for the internal memory. | +| 12 | FORCE_CLK_ON | R/W | 0x0 | This bit forces the SD I/O pad clock to remain on.
Setting this field to 0x1 overrides the SD Clock I/O pad clock gate, ensuring the clock is continuously active. It is typically used together with the field
Bit[12:11] Setting:
2'bx0: setting is ignored (not used)
2'b01: Clocks are forced off
2'b11: Clocks are forced on | +| 11 | OVRRD_CLK_OEN | R/W | 0x0 | Override Pad Clock Output Enable
Setting this field to 0x1 overrides the SD Pad clock output enable. It is typically used together with the field. | +| 10 | CLK_OE_USE_POS | R/W | 0x1 | This field controls the SD/eMMC bus CLK PAD output enable signal use clock rising edge output or use clock falling edge output
0: Use internal clock falling edge output (to eliminate clock signal Tri-state issue)
1: Use internal clock rising edge output | +| 9 | CLK_GATE_ON | R/W | 0x0 | Clock Gate On
0: Enable dynmical clock gate
1: Enable clock free running
This field affects all clock gates in the SD design if the field is set to 1. | +| 8 | CLK_GATE_CTL | R/W | 0x0 | Clock Gate Control
0: Disable software clock gating override
1: Enable software clock gating override | +| 7 | USE_DAT3 | R/W | 0x0 | This field allows the card detect functionality to be detected using the DAT[3] pin.
This field controls whether the DAT[3] pin is used for card detection.
0x0: Use dedicated pin for card detection
0x1: Use DAT[3] for card detection | +| 6 | PDWN | R/W | 0x0 | Power Down
This bit controls the Power Down port on the internal DPFIFO. | +| 5 | FIFO_CS | R/W | 0x0 | FIFO CS
This field should be written to 0x1 before any toggling of the PDWN bit. | +| 4 | FIFO_CLK | R/W | 0x0 | FIFO Clock
This field should be set to 0x1 before any toggling of the PDWN bit. | +| 3:2 | WTC | R/W | 0x0 | WTC
This field is used for FIFO speed setting. | +| 1:0 | RTC | R/W | 0x0 | RTC
This field is used for FIFO speed setting. | #### SDHC_LEGACY_CTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x10C
BitsFieldTypeResetDescription
31:24GEN_PAD_CLK_CNTR/W0x4aPad Clock Count
This field should be used with <gen_pad_clk_on>
This field configures the number of clock cycles generated on the IO pad.
The default value of 0x4A generates 75 clock cycles.
23:14RSVDR0Reserved for future use
13:9SPI_ERR_TOKENR/W0x0SPI Error Token
This is the SPI Error token received in command response when SPI mode is enabled.
8SPI_ENR/W0x0Enable SPI Mode
This field indicates whether SPI mode is enabled. When enabled, the host controller drives the signals according to the SPI protocol.
1 = SPI mode enabled
0 = SPI mode disabled
7RSVDR0Reserved for future use
6GEN_PAD_CLK_ONR/WAC0x0Generate Pad Clock
This bit works together with the <gen_pad_clk_cnt> field.
Setting this bit to 0x1 will generate the programmed number of clock cycles on the IO pad.
5SQU_FULL_CHKR/W0x0SQU Full Check
This bit should be set to 0x1 only when using a specific piece of memory in the SQU in FIFO mode and performing a "read" transaction on the SD device.
4SQU_EMPTY_CHKR/W0x0SQU Empty Check
This bit should be set to 0x1 only when using a specific piece of memory in the SQU in FIFO mode and performing a "write" transaction on the SD device.
3BOOT_ACKR/W0x0Boot Acknowledgment
If the boot nowledgment mode is enabled in the MMC device, then this field should be written to 0x1 before issuing the alternate boot CMD0.
2INAND_SELR/W0x1When the driver programs the highest byte of Rx0c, the host DAT/CMD line related registers will be reset.
0x1: Enable soft reset when trigger command.
0x0: Disable soft reset when trigger command.
1ASYNC_IO_ENR/W0x0Asynchronous Read Interface Enable
This bit enables the asynchronous latching of input data.
0x1: Async interface is enabled. The clock used to latch the input data is asynchronous with the internal logic clock.
0x0: Async interface is disabled.
0PIO_RDFCR/W0x1PIO mode read operation FIFO check.
0x0: The system checks if all FIFO data has been read by the CPU. If not, the bus clock will stop, and the state will wait until the last block of FIFO data has been read by the CPU. Once the data is done being read, the next block will begin transferring.
0x1 = The system does not check if the FIFO data has been read by the CPU. It is recommended setting this bit to 1 before use PIO mode. This is especially important in high-speed modes like HS200/SDR104, where the software must set this bit to 1 to ensure proper operation.
+**Offset: 0x10C** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | GEN_PAD_CLK_CNT | R/W | 0x4a | Pad Clock Count
This field should be used with
This field configures the number of clock cycles generated on the IO pad.
The default value of 0x4A generates 75 clock cycles. | +| 23:14 | RSVD | R | 0 | Reserved for future use
| +| 13:9 | SPI_ERR_TOKEN | R/W | 0x0 | SPI Error Token
This is the SPI Error token received in command response when SPI mode is enabled. | +| 8 | SPI_EN | R/W | 0x0 | Enable SPI Mode
This field indicates whether SPI mode is enabled. When enabled, the host controller drives the signals according to the SPI protocol.
1 = SPI mode enabled
0 = SPI mode disabled | +| 7 | RSVD | R | 0 | Reserved for future use | +| 6 | GEN_PAD_CLK_ON | R/WAC | 0x0 | Generate Pad Clock
This bit works together with the field.
Setting this bit to 0x1 will generate the programmed number of clock cycles on the IO pad. | +| 5 | SQU_FULL_CHK | R/W | 0x0 | SQU Full Check
This bit should be set to 0x1 only when using a specific piece of memory in the SQU in FIFO mode and performing a "read" transaction on the SD device. | +| 4 | SQU_EMPTY_CHK | R/W | 0x0 | SQU Empty Check
This bit should be set to 0x1 only when using a specific piece of memory in the SQU in FIFO mode and performing a "write" transaction on the SD device. | +| 3 | BOOT_ACK | R/W | 0x0 | Boot Acknowledgment
If the boot nowledgment mode is enabled in the MMC device, then this field should be written to 0x1 before issuing the alternate boot CMD0. | +| 2 | INAND_SEL | R/W | 0x1 | When the driver programs the highest byte of Rx0c, the host DAT/CMD line related registers will be reset.
0x1: Enable soft reset when trigger command.
0x0: Disable soft reset when trigger command. | +| 1 | ASYNC_IO_EN | R/W | 0x0 | Asynchronous Read Interface Enable
This bit enables the asynchronous latching of input data.
0x1: Async interface is enabled. The clock used to latch the input data is asynchronous with the internal logic clock.
0x0: Async interface is disabled. | +| 0 | PIO_RDFC | R/W | 0x1 | PIO mode read operation FIFO check.
0x0: The system checks if all FIFO data has been read by the CPU. If not, the bus clock will stop, and the state will wait until the last block of FIFO data has been read by the CPU. Once the data is done being read, the next block will begin transferring.
0x1 = The system does not check if the FIFO data has been read by the CPU. It is recommended setting this bit to 1 before use PIO mode. This is especially important in high-speed modes like HS200/SDR104, where the software must set this bit to 1 to ensure proper operation. | #### SDHC_LEGACY_CEATA_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x110
BitsFieldTypeResetDescription
31:30RSVDR0Reserved for future use
29:16CPL_TIMEOUTR/W0x3FFFCommand Completion Signal Timeout Value
15:3RSVDR0Reserved for future use
2CHK_CPLR/W0x0Check Command Completion Signal
When this field is set to 0x1 and the <CE-ATA Card> field is set to 1, indication is sent to the host controller to check for command completion signal from the CE-ATA card.
1SND_CPLR/W0x0Send Command Completion Disable Signal
When this field is set to 1 and the <CE-ATA Card> field is set to 1, indication is sent to the host controller to send the command completion disable signal to the CE-ATA card.
0CEATA_CARDR/W0x0CE-ATA Card
1: CE-ATA Card mode
0: Non CE-ATA card mode
+**Offset: 0x110** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | RSVD | R | 0 | Reserved for future use | +| 29:16 | CPL_TIMEOUT | R/W | 0x3FFF | Command Completion Signal Timeout Value
| +| 15:3 | RSVD | R | 0 | Reserved for future use | +| 2 | CHK_CPL | R/W | 0x0 | Check Command Completion Signal
When this field is set to 0x1 and the field is set to 1, indication is sent to the host controller to check for command completion signal from the CE-ATA card. | +| 1 | SND_CPL | R/W | 0x0 | Send Command Completion Disable Signal
When this field is set to 1 and the field is set to 1, indication is sent to the host controller to send the command completion disable signal to the CE-ATA card. | +| 0 | CEATA_CARD | R/W | 0x0 | CE-ATA Card
1: CE-ATA Card mode
0: Non CE-ATA card mode | #### SDHC_MMC_CTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x114
BitsFieldTypeResetDescription
31:24DAT_LEVELR0xFFMMC1_DAT[7:0] Line Signal Level
This status is used to check the MMC_DAT[7:0] line level. It is useful for error recovery and debugging.
This helps in detecting issues, especially the busy signal level from MMC_DAT[0].
23:13RSVDR0Reserved for future use
12MMC_CARDR/W0x0MMC Card
1: MMC Card mode
0: SD Card mode
11MMC_RESETNR/W0x1MMC Resetn
This bit controls the value of the pin MMC_RESETN going to the eMMC device.
10MMC_HS200R/W0x0This bit is set when host read DEVICE_TYPE[196] field of Extended CSD register in MMC card, and the card support HS200 mode. It should be set before the host clock changes to 200Mhz.
1: MMC HS200 mode enable.
0: MMC HS200 mode disable
9MMC_HS400R/W0x0This bit is set when the host reads the DEVICE_TYPE[196] field of the Extended CSD register in the MMC card, and the card supports HS400 mode. It should be set before the host clock changes to 200 MHz, following the eMMC 5.0 specification.
1: MMC HS400 mode enable.
0: MMC HS400 mode disable
8ENHANCE_STROBE_ENR/W0x0Enhanced Strobe Enable
This bit controls whether the host/PHY will use the delayed strobe signal to sample the CMD response. This feature is part of the eMMC 5.1 specification to enhance HS400 mode. Software (SW) should check the device-related EXT to decide whether the host/PHY should support this feature.
7RSVDR0Reserved for future use
6CPL_COMPLETER/W1C0x0This bit is set to 1 when a command completion signal is detected and the <cpl_complete Enable> field has been set to 1.
The field is cleared by writing 0x1. A write of 0x0 has no effect.
5CPL_COMPLETE_ENR/W0x0This bit controls whether the CPL_COMPLETE bit gets set when a command completion signal is detected.
When set to 1, the CPL_COMPLETE bit will be set to 1 when a command completion signal is detected.
4CPL_COMPLETE_INT_ENR/W0x0cpl_complete Interrupt Enable
1: An interrupt will be generated when the <cpl_complete> field is set
3RSVDR0Reserved for future use
2MISC_INTR/W1C0x0Miscellaneous Interrupt
This status bit is set to 1 when the programmed number of clocks in the <gen_pad_clk_cnt> field is completed and the <misc_int_en> field has been set to 0x1.
This field is cleared by writing 0x1. A write of 0x0 has no effect.
1MISC_INT_ENR/W0x0Miscellaneous Interrupt Status Enable
When this bit is set to 0x1 will enable the misc_int bit to be set to 0x1 when the programmed number of clocks have been generated on the Pad.
0MISC_INT_INT_ENR/W0x0misc_int Interrupt Enable
0x1: An interrupt will be generated when the <misc_int> field is set to 0x1.
+**Offset: 0x114** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | DAT_LEVEL | R | 0xFF | MMC1_DAT[7:0] Line Signal Level
This status is used to check the MMC_DAT[7:0] line level. It is useful for error recovery and debugging.
This helps in detecting issues, especially the busy signal level from MMC_DAT[0]. | +| 23:13 | RSVD | R | 0 | Reserved for future use | +| 12 | MMC_CARD | R/W | 0x0 | MMC Card
1: MMC Card mode
0: SD Card mode | +| 11 | MMC_RESETN | R/W | 0x1 | MMC Resetn
This bit controls the value of the pin MMC_RESETN going to the eMMC device. | +| 10 | MMC_HS200 | R/W | 0x0 | This bit is set when host read DEVICE_TYPE[196] field of Extended CSD register in MMC card, and the card support HS200 mode. It should be set before the host clock changes to 200Mhz.
1: MMC HS200 mode enable.
0: MMC HS200 mode disable | +| 9 | MMC_HS400 | R/W | 0x0 | This bit is set when the host reads the DEVICE_TYPE[196] field of the Extended CSD register in the MMC card, and the card supports HS400 mode. It should be set before the host clock changes to 200 MHz, following the eMMC 5.0 specification.
1: MMC HS400 mode enable.
0: MMC HS400 mode disable | +| 8 | ENHANCE_STROBE_EN | R/W | 0x0 | Enhanced Strobe Enable
This bit controls whether the host/PHY will use the delayed strobe signal to sample the CMD response. This feature is part of the eMMC 5.1 specification to enhance HS400 mode. Software (SW) should check the device-related EXT to decide whether the host/PHY should support this feature. | +| 7 | RSVD | R | 0 | Reserved for future use | +| 6 | CPL_COMPLETE | R/W1C | 0x0 | This bit is set to 1 when a command completion signal is detected and the field has been set to 1.
The field is cleared by writing 0x1. A write of 0x0 has no effect. | +| 5 | CPL_COMPLETE_EN | R/W | 0x0 | This bit controls whether the CPL_COMPLETE bit gets set when a command completion signal is detected.
When set to 1, the CPL_COMPLETE bit will be set to 1 when a command completion signal is detected. | +| 4 | CPL_COMPLETE_INT_EN | R/W | 0x0 | cpl_complete Interrupt Enable
1: An interrupt will be generated when the field is set | +| 3 | RSVD | R | 0 | Reserved for future use | +| 2 | MISC_INT | R/W1C | 0x0 | Miscellaneous Interrupt
This status bit is set to 1 when the programmed number of clocks in the field is completed and the field has been set to 0x1.
This field is cleared by writing 0x1. A write of 0x0 has no effect. | +| 1 | MISC_INT_EN | R/W | 0x0 | Miscellaneous Interrupt Status Enable
When this bit is set to 0x1 will enable the misc_int bit to be set to 0x1 when the programmed number of clocks have been generated on the Pad. | +| 0 | MISC_INT_INT_EN | R/W | 0x0 | misc_int Interrupt Enable
0x1: An interrupt will be generated when the field is set to 0x1. | #### SDHC_RX_CFG_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x118
BitsFieldTypeResetDescription
31:28RSVDR0Reserved for future use
27:18TUNING_DLY_INCR/W0x0Tuning Delay Increment
This field defines the increment value used for each step when the hardware performs auto-tuning. When the host controller takes control of the delay value during auto-tuning, this field specifies by how much the delay value will be incremented at each step.
17:8SDCLK_DELAYR/W0x0This field controls the delay value to the delay element.
7:4RSVDR0Reserved for future use
3:2SDCLK_SEL1R/W0x0This field is used for Rx data/CMD sample clock selections.
This field controls the second mux selects.
0x0: Select the clock from GPIO pad feedback.
0x1: Select the clock output from DDL. If for software tuning, set this value to 0x1
0x2: Select internal clock
0x3: Select internal clock
1:0SDCLK_SEL0R/W0x0This field is used for the software tuning process.
This field controls the first mux selects.
0x0: Select clock from pad
0x1: Select inverted clock from pad
0x2: Select internal clock
0x3: Select inverted internal clock.
+**Offset: 0x118** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | RSVD | R | 0 | Reserved for future use | +| 27:18 | TUNING_DLY_INC | R/W | 0x0 | Tuning Delay Increment
This field defines the increment value used for each step when the hardware performs auto-tuning. When the host controller takes control of the delay value during auto-tuning, this field specifies by how much the delay value will be incremented at each step. | +| 17:8 | SDCLK_DELAY | R/W | 0x0 | This field controls the delay value to the delay element. | +| 7:4 | RSVD | R | 0 | Reserved for future use | +| 3:2 | SDCLK_SEL1 | R/W | 0x0 | This field is used for Rx data/CMD sample clock selections.
This field controls the second mux selects.
0x0: Select the clock from GPIO pad feedback.
0x1: Select the clock output from DDL. If for software tuning, set this value to 0x1
0x2: Select internal clock
0x3: Select internal clock | +| 1:0 | SDCLK_SEL0 | R/W | 0x0 | This field is used for the software tuning process.
This field controls the first mux selects.
0x0: Select clock from pad
0x1: Select inverted clock from pad
0x2: Select internal clock
0x3: Select inverted internal clock. | #### SDHC_TX_CFG_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x11C
BitsFieldTypeResetDescription
31TX_MUX_SELRW0x0TX output clock selection
0x0: Select clock from inverter of base clock input
0x1: Select clock from DDLLoutput clock
30TX_INT_CLK_SELRW0x0TX output clock selection.
0x0: Select the clock from the original inverter of base clock or DDLL output clock
0x1: Select the clock from the inverter of the internal work clock, ensuring the hold time in default speed mode or high-speed mode.
29TX_DLINE_SRC_SELRW0x0TX delayline clock source selection.
0x0: Select the base clock as TX delayline input source clock
0x1: Select the internal work clock as the TX delayline input source clock. Normally, this bit only worked at HS200 mode, but in DDR mode, if TX tuning is required, this TX delayline input clock source bit should be force to 0
28:26RSVDR0Reserved for future use
25:16TX_HOLD_DELAY1RW0x37This field controls the delay value of the TX delay element for SDR104 mode.
15:10RSVDR0Reserved for future use
9:0TX_HOLD_DELAY0RW0xc5This field controls the delay value of the TX delay element for all modes other than the SDR104 mode.
+**Offset: 0x11C** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | TX_MUX_SEL | RW | 0x0 | TX output clock selection
0x0: Select clock from inverter of base clock input
0x1: Select clock from DDLLoutput clock | +| 30 | TX_INT_CLK_SEL | RW | 0x0 | TX output clock selection.
0x0: Select the clock from the original inverter of base clock or DDLL output clock
0x1: Select the clock from the inverter of the internal work clock, ensuring the hold time in default speed mode or high-speed mode. | +| 29 | TX_DLINE_SRC_SEL | RW | 0x0 | TX delayline clock source selection.
0x0: Select the base clock as TX delayline input source clock
0x1: Select the internal work clock as the TX delayline input source clock. Normally, this bit only worked at HS200 mode, but in DDR mode, if TX tuning is required, this TX delayline input clock source bit should be force to 0 | +| 28:26 | RSVD | R | 0 | Reserved for future use | +| 25:16 | TX_HOLD_DELAY1 | RW | 0x37 | This field controls the delay value of the TX delay element for SDR104 mode. | +| 15:10 | RSVD | R | 0 | Reserved for future use | +| 9:0 | TX_HOLD_DELAY0 | RW | 0xc5 | This field controls the delay value of the TX delay element for all modes other than the SDR104 mode. | #### SDHC_HWTUNE_CFG_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x120
BitsFieldTypeResetDescription
31:30RSVDR0Reserved for future use
29:20TUNING_CLK_DLYR0x0This read-only field indicates the final DDLL delay counter value after the tuning process is completed. During the tuning process, this field increments step by step. Therefore, it is typically not meaningful to read this value during hardware tuning.
19:10TUNING_WD_CNTR/W0x0aThis field controls the tuning success window width.
If tuning success times ≥ TUNING_WD_CNT, the tuning is considered successful. Then, hardware will select the middle of the window as the final tuning DDLL delay counter value.
The default value is 10, which aligns with the specifications, but the driver can adjust this count based on real-world conditions.
9:0TUNING_TT_CNTR/W0x27This field controls the total tuning times.
The default value is 40, as specified in the specifications. The driver can adjust this count based on real-world conditions.
The total number of tuning attempts is calculated as TUNING_TT_CNT + 1
+**Offset: 0x120** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | RSVD | R | 0 | Reserved for future use | +| 29:20 | TUNING_CLK_DLY | R | 0x0 | This read-only field indicates the final DDLL delay counter value after the tuning process is completed. During the tuning process, this field increments step by step. Therefore, it is typically not meaningful to read this value during hardware tuning. | +| 19:10 | TUNING_WD_CNT | R/W | 0x0a | This field controls the tuning success window width.
If tuning success times 鈮?TUNING_WD_CNT, the tuning is considered successful. Then, hardware will select the middle of the window as the final tuning DDLL delay counter value.
The default value is 10, which aligns with the specifications, but the driver can adjust this count based on real-world conditions. | +| 9:0 | TUNING_TT_CNT | R/W | 0x27 | This field controls the total tuning times.
The default value is 40, as specified in the specifications. The driver can adjust this count based on real-world conditions.
The total number of tuning attempts is calculated as TUNING_TT_CNT + 1 | #### SDHC_HWTUNE_CFG2_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x124
BitsFieldTypeResetDescription
31:26RSVD
R0Reserved for future use
25:16TUNING_HW_START_CNTR/W0x0This field allows software to configure the starting DLL counter value for hardware auto-tuning. The value set here determines where the hardware auto-tuning process will begin.
15:6_TUNING_SUCCESS_CNTR0x0This field provides software with a reference to determine if the tuning step (TUNING_DLY_INC) or the tuning window count (TUNING_WD_CNT) should be adjusted. It is only valid after the tuning process has completed and failed. Reading this field during the tuning process is meaningless.
5:4RSVDR0Reserved for future use
3:2TUNING_HW_SDCLK_SEL1R0x0This field is used for hardware auto-tuning, and its function is similar to the SW tuning definition at 0x118<3:2>.
1:0TUNING_HW_SDCLK_SEL0R/W0x0This field allows software to configure the hardware auto-tuning DLL source clock selection. It provides flexibility in choosing the clock source for the tuning process.
+**Offset: 0x124** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:26 | RSVD
| R | 0 | Reserved for future use | +| 25:16 | TUNING_HW_START_CNT | R/W | 0x0 | This field allows software to configure the starting DLL counter value for hardware auto-tuning. The value set here determines where the hardware auto-tuning process will begin. | +| 15:6 | _TUNING_SUCCESS_CNT | R | 0x0 | This field provides software with a reference to determine if the tuning step (TUNING_DLY_INC) or the tuning window count (TUNING_WD_CNT) should be adjusted. It is only valid after the tuning process has completed and failed. Reading this field during the tuning process is meaningless. | +| 5:4 | RSVD | R | 0 | Reserved for future use | +| 3:2 | TUNING_HW_SDCLK_SEL1 | R | 0x0 | This field is used for hardware auto-tuning, and its function is similar to the SW tuning definition at 0x118<3:2>. | +| 1:0 | TUNING_HW_SDCLK_SEL0 | R/W | 0x0 | This field allows software to configure the hardware auto-tuning DLL source clock selection. It provides flexibility in choosing the clock source for the tuning process. | #### SDHC_ROUNDTRIP_TIMING_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x128
BitsFieldTypeResetDescription
31:28RSVDR0Reserved for future use
27:24DATA0BUSY_WAIT_CYCLESR/W0x2This field controls how many clock cycles the host should wait before checking the DATA0 busy signal after detecting the end bit of the CRC status in a write operation. This setting is mainly applicable to high-speed modes such as HS200, SDR104, and HS400.
23:20RSVDR0Reserved for future use
19:16WRDATA0_WAIT_CYCLESR/W0x5This field is valid only when bit [2], bit [1], or bit [0] of this register is set in the corresponding speed mode.
- If bit [1] or bit [0] is set, this field specifies how many cycles the host controller's internal logic should wait before changing the bus driving direction—from the end bit of DATA0 to the start bit of the CRC status—during a write operation.
15:12RSVDR0Reserved for future use
11:8CMD2RESP_WAIT_CYCLESR/W0x5This field only valid when this register bit[2] or bit[1] or bit[0] be set at corresponding speed mode, if bit[1] or bit[0] be set, this field indicate the host controller internal logic CMD FSM should wait how many clock cycles between the bus driving direction turn around from CMD end bit to response start bit.
This field is valid only when bit [2], bit [1], or bit [0] of this register is set for the corresponding speed mode.
- If bit [1] or bit [0] is set, this field specifies how many clock cycles the host controller's internal logic should wait before changing the bus driving direction—from the end bit of a CMD to the start bit of the response.
7:3RSVDR0Reserved for future use
2TRS2RCV_PARAM_EN2R/W0x0This field controls whether, in HS400 mode, software can manually configure the number of wait cycles that should be inserted between CMD/DATA transmission and reception during direction turnaround.
In HS400 mode, PHY output and input DLL latency should be enabled when setting this field.
1TRS2RCV_PARAM_EN1R/W0x0This field controls whether, in DDR50/SDR50 mode, software can manually configure the number of wait cycles that should be inserted between CMD/DATA transmission and reception during direction turnaround.
0TRS2RCV_PARAM_EN0R/W0x0This field controls whether, in HS200/SDR104 mode, software can manually configure the number of wait cycles that should be inserted between CMD/DATA transmission and reception during direction turnaround.
+**Offset: 0x128** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | RSVD | R | 0 | Reserved for future use | +| 27:24 | DATA0BUSY_WAIT_CYCLES | R/W | 0x2 | This field controls how many clock cycles the host should wait before checking the DATA0 busy signal after detecting the end bit of the CRC status in a write operation. This setting is mainly applicable to high-speed modes such as HS200, SDR104, and HS400. | +| 23:20 | RSVD | R | 0 | Reserved for future use | +| 19:16 | WRDATA0_WAIT_CYCLES | R/W | 0x5 | This field is valid only when bit [2], bit [1], or bit [0] of this register is set in the corresponding speed mode.
- If bit [1] or bit [0] is set, this field specifies how many cycles the host controller's internal logic should wait before changing the bus driving direction鈥攆rom the end bit of DATA0 to the start bit of the CRC status鈥攄uring a write operation. | +| 15:12 | RSVD | R | 0 | Reserved for future use | +| 11:8 | CMD2RESP_WAIT_CYCLES | R/W | 0x5 | This field only valid when this register bit[2] or bit[1] or bit[0] be set at corresponding speed mode, if bit[1] or bit[0] be set, this field indicate the host controller internal logic CMD FSM should wait how many clock cycles between the bus driving direction turn around from CMD end bit to response start bit.
This field is valid only when bit [2], bit [1], or bit [0] of this register is set for the corresponding speed mode.
- If bit [1] or bit [0] is set, this field specifies how many clock cycles the host controller's internal logic should wait before changing the bus driving direction鈥攆rom the end bit of a CMD to the start bit of the response. | +| 7:3 | RSVD | R | 0 | Reserved for future use | +| 2 | TRS2RCV_PARAM_EN2 | R/W | 0x0 | This field controls whether, in HS400 mode, software can manually configure the number of wait cycles that should be inserted between CMD/DATA transmission and reception during direction turnaround.
In HS400 mode, PHY output and input DLL latency should be enabled when setting this field. | +| 1 | TRS2RCV_PARAM_EN1 | R/W | 0x0 | This field controls whether, in DDR50/SDR50 mode, software can manually configure the number of wait cycles that should be inserted between CMD/DATA transmission and reception during direction turnaround. | +| 0 | TRS2RCV_PARAM_EN0 | R/W | 0x0 | This field controls whether, in HS200/SDR104 mode, software can manually configure the number of wait cycles that should be inserted between CMD/DATA transmission and reception during direction turnaround. | #### SDHC_GPIO_CFG_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x12C
BitsFieldTypeResetDescription
31:16SDHC_GPOR0x0Value to be driven to GPO pins. Software programs these 16-bit fields, and the values will appear on the GPO output ports of the SDHC top module.
15:0SDHC_GPIR0x0Value on GPI ports. These 16-bit fields are read-only and reflect the current state of the GPI input ports.
+**Offset: 0x12C** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | SDHC_GPO | R | 0x0 | Value to be driven to GPO pins. Software programs these 16-bit fields, and the values will appear on the GPO output ports of the SDHC top module. | +| 15:0 | SDHC_GPI | R | 0x0 | Value on GPI ports. These 16-bit fields are read-only and reflect the current state of the GPI input ports. | #### SDHC_DLINE_CTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x130
BitsFieldTypeResetDescription
31:24TX_DLINE_CODER/W0x0Delayline DTC delay control signals for transmission. Software programs this field during the tuning process.
23:16RX_DLINE_CODER/W0x0Delayline DTC delay control signals for reception. Software programs this field during the tuning process.
15:1RSVDR0Reserved for future use
0DLINE_PUR/W0x0Power-up signal for delayline:
0: Power down
1: Power up
The time period from setting the power-up signal to the internal regulator voltage stabilizing is approximately 100ns.
+**Offset: 0x130** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | TX_DLINE_CODE | R/W | 0x0 | Delayline DTC delay control signals for transmission. Software programs this field during the tuning process. | +| 23:16 | RX_DLINE_CODE | R/W | 0x0 | Delayline DTC delay control signals for reception. Software programs this field during the tuning process.
| +| 15:1 | RSVD | R | 0 | Reserved for future use | +| 0 | DLINE_PU | R/W | 0x0 | Power-up signal for delayline:
0: Power down
1: Power up
The time period from setting the power-up signal to the internal regulator voltage stabilizing is approximately 100ns. | #### SDHC_DLINE_CFG_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x134
BitsFieldTypeResetDescription
31:25RSVDR0Reserved for future use
24TX_DLINE_GAINR/W0x0This field is only effective when TX_DLINE_REG[6] is set.
1: Extended delayline delay range with decreased resolution. Typically used for a frequency of 100 MHz, where the DLL delayline is still required.
0: Default setting (for 200 MHz)
23:16TX_DLINE_REGR/W0x0Set the delay line parameters for the tuned clock in HS200 and DDR52 modes.
- Bits 7:6: Reserved
- Bits 5:4: Delay line tuning range (Default: 2'b01).
- Bits 3:2: Delay line LDO output voltage (Default: 2'b11):
1. 2'b00: 0.7V
2. 2'b01: 0.8V
3. 2'b10: 0.85V
4. 2'b11: 0.9V
- Bit 1: Enable delay line LDO resistor load (Default: 1'b1).
- Bit 0: Enable delay line LDO soft start (Default: 1'b1).
15:9RSVDR0Reserved for future use
8RX_DLINE_GAINR/W0x0This field is only effective when RX_DLINE_REG[6] is set.
1 = Extended delayline delay range with decreased resolution. Typically used for a frequency of 100 MHz, where the DLL delayline is still required.
0 = Default (for 200Mhz case)
7:0RX_DLINE_REGR/W0x1Fset delay line parameter for tuned clock in HS200 and DDR52 mode.
- Bits 7:6: Reserved
- Bits 5:4: Delay line tuning range (Default: 2'b01).
- Bits 3:2: Delay line LDO output voltage (Default: 2'b11):
1. 2'b00: 0.7V
2. 2'b01: 0.8V
3. 2'b10: 0.85V
4. 2'b11: 0.9V
- Bit 1: Enable delay line LDO resistor load (Default: 1'b1).
- Bit 0: Enable delay line LDO soft start (Default: 1'b1).
+**Offset: 0x134** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:25 | RSVD | R | 0 | Reserved for future use | +| 24 | TX_DLINE_GAIN | R/W | 0x0 | This field is only effective when TX_DLINE_REG[6] is set.
1: Extended delayline delay range with decreased resolution. Typically used for a frequency of 100 MHz, where the DLL delayline is still required.
0: Default setting (for 200 MHz) | +| 23:16 | TX_DLINE_REG | R/W | 0x0 | Set the delay line parameters for the tuned clock in HS200 and DDR52 modes.
- Bits 7:6: Reserved
- Bits 5:4: Delay line tuning range (Default: 2'b01).
- Bits 3:2: Delay line LDO output voltage (Default: 2'b11):
1. 2'b00: 0.7V
2. 2'b01: 0.8V
3. 2'b10: 0.85V
4. 2'b11: 0.9V
- Bit 1: Enable delay line LDO resistor load (Default: 1'b1).
- Bit 0: Enable delay line LDO soft start (Default: 1'b1). | +| 15:9 | RSVD | R | 0 | Reserved for future use | +| 8 | RX_DLINE_GAIN | R/W | 0x0 | This field is only effective when RX_DLINE_REG[6] is set.
1 = Extended delayline delay range with decreased resolution. Typically used for a frequency of 100 MHz, where the DLL delayline is still required.
0 = Default (for 200Mhz case) | +| 7:0 | RX_DLINE_REG | R/W | 0x1F | set delay line parameter for tuned clock in HS200 and DDR52 mode.
- Bits 7:6: Reserved
- Bits 5:4: Delay line tuning range (Default: 2'b01).
- Bits 3:2: Delay line LDO output voltage (Default: 2'b11):
1. 2'b00: 0.7V
2. 2'b01: 0.8V
3. 2'b10: 0.85V
4. 2'b11: 0.9V
- Bit 1: Enable delay line LDO resistor load (Default: 1'b1).
- Bit 0: Enable delay line LDO soft start (Default: 1'b1). | #### SDHC_PHY_CTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x160
BitsFieldTypeResetDescription
31HOST_LEGACY_MODER/W0x0This field is backdoor register for SW to use old legacy topology host mode. By default, due to EMMC5 PHY/host topology changes, clock generation logic will moved into PHY inside, PHY will output working clock to host. if SW set this bit, below factors will be true:
This field is a backdoor register for software to enable the old legacy topology host mode. By default, the EMMC5 PHY/host topology has changed so that the clock generation logic is moved into the PHY, which outputs the working clock to the host. When this bit is set, the following happens:
- The host will use the internal clock divider to generate the clock.
- SW/HW RX tuning will be affected. The host will use the 0x118/0x130 register settings for DLL slave delayline control, instead of the new 0x168 setting for DLL slave delayline control.
- The host will treat the PHY as just GPIO and use the PHY test mode interface signals (TDI/TDO/TDOE) to output/input data, CMD, and CLK.
- If the host legacy mode is set, it's recommended not to support HS400 mode. The base clock frequency should be ≤ 200MHz, with a maximum of HS200 mode.
- TBD: Whether to add a backdoor delayline in the RX/TX tuning path for clock tuning (without using the PHY internal delayline).
0x0: Disable Host legacy mode (default, using the new external EMMC5.0/SD PHY topology).
0x1: Enable Host legacy mode.
30:24RSVDR0Reserved for future use
23:16PHY_DCHNL_STATUSR0x01Indicates the current status of the PHY 8 data channel enable settings.
After a reset, the hardware logic defaults to enabling the 1-bit mode data channel.
15:8PHY_DCHNL_SWR/W0x0Software-programmed 8 data channel enable signals. Each bit represents one data channel:
0x1: This data channel is enabled.
0x0: This data channel is disabled.
> Note. The CMD channel is always enabled inside the PHY.
7:3RSVDR0Reserved for future use
2PHY_DCHNL_SELR/W0x0Controls the selection method for enabling PHY 8 data channels:
0x1: PHY data channel function is controlled by software using bits [15:8]. If this bit is set, software must configure [15:8] before using PHY for data transfer.
0x0: PHY data channel function is automatically managed by host hardware.
- In this mode, software can read [23:16] for the current hardware data channel status.
- Normally, for eMMC, the host hardware enables all 8 data channels during initialization.
- For SD, the host hardware enables 4 data channels during initialization.
1PHY_PLL_LOCKR/W0x0When following the PHY programming sequence, after enabling the PHY input source clock from APMU offset 0xE0, software should set this bit to 1 to notify the PHY that the internal 400MHz clock source is stable.
0x1: PHY 400MHz clock source is stable.
0x0: PHY 400MHz clock source is unstable.
0PHY_FUNC_ENR/W0x0This bit controls the PHY function enable signal, which is used for internal circuit reset. If the host core logic enters a lower power mode with power gating (UDR latch), phy_en should remain 0.
For normal operation, software should set this bit before using the PHY and configure other PHY-related settings beforehand.
- 0x1: PHY function enabled / PHY powered up.
- 0x0: PHY function disabled / PHY enters lower power mode.
+**Offset: 0x160** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | HOST_LEGACY_MODE | R/W | 0x0 | This field is backdoor register for SW to use old legacy topology host mode. By default, due to EMMC5 PHY/host topology changes, clock generation logic will moved into PHY inside, PHY will output working clock to host. if SW set this bit, below factors will be true:
This field is a backdoor register for software to enable the old legacy topology host mode. By default, the EMMC5 PHY/host topology has changed so that the clock generation logic is moved into the PHY, which outputs the working clock to the host. When this bit is set, the following happens:
- The host will use the internal clock divider to generate the clock.
- SW/HW RX tuning will be affected. The host will use the 0x118/0x130 register settings for DLL slave delayline control, instead of the new 0x168 setting for DLL slave delayline control.
- The host will treat the PHY as just GPIO and use the PHY test mode interface signals (TDI/TDO/TDOE) to output/input data, CMD, and CLK.
- If the host legacy mode is set, it's recommended not to support HS400 mode. The base clock frequency should be 鈮?200MHz, with a maximum of HS200 mode.
- TBD: Whether to add a backdoor delayline in the RX/TX tuning path for clock tuning (without using the PHY internal delayline).
0x0: Disable Host legacy mode (default, using the new external EMMC5.0/SD PHY topology).
0x1: Enable Host legacy mode. | +| 30:24 | RSVD | R | 0 | Reserved for future use | +| 23:16 | PHY_DCHNL_STATUS | R | 0x01 | Indicates the current status of the PHY 8 data channel enable settings.
After a reset, the hardware logic defaults to enabling the 1-bit mode data channel. | +| 15:8 | PHY_DCHNL_SW | R/W | 0x0 | Software-programmed 8 data channel enable signals. Each bit represents one data channel:
0x1: This data channel is enabled.
0x0: This data channel is disabled.
> Note. The CMD channel is always enabled inside the PHY. | +| 7:3 | RSVD | R | 0 | Reserved for future use | +| 2 | PHY_DCHNL_SEL | R/W | 0x0 | Controls the selection method for enabling PHY 8 data channels:
0x1: PHY data channel function is controlled by software using bits [15:8]. If this bit is set, software must configure [15:8] before using PHY for data transfer.
0x0: PHY data channel function is automatically managed by host hardware.
- In this mode, software can read [23:16] for the current hardware data channel status.
- Normally, for eMMC, the host hardware enables all 8 data channels during initialization.
- For SD, the host hardware enables 4 data channels during initialization. | +| 1 | PHY_PLL_LOCK | R/W | 0x0 | When following the PHY programming sequence, after enabling the PHY input source clock from APMU offset 0xE0, software should set this bit to 1 to notify the PHY that the internal 400MHz clock source is stable.
0x1: PHY 400MHz clock source is stable.
0x0: PHY 400MHz clock source is unstable. | +| 0 | PHY_FUNC_EN | R/W | 0x0 | This bit controls the PHY function enable signal, which is used for internal circuit reset. If the host core logic enters a lower power mode with power gating (UDR latch), phy_en should remain 0.
For normal operation, software should set this bit before using the PHY and configure other PHY-related settings beforehand.
- 0x1: PHY function enabled / PHY powered up.
- 0x0: PHY function disabled / PHY enters lower power mode. | #### SDHC_PHY_FUNC_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x164
BitsFieldTypeResetDescription
31:19RSVDR0Reserved for future use
18RX_USE_STROBER0x0Indicates whether the host is in HS400 DDR mode. The value is determined by the following condition:
rx_use_strobe = (uhs_mode[2:0] == 110b) | hs400_mode | enhance_strobe_en;
This means RX strobe is used when:
- UHS mode is set to 110b
- HS400 mode is enabled
- Enhanced strobe is enabled
17RX_USE_DLYLINER0x0Indicates that the host is in HS200 or SDR104 mode. The host also has a backdoor register (bit3) to set this bit in SDR50/DDR50(52) modes.
16TX_USE_INVERTR0x0This bit is set under either of the following conditions:
- 0x3E<2:0> is set to all SDR modes.
- 0x118<30> = 0 is set. However, when 0x118<30> = 1, it only affects PHY test mode output paths (TDO/TDOE signals), while all functional output data, CMD, and output enable signals are still controlled by PHY logic.
15HS200_USE_RFIFOR/W0x1This bit control whether software enables CMD line RFIFO in HS200/HS400 mode:
0x0: Disables CMD line RFIFO in HS200/HS400 mode (default for HS200 mode). In this case, the data is sampled using the Delayline output clock and directly sampled again by the host internal core clock.
0x1: Enables CMD line RFIFO in HS200/HS400 mode. When RFIFO is enabled, data sampled from the Delayline output clock is sent to the Async FIFO, then popped from the FIFO and sent to the host.
14RX_DIS_CKSTOPR/W0x0This bit is a backdoor register added by the host to prevent the clock from being stopped in the middle of a data block during FIFO overflow conditions. The clock can only be stopped during a block gap.
This field is actually a backdoor register for only SDR25/HS50/DDR50 or lower mode, since for HS200/HS400 higher mode SPEC claimed could not stop the bus clock in middle of the data block.
13PHY_TDI_SELR/W0x1This field control PHY test mode input signal TDI source selection:
0x0: TDI is sampled by PHY internal clock signal, which is the same as the host working clock (cclk_in) from PHY.
0x1: TDI is directly from PHY internal IO pad DI port.
12TX_CKOUT_REVERSER/W0x0This field is backdoor register to control whether host controller reverse the output data phase:
0x0: Keep the original clock phase design. The odd phase is always 0, and the even phase is controlled by card_clk_en.
0x1: Reverse the odd phase data to the even output port, and reverse the even phase data to the odd output port.
11TX_DDR_REVERSER/W0x0This field is backdoor register to control whether host controller reverse the output data phase:
0x0: Keep the original design data for odd/even output phase
0x1: Reverse the odd phase data to the even output port and the even phase data to the odd output port.
10RX_DDR_BKENR/W0x0This backdoor register controls the DDR mode RX direction in DDR50 mode. It forces PHY to use the delayline output clock to sample bus data on both edges, then outputs dq_in_o[7:0] and dq_in_e[7:0] to the host. The delayline's input clock is cki.
0x1: Backdoor mode is enabled.
0x0: Backdoor mode is disabled.
9RFIFO_BYPASSR/W0x0When set, the host bypasses the PHY interface Read FIFO in HS400 mode. If not set, the host uses ck_rx_cmd to directly sample the CMD in certain modes. Normally, RFIFO is used in HS400 mode because the internal clock is asynchronous with the PHY output data/CMD Rx clock.
> Note. This bit only works in HS400 mode. In tuning mode with a free-running clock, the DATA/CMD async read path can choose to use the data async FIFO in the host RX interface (via async_io_en, 0x10C<1>).
8CMD_USE_EVENR/W0x1This bit indicates whether the CMD uses a 3/4T DS sampled signal as the controller input in enhanced HS400 mode.
By default, it uses a 1/4T DS sampled signal.
7PHY_TEST_ENR/W0x0This bit enables PHY test mode and controls the source of pad output and output enable signals.
- 0x1: Enables test mode (PHY bypass mode), where the pad output is controlled by TDO (output data) and TDOE (output enable) from the host. In this mode, the host treats PHY as GPIO and uses the test mode interface signals TDI/TDO/TDOE for data, CMD, and CLK input/output.
- 0x0: Uses the normal EMMC function for data, CMD, and CLK paths.
This field works differently from 0x160<31> (host_legacy_mode). While host_legacy_mode has a broader effect, this field only impacts the data, CMD, and CLK input/output paths. If this bit is set, only item 3 of 0x160<31> will take effect, meaning:
- 0x1: The host treats PHY as GPIO and uses the test mode interface signals (TDI/TDO/TDOE) for I/O.
- 0x0: The host uses the normal EMMC data/CMD/CLK paths.
> Note: It is recommended to set this bit in the Bootrom for safety. The APMU also has a backdoor register to configure PHY bypass mode, but setting the APMU register will let TDO/TDOE come from other MFPI functions, not the EMMC controller. If this mode is used, it assumes the PHY’s internal clock generation logic is functioning, and this bit is not suitable for DDR mode backup. For full backup mode, use 0x160<31> to rely solely on PHY’s IO pad.
6:4PHY_MODE_STATUSR0x0These 3 bits reflect current PHY working mode selection in host design,
- If PHY_MODE_SWEN = 1, then the value equals PHY_MODE_SW[2:0].
- If PHY_MODE_SWEN = 0, then the value reflects the hardware-controlled signal PHY_MODE_HW[2:0].
3:1PHY_MODE_SWR/W0x0These 3 bits are valid only when PHY_MODE_SWEN = 1. When enabled, the host controller uses this field instead of the internally generated PHY_MODE_HW signal.
0x000: MMC Default Speed Mode (≤26 MHz), SD DS/SDR12/SDR25 (≤50 MHz)
0x001: MMC HS Mode (≤50 MHz, SDR protocol), SD SDR50 (≤100 MHz)
0x010: DDR50 (or DDR52)
0x011: HS200 (or SDR104)
0x100: HS400
0x101: HS400 CMD Enhanced Mode
Others: Reserved
0PHY_MODE_SWENR/W0x0This bit allows software to control the PHY working mode selection. If set, software should ensure proper synchronization when setting this bit.
+**Offset: 0x164** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | RSVD | R | 0 | Reserved for future use | +| 18 | RX_USE_STROBE | R | 0x0 | Indicates whether the host is in HS400 DDR mode. The value is determined by the following condition:
rx_use_strobe = (uhs_mode[2:0] == 110b) | hs400_mode | enhance_strobe_en;
This means RX strobe is used when:
- UHS mode is set to 110b
- HS400 mode is enabled
- Enhanced strobe is enabled | +| 17 | RX_USE_DLYLINE | R | 0x0 | Indicates that the host is in HS200 or SDR104 mode. The host also has a backdoor register (bit3) to set this bit in SDR50/DDR50(52) modes. | +| 16 | TX_USE_INVERT | R | 0x0 | This bit is set under either of the following conditions:
- 0x3E<2:0> is set to all SDR modes.
- 0x118<30> = 0 is set. However, when 0x118<30> = 1, it only affects PHY test mode output paths (TDO/TDOE signals), while all functional output data, CMD, and output enable signals are still controlled by PHY logic. | +| 15 | HS200_USE_RFIFO | R/W | 0x1 | This bit control whether software enables CMD line RFIFO in HS200/HS400 mode:
0x0: Disables CMD line RFIFO in HS200/HS400 mode (default for HS200 mode). In this case, the data is sampled using the Delayline output clock and directly sampled again by the host internal core clock.
0x1: Enables CMD line RFIFO in HS200/HS400 mode. When RFIFO is enabled, data sampled from the Delayline output clock is sent to the Async FIFO, then popped from the FIFO and sent to the host. | +| 14 | RX_DIS_CKSTOP | R/W | 0x0 | This bit is a backdoor register added by the host to prevent the clock from being stopped in the middle of a data block during FIFO overflow conditions. The clock can only be stopped during a block gap.
This field is actually a backdoor register for only SDR25/HS50/DDR50 or lower mode, since for HS200/HS400 higher mode SPEC claimed could not stop the bus clock in middle of the data block. | +| 13 | PHY_TDI_SEL | R/W | 0x1 | This field control PHY test mode input signal TDI source selection:
0x0: TDI is sampled by PHY internal clock signal, which is the same as the host working clock (cclk_in) from PHY.
0x1: TDI is directly from PHY internal IO pad DI port. | +| 12 | TX_CKOUT_REVERSE | R/W | 0x0 | This field is backdoor register to control whether host controller reverse the output data phase:
0x0: Keep the original clock phase design. The odd phase is always 0, and the even phase is controlled by card_clk_en.
0x1: Reverse the odd phase data to the even output port, and reverse the even phase data to the odd output port. | +| 11 | TX_DDR_REVERSE | R/W | 0x0 | This field is backdoor register to control whether host controller reverse the output data phase:
0x0: Keep the original design data for odd/even output phase
0x1: Reverse the odd phase data to the even output port and the even phase data to the odd output port. | +| 10 | RX_DDR_BKEN | R/W | 0x0 | This backdoor register controls the DDR mode RX direction in DDR50 mode. It forces PHY to use the delayline output clock to sample bus data on both edges, then outputs dq_in_o[7:0] and dq_in_e[7:0] to the host. The delayline's input clock is cki.
0x1: Backdoor mode is enabled.
0x0: Backdoor mode is disabled. | +| 9 | RFIFO_BYPASS | R/W | 0x0 | When set, the host bypasses the PHY interface Read FIFO in HS400 mode. If not set, the host uses ck_rx_cmd to directly sample the CMD in certain modes. Normally, RFIFO is used in HS400 mode because the internal clock is asynchronous with the PHY output data/CMD Rx clock.
> Note. This bit only works in HS400 mode. In tuning mode with a free-running clock, the DATA/CMD async read path can choose to use the data async FIFO in the host RX interface (via async_io_en, 0x10C<1>). | +| 8 | CMD_USE_EVEN | R/W | 0x1 | This bit indicates whether the CMD uses a 3/4T DS sampled signal as the controller input in enhanced HS400 mode.
By default, it uses a 1/4T DS sampled signal. | +| 7 | PHY_TEST_EN | R/W | 0x0 | This bit enables PHY test mode and controls the source of pad output and output enable signals.
- 0x1: Enables test mode (PHY bypass mode), where the pad output is controlled by TDO (output data) and TDOE (output enable) from the host. In this mode, the host treats PHY as GPIO and uses the test mode interface signals TDI/TDO/TDOE for data, CMD, and CLK input/output.
- 0x0: Uses the normal EMMC function for data, CMD, and CLK paths.
This field works differently from 0x160<31> (host_legacy_mode). While host_legacy_mode has a broader effect, this field only impacts the data, CMD, and CLK input/output paths. If this bit is set, only item 3 of 0x160<31> will take effect, meaning:
- 0x1: The host treats PHY as GPIO and uses the test mode interface signals (TDI/TDO/TDOE) for I/O.
- 0x0: The host uses the normal EMMC data/CMD/CLK paths.
> Note: It is recommended to set this bit in the Bootrom for safety. The APMU also has a backdoor register to configure PHY bypass mode, but setting the APMU register will let TDO/TDOE come from other MFPI functions, not the EMMC controller. If this mode is used, it assumes the PHY鈥檚 internal clock generation logic is functioning, and this bit is not suitable for DDR mode backup. For full backup mode, use 0x160<31> to rely solely on PHY鈥檚 IO pad. | +| 6:4 | PHY_MODE_STATUS | R | 0x0 | These 3 bits reflect current PHY working mode selection in host design,
- If PHY_MODE_SWEN = 1, then the value equals PHY_MODE_SW[2:0].
- If PHY_MODE_SWEN = 0, then the value reflects the hardware-controlled signal PHY_MODE_HW[2:0]. | +| 3:1 | PHY_MODE_SW | R/W | 0x0 | These 3 bits are valid only when PHY_MODE_SWEN = 1. When enabled, the host controller uses this field instead of the internally generated PHY_MODE_HW signal.
0x000: MMC Default Speed Mode (鈮?6 MHz), SD DS/SDR12/SDR25 (鈮?0 MHz)
0x001: MMC HS Mode (鈮?0 MHz, SDR protocol), SD SDR50 (鈮?00 MHz)
0x010: DDR50 (or DDR52)
0x011: HS200 (or SDR104)
0x100: HS400
0x101: HS400 CMD Enhanced Mode
Others: Reserved | +| 0 | PHY_MODE_SWEN | R/W | 0x0 | This bit allows software to control the PHY working mode selection. If set, software should ensure proper synchronization when setting this bit. | #### SDHC_PHY_DLLCFG_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x168
BitsFieldTypeResetDescription
31DLL_ENABLER/W0x0Enable DLL.
0: DLL function disable (power down)
1: DLL function enable (power up)
30DLL_DELAY_SRCR/W0x0PHY internal dedicated delayline input clock source selection.
0: Uses PCLK (bus clock feedback) as the default source.
1: Switches to PHY internal cki (cclk_in), typically used for manual tuning in HS200 mode.
29DLL_REFRESH_SWR/W0x0Controls manual updates to the DLL_REFRESH signal:
1: Triggers a manual update.
0: Keeps the DLL_REFRESH signal invalid.
28DLL_REFRESH_SWENR/W0x01: Software manually controls DLL_REFRESH updates.
0: Host Hardware manually controls DLL_REFRESH updates.
27DLL_REFRESH_ENABLER/W0x11: Host controller generates DLL_REFRESH signal for manually adjusting the delay of strobe signal;
0: DLL_RERRESH remains inactive
26:16RSVDR0Reserved for future use
15:8DLL_DELAY_CTRLR/W0x0Controls the delay value for the PHY DLL slave delayline tuning in HS400 mode, used when the PHY does not use the internal DLL master counter to update the DLL slave. This field only takes effect when dll_reg1<1> (0x168<1>) = 1.
> Note. In the new EMMC5.x topology, the DLL slave delay line is integrated into the PHY. For older topologies (such as those in host_legacy_mode with 0x160<31>=1) or for HS200/DDR50 tuning, the 0x114/0x130/0x134 registers will be used to control the tuning process.
7:6DLL_VREG_CTRLR/W0x1DLL regulator output voltage control
5:4DLL_FULLDLY_RANGER/W0x1DLL delayline full delay range
3:2DLL_PREDLY_NUMR/W0x1DLL delayline Pre-delay numbers
1DLL_BYPASS_ENABLER/W0x0DLL Master Bypass Enable for HS400
1: DLL master is bypassed, and DLL_DELAY_CTRL directly controls the slave DLL.
0: DLL is enabled. Use delay value is from the master DLL.
0DLL_REFRESH_METHODR/W0x0DLL master code refresh method:
After locked: refreshed by host generated dll_refresh rising edge.
1: Always refreshed by ck_refresh, synchronized to the filter clock.
0: Before lock: refreshed by ck_refresh. After lock: refreshed by the host-generated dll_refresh rising edge.
+**Offset: 0x168** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | DLL_ENABLE | R/W | 0x0 | Enable DLL.
0: DLL function disable (power down)
1: DLL function enable (power up) | +| 30 | DLL_DELAY_SRC | R/W | 0x0 | PHY internal dedicated delayline input clock source selection.
0: Uses PCLK (bus clock feedback) as the default source.
1: Switches to PHY internal cki (cclk_in), typically used for manual tuning in HS200 mode. | +| 29 | DLL_REFRESH_SW | R/W | 0x0 | Controls manual updates to the DLL_REFRESH signal:
1: Triggers a manual update.
0: Keeps the DLL_REFRESH signal invalid. | +| 28 | DLL_REFRESH_SWEN | R/W | 0x0 | 1: Software manually controls DLL_REFRESH updates.
0: Host Hardware manually controls DLL_REFRESH updates. | +| 27 | DLL_REFRESH_ENABLE | R/W | 0x1 | 1: Host controller generates DLL_REFRESH signal for manually adjusting the delay of strobe signal;
0: DLL_RERRESH remains inactive | +| 26:16 | RSVD | R | 0 | Reserved for future use | +| 15:8 | DLL_DELAY_CTRL | R/W | 0x0 | Controls the delay value for the PHY DLL slave delayline tuning in HS400 mode, used when the PHY does not use the internal DLL master counter to update the DLL slave. This field only takes effect when dll_reg1<1> (0x168<1>) = 1.
> Note. In the new EMMC5.x topology, the DLL slave delay line is integrated into the PHY. For older topologies (such as those in host_legacy_mode with 0x160<31>=1) or for HS200/DDR50 tuning, the 0x114/0x130/0x134 registers will be used to control the tuning process. | +| 7:6 | DLL_VREG_CTRL | R/W | 0x1 | DLL regulator output voltage control
| +| 5:4 | DLL_FULLDLY_RANGE | R/W | 0x1 | DLL delayline full delay range | +| 3:2 | DLL_PREDLY_NUM | R/W | 0x1 | DLL delayline Pre-delay numbers | +| 1 | DLL_BYPASS_ENABLE | R/W | 0x0 | DLL Master Bypass Enable for HS400
1: DLL master is bypassed, and DLL_DELAY_CTRL directly controls the slave DLL.
0: DLL is enabled. Use delay value is from the master DLL. | +| 0 | DLL_REFRESH_METHOD | R/W | 0x0 | DLL master code refresh method:
After locked: refreshed by host generated dll_refresh rising edge.
1: Always refreshed by ck_refresh, synchronized to the filter clock.
0: Before lock: refreshed by ck_refresh. After lock: refreshed by the host-generated dll_refresh rising edge. | #### SDHC_PHY_DLLCFG1_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x16C
BitsFieldTypeResetDescription
31:24DLL_REG4_CTRLR/W0x00Detailed bits refer to analog PHY pin list 'dll_reg4' descriptions
23:16DLL_REG3_CTRLR/W0x0eDetailed bits refer to analog PHY pin list 'dll_reg3' descriptions
15:8DLL_REG2_CTRLR/W0x4aDetailed bits refer to analog PHY pin list 'dll_reg2' descriptions
7:0DLL_REG1_CTRLR/W0x00 Detailed bits refer to analog PHY pinlist 'dll_reg1' descriptions
+**Offset: 0x16C** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | DLL_REG4_CTRL | R/W | 0x00 | Detailed bits refer to analog PHY pin list 'dll_reg4' descriptions | +| 23:16 | DLL_REG3_CTRL | R/W | 0x0e | Detailed bits refer to analog PHY pin list 'dll_reg3' descriptions | +| 15:8 | DLL_REG2_CTRL | R/W | 0x4a | Detailed bits refer to analog PHY pin list 'dll_reg2' descriptions | +| 7:0 | DLL_REG1_CTRL | R/W | 0x00 | Detailed bits refer to analog PHY pinlist 'dll_reg1' descriptions | #### SDHC_PHY_DLLSTS_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x170
BitsFieldTypeResetDescription
31:16RSVDR0Reserved for future use
15:8PHY_WORK_MODER0x0This field indicates the current PHY working mode flag, from PHY output signal rdo_reg2[7:0]:
- [7]: SDR26
- [6]: SDR52
- [5]: DDR52
- [4]: HS200
- [3]: HS400
- [2]: cmd__extd_mode
- [1]: start_dll
- [0]: dll_error
7:2RSVDR0Reserved for future use
1DLL_REFRESH_STATER0x0This bit indicates DLL manully refresh mode refresh signal state, this bit only valid when DLL_REFRESH_EN is set.
0: No refresh
1: Manully refresh state, is from DLL_REFRESH_HW (host HW control logic)
0DLL_LOCK_STATER0x0This bit indicates whether Master DLL is at LOCK State
0: UNLOCK State
1: LOCK State. The RX path only works in HS400 and HS400_extend mode when dll_lk is set to 1'b1
+**Offset: 0x170** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RSVD | R | 0 | Reserved for future use | +| 15:8 | PHY_WORK_MODE | R | 0x0 | This field indicates the current PHY working mode flag, from PHY output signal rdo_reg2[7:0]:
- [7]: SDR26
- [6]: SDR52
- [5]: DDR52
- [4]: HS200
- [3]: HS400
- [2]: cmd__extd_mode
- [1]: start_dll
- [0]: dll_error | +| 7:2 | RSVD | R | 0 | Reserved for future use | +| 1 | DLL_REFRESH_STATE | R | 0x0 | This bit indicates DLL manully refresh mode refresh signal state, this bit only valid when DLL_REFRESH_EN is set.
0: No refresh
1: Manully refresh state, is from DLL_REFRESH_HW (host HW control logic) | +| 0 | DLL_LOCK_STATE | R | 0x0 | This bit indicates whether Master DLL is at LOCK State
0: UNLOCK State
1: LOCK State. The RX path only works in HS400 and HS400_extend mode when dll_lk is set to 1'b1 | #### SDHC_PHY_DLLSTS1_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x174
BitsFieldTypeResetDescription
31:24RSVDR0Reserved for future use
23:16DLL_MASTER_DELAYR0x0The newest delay value for the delay line in master DLL.
Note: This field always reflects the most recent value regardless of whether the DLL is locked or not.
15:8RSVDR0Reserved for future use
7:0DLL_SLAVE_DELAYR0x0This field reflects the delay value currently used for Strobe Signal or the final delay value from SW/HW tuning process.
+**Offset: 0x174** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | RSVD | R | 0 | Reserved for future use | +| 23:16 | DLL_MASTER_DELAY | R | 0x0 | The newest delay value for the delay line in master DLL.
Note: This field always reflects the most recent value regardless of whether the DLL is locked or not. | +| 15:8 | RSVD | R | 0 | Reserved for future use | +| 7:0 | DLL_SLAVE_DELAY | R | 0x0 | This field reflects the delay value currently used for Strobe Signal or the final delay value from SW/HW tuning process. | #### SDHC_PHY_PADCFG_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x178
BitsFieldTypeResetDescription
31:22RSVDR0Reserved for future use
21:20CLK_PUR/W0x0CLK Pullup 2 bits resistor selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm
19:18DS_PUR/W0x0DS Pullup 2 bits resistor selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm
17:16CMD_PUR/W0x2CMD Pullup 2 bits resistor selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm
15:14RSVDR0Reserved for future use
13:12CLK_PDR/W0x2CLK Pulldown 2 bits resistor selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm
11:10DS_PDR/W0x2DS Pulldown 2 bits resistor selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm
9:8CMD_PDR/W0x0 CMD Pulldown 2 bits resistor selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm
7RSVDR0Reserved for future use
6IO_DRV_HZR/W0x0This backdoor bit enables the bus IO high-Z state after the Analog EMMC PHY fix for the AutoCMD23 timeout issue (when IO becomes floating or uncontrollable) during PHY_EN switching.
- 1'b1: Enable High-Z state
- 1'b0: Disable High-Z state
5RX_BIASR/W0x1- 1'b0: High current mode
- 1'b1: Low current mode
4:3SLEW_RATER/W0x0PAD slew rate control:
- 2'b00: Low
- 2'b01: Medium
- 2'b10: High
- 2'b11: Very high
2:0DRIVE_SELR/W0x4For Drive Nominal Impedance selection:
- 3'b000: high-Z
- 3'b001: 200
- 3'b010: 100
- 3'b011: 66
- 3'b100: 50
- 3'b101: 40
- 3'b110: 33
- 3'b111: 33
+**Offset: 0x178** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:22 | RSVD | R | 0 | Reserved for future use | +| 21:20 | CLK_PU | R/W | 0x0 | CLK Pullup 2 bits resistor selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm | +| 19:18 | DS_PU | R/W | 0x0 | DS Pullup 2 bits resistor selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm | +| 17:16 | CMD_PU | R/W | 0x2 | CMD Pullup 2 bits resistor selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm | +| 15:14 | RSVD | R | 0 | Reserved for future use | +| 13:12 | CLK_PD | R/W | 0x2 | CLK Pulldown 2 bits resistor selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm | +| 11:10 | DS_PD | R/W | 0x2 | DS Pulldown 2 bits resistor selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm | +| 9:8 | CMD_PD | R/W | 0x0 | CMD Pulldown 2 bits resistor selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm | +| 7 | RSVD | R | 0 | Reserved for future use | +| 6 | IO_DRV_HZ | R/W | 0x0 | This backdoor bit enables the bus IO high-Z state after the Analog EMMC PHY fix for the AutoCMD23 timeout issue (when IO becomes floating or uncontrollable) during PHY_EN switching.
- 1'b1: Enable High-Z state
- 1'b0: Disable High-Z state | +| 5 | RX_BIAS | R/W | 0x1 | - 1'b0: High current mode
- 1'b1: Low current mode | +| 4:3 | SLEW_RATE | R/W | 0x0 | PAD slew rate control:
- 2'b00: Low
- 2'b01: Medium
- 2'b10: High
- 2'b11: Very high | +| 2:0 | DRIVE_SEL | R/W | 0x4 | For Drive Nominal Impedance selection:
- 3'b000: high-Z
- 3'b001: 200
- 3'b010: 100
- 3'b011: 66
- 3'b100: 50
- 3'b101: 40
- 3'b110: 33
- 3'b111: 33 | #### SDHC_PHY_PADCFG1_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x17C
BitsFieldTypeResetDescription
31:16DQX_PUR/W0xaaaaDQ Pullup Resistor value selection, every two bits stands for one IO selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm
15:0DQX_PDR/W0x0DQ Pulldown Resistor value selection, every two bits stands for one IO selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm
+**Offset: 0x17C** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | DQX_PU | R/W | 0xaaaa | DQ Pullup Resistor value selection, every two bits stands for one IO selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm | +| 15:0 | DQX_PD | R/W | 0x0 | DQ Pulldown Resistor value selection, every two bits stands for one IO selection:
- 2'b00: high-Z
- 2'b01: 50K Ohm
- 2'b10: 40K Ohm
- 2'b11: 33K Ohm | #### SDHC_PHY_LBCTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x180
BitsFieldTypeResetDescription
31CLEAR_LB_ERR_STATUSW0x0Write 1 to clear SDHC_PHY_LBSTS_REG register
30:3RSVDR0Reserved for future use
2START_STUCK0_DET_CLKR/WAC0x0After operation is finished, check EMMC_LB_Err_Status Register.
1START_STUCK1_DET_CLKR/WAC0x0After operation is finished, check EMMC_LB_Err_Status Register.
0LB_TEST_TRIGGERR/WAC0x0Triggers Loopback Testing immediately. Before setting this bit, the host driver should configure the SDHC_PHY_LBCNT_REG register (offset: 0x188).
- The test will run until SDHC_PHY_LBCNT_REG reaches 0, at which point the test stops and this bit clears automatically.
- This bit is only effective when Loopback Mode Enable is set.
+**Offset: 0x180** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | CLEAR_LB_ERR_STATUS | W | 0x0 | Write 1 to clear SDHC_PHY_LBSTS_REG register | +| 30:3 | RSVD | R | 0 | Reserved for future use | +| 2 | START_STUCK0_DET_CLK | R/WAC | 0x0 | After operation is finished, check EMMC_LB_Err_Status Register. | +| 1 | START_STUCK1_DET_CLK | R/WAC | 0x0 | After operation is finished, check EMMC_LB_Err_Status Register. | +| 0 | LB_TEST_TRIGGER | R/WAC | 0x0 | Triggers Loopback Testing immediately. Before setting this bit, the host driver should configure the SDHC_PHY_LBCNT_REG register (offset: 0x188).
- The test will run until SDHC_PHY_LBCNT_REG reaches 0, at which point the test stops and this bit clears automatically.
- This bit is only effective when Loopback Mode Enable is set. | #### SDHC_PHY_LBFUNC_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x184
BitsFieldTypeResetDescription
31:28RSVDR0Reserved for future use
27:24LB_DS_CNTR/W0x0Represents the total latency from TX to RX through the PHY loopback path.
- Software should program this field to match PHY characteristics.
- Recommended values:
1. HS400 or HS200 with RFIFO mode: Set to 5
2. Other modes: Set to 4
- Must be greater than 1.
Note: this field should be > 1.
23:20LB_FILTER_CNTR/W0x0The first LB_FILTER_CNT bits and the last LB_FILTER_CNT bits are ignored in the comparison process.
19:17RSVDR0Reserved for future use
16LB_CMD_MASKR/W0x0If set, the corresponding path will not perform lookback test.
15:8LB_DQ_MASKR/W0x0If set, the corresponding path will not perform lookback test.
7:4RSVDR0Reserved for future use
3LB_INVERT_CLKR/W0x0Normally, when loopback test is triggered and data pattern starts to be driven, Ckout_e will become 1 and Ckout_o stays at 0.
If this bit is set, Ckout_e will become 1 and Ckout_o stays at 0.
Only valid when bit[28] is set.
2CLK_PASSTH_DSR/W0x0Controls whether the host needs to send clock control signals (wr_ck_o/wr_ck_e/wr_ck_oe) to the PHY during loopback mode.
0: No need to output clock control signals to PHY. Used for HS400 mode with DS test, as the DS in loopback mode comes from the PHY’s internal free-running clock (cki).
1: Required for other working modes in loopback mode. In this case, wr_ck_oe will be 1T earlier than wr_ck_o/wr_ck_e.
1LB_PATTERN_SELR/W0x00: Use programmable 32-bit pattern;
1: PRBS7
0LB_MODE_ENR/W0x0Enter Loopback Mode.
Normally, host driver shall only change this bit when no other operation is processing.
+**Offset: 0x184** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | RSVD | R | 0 | Reserved for future use | +| 27:24 | LB_DS_CNT | R/W | 0x0 | Represents the total latency from TX to RX through the PHY loopback path.
- Software should program this field to match PHY characteristics.
- Recommended values:
1. HS400 or HS200 with RFIFO mode: Set to 5
2. Other modes: Set to 4
- Must be greater than 1.
Note: this field should be > 1. | +| 23:20 | LB_FILTER_CNT | R/W | 0x0 | The first LB_FILTER_CNT bits and the last LB_FILTER_CNT bits are ignored in the comparison process. | +| 19:17 | RSVD | R | 0 | Reserved for future use | +| 16 | LB_CMD_MASK | R/W | 0x0 | If set, the corresponding path will not perform lookback test. | +| 15:8 | LB_DQ_MASK | R/W | 0x0 | If set, the corresponding path will not perform lookback test. | +| 7:4 | RSVD | R | 0 | Reserved for future use | +| 3 | LB_INVERT_CLK | R/W | 0x0 | Normally, when loopback test is triggered and data pattern starts to be driven, Ckout_e will become 1 and Ckout_o stays at 0.
If this bit is set, Ckout_e will become 1 and Ckout_o stays at 0.
Only valid when bit[28] is set. | +| 2 | CLK_PASSTH_DS | R/W | 0x0 | Controls whether the host needs to send clock control signals (wr_ck_o/wr_ck_e/wr_ck_oe) to the PHY during loopback mode.
0: No need to output clock control signals to PHY. Used for HS400 mode with DS test, as the DS in loopback mode comes from the PHY鈥檚 internal free-running clock (cki).
1: Required for other working modes in loopback mode. In this case, wr_ck_oe will be 1T earlier than wr_ck_o/wr_ck_e. | +| 1 | LB_PATTERN_SEL | R/W | 0x0 | 0: Use programmable 32-bit pattern;
1: PRBS7 | +| 0 | LB_MODE_EN | R/W | 0x0 | Enter Loopback Mode.
Normally, host driver shall only change this bit when no other operation is processing. | #### SDHC_PHY_LBCNT_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x188
BitsFieldTypeResetDescription
31:0LB_COMP_CNTR/W0x0This field specifies the number of bits to be compared during the current loopback testing.
- Once loopback testing starts, the host controller decrements this counter until it reaches 0.
- Please note that after SW writes this field, the host will dynamically control this counter value.
- During the loopback test process, this counter may be changed cycle by cycle.
+**Offset: 0x188** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | LB_COMP_CNT | R/W | 0x0 | This field specifies the number of bits to be compared during the current loopback testing.
- Once loopback testing starts, the host controller decrements this counter until it reaches 0.
- Please note that after SW writes this field, the host will dynamically control this counter value.
- During the loopback test process, this counter may be changed cycle by cycle. | #### SDHC_PHY_LBSTS_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x18C
BitsFieldTypeResetDescription
31:22RSVDR0Reserved for future use
21LB_CLK_STUCK0_ERRRC0x0CLK Path is stuck at 0
20LB_CLK_STUCK1_ERRRC0x0CLK Path is stuck at 1
19:18RSVDR0Reserved for future use
17LB_CMD_EVEN_ERRRC0x0If set, the CMD line path failed the Loopback testing
16LB_CMD_ODD_ERRRC0x0If set, the CMD line path failed the Loopback testing
15:8LB_DQ_EVEN_ERRRC0x0If set, the corresponding data path failed Loopback testing
7:0LB_DQ_ODD_ERRRC0x0If set, the corresponding data path failed Loopback testing
+**Offset: 0x18C** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:22 | RSVD | R | 0 | Reserved for future use | +| 21 | LB_CLK_STUCK0_ERR | RC | 0x0 | CLK Path is stuck at 0 | +| 20 | LB_CLK_STUCK1_ERR | RC | 0x0 | CLK Path is stuck at 1 | +| 19:18 | RSVD | R | 0 | Reserved for future use | +| 17 | LB_CMD_EVEN_ERR | RC | 0x0 | If set, the CMD line path failed the Loopback testing | +| 16 | LB_CMD_ODD_ERR | RC | 0x0 | If set, the CMD line path failed the Loopback testing | +| 15:8 | LB_DQ_EVEN_ERR | RC | 0x0 | If set, the corresponding data path failed Loopback testing
| +| 7:0 | LB_DQ_ODD_ERR | RC | 0x0 | If set, the corresponding data path failed Loopback testing | #### CQE_CQBDCTRL_REG0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1F0
BitsFieldTypeResetDescription
31CQE_FSM_RSTR/W0x0- This is a backdoor register allowing software to force the CQE state machine into a stable IDLE state if the hardware encounters issues.
- 1: Forces CQE FSM into IDLE state.
- 0: No effect.
30:4RSVDR0Reserved for future use
3:0CQE_DEBUG_SELR/W0x0These 4 bits field register selects which internal 32-bit debug bus signals are presented in the 0x1f4 register:
- 4'b0000: Slot index & FSM informations
- 4'b0001: Slot index informations
- 4'b0010: Internal task slot fetch signals
- 4'b0011: Internal task ready signals
> Note. This field is mainly intended for hardware designers to debug.
+**Offset: 0x1F0** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | CQE_FSM_RST | R/W | 0x0 | - This is a backdoor register allowing software to force the CQE state machine into a stable IDLE state if the hardware encounters issues.
- 1: Forces CQE FSM into IDLE state.
- 0: No effect. | +| 30:4 | RSVD | R | 0 | Reserved for future use | +| 3:0 | CQE_DEBUG_SEL | R/W | 0x0 | These 4 bits field register selects which internal 32-bit debug bus signals are presented in the 0x1f4 register:
- 4'b0000: Slot index & FSM informations
- 4'b0001: Slot index informations
- 4'b0010: Internal task slot fetch signals
- 4'b0011: Internal task ready signals
> Note. This field is mainly intended for hardware designers to debug. | #### CQE_CQBDCTRL_REG1 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1F4
BitsFieldTypeResetDescription
31:0CQE_DEBUG_INFOR0x032-bit debug signal information output to software.
> Note. These register values may change on each cycle because the internal design logic of the CQE hardware may still be running when the software reads these values. To determine which 32-bit debug bus information is selected for output to this field, refer to 0x1F0<3:0>.
+**Offset: 0x1F4** +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CQE_DEBUG_INFO | R | 0x0 | 32-bit debug signal information output to software.
> Note. These register values may change on each cycle because the internal design logic of the CQE hardware may still be running when the software reads these values. To determine which 32-bit debug bus information is selected for output to this field, refer to 0x1F0<3:0>. | diff --git a/en/key_stone/k1/k1_docs/k1_usermanual/11.Video_&_Graphics.md b/en/key_stone/k1/k1_docs/k1_usermanual/11.Video_&_Graphics.md index ce5249b..8449d8f 100644 --- a/en/key_stone/k1/k1_docs/k1_usermanual/11.Video_&_Graphics.md +++ b/en/key_stone/k1/k1_docs/k1_usermanual/11.Video_&_Graphics.md @@ -57,7 +57,7 @@ To be highlighted: - Optional source frame rotation in 90-degree steps before encoding (not applicable to AFBC input format) > **Note.** If YUV422 is rotated by 90 or 270 degrees and not converting to YUV420, the result will be converted to YUV440. - + - Encoding support for the following source-frame input formats: - 1-plane YUV422, scan-line format, interleaved in YUYV or UYVY order @@ -120,7 +120,7 @@ To be highlighted: - Context Adaptive Binary Arithmetic Coding (CABAC) or Context Adaptive Variable Length Coding (CAVLC) entropy coding > **Note.** B frames are not supported with CAVLC entropy coding - + - Motion Estimation (ME) search window dimensions: ±128 pixels horizontally, ±64 pixels vertically - ME search precision: down to Quarter Picture Element (QPEL) resolution - Luma intra-modes: 4×4, 8×8, 16×16 @@ -504,7 +504,7 @@ Rect_width = Rect_left%4 + Rect_width; Rect_height = Rect_top%4 + Rect_height; Rect_left = Rect_left/4 × 4; Rect_top = Rect_top/4 × 4; -if LayerX_format == YUV420 +if LayerX_format == YUV420 { Rect_width = ALIGN(Rect_left %2 + Rect_width, 2); Rect_height = ALIGN(Rect_top%2 + Rect_height, 2); @@ -659,7 +659,7 @@ if LayerX_degree == ROT_90{ Org_rect_top = ALIGN(LayerX_height,16) - Rect_left - Rect_width; Org_rect_width = Rect_height; Org_rect_height = Rect_width; -} +} if LayerX_degree == ROT_180{ Org_rect_left = ALIGN(LayerX_width,16) - Rect_left - Rect_width; Org_rect_top = ALIGN(LayerX_height,16) - Rect_top - Rect_height; @@ -825,7 +825,7 @@ if output_format == YUV420 } } } -if output_format == RGB888 +if output_format == RGB888 { s0=0; s1=1; @@ -861,7 +861,7 @@ if output_format == RGBX888 || output_format == RGBA888 } } } -if output_format == ARGB8888 +if output_format == ARGB8888 { s0=3; s1=0; diff --git a/en/key_stone/k1/k1_docs/k1_usermanual/12.Display_Subsystem.md b/en/key_stone/k1/k1_docs/k1_usermanual/12.Display_Subsystem.md index 553f64c..24a8ca3 100644 --- a/en/key_stone/k1/k1_docs/k1_usermanual/12.Display_Subsystem.md +++ b/en/key_stone/k1/k1_docs/k1_usermanual/12.Display_Subsystem.md @@ -111,3831 +111,879 @@ The DSI Timing Relationship with LCD Timing is as follows: #### DSI_CTRL_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31CFG_SOFT_RSTRW
0x0Software Reset DSI Module
1: Reset DSI module
0: De-assert software reset
30
CFG_SOFT_RST_REGRW0x0Software Reset Configuration Registers
1: Reset DSI configuration registers to default values
0: De-assert reset
29CFG_CLR_PHY_FIFORW0x0Configure Clear PHY Tx FIFO
1: Clear FIFO data to 0
0: De-assert clear
It is NOT used currently and reserved for future use.
28CFG_RST_TXLPRW0x0Software Reset LP TX submodule
1: Reset LP TX module
0: De-assert software reset
27CFG_RST_CPURW0x0Software Reset CPU TX submodule
1: Reset CPU TX module
0: De-assert software reset
26CFG_RST_CPNRW0x0Software Reset CPN TX submodule
1: Reset CPN TX module
0: De-assert software reset
25RSVDRO0Reserved for future use
24CFG_RST_VPNRW0x0Software Reset Video Panel submodule
1: Reset VPN module
0: De-assert software reset
23CFG_DSI_PHY_RSTRW0x0Software Reset DPHY submodule
1: Reset DPHY
0: De-assert software reset
22:18RSVDRO0Reserved for future use
17CFG_DSI_HCLK_DISRW0x0DSI AHB Clock Disable
> Note. DSI configuration registers can still be written or read even if the DSI AHB clock is disabled.
1: DSI AHB clock will be gated
0: DSI AHB clock is passed to DSI module
16CFG_DSI_CLK_DISRW0x0DSI Clock disable
1: DSI clock will be gated
0: DSI clock is passed to DSI module
15:9RSVDRO0Reserved for future use
8CFG_VPN_TX_ENRW0x1Video Panel Interface TX Enable
1: Enable Video Panel TX packet to DPHY. DSI will send video packets to peripherals.
0: Disable Video Panel interface TX.
7:5RSVDRO0Reserved for future use
4CFG_VPN_SLVRW0x1Video Panel Interface in slave mode
1: Video Panel works in slave mode. It receives VSYNC from input LCD interface, and is used to control the internal timing.
0: Video Panel interface works in master mode. DSI sends VSYNC to LCD module, and controls the V timing and H timing.
> Note. This bit must set to 1, VPN only supports slave mode.
3RSVDRO0Reserved for future use
2CFG_CPN_ENRW0x0Command Panel Interface Enable
1: Command panel is running and can accept data from the Command Panel interface
0: Disable Command Panel interface
1RSVDRO0Reserved for future use
0CFG_VPN_ENRW0x0Video Panel Interface Enable
1: Video Panel is active and running.
0: Video Panel interface is disabled.
> Note. Set this field to 1 to start the Video Panel timing.
+**Offset: 0x0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | CFG_SOFT_RST | RW | 0x0 | Software Reset DSI Module
1: Reset DSI module
0: De-assert software reset | +| 30 | CFG_SOFT_RST_REG | RW | 0x0 | Software Reset Configuration Registers
1: Reset DSI configuration registers to default values
0: De-assert reset | +| 29 | CFG_CLR_PHY_FIFO | RW | 0x0 | Configure Clear PHY Tx FIFO
1: Clear FIFO data to 0
0: De-assert clear
It is NOT used currently and reserved for future use. | +| 28 | CFG_RST_TXLP | RW | 0x0 | Software Reset LP TX submodule
1: Reset LP TX module
0: De-assert software reset | +| 27 | CFG_RST_CPU | RW | 0x0 | Software Reset CPU TX submodule
1: Reset CPU TX module
0: De-assert software reset | +| 26 | CFG_RST_CPN | RW | 0x0 | Software Reset CPN TX submodule
1: Reset CPN TX module
0: De-assert software reset | +| 25 | RSVD | RO | 0 | Reserved for future use | +| 24 | CFG_RST_VPN | RW | 0x0 | Software Reset Video Panel submodule
1: Reset VPN module
0: De-assert software reset | +| 23 | CFG_DSI_PHY_RST | RW | 0x0 | Software Reset DPHY submodule
1: Reset DPHY
0: De-assert software reset | +| 22:18 | RSVD | RO | 0 | Reserved for future use | +| 17 | CFG_DSI_HCLK_DIS | RW | 0x0 | DSI AHB Clock Disable
**Note. DSI configuration registers can still be written or read even if the DSI AHB clock is disabled.**
1: DSI AHB clock will be gated
0: DSI AHB clock is passed to DSI module | +| 16 | CFG_DSI_CLK_DIS | RW | 0x0 | DSI Clock disable
1: DSI clock will be gated
0: DSI clock is passed to DSI module | +| 15:9 | RSVD | RO | 0 | Reserved for future use | +| 8 | CFG_VPN_TX_EN | RW | 0x1 | Video Panel Interface TX Enable
1: Enable Video Panel TX packet to DPHY. DSI will send video packets to peripherals.
0: Disable Video Panel interface TX. | +| 7:5 | RSVD | RO | 0 | Reserved for future use | +| 4 | CFG_VPN_SLV | RW | 0x1 | Video Panel Interface in slave mode
1: Video Panel works in slave mode. It receives VSYNC from input LCD interface, and is used to control the internal timing.
0: Video Panel interface works in master mode. DSI sends VSYNC to LCD module, and controls the V timing and H timing.
**Note. This bit must set to 1, VPN only supports slave mode.** | +| 3 | RSVD | RO | 0 | Reserved for future use | +| 2 | CFG_CPN_EN | RW | 0x0 | Command Panel Interface Enable
1: Command panel is running and can accept data from the Command Panel interface
0: Disable Command Panel interface | +| 1 | RSVD | RO | 0 | Reserved for future use | +| 0 | CFG_VPN_EN | RW | 0x0 | Video Panel Interface Enable
1: Video Panel is active and running.
0: Video Panel interface is disabled.
**Note. Set this field to 1 to start the Video Panel timing.** | #### DSI_CTRL_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31:9RSVDRO0Reserved for future use
8CFG_EOTP_ENRW0x0EOTP Enable
1: Enable EOTP packet
0: Disable EOTP packet
7:6CFG_CPN_VCH_NORW0x3Command Panel Virtual Channel Number
5:2RSVDRO0Reserved for future use
1:0CFG_VPN_VCH_NORW0x0Video Panel Virtual Channel Number for Active Panel 1
This parameter defines the virtual channel number for VPN
+**Offset: 0x4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:9 | RSVD | RO | 0 | Reserved for future use | +| 8 | CFG_EOTP_EN | RW | 0x0 | EOTP Enable
1: Enable EOTP packet
0: Disable EOTP packet | +| 7:6 | CFG_CPN_VCH_NO | RW | 0x3 | Command Panel Virtual Channel Number | +| 5:2 | RSVD | RO | 0 | Reserved for future use | +| 1:0 | CFG_VPN_VCH_NO | RW | 0x0 | Video Panel Virtual Channel Number for Active Panel 1
This parameter defines the virtual channel number for VPN | #### DSI_IRQ_ST1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8
BitsFieldTypeResetDescription
31:4RSVDRO0Reserved for future use
3IRQ_DPHY_ERR_HS_RXPRO0x0DPHY HSTX contention RXP Error
2IRQ_DPHY_ERR_HS_RXNRO0x0DPHY HSTX contention RXN Error
1IRQ_DPHY_ERR_HS_CONTPRO0x0DPHY HSTX contention contp Error
0IRQ_DPHY_ERR_HS_CONTNRO0x0DPHY HSTX contention contn Error
+**Offset: 0x8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | RSVD | RO | 0 | Reserved for future use | +| 3 | IRQ_DPHY_ERR_HS_RXP | RO | 0x0 | DPHY HSTX contention RXP Error | +| 2 | IRQ_DPHY_ERR_HS_RXN | RO | 0x0 | DPHY HSTX contention RXN Error | +| 1 | IRQ_DPHY_ERR_HS_CONTP | RO | 0x0 | DPHY HSTX contention contp Error | +| 0 | IRQ_DPHY_ERR_HS_CONTN | RO | 0x0 | DPHY HSTX contention contn Error | #### DSI_IRQ_MASK1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xc
BitsFieldTypeResetDescription
31:4RSVDRO0Reserved for future use
3:0CFG_IRQ_MASK1RW0x0DSI interrupt mask
This field is used to mask interrupt requests.
If one bit is set to 0x1, the corresponding interrupt status is masked.
+**Offset: 0xc** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | RSVD | RO | 0 | Reserved for future use | +| 3:0 | CFG_IRQ_MASK1 | RW | 0x0 | DSI interrupt mask
This field is used to mask interrupt requests.
If one bit is set to 0x1, the corresponding interrupt status is masked. | #### DSI_IRQ_ST REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x10
BitsFieldTypeResetDescription
31IRQ_LAST_LINERO0x0Last Line interrupt
30IRQ_CPN_TERO0x0Command Panel Tearing Effect.
29IRQ_TA_TIMEOUTRO0x0Turnaround Acknowledgement Timeout for DPHY
28IRQ_RX_TIMEOUTRO0x0LP-RX Timeout for DPHY
27IRQ_TX_TIMEOUTRO0x0HS TX Timeout for DPHY
26IRQ_RX_STATE_ERRRO0x0Peripheral Status Error
After DSI receives an acknowledgement with error report packet from slave, it will mark this bit if an error status is reported.
25IRQ_RX_ERRRO0x0DSI RX Packet Error
DSI receives a packet (with error status, such as ecc error/crc error/unknown packet) from slave
24IRQ_RX_FIFO_FULL_ERRRO0x0RX FIFO Full Error
23IRQ_PHY_FIFO_UNDERRUNRO0x0PHY FIFO Underrun Error
22IRQ_REQ_CNT_ERRRO0x0TX Request Count Error
This error occurs when the delays between an Active Panel TX request and the DPHY ready signal are inconsistent.
21IRQ_RXPSR_FIFO_FULL_ERRRO0x0RX Parser FIFO Full Error
20IRQ_VPN_REQ_PHY_DLY_ERRRO0x0VPN Request Delay Error at PHY Interface
VPN packets are delayed at the PHY interface.
19IRQ_VPN_BF_UNDERRUN_ERRRO0x0VPN Buffer Underrun Error
18IRQ_VPN_REQ_ARB_DLY_ERRRO0x0VPN Request Delay Error at Arbiter Interface
VPN packets are delayed at arbiter point.
17IRQ_VPN_BF_OVERRUN_ERRRO0x0VPN Buffer Overrun Error
16IRQ_VPN_TIMING_ERRRO0x0VPN Data Timing Error
This error indicates that pixel data might be incorrect. It occurs when the Data FIFO for the VPN path is read too early or too late, leading to an empty FIFO when it is accessed.
15IRQ_VPN_VACT_DONERO0x0VPN VACT Done
14IRQ_VPN_BF_FULLRO0x0VPN Buffer Full Error
Pixel data may be incorrect.
13IRQ_CPN_BF_FULLRO0x0CPN Buffer Full Error
Pixel data may be incorrect.
12IRQ_DPHY_ERR_CONT_LP1RO0x0DPHY LP1 Contention Detect PPI ErrContertionLP1
11IRQ_DPHY_ERR_CONT_LP0RO0x0DPHY LP0 Contention Detect PPI ErrContertionLP0
10IRQ_DPHY_ERR_SYNC_ESCRO0x0DPHY Sync Error PPI ErrSyncEsc
Partial byte is detected
9IRQ_DPHY_ERR_ESCRO0x0DPHY Invalid Command Detect PPI ErrEsc
Invalid ESC command is detected
8IRQ_DPHY_RX_LINE_ERRRO0x0DPHY Invalid Line State Detect PPI ErrControl
7IRQ_RX_TRG3RO0x0DPHY RX Trigger 3 Received
By default, the value of trigger 3 is 0x05,
Note: Its exact meaning is not defined by specification.
6IRQ_RX_TRG2RO0x0DPHY RX Trigger 2 Received
By default, trigger 2 is for acknowledgement Trigger, and its value is 0x84.
5IRQ_RX_TRG1RO0x0DPHY RX Trigger 1 Received
By default, trigger 1 is for TE Trigger, and its value is 0xBA.
4IRQ_RX_TRG0RO0x0DPHY RX Trigger 0 Received
By default, trigger 0 is for Reset Trigger, and its value is 0x46.
3IRQ_RX_ULPSRO0x0DPHY RX ULPS Received
2IRQ_RX_PKTRO0x0DPHY RX Packet Received
1IRQ_CPN_TX_DONERO0x0Command Panel Data Transmission Done
0IRQ_CPU_TX_DONERO0x0CPU Packet Transmission Done
+**Offset: 0x10** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | IRQ_LAST_LINE | RO | 0x0 | Last Line interrupt | +| 30 | IRQ_CPN_TE | RO | 0x0 | Command Panel Tearing Effect. | +| 29 | IRQ_TA_TIMEOUT | RO | 0x0 | Turnaround Acknowledgement Timeout for DPHY | +| 28 | IRQ_RX_TIMEOUT | RO | 0x0 | LP-RX Timeout for DPHY | +| 27 | IRQ_TX_TIMEOUT | RO | 0x0 | HS TX Timeout for DPHY | +| 26 | IRQ_RX_STATE_ERR | RO | 0x0 | Peripheral Status Error
After DSI receives an acknowledgement with error report packet from slave, it will mark this bit if an error status is reported. | +| 25 | IRQ_RX_ERR | RO | 0x0 | DSI RX Packet Error
DSI receives a packet (with error status, such as ecc error/crc error/unknown packet) from slave | +| 24 | IRQ_RX_FIFO_FULL_ERR | RO | 0x0 | RX FIFO Full Error | +| 23 | IRQ_PHY_FIFO_UNDERRUN | RO | 0x0 | PHY FIFO Underrun Error | +| 22 | IRQ_REQ_CNT_ERR | RO | 0x0 | TX Request Count Error
This error occurs when the delays between an Active Panel TX request and the DPHY ready signal are inconsistent. | +| 21 | IRQ_RXPSR_FIFO_FULL_ERR | RO | 0x0 | RX Parser FIFO Full Error | +| 20 | IRQ_VPN_REQ_PHY_DLY_ERR | RO | 0x0 | VPN Request Delay Error at PHY Interface
VPN packets are delayed at the PHY interface. | +| 19 | IRQ_VPN_BF_UNDERRUN_ERR | RO | 0x0 | VPN Buffer Underrun Error | +| 18 | IRQ_VPN_REQ_ARB_DLY_ERR | RO | 0x0 | VPN Request Delay Error at Arbiter Interface
VPN packets are delayed at arbiter point. | +| 17 | IRQ_VPN_BF_OVERRUN_ERR | RO | 0x0 | VPN Buffer Overrun Error | +| 16 | IRQ_VPN_TIMING_ERR | RO | 0x0 | VPN Data Timing Error
This error indicates that pixel data might be incorrect. It occurs when the Data FIFO for the VPN path is read too early or too late, leading to an empty FIFO when it is accessed. | +| 15 | IRQ_VPN_VACT_DONE | RO | 0x0 | VPN VACT Done | +| 14 | IRQ_VPN_BF_FULL | RO | 0x0 | VPN Buffer Full Error
Pixel data may be incorrect. | +| 13 | IRQ_CPN_BF_FULL | RO | 0x0 | CPN Buffer Full Error
Pixel data may be incorrect. | +| 12 | IRQ_DPHY_ERR_CONT_LP1 | RO | 0x0 | DPHY LP1 Contention Detect PPI ErrContertionLP1 | +| 11 | IRQ_DPHY_ERR_CONT_LP0 | RO | 0x0 | DPHY LP0 Contention Detect PPI ErrContertionLP0 | +| 10 | IRQ_DPHY_ERR_SYNC_ESC | RO | 0x0 | DPHY Sync Error PPI ErrSyncEsc
Partial byte is detected | +| 9 | IRQ_DPHY_ERR_ESC | RO | 0x0 | DPHY Invalid Command Detect PPI ErrEsc
Invalid ESC command is detected | +| 8 | IRQ_DPHY_RX_LINE_ERR | RO | 0x0 | DPHY Invalid Line State Detect PPI ErrControl | +| 7 | IRQ_RX_TRG3 | RO | 0x0 | DPHY RX Trigger 3 Received
By default, the value of trigger 3 is 0x05,
Note: Its exact meaning is not defined by specification. | +| 6 | IRQ_RX_TRG2 | RO | 0x0 | DPHY RX Trigger 2 Received
By default, trigger 2 is for acknowledgement Trigger, and its value is 0x84. | +| 5 | IRQ_RX_TRG1 | RO | 0x0 | DPHY RX Trigger 1 Received
By default, trigger 1 is for TE Trigger, and its value is 0xBA. | +| 4 | IRQ_RX_TRG0 | RO | 0x0 | DPHY RX Trigger 0 Received
By default, trigger 0 is for Reset Trigger, and its value is 0x46. | +| 3 | IRQ_RX_ULPS | RO | 0x0 | DPHY RX ULPS Received | +| 2 | IRQ_RX_PKT | RO | 0x0 | DPHY RX Packet Received | +| 1 | IRQ_CPN_TX_DONE | RO | 0x0 | Command Panel Data Transmission Done | +| 0 | IRQ_CPU_TX_DONE | RO | 0x0 | CPU Packet Transmission Done | #### DSI_IRQ_MASK REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14
BitsFieldTypeResetDescription
31:0CFG_IRQ_MASKRW0x0DSI interrupt mask
This field is used to mask interrupt requests.
If one bit is set to 0x1, the corresponding interrupt status is masked.
+**Offset: 0x14** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFG_IRQ_MASK | RW | 0x0 | DSI interrupt mask
This field is used to mask interrupt requests.
If one bit is set to 0x1, the corresponding interrupt status is masked. | #### DSI_CPU_CMD_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x20
BitsFieldTypeResetDescription
31CFG_CPU_CMD_REQRW0x0CPU Command Request
1: CPU packet request
0: No request or request done
After software writes a command with this bit set to 1, the DSI module sends out a packet as requested. DSI de-asserts this field after packet is sent.
30CFG_CPU_SPRW0x0CPU Short Packet
1: CPU packet is a short packet
0: CPU packet is a long packet
29CFG_CPU_TURNRW0x0CPU Turn Around
1: After CPU packet, turn around the bus
0: Don't turn around bus after CPU packet
28RSVDRO0Reserved for future use
27CFG_CPU_TXLPRW0x0Low Power TX for CPU Packets
1 = Transfer CPU packets in low power mode
0 = Use high-speed mode to send CPU packets
26:16RSVDRO0Reserved for future use
15:0CFG_CPU_WCRW0x0CPU Packet Byte Count
For high-speed transfer, this represents the payload byte count for long packets (excluding CRC bytes).
For high-speed short packet transfer, this field is ignored.
For low power transfer, this is the byte count for the entire packet, including CRC bytes, and CFG_CPU_SP is ignored.
+**Offset: 0x20** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | CFG_CPU_CMD_REQ | RW | 0x0 | CPU Command Request
1: CPU packet request
0: No request or request done
After software writes a command with this bit set to 1, the DSI module sends out a packet as requested. DSI de-asserts this field after packet is sent. | +| 30 | CFG_CPU_SP | RW | 0x0 | CPU Short Packet
1: CPU packet is a short packet
0: CPU packet is a long packet | +| 29 | CFG_CPU_TURN | RW | 0x0 | CPU Turn Around
1: After CPU packet, turn around the bus
0: Don't turn around bus after CPU packet | +| 28 | RSVD | RO | 0 | Reserved for future use | +| 27 | CFG_CPU_TXLP | RW | 0x0 | Low Power TX for CPU Packets
1 = Transfer CPU packets in low power mode
0 = Use high-speed mode to send CPU packets | +| 26:16 | RSVD | RO | 0 | Reserved for future use | +| 15:0 | CFG_CPU_WC | RW | 0x0 | CPU Packet Byte Count
For high-speed transfer, this represents the payload byte count for long packets (excluding CRC bytes).
For high-speed short packet transfer, this field is ignored.
For low power transfer, this is the byte count for the entire packet, including CRC bytes, and CFG_CPU_SP is ignored. | #### DSI_CPU_CMD_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x24
BitsFieldTypeResetDescription
31:24RSVDRO0Reserved for future use
23:20CFG_TXLP_LPDTRW0x0LPDT TX Enable
LPDT TX enables signals for low power TX
19:16CFG_TXLP_ULPSRW0x0ULPS TX Enable
ULPS TX enables signals for Low power TX
15:0CFG_TXLP_TRIGGER_CODERW0x0Low Power TX Trigger Code
+**Offset: 0x24** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | RSVD | RO | 0 | Reserved for future use | +| 23:20 | CFG_TXLP_LPDT | RW | 0x0 | LPDT TX Enable
LPDT TX enables signals for low power TX | +| 19:16 | CFG_TXLP_ULPS | RW | 0x0 | ULPS TX Enable
ULPS TX enables signals for Low power TX | +| 15:0 | CFG_TXLP_TRIGGER_CODE | RW | 0x0 | Low Power TX Trigger Code | #### DSI_CPU_CMD_3 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x2c
BitsFieldTypeResetDescription
31CFG_CPU_DAT_REQRW0x0CPU Packet Data Buffer Read/Write Request
1: CPU packet data request
0: No request or request done
After software writes a command with this bit set to 1, the DSI module will write data to the packet data buffer or read data from the data buffer as requested. DSI will de-assert this bit after write/read operation is done. Read data will be valid after this bit is reset to 0.
30CFG_CPU_DAT_RWRW0x0CPU Packet Data Buffer Read/Write Operation
1: CPU packet data write operation
0: CPU packet data read operation
29:24RSVDRO0Reserved for future use
23:16CFG_CPU_DAT_ADDRRW0x0CPU Packet Data Address
This is the byte address for the packet data.
- For each read/write operation, 4 bytes of data are written or read. Software should increment the address by 4 after each operation.
- The packet data starts with the packet header:
1. At address 0:
- Bits [7:0] represent Type_id
- Bits [23:8] represent Length
- Bits [31:24] represent ECC
2. At address 4: Payload data if it's a long packet, and so on.
- The maximum packet data buffer is 256 bytes.
15:0RSVDRO0Reserved for future use
+**Offset: 0x2c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | CFG_CPU_DAT_REQ | RW | 0x0 | CPU Packet Data Buffer Read/Write Request
1: CPU packet data request
0: No request or request done
After software writes a command with this bit set to 1, the DSI module will write data to the packet data buffer or read data from the data buffer as requested. DSI will de-assert this bit after write/read operation is done. Read data will be valid after this bit is reset to 0. | +| 30 | CFG_CPU_DAT_RW | RW | 0x0 | CPU Packet Data Buffer Read/Write Operation
1: CPU packet data write operation
0: CPU packet data read operation | +| 29:24 | RSVD | RO | 0 | Reserved for future use | +| 23:16 | CFG_CPU_DAT_ADDR | RW | 0x0 | CPU Packet Data Address
This is the byte address for the packet data.
- For each read/write operation, 4 bytes of data are written or read. Software should increment the address by 4 after each operation.
- The packet data starts with the packet header:
1. At address 0:
- Bits [7:0] represent Type_id
- Bits [23:8] represent Length
- Bits [31:24] represent ECC
2. At address 4: Payload data if it's a long packet, and so on.
- The maximum packet data buffer is 256 bytes. | +| 15:0 | RSVD | RO | 0 | Reserved for future use | #### DSI_CPU_WDAT REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x30
BitsFieldTypeResetDescription
31:0CFG_CPU_WDATRW0x0CPU Data Write Register (wdata 0)
This register defines the data for CPU packets. It holds the CPU packet data that will be written to the packet data buffer.
- Software should first program the packet data into this register, then configure the DSI CPU Packet Command Register 3 to load the packet data into the Tx packet data buffer.
- For each read/write operation, 4 bytes of data are written or read.
1. Bits [7:0]: LSB
2. Bits [31:24]: MSB
- For packet data at address 0:
1. Bits [7:0]: Type_id
2. Bits [23:8]: Length
3. Bits [31:24]: ECC
- For data at address 4: The payload data if it's a long packet, and so on.
- High-speed transmission: Hardware automatically generates ECC and CRC codes, replacing them in the packet data buffer.
- Low-power transmission: Hardware does not insert ECC/CRC, and instead sends out the ECC/CRC from the packet data buffer
+**Offset: 0x30** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFG_CPU_WDAT | RW | 0x0 | CPU Data Write Register (wdata 0)
This register defines the data for CPU packets. It holds the CPU packet data that will be written to the packet data buffer.
- Software should first program the packet data into this register, then configure the DSI CPU Packet Command Register 3 to load the packet data into the Tx packet data buffer.
- For each read/write operation, 4 bytes of data are written or read.
1. Bits [7:0]: LSB
2. Bits [31:24]: MSB
- For packet data at address 0:
1. Bits [7:0]: Type_id
2. Bits [23:8]: Length
3. Bits [31:24]: ECC
- For data at address 4: The payload data if it's a long packet, and so on.
- High-speed transmission: Hardware automatically generates ECC and CRC codes, replacing them in the packet data buffer.
- Low-power transmission: Hardware does not insert ECC/CRC, and instead sends out the ECC/CRC from the packet data buffer | #### DSI_CPU_STATUS_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x34
BitsFieldTypeResetDescription
31:16RSVDRO0Reserved for future use
15:0CFG_CPU_PKT_CNTRW0x0CPU Packet Counter
This counter counts the number of CPU packets sent out through DSI.
This register is write clear.
- -####DSI_CPU_STATUS_1 REGISTER - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x38
BitsFieldTypeResetDescription
31:0CFG_CPU_CMD_TX_CNTRO0x0CPU CMD TX Counter
This counter counts the number of byte clock cycles required to transfer the current CPU command.
It begins to count after CPU command is received, and stops to counter after DPHY gets ready for another TX request.
This counter could help to decide the values of DSI_VPN_SLOT_CNT_0 and DSI_VPN_SLOT_CNT_1 register.
- -#### DSI_CPU_STATUS_2 REGIST - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x3c
BitsFieldTypeResetDescription
31:0CFG_CPU_CMD_CNTRW0x0CPU CMD Execution Counter
This counter counts the number of byte clock cycles required to execute the current CPU command.
This counter only counts the cycles which CPU engine is busy.
This counter could help to decide the values of DSI_VPN_SLOT_CNT_0 and DSI_VPN_SLOT_CNT_1 register.
+**Offset: 0x34** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RSVD | RO | 0 | Reserved for future use | +| 15:0 | CFG_CPU_PKT_CNT | RW | 0x0 | CPU Packet Counter
This counter counts the number of CPU packets sent out through DSI.
This register is write clear. | + +#### DSI_CPU_STATUS_1 REGISTER + +**Offset: 0x38** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFG_CPU_CMD_TX_CNT | RO | 0x0 | CPU CMD TX Counter
This counter counts the number of byte clock cycles required to transfer the current CPU command.
It begins to count after CPU command is received, and stops to count after DPHY gets ready for another TX request.
This counter could help to decide the values of DSI_VPN_SLOT_CNT_0 and DSI_VPN_SLOT_CNT_1 register. | + +#### DSI_CPU_STATUS_2 REGISTER + +**Offset: 0x3c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFG_CPU_CMD_CNT | RW | 0x0 | CPU CMD Execution Counter
This counter counts the number of byte clock cycles required to execute the current CPU command.
This counter only counts the cycles which CPU engine is busy.
This counter could help to decide the values of DSI_VPN_SLOT_CNT_0 and DSI_VPN_SLOT_CNT_1 register. | #### DSI_CPU_STATUS_3 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x40
BitsFieldTypeResetDescription
31:0
CFG_TXLP_CNTRO0x0Low Power TX byte clock count
This counter counts the number of byte clock cycles required to transfer a low power packet.
+**Offset: 0x40** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFG_TXLP_CNT | RO | 0x0 | Low Power TX byte clock count
This counter counts the number of byte clock cycles required to transfer a low power packet. | #### DSI_CPU_STATUS_4 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x44
BitsFieldTypeResetDescription
31:0CFG_BTA_CNTRO0x0Bus Turn Around byte clock count
This counter counts the number of byte clock cycles required to complete a bus turn around operation.
+**Offset: 0x44** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFG_BTA_CNT | RO | 0x0 | Bus Turn Around byte clock count
This counter counts the number of byte clock cycles required to complete a bus turn around operation. | #### DSI_CPN_STATUS_1 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4c
BitsFieldTypeResetDescription
31:0
CFG_CPN_STATUS_1RW0x0Command Panel Path Status 1
It includes the following fields:
- smt_bf_cnt[5:0]
- smt_fifo_bcnt[9:0]
- smt_cs[4:0]
- smt_wr_on
- smt_dma_on
- smt_fifo_empty
- smt_bf_empty
- smt_fifo_full_r
- smt_bf_full_r
+**Offset: 0x4c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFG_CPN_STATUS_1 | RW | 0x0 | Command Panel Path Status 1
It includes the following fields:
- smt_bf_cnt[5:0]
- smt_fifo_bcnt[9:0]
- smt_cs[4:0]
- smt_wr_on
- smt_dma_on
- smt_fifo_empty
- smt_bf_empty
- smt_fifo_full_r
- smt_bf_full_r | #### DSI_CPN_CMD REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x50
BitsFieldTypeResetDescription
31:28CFG_CPN_TE_ENRW0x0Command Panel Tearing Effect Signal Enable
27RSVDRO0Reserved for future use
26:24CFG_CPN_RGB_TYPERW0x0Command Panel Data RGB Type
0x0: 888 mode
0x1: 666 unpacked mode
0x2: 565 mode
0x3: 444 mode
0x4: 332 mode
0x5: 111 mode
23:4RSVDRO0Reserved for future use
3CFG_CPN_BURST_MODERW0x1Command Panel Interface Burst Mode Enable
0: Enable Previous Command Pandel interface.
1: Burst mode interface between LCD and DSI will take effect.
This interface provides a more efficient connection than the previous mode
2CFG_CPN_FIRSTP_SELRW0x0Command panel First packet select
0: FIFO empty
1: vsync from DP650
1CFG_CPN_DMA_DISRW0x0Command Panel dma_on Disable
1: Disable smt_dma_on signal from LCD controller. DSI will not receive Command Panel interface data from LCD even smt_dma_on signal is active high.
0 = Receive LCD Command Panel interface data when smt_dma_on is high.
0CFG_CPN_ADDR0_ENRW0x0Command Panel Address Bit Indicator
0 : When smt_addr = 1, bus data is for pixel RGB data.
When smt_addr = 0, bus data is ignored.
1 : When smt_addr = 0, bus data is for pixel RGB data.
When smt_addr = 1, bus data is ignored.
+**Offset: 0x50** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | CFG_CPN_TE_EN | RW | 0x0 | Command Panel Tearing Effect Signal Enable | +| 27 | RSVD | RO | 0 | Reserved for future use | +| 26:24 | CFG_CPN_RGB_TYPE | RW | 0x0 | Command Panel Data RGB Type
0x0: 888 mode
0x1: 666 unpacked mode
0x2: 565 mode
0x3: 444 mode
0x4: 332 mode
0x5: 111 mode | +| 23:4 | RSVD | RO | 0 | Reserved for future use | +| 3 | CFG_CPN_BURST_MODE | RW | 0x1 | Command Panel Interface Burst Mode Enable
0: Enable Previous Command Pandel interface.
1: Burst mode interface between LCD and DSI will take effect.
This interface provides a more efficient connection than the previous mode | +| 2 | CFG_CPN_FIRSTP_SEL | RW | 0x0 | Command panel First packet select
0: FIFO empty
1: vsync from DP650 | +| 1 | CFG_CPN_DMA_DIS | RW | 0x0 | Command Panel dma_on Disable
1: Disable smt_dma_on signal from LCD controller. DSI will not receive Command Panel interface data from LCD even smt_dma_on signal is active high.
0 = Receive LCD Command Panel interface data when smt_dma_on is high. | +| 0 | CFG_CPN_ADDR0_EN | RW | 0x0 | Command Panel Address Bit Indicator
0: When smt_addr = 1, bus data is for pixel RGB data.
When smt_addr = 0, bus data is ignored.
1: When smt_addr = 0, bus data is for pixel RGB data.
When smt_addr = 1, bus data is ignored. | #### DSI_CPN_CTRL_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x54
BitsFieldTypeResetDescription
31:22RSVDRO0Reserved for future use
21:16CFG_DCS_LONGWR_CODERW0x39DSI Command Code for Writing Command Panel Data
The default data is 0x39 from DSI specification.
15:8CFG_DCS_WR_CON_CODERW0x3CDCS Command for Continuous Write
The default value is 0x3C in MIPI Alliance Standard for Display Command Set Specification.
7:0CFG_DCS_WR_STR_CODERW0x2CDCS Command for First Write
The default value is 0x2C in the MIPI Alliance Standard for Display Command Set Specification.
+**Offset: 0x54** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:22 | RSVD | RO | 0 | Reserved for future use | +| 21:16 | CFG_DCS_LONGWR_CODE | RW | 0x39 | DSI Command Code for Writing Command Panel Data
The default data is 0x39 from DSI specification. | +| 15:8 | CFG_DCS_WR_CON_CODE | RW | 0x3C | DCS Command for Continuous Write
The default value is 0x3C in MIPI Alliance Standard for Display Command Set Specification. | +| 7:0 | CFG_DCS_WR_STR_CODE | RW | 0x2C | DCS Command for First Write
The default value is 0x2C in the MIPI Alliance Standard for Display Command Set Specification. | #### DSI_CPN_CTRL_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x58
BitsFieldTypeResetDescription
31:26RSVDRO0Reserved for future use
25:16CFG_CPN_PKT_CNTRW0x100Command Panel Packet Length
This field defines the packet length for Command Panel packets.
15:10RSVDRO0Reserved for future use
9:0CFG_CPN_FIFO_FULL_LEVELRW0x200 Command Panel FIFO Full Level, in byte count
+**Offset: 0x58** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:26 | RSVD | RO | 0 | Reserved for future use | +| 25:16 | CFG_CPN_PKT_CNT | RW | 0x100 | Command Panel Packet Length
This field defines the packet length for Command Panel packets. | +| 15:10 | RSVD | RO | 0 | Reserved for future use | +| 9:0 | CFG_CPN_FIFO_FULL_LEVEL | RW | 0x200 | Command Panel FIFO Full Level, in byte count | #### DSI_CPN_STATUS_0 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x5c
BitsFieldTypeResetDescription
31:0CFG_CPN_FRM_CNTRW0x0Command Panel Frame Counter
This counter counts the numbers of Command Panel frames sent through DSI.
This register is write clear.
+**Offset: 0x5c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFG_CPN_FRM_CNT | RW | 0x0 | Command Panel Frame Counter
This counter counts the numbers of Command Panel frames sent through DSI.
This register is write clear. | #### DSI_RX_PKT_ST_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x60
BitsFieldTypeResetDescription
31RX_PKT0_ST_VLDRWC0x0Rx Packet 0 Status Valid
1: Valid status
0: Invalid status
30:27RSVDRO0Reserved for future use
26RX_PKT0_ST_EOTPRWC0x0Rx Packet 0 is EOTP
1: Received packet is EOTP packet
0: Other packet. It is valid only when RX_PKT0_ST_VLD = 1.
25RX_PKT0_ST_ACKRWC0x0Rx Packet 0 is ACK Packet
1: Received packet is an ACK packet, with or without errors.
0 :Other packet. It is valid only when RX_PKT0_ST_VLD = 1.
24RX_PKT0_ST_SPRWC0x0Rx Packet 0 Short Packet
1: Received packet is a short packet.
0: Long packet, it is valid only when RX_PKT0_ST_VLD = 1.
23:22RSVDRO0Reserved for future use
21:16RX_PKT0_PKT_PTRRWC0x0Rx Packet 0 Data Pointer
Packet header in FIFO is the raw data from DPHY and is before ECC correction.
It is valid only when RX_PKT0_ST_VLD = 1.
15:14RX_PKT0_VCHRWC0x0Rx Packet 0 Virtual Channel Number
It is valid only when RX_PKT0_ST_VLD = 1.
13:12RSVDRO0Reserved for future use
11:8RX_PKT0_ECC_FLAGSRWC0x0Rx Packet 0 ECC Error Flags
Bit [11]:
1: No ECC error
0: ECC error
Bit [10]:
1: Correctable error in data bits.
Bit [9]:
1: Correctable error happens at parity bits.
Bit [8]:
1: Incorrectable error
It is valid only when RX_PKT0_ST_VLD = 1.
7:5RSVDRO0Reserved for future use
4RX_PKT0_NO_CRCRWC0x0Rx Packet 0 Without CRC
Rx packet does not include CRC, and CRC part contains 0x0000.
It is valid only when RX_PKT0_ST_VLD = 1.
3RX_PKT0_UNKNOWN_ERRRWC0x0Rx Packet 0 Type Unknown Error
It is valid only when RX_PKT0_ST_VLD = 1.
2RX_PKT0_ST_ERRRWC0x0Rx Packet 0 ack Status Error
Indicates an error in the acknowledge packet status.
The DSI_RX_PKT_HDR_0 should be checked to identify the specific error.
It is valid only when RX_PKT0_ST_VLD = 1.
1RX_PKT0_ECC_ERRRWC0x0Rx Packet 0 ECC Error
It is valid only when RX_PKT0_ST_VLD = 1.
0RX_PKT0_CRC_ERRRWC0x0Rx Packet CRC Error
It is valid only when RX_PKT0_ST_VLD = 1.
+**Offset: 0x60** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | RX_PKT0_ST_VLD | RWC | 0x0 | Rx Packet 0 Status Valid
1: Valid status
0: Invalid status | +| 30:27 | RSVD | RO | 0 | Reserved for future use | +| 26 | RX_PKT0_ST_EOTP | RWC | 0x0 | Rx Packet 0 is EOTP
1: Received packet is EOTP packet
0: Other packet. It is valid only when RX_PKT0_ST_VLD = 1. | +| 25 | RX_PKT0_ST_ACK | RWC | 0x0 | Rx Packet 0 is ACK Packet
1: Received packet is an ACK packet, with or without errors.
0: Other packet. It is valid only when RX_PKT0_ST_VLD = 1. | +| 24 | RX_PKT0_ST_SP | RWC | 0x0 | Rx Packet 0 Short Packet
1: Received packet is a short packet.
0: Long packet, it is valid only when RX_PKT0_ST_VLD = 1. | +| 23:22 | RSVD | RO | 0 | Reserved for future use | +| 21:16 | RX_PKT0_PKT_PTR | RWC | 0x0 | Rx Packet 0 Data Pointer
Packet header in FIFO is the raw data from DPHY and is before ECC correction.
It is valid only when RX_PKT0_ST_VLD = 1. | +| 15:14 | RX_PKT0_VCH | RWC | 0x0 | Rx Packet 0 Virtual Channel Number
It is valid only when RX_PKT0_ST_VLD = 1. | +| 13:12 | RSVD | RO | 0 | Reserved for future use | +| 11:8 | RX_PKT0_ECC_FLAGS | RWC | 0x0 | Rx Packet 0 ECC Error Flags
Bit [11]:
1: No ECC error
0: ECC error
Bit [10]:
1: Correctable error in data bits.
Bit [9]:
1: Correctable error happens at parity bits.
Bit [8]:
1: Incorrectable error
It is valid only when RX_PKT0_ST_VLD = 1. | +| 7:5 | RSVD | RO | 0 | Reserved for future use | +| 4 | RX_PKT0_NO_CRC | RWC | 0x0 | Rx Packet 0 Without CRC
Rx packet does not include CRC, and CRC part contains 0x0000.
It is valid only when RX_PKT0_ST_VLD = 1. | +| 3 | RX_PKT0_UNKNOWN_ERR | RWC | 0x0 | Rx Packet 0 Type Unknown Error
It is valid only when RX_PKT0_ST_VLD = 1. | +| 2 | RX_PKT0_ST_ERR | RWC | 0x0 | Rx Packet 0 ack Status Error
Indicates an error in the acknowledge packet status.
The DSI_RX_PKT_HDR_0 should be checked to identify the specific error.
It is valid only when RX_PKT0_ST_VLD = 1. | +| 1 | RX_PKT0_ECC_ERR | RWC | 0x0 | Rx Packet 0 ECC Error
It is valid only when RX_PKT0_ST_VLD = 1. | +| 0 | RX_PKT0_CRC_ERR | RWC | 0x0 | Rx Packet CRC Error
It is valid only when RX_PKT0_ST_VLD = 1. | #### DSI_RX_PKT_HDR_0 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x64
BitsFieldTypeResetDescription
31:0RX_PKT0_HDRRW0x0Rx Packet 0 Header
Bits [7:0]: DataID
Bits [23:8]: Length
Bits [31:23]: ECC--Corrected if an error is detected
+**Offset: 0x64** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RX_PKT0_HDR | RW | 0x0 | Rx Packet 0 Header
Bits [7:0]: DataID
Bits [23:8]: Length
Bits [31:23]: ECC--Corrected if an error is detected | #### DSI_RX_PKT_ST_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x68
BitsFieldTypeResetDescription
31
RX_PKT1_ST_VLDRWC0x0Rx Packet 1 Status Valid
1: Valid status
0: Invalid status
30:27RSVDRO0Reserved for future use
26RX_PKT1_ST_EOTPRWC0x0Rx Packet 1 is EOTP
1: Received packet is EOTP packet.
0: Other packet. It is valid only when RX_PKT0_ST_VLD = 1.
25RX_PKT1_ST_ACKRWC0x0Rx Packet 1 is ACK Packet
1 = Received packet is an ACK packet, with or without error.
0 = Other packet. It is valid only when RX_PKT0_ST_VLD = 1.
24RX_PKT1_ST_SPRWC0x0Rx Packet 1 Short Packet
1: Received packet is a short packet.
0: Long packet valid only when RX_PKT0_ST_VLD = 1.
23:22RSVDRO0Reserved for future use
21:16RX_PKT1_PKT_PTRRWC0x0Rx Packet 1 Data Pointer
Packet header in FIFO is the raw data from DPHY before ECC correction.
Valid only when RX_PKT0_ST_VLD = 1.
15:14RX_PKT1_VCHRWC0x0Rx Packet 1 Virtual Channel Number
Valid only when RX_PKT0_ST_VLD = 1.
13:12RSVDRO0Reserved for future use
11:8RX_PKT1_ECC_FLAGSRWC0x0Rx Packet 1 ECC Error Flags
Bit [11]:
1: No ECC error
0: ECC error
Bit [10]:
1: Correctable error in data bits
Bit [9]:
1: Correctable error happens at parity bits
Bit [8]:
1: Incorrectable error. It is valid only when RX_PKT0_ST_VLD = 1.
7:5RSVDRO0Reserved for future use
4RX_PKT1_NO_CRCRWC0x0 Rx Packet 1 Without CRC
Rx packet does not include CRC, and CRC part contains 0x0000.
It is valid only when RX_PKT0_ST_VLD = 1.
3RX_PKT1_UNKNOWN_ERRRWC0x0Rx Packet Type Unknown Error
It is valid only when RX_PKT0_ST_VLD = 1.
2RX_PKT1_ST_ERRRWC0x0Rx Packet 1 ack Status Error
DSI_RX_PKT_HDR_0 should be checked to identify the specific error.
It is valid only when RX_PKT0_ST_VLD = 1.
1RX_PKT1_ECC_ERRRWC0x0Rx Packet 1 ECC Error
It is valid only when RX_PKT0_ST_VLD = 1.
0RX_PKT1_CRC_ERRRWC0x0Rx Packet 1 CRC Error
It is valid only when RX_PKT0_ST_VLD = 1.
+**Offset: 0x68** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | RX_PKT1_ST_VLD | RWC | 0x0 | Rx Packet 1 Status Valid
1: Valid status
0: Invalid status | +| 30:27 | RSVD | RO | 0 | Reserved for future use | +| 26 | RX_PKT1_ST_EOTP | RWC | 0x0 | Rx Packet 1 is EOTP
1: Received packet is EOTP packet.
0: Other packet. It is valid only when RX_PKT0_ST_VLD = 1. | +| 25 | RX_PKT1_ST_ACK | RWC | 0x0 | Rx Packet 1 is ACK Packet
1 = Received packet is an ACK packet, with or without error.
0 = Other packet. It is valid only when RX_PKT0_ST_VLD = 1. | +| 24 | RX_PKT1_ST_SP | RWC | 0x0 | Rx Packet 1 Short Packet
1: Received packet is a short packet.
0: Long packet valid only when RX_PKT0_ST_VLD = 1. | +| 23:22 | RSVD | RO | 0 | Reserved for future use | +| 21:16 | RX_PKT1_PKT_PTR | RWC | 0x0 | Rx Packet 1 Data Pointer
Packet header in FIFO is the raw data from DPHY before ECC correction.
Valid only when RX_PKT0_ST_VLD = 1. | +| 15:14 | RX_PKT1_VCH | RWC | 0x0 | Rx Packet 1 Virtual Channel Number
Valid only when RX_PKT0_ST_VLD = 1. | +| 13:12 | RSVD | RO | 0 | Reserved for future use | +| 11:8 | RX_PKT1_ECC_FLAGS | RWC | 0x0 | Rx Packet 1 ECC Error Flags
Bit [11]:
1: No ECC error
0: ECC error
Bit [10]:
1: Correctable error in data bits
Bit [9]:
1: Correctable error happens at parity bits
Bit [8]:
1: Incorrectable error. It is valid only when RX_PKT0_ST_VLD = 1. | +| 7:5 | RSVD | RO | 0 | Reserved for future use | +| 4 | RX_PKT1_NO_CRC | RWC | 0x0 | Rx Packet 1 Without CRC
Rx packet does not include CRC, and CRC part contains 0x0000.
It is valid only when RX_PKT0_ST_VLD = 1. | +| 3 | RX_PKT1_UNKNOWN_ERR | RWC | 0x0 | Rx Packet Type Unknown Error
It is valid only when RX_PKT0_ST_VLD = 1. | +| 2 | RX_PKT1_ST_ERR | RWC | 0x0 | Rx Packet 1 ack Status Error
DSI_RX_PKT_HDR_0 should be checked to identify the specific error.
It is valid only when RX_PKT0_ST_VLD = 1. | +| 1 | RX_PKT1_ECC_ERR | RWC | 0x0 | Rx Packet 1 ECC Error
It is valid only when RX_PKT0_ST_VLD = 1. | +| 0 | RX_PKT1_CRC_ERR | RWC | 0x0 | Rx Packet 1 CRC Error
It is valid only when RX_PKT0_ST_VLD = 1. | #### DSI_RX_PKT_HDR_1 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x6c
BitsFieldTypeResetDescription
31:0RX_PKT1_HDRRW0x0Rx Packet 1 Header
Bits [7:0]: DataID
Bits [23:8]: Length
Bits [31:23]: ECC--Corrected if an error is detected
+**Offset: 0x6c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RX_PKT1_HDR | RW | 0x0 | Rx Packet 1 Header
Bits [7:0]: DataID
Bits [23:8]: Length
Bits [31:23]: ECC--Corrected if an error is detected | #### DSI_RX_PKT_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x70
BitsFieldTypeResetDescription
31RX_PKT_RD_REQRW0x0Rx Packet FIFO Read Request
1 = Read request
0 = Invalid request
This bit will be cleared to 0 after read operation is done, and Rx data is valid.
30:22RSVDRO0Reserved for future use
21:16RX_PKT_RD_PTRRW0x0Rx Packet Data FIFO Read Pointer
For every read operation, the hardware returns data from the current pointer address. Software must increment this pointer for the next data after each byte is read.
15:8RSVDRO0Reserved for future use
7:0RX_PKT_RD_DATARW0x0Rx FIFO Read Data Valid when RX_PKT_RD_REQ = 0.
- First byte: DataID
- Second byte: wc0
- Third byte: wc1
- Fourth byte: raw ECC received from DPHY, not corrected
- Fifth byte and beyond: long packet data
+**Offset: 0x70** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | RX_PKT_RD_REQ | RW | 0x0 | Rx Packet FIFO Read Request
1 = Read request
0 = Invalid request
This bit will be cleared to 0 after read operation is done, and Rx data is valid. | +| 30:22 | RSVD | RO | 0 | Reserved for future use | +| 21:16 | RX_PKT_RD_PTR | RW | 0x0 | Rx Packet Data FIFO Read Pointer
For every read operation, the hardware returns data from the current pointer address. Software must increment this pointer for the next data after each byte is read. | +| 15:8 | RSVD | RO | 0 | Reserved for future use | +| 7:0 | RX_PKT_RD_DATA | RW | 0x0 | Rx FIFO Read Data Valid when RX_PKT_RD_REQ = 0.
- First byte: DataID
- Second byte: wc0
- Third byte: wc1
- Fourth byte: raw ECC received from DPHY, not corrected
- Fifth byte and beyond: long packet data | #### DSI_RX_PKT_CTRL_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x74
BitsFieldTypeResetDescription
31:12RSVDRO0Reserved for future use
11:8RX_PKT_CNTRWC0x0RX Packet Count in Rx FIFO All LP
RX packets are stored in the FIFO and start from address 0.
7:0RX_PKT_BCNTRWC0x0RX Byte Count in Rx FIFO
The whole LP RX data is stored in the FIFO and starts from address 0.
+**Offset: 0x74** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:12 | RSVD | RO | 0 | Reserved for future use | +| 11:8 | RX_PKT_CNT | RWC | 0x0 | RX Packet Count in Rx FIFO All LP
RX packets are stored in the FIFO and start from address 0. | +| 7:0 | RX_PKT_BCNT | RWC | 0x0 | RX Byte Count in Rx FIFO
The whole LP RX data is stored in the FIFO and starts from address 0. | #### DSI_RX_PKT_ST_2 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x78
BitsFieldTypeResetDescription
31RX_PKT2_ST_VLDRWC0x0Rx Packet 2 Status Valid
1: Valid status
0: Invalid status
30:27RSVDRO0Reserved for future use
26RX_PKT2_ST_EOTPRWC0x0Rx Packet 2 is EOTP
1: Received packet is EOTP packet
0: Other packet. It is valid only when RX_PKT0_ST_VLD = 1.
25RX_PKT2_ST_ACKRWC0x0Rx Packet 2 is an ACK Packet
1: Received packet is an ACK packet, with or without error
0: Other packet. It is valid only when RX_PKT0_ST_VLD = 1.
24RX_PKT2_ST_SPRWC0x0Rx Packet 2 Short Packet
1: Received packet is a short packet
0: Long packet Valid only when RX_PKT0_ST_VLD = 1
23:22RSVDRO0Reserved for future use
21:16RX_PKT2_PKT_PTRRWC0x0Rx Packet 2 Data Pointer
The packet header in FIFO is the raw data from DPHY before ECC correction.
Valid only when RX_PKT0_ST_VLD = 1.
15:14RX_PKT2_VCHRWC0x0Rx Packet 2 Virtual Channel Number
Valid only when RX_PKT0_ST_VLD = 1
13:12RSVDRO0Reserved for future use
11:8RX_PKT2_ECC_FLAGSRWC0x0Rx Packet 2 ECC Error Flags
bit [11]:
1: No ECC error
0: ECC error
Bit [10]:
1: Correctable error in data bits
Bit [9]:
1: Correctable error happens at parity bits
Bit [8]:
1: Incorrectable error. It is valid only when RX_PKT0_ST_VLD = 1.
7:5RSVDRO0Reserved for future use
4RX_PKT2_NO_CRCRWC0x0Rx Packet 2 Without CRC
Rx packet does not include CRC and CRC part contains 0x0000.
It is valid only when RX_PKT0_ST_VLD = 1.
3RX_PKT2_UNKNOWN_ERRRWC0x0Rx Packet 2 Type Unknown Error
It is valid only when RX_PKT0_ST_VLD = 1.
2RX_PKT2_ST_ERRRWC0x0Rx Packet 2 ack Status Error
DSI_RX_PKT_HDR_0 should be checked to identify the specific error.
It is valid only when RX_PKT0_ST_VLD = 1.
1RX_PKT2_ECC_ERRRWC0x0Rx Packet 2 ECC Error
It is valid only when RX_PKT0_ST_VLD = 1.
0RX_PKT2_CRC_ERRRWC0x0Rx Packet 2 CRC Error
It is valid only when RX_PKT0_ST_VLD = 1.
+**Offset: 0x78** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | RX_PKT2_ST_VLD | RWC | 0x0 | Rx Packet 2 Status Valid
1: Valid status
0: Invalid status | +| 30:27 | RSVD | RO | 0 | Reserved for future use | +| 26 | RX_PKT2_ST_EOTP | RWC | 0x0 | Rx Packet 2 is EOTP
1: Received packet is EOTP packet
0: Other packet. It is valid only when RX_PKT0_ST_VLD = 1. | +| 25 | RX_PKT2_ST_ACK | RWC | 0x0 | Rx Packet 2 is an ACK Packet
1: Received packet is an ACK packet, with or without error
0: Other packet. It is valid only when RX_PKT0_ST_VLD = 1. | +| 24 | RX_PKT2_ST_SP | RWC | 0x0 | Rx Packet 2 Short Packet
1: Received packet is a short packet
0: Long packet Valid only when RX_PKT0_ST_VLD = 1 | +| 23:22 | RSVD | RO | 0 | Reserved for future use | +| 21:16 | RX_PKT2_PKT_PTR | RWC | 0x0 | Rx Packet 2 Data Pointer
The packet header in FIFO is the raw data from DPHY before ECC correction.
Valid only when RX_PKT0_ST_VLD = 1. | +| 15:14 | RX_PKT2_VCH | RWC | 0x0 | Rx Packet 2 Virtual Channel Number
Valid only when RX_PKT0_ST_VLD = 1 | +| 13:12 | RSVD | RO | 0 | Reserved for future use | +| 11:8 | RX_PKT2_ECC_FLAGS | RWC | 0x0 | Rx Packet 2 ECC Error Flags
bit [11]:
1: No ECC error
0: ECC error
Bit [10]:
1: Correctable error in data bits
Bit [9]:
1: Correctable error happens at parity bits
Bit [8]:
1: Incorrectable error. It is valid only when RX_PKT0_ST_VLD = 1. | +| 7:5 | RSVD | RO | 0 | Reserved for future use | +| 4 | RX_PKT2_NO_CRC | RWC | 0x0 | Rx Packet 2 Without CRC
Rx packet does not include CRC and CRC part contains 0x0000.
It is valid only when RX_PKT0_ST_VLD = 1. | +| 3 | RX_PKT2_UNKNOWN_ERR | RWC | 0x0 | Rx Packet 2 Type Unknown Error
It is valid only when RX_PKT0_ST_VLD = 1. | +| 2 | RX_PKT2_ST_ERR | RWC | 0x0 | Rx Packet 2 ack Status Error
DSI_RX_PKT_HDR_0 should be checked to identify the specific error.
It is valid only when RX_PKT0_ST_VLD = 1. | +| 1 | RX_PKT2_ECC_ERR | RWC | 0x0 | Rx Packet 2 ECC Error
It is valid only when RX_PKT0_ST_VLD = 1. | +| 0 | RX_PKT2_CRC_ERR | RWC | 0x0 | Rx Packet 2 CRC Error
It is valid only when RX_PKT0_ST_VLD = 1. | #### DSI_RX_PKT_HDR_2REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x7c
BitsFieldTypeResetDescription
31:0RX_PKT2_HDRRW0x0 Rx Packet 2 Header
+**Offset: 0x7c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RX_PKT2_HDR | RW | 0x0 | Rx Packet 2 Header | #### DSI_LCD_BDG_CTRL0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x84
BitsFieldTypeResetDescription
31:28RSVDRO0Reserved for future use
27:16CFG_VPN_FIFO_AFULL_CNTRW0x0DSI VPN FIFO Almost Full Count
The difference between the FIFO read pointer and write pointer must be greater than this value.
15:10RSVDRO0Reserved for future use
9CFG_HSYNC_MISSING_FIXRW0x0Fix for the Hsync missing bug
8CFG_TXLP_LANE_TURN_FIXRW0x0Fix for the TXLP lane turn bug
7RSVDRO0Reserved for future use
6CFG_VPN_FIFO_AFULL_BYPASSRW0x0Bypass VPN FIFO almost full
0: Not bypass
1: Bypass (LCD outputs pixel data to VPN FIFO regardless of the almost full signal)
5CFG_CPN_VSYNC_EDGERW0x0CPN Vsync signal edge select
0: posedge (Positive edge) select
1: negedge (Negative edge) select
4CFG_CPN_TE_EDGERW0x0CPN tearing effect signal edge select
0: posedge (Positive edge) select
1: negedge (Negative edge) select
3:2CFG_CPN_TE_MODERW0x0CPN tearing effect mode select
0: No Tearing Effect
1: Mode A – Tearing effect signal consists of V-Blanking only
2: Mode B – Tearing effect signal consists of both V-Blanking and H-Blanking
3: Mode C – Tearing effect signal outputs the N H-Blanking
1CFG_PIXEL_SWAPRW0x0LCD output pixel swap
0: Do not swap LCD output pixel data
1: Swap LCD output pixel data
0CFG_SPLIT_ENRW0x0Split Mode enable
This bit should be set as same as LCD split mode
0: Split mode disable, only DSIA is used for display
1: Split mode enable, both DSIA and DSIB are used for display
+**Offset: 0x84** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | RSVD | RO | 0 | Reserved for future use | +| 27:16 | CFG_VPN_FIFO_AFULL_CNT | RW | 0x0 | DSI VPN FIFO Almost Full Count
The difference between the FIFO read pointer and write pointer must be greater than this value. | +| 15:10 | RSVD | RO | 0 | Reserved for future use | +| 9 | CFG_HSYNC_MISSING_FIX | RW | 0x0 | Fix for the Hsync missing bug | +| 8 | CFG_TXLP_LANE_TURN_FIX | RW | 0x0 | Fix for the TXLP lane turn bug | +| 7 | RSVD | RO | 0 | Reserved for future use | +| 6 | CFG_VPN_FIFO_AFULL_BYPASS | RW | 0x0 | Bypass VPN FIFO almost full
0: Not bypass
1: Bypass (LCD outputs pixel data to VPN FIFO regardless of the almost full signal) | +| 5 | CFG_CPN_VSYNC_EDGE | RW | 0x0 | CPN Vsync signal edge select
0: posedge (Positive edge) select
1: negedge (Negative edge) select | +| 4 | CFG_CPN_TE_EDGE | RW | 0x0 | CPN tearing effect signal edge select
0: posedge (Positive edge) select
1: negedge (Negative edge) select | +| 3:2 | CFG_CPN_TE_MODE | RW | 0x0 | CPN tearing effect mode select
0: No Tearing Effect
1: Mode A – Tearing effect signal consists of V-Blanking only
2: Mode B – Tearing effect signal consists of both V-Blanking and H-Blanking
3: Mode C – Tearing effect signal outputs the N H-Blanking | +| 1 | CFG_PIXEL_SWAP | RW | 0x0 | LCD output pixel swap
0: Do not swap LCD output pixel data
1: Swap LCD output pixel data | +| 0 | CFG_SPLIT_EN | RW | 0x0 | Split Mode enable
This bit should be set as same as LCD split mode
0: Split mode disable, only DSIA is used for display
1: Split mode enable, both DSIA and DSIB are used for display | #### DSI_LCD_BDG_CTRL1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x88
BitsFieldTypeResetDescription
31:16CFG_CPN_TE_DLY_CNTRW0x10CPN Tearing Effect Delay Count
The LCD output pixel data will be delayed by the number of cycles specified in this field after the TE pulse.
15:0CFG_CPN_TE_LINE_CNTRW0x0CPN Tearing Effect line Count
When TE_MODE = 2, this field takes effect.
The LCD output pixel data will be delayed for a number of TE pulses specified by this field.
+**Offset: 0x88** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_CPN_TE_DLY_CNT | RW | 0x10 | CPN Tearing Effect Delay Count
The LCD output pixel data will be delayed by the number of cycles specified in this field after the TE pulse. | +| 15:0 | CFG_CPN_TE_LINE_CNT | RW | 0x0 | CPN Tearing Effect line Count
When TE_MODE = 2, this field takes effect.
The LCD output pixel data will be delayed for a number of TE pulses specified by this field. | #### DSI_TX_TIMER REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0xe4
BitsFieldTypeResetDescription
31:0CFG_TX_TIMER_CNTRW0xffffffffTx Transmission Timer Value
This timer monitors the Tx operation on the DSI output side.
It could generate IRQ after timer timeout.
By default setting, timeout will not occur because the reset value is set to the maximum value (0xffffffff).
+**Offset: 0xe4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFG_TX_TIMER_CNT | RW | 0xffffffff | Tx Transmission Timer Value
This timer monitors the Tx operation on the DSI output side.
It could generate IRQ after timer timeout.
By default setting, timeout will not occur because the reset value is set to the maximum value (0xffffffff). | #### DSI_RX_TIMER REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0xe8
BitsFieldTypeResetDescription
31:0CFG_RX_TIMER_CNTRW0xffffffffRx Timer Value
This timer monitors the Rx operation on the DSI operation.
It could generate IRQ after timer timeout.
By default setting, timeout will not occur because the reset value is set to the maximum value (0xffffffff).
+**Offset: 0xe8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFG_RX_TIMER_CNT | RW | 0xffffffff | Rx Timer Value
This timer monitors the Rx operation on the DSI operation.
It could generate IRQ after timer timeout.
By default setting, timeout will not occur because the reset value is set to the maximum value (0xffffffff). | #### DSI_TURN_TIMER REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0xec
BitsFieldTypeResetDescription
31:0CFG_TURN_TIMER_CNTRW0xffffffffBus Turn Around Timer Value
This timer monitors the turn around operation on the DSI.
It could generate IRQ after timer timeout.
By default setting, timeout will not occur because the reset value is set to the maximum value (0xffffffff).
+**Offset: 0xec** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFG_TURN_TIMER_CNT | RW | 0xffffffff | Bus Turn Around Timer Value
This timer monitors the turn around operation on the DSI.
It could generate IRQ after timer timeout.
By default setting, timeout will not occur because the reset value is set to the maximum value (0xffffffff). | #### DSI_VPN_CTRL_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x100
BitsFieldTypeResetDescription
31:16CFG_VPN_DLY_CNTRW0x100VPN Vsync Delay Count in slave mode.
In slave mode, the DSI begins H/V timing based on the input Vsync from the LCD module. After receiving the Vsync from the LCD controller, the DSI will start the Vsync timing by delaying it for the number of clock cycles specified by this field.
15:8RSVDRO0Reserved for future use
7:0
CFG_VPN_TX_DLY_CNTRW0x10VPN TX Delay Count
After the DSI starts Hsync timing, this field defines the delay in DPHY byte clock cycles before initiating a VSS packet transfer. This internal delay ensures a fixed TX timing at the DPHY interface.
+**Offset: 0x100** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_DLY_CNT | RW | 0x100 | VPN Vsync Delay Count in slave mode.
In slave mode, the DSI begins H/V timing based on the input Vsync from the LCD module. After receiving the Vsync from the LCD controller, the DSI will start the Vsync timing by delaying it for the number of clock cycles specified by this field. | +| 15:8 | RSVD | RO | 0 | Reserved for future use | +| 7:0 | CFG_VPN_TX_DLY_CNT | RW | 0x10 | VPN TX Delay Count
After the DSI starts Hsync timing, this field defines the delay in DPHY byte clock cycles before initiating a VSS packet transfer. This internal delay ensures a fixed TX timing at the DPHY interface. | #### DSI_VPN_CTRL_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x104
BitsFieldTypeResetDescription
31CFG_VPN_VSYNC_RST_ENRW0x0LCD Vsync Reset Enable in slave mode
1: Reset DSI vertical state machine when LCD Vsync comes. This will only take effect when LCD is in slave mode.
0: Do not reset the DSI vertical state machine
30:28RSVDRO0Reserved for future use
27CFG_VPN_AUTO_WC_DISRW0x0VPN Auto Word Count Disable
This bit has lower priority than CFG_VPN_HACT_WC_EN
0x0: Enable auto word count calculation, and hardware automatically calculates the number of bytes that will be sent in each H line slot
0x1: Auto word count calculation will not be effective
26CFG_VPN_HACT_WC_ENRW0x0VPN Hact Word Count Enable
This bit has higher priority than CFG_VPN_AUTO_WC_EN
0x0: CFG_HACT_WC will not be effective if CFG_VPN_AUTO_WC_DIS is set to 0
0x1: Enable Hact word count parameter, and CFG_HACT_WC will be used to decide the number of bytes that are sent
25CFG_VPN_TIMING_CHECK_DISRW0x0VPN Hss/Hse/Hact TX Timing Check Disable
0x0: Check timing before requesting DPHY for TX
0x1: No check timing before requesting DPHY for TX
24CFG_VPN_AUTO_DLY_DISRW0x0VPN Auto Vsync Delay Count Disable
0x0: Enable automatic Vsync delay count calculation, and hardware will automatically use half of CFG_HTOTAL_CNT to replace CFG_VPN_DLY_CNT for Vsync delay.
0x1: Disables the auto Vsync delay count. The hardware will use the value in CFG_VPN_DLY_CNT for Vsync delay.
23RSVDRO0Reserved for future use
22CFG_VPN_HLP_PKT_EN
RW0x0Long Blanking Packet Enable
1: DSI sends out a long blanking packet during the HLP time slot.
0: Long blanking packet is disabled. DSI will enter low power during this time slot (In most cases, this field should be programmed to 0x0)
21CFG_VPN_HEX_PKT_ENRW0x0Extra Long Blanking Packet Enable
1: DSI sends out a long blanking packet after pixel data transmission and before the hfp.
0: Extra long blanking packet is disabled. DSI enter low power during this time slot (In most cases, this field should be programmed to 0x0)
20CFG_VPN_HFP_PKT_ENRW0x0Front Porch Packet Enable
1: DSI sends out a long blanking packet during the hfp time slot
0: hfp long blanking packet is disabled
DSI will go to low power during this time slot If front porch period is not long enough for DPHY to go to low power state and come back to HS again timely for next Hss packet, this field should be programmed to 0x1.
19RSVDRO0Reserved for future use
18CFG_VPN_HBP_PKT_ENRW0x0Back Porch Packet Enable
1: DSI sends out a long blanking packet during the hbp time slot
0: hbp long blanking packet is disabled. DSI will enter low power during this time slot
If the back porch period is not long enough for DPHY to go to low power state and return to HS mode in time for next pixel data packet, this field should be programmed to 0x1.
17CFG_VPN_HSE_PKT_ENRW0x0Hse Packet Enable
1: DSI will send out hse packet during hbp time slot
0: hse packet is disabled
DSI will go to low power during this time slot
> Note. Enable this bit when transmission mode is in Non-burst mode with sync pulse.
16CFG_VPN_HSA_PKT_ENRW0x0Hsa Packet Enable
1: DSI sends out hsa long blanking packet during the hbp time slot
0: hsa packet is disabled. DSI will go to low power during this time slot
- If transmission mode is in non-burst mode (with sync event) or burst mode, this field should be disabled.
- If transmission mode is non-burst mode (with sync pulse), this field can be programmed to 0x1.
15RSVDRO0Reserved for future use
14CFG_VPN_HEX_SLOT_ENRW0x0Extra Long Packet Enable after Pixel Data
1: Enable extra long packet after pixel data transfer, this will insert a long blanking packet before hfp
0: No extra long packet is inserted after pixel data transfer
This field takes effect only in burst mode. In most cases, this field should be programmed to 0x0.
13:11RSVDRO0Reserved for future use
10CFG_VPN_LAST_LINE_TURNRW0x0Turn Around Bus at Last h Line
1: DSI will turn around the bus at the last horizontal line of each frame. This will request the slave to return an acknowledgment or an acknowledgment with an error.
0: DSI will not turn around the bus during the last horizontal line of the frame.
In most cases, this field should be set to 0x0.
9CFG_VPN_LPM_FRAME_ENRW0x0Go to Low Power Every Frame
1: DSI will go to low power mode during the last horizontal line of every frame
0: DSI will not go to low power mode during the last h line
In most cases, this field should be programmed to 0x0.
8:4RSVDRO0Reserved for future use
3:2CFG_VPN_BURST_MODERW0x0DSI Transmission Mode for LCD 1
0x0: Non-burst mode with sync pulse
0x1: Non-burst mode with sync event
0x2: Burst mode
1:0CFG_VPN_RGB_TYPERW0x0LCD 1 Input Data RGB Mode for LCD 1
0x0: 565 RGB mode
0x1: 666 packet mode
0x2: 666 un-packet mode
0x3: 888 RGB mode
+**Offset: 0x104** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | CFG_VPN_VSYNC_RST_EN | RW | 0x0 | LCD Vsync Reset Enable in slave mode
1: Reset DSI vertical state machine when LCD Vsync comes. This will only take effect when LCD is in slave mode.
0: Do not reset the DSI vertical state machine | +| 30:28 | RSVD | RO | 0 | Reserved for future use | +| 27 | CFG_VPN_AUTO_WC_DIS | RW | 0x0 | VPN Auto Word Count Disable
This bit has lower priority than CFG_VPN_HACT_WC_EN
0x0: Enable auto word count calculation, and hardware automatically calculates the number of bytes that will be sent in each H line slot
0x1: Auto word count calculation will not be effective | +| 26 | CFG_VPN_HACT_WC_EN | RW | 0x0 | VPN Hact Word Count Enable
This bit has higher priority than CFG_VPN_AUTO_WC_EN
0x0: CFG_HACT_WC will not be effective if CFG_VPN_AUTO_WC_DIS is set to 0
0x1: Enable Hact word count parameter, and CFG_HACT_WC will be used to decide the number of bytes that are sent | +| 25 | CFG_VPN_TIMING_CHECK_DIS | RW | 0x0 | VPN Hss/Hse/Hact TX Timing Check Disable
0x0: Check timing before requesting DPHY for TX
0x1: No check timing before requesting DPHY for TX | +| 24 | CFG_VPN_AUTO_DLY_DIS | RW | 0x0 | VPN Auto Vsync Delay Count Disable
0x0: Enable automatic Vsync delay count calculation, and hardware will automatically use half of CFG_HTOTAL_CNT to replace CFG_VPN_DLY_CNT for Vsync delay.
0x1: Disables the auto Vsync delay count. The hardware will use the value in CFG_VPN_DLY_CNT for Vsync delay. | +| 23 | RSVD | RO | 0 | Reserved for future use | +| 22 | CFG_VPN_HLP_PKT_EN | RW | 0x0 | Long Blanking Packet Enable
1: DSI sends out a long blanking packet during the HLP time slot.
0: Long blanking packet is disabled. DSI will enter low power during this time slot (In most cases, this field should be programmed to 0x0) | +| 21 | CFG_VPN_HEX_PKT_EN | RW | 0x0 | Extra Long Blanking Packet Enable
1: DSI sends out a long blanking packet after pixel data transmission and before the hfp.
0: Extra long blanking packet is disabled. DSI enter low power during this time slot (In most cases, this field should be programmed to 0x0) | +| 20 | CFG_VPN_HFP_PKT_EN | RW | 0x0 | Front Porch Packet Enable
1: DSI sends out a long blanking packet during the hfp time slot
0: hfp long blanking packet is disabled
DSI will go to low power during this time slot If front porch period is not long enough for DPHY to go to low power state and come back to HS again timely for next Hss packet, this field should be programmed to 0x1. | +| 19 | RSVD | RO | 0 | Reserved for future use | +| 18 | CFG_VPN_HBP_PKT_EN | RW | 0x0 | Back Porch Packet Enable
1: DSI sends out a long blanking packet during the hbp time slot
0: hbp long blanking packet is disabled. DSI will enter low power during this time slot
If the back porch period is not long enough for DPHY to go to low power state and return to HS mode in time for next pixel data packet, this field should be programmed to 0x1. | +| 17 | CFG_VPN_HSE_PKT_EN | RW | 0x0 | Hse Packet Enable
1: DSI will send out hse packet during hbp time slot
0: hse packet is disabled
DSI will go to low power during this time slot
**Note. Enable this bit when transmission mode is in Non-burst mode with sync pulse.** | +| 16 | CFG_VPN_HSA_PKT_EN | RW | 0x0 | Hsa Packet Enable
1: DSI sends out hsa long blanking packet during the hbp time slot
0: hsa packet is disabled. DSI will go to low power during this time slot
- If transmission mode is in non-burst mode (with sync event) or burst mode, this field should be disabled.
- If transmission mode is non-burst mode (with sync pulse), this field can be programmed to 0x1. | +| 15 | RSVD | RO | 0 | Reserved for future use | +| 14 | CFG_VPN_HEX_SLOT_EN | RW | 0x0 | Extra Long Packet Enable after Pixel Data
1: Enable extra long packet after pixel data transfer, this will insert a long blanking packet before hfp
0: No extra long packet is inserted after pixel data transfer
This field takes effect only in burst mode. In most cases, this field should be programmed to 0x0. | +| 13:11 | RSVD | RO | 0 | Reserved for future use | +| 10 | CFG_VPN_LAST_LINE_TURN | RW | 0x0 | Turn Around Bus at Last h Line
1: DSI will turn around the bus at the last horizontal line of each frame. This will request the slave to return an acknowledgment or an acknowledgment with an error.
0: DSI will not turn around the bus during the last horizontal line of the frame.
In most cases, this field should be set to 0x0. | +| 9 | CFG_VPN_LPM_FRAME_EN | RW | 0x0 | Go to Low Power Every Frame
1: DSI will go to low power mode during the last horizontal line of every frame
0: DSI will not go to low power mode during the last h line
In most cases, this field should be programmed to 0x0. | +| 8:4 | RSVD | RO | 0 | Reserved for future use | +| 3:2 | CFG_VPN_BURST_MODE | RW | 0x0 | DSI Transmission Mode for LCD 1
0x0: Non-burst mode with sync pulse
0x1: Non-burst mode with sync event
0x2: Burst mode | +| 1:0 | CFG_VPN_RGB_TYPE | RW | 0x0 | LCD 1 Input Data RGB Mode for LCD 1
0x0: 565 RGB mode
0x1: 666 packet mode
0x2: 666 un-packet mode
0x3: 888 RGB mode | #### DSI_VPN_TIMING_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x110
BitsFieldTypeResetDescription
31:16CFG_VPN_HACT_CNTRW0x0VPN hact Clock Count in byte clock domain
This parameter defines the byte clock cycle numbers for horizontal line pixel data period
The data byte number for this period is
HACT_BYTE_CNT= HACT_CNT*lane_num
15:0CFG_VPN_HTOTAL_CNTRW0x0VPN htotal Clock Count in byte clock domain.
This parameter defines the byte clock cycle numbers for horizontal line period
The data byte number for this period is
HTOTAL_BYTE_CNT = HTOTAL_CNT*lane_num
+**Offset: 0x110** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_HACT_CNT | RW | 0x0 | VPN hact Clock Count in byte clock domain
This parameter defines the byte clock cycle numbers for horizontal line pixel data period
The data byte number for this period is
HACT_BYTE_CNT= HACT_CNT*lane_num | +| 15:0 | CFG_VPN_HTOTAL_CNT | RW | 0x0 | VPN htotal Clock Count in byte clock domain.
This parameter defines the byte clock cycle numbers for horizontal line period
The data byte number for this period is
HTOTAL_BYTE_CNT = HTOTAL_CNT*lane_num | #### DSI_VPN_TIMING_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x114
BitsFieldTypeResetDescription
31:16
CFG_VPN_HSYNC_CNTRW0x0VPN hsync Clock Count in byte clock domain.
This parameter defines the byte clock cycle numbers for horizontal line hsync period
The data byte number for this period is
HSYNC__BYTE_CNT= HSYNC_CNT*lane_num
15:0CFG_VPN_HBP_CNTRW0x0VPN hbp Clock Count in byte clock domain.
This parameter defines the byte clock cycle numbers for horizontal line back porch period
- The data byte number for this period is
HBP_BYTE_CNT= HBP_CNT*lane_num
- Front porch clock count can be calculated by:
HFP_CNT = HTOTAL_CNT - HSYNC_CNT - HACT_CNT - HBP_CNT
- The data byte number for front porch period is
HFP_BYTE_CNT= HFP_CNT*lane_num
+**Offset: 0x114** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_HSYNC_CNT | RW | 0x0 | VPN hsync Clock Count in byte clock domain.
This parameter defines the byte clock cycle numbers for horizontal line hsync period
The data byte number for this period is
HSYNC__BYTE_CNT= HSYNC_CNT*lane_num | +| 15:0 | CFG_VPN_HBP_CNT | RW | 0x0 | VPN hbp Clock Count in byte clock domain.
This parameter defines the byte clock cycle numbers for horizontal line back porch period
- The data byte number for this period is
HBP_BYTE_CNT= HBP_CNT*lane_num
- Front porch clock count can be calculated by:
HFP_CNT = HTOTAL_CNT - HSYNC_CNT - HACT_CNT - HBP_CNT
- The data byte number for front porch period is
HFP_BYTE_CNT= HFP_CNT*lane_num | #### DSI_VPN_TIMING_2 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x118
BitsFieldTypeResetDescription
31:16CFG_VPN_VACT_CNTRW0x0 VPN vact Line Count
15:0CFG_VPN_VTOTAL_CNTRW0x0 VPN vtotal Line Count
+**Offset: 0x118** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_VACT_CNT | RW | 0x0 | VPN vact Line Count | +| 15:0 | CFG_VPN_VTOTAL_CNT | RW | 0x0 | VPN vtotal Line Count | #### DSI_VPN_TIMING_3 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x11c
BitsFieldTypeResetDescription
31:16CFG_VPN_VSYNC_CNTRW0x0 VPN vsync Line Count
15:0CFG_VPN_VBP_CNTRW0x0 VPN vbp Line Count
+**Offset: 0x11c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_VSYNC_CNT | RW | 0x0 | VPN vsync Line Count | +| 15:0 | CFG_VPN_VBP_CNT | RW | 0x0 | VPN vbp Line Count | #### DSI_VPN_WC_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x120
BitsFieldTypeResetDescription
31:16CFG_VPN_HBP_WCRW0x0VPN hbp packet payload data Byte Count
This parameter must be programmed if HBP_PKT_EN is 0x1, otherwise it can be kept as 0x0
- If transmission mode is non-burst mode with sync pulse, the formula is:
HBP_WC=HBP_BYTE_CNT−HSE_BYTE_CNT(4)−HBP_PKT_OVERHEAD(6)
- If transmission mode is non-burst mode with sync event or burst mode, the formula is:
HBP_WC=HSYNC_BYTE_CNT+HBP_BYTE_CNT−HSS_BYTE_CNT(4)−HBP_PKT_OVERHEAD(6)
15:0CFG_VPN_HSA_WCRW0x0VPN hsa packet payload data Byte Count
This parameter must be programmed if HSA_PKT_EN is 0x1, otherwise it can be kept as 0x0
- If transmission mode is non-burst mode with sync pulse, the formula is:
HSA_WC = HSYNC_BYTE_CNT - HSS_BYTE_CNT(4) - HSA_PKT_OVERHEAD(6)
- Otherwise it is 0x0
+**Offset: 0x120** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_HBP_WC | RW | 0x0 | VPN hbp packet payload data Byte Count
This parameter must be programmed if HBP_PKT_EN is 0x1, otherwise it can be kept as 0x0
- If transmission mode is non-burst mode with sync pulse, the formula is:
HBP_WC=HBP_BYTE_CNT−HSE_BYTE_CNT(4)−HBP_PKT_OVERHEAD(6)
- If transmission mode is non-burst mode with sync event or burst mode, the formula is:
HBP_WC=HSYNC_BYTE_CNT+HBP_BYTE_CNT−HSS_BYTE_CNT(4)−HBP_PKT_OVERHEAD(6) | +| 15:0 | CFG_VPN_HSA_WC | RW | 0x0 | VPN hsa packet payload data Byte Count
This parameter must be programmed if HSA_PKT_EN is 0x1, otherwise it can be kept as 0x0
- If transmission mode is non-burst mode with sync pulse, the formula is:
HSA_WC = HSYNC_BYTE_CNT - HSS_BYTE_CNT(4) - HSA_PKT_OVERHEAD(6)
- Otherwise it is 0x0 | #### DSI_VPN_WC_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x124
BitsFieldTypeResetDescription
31:16CFG_VPN_HFP_WCRW0x0VPN hfp packet payload data Byte Count
This parameter must be programmed if HFP_PKT_EN is 0x1, otherwise it can be kept as 0x0
- If transmission mode is non-burst mode with sync pulse, or non-burst mode with sync event, the formula is:
HFP_WC = HFP_BYTE_CNT - HACT_PKT_OVERHEAD(6) - HFP_PKT_OVERHEAD(6)
- If transmission mode is burst mode and HEX_PKT_EN = 1, the formula is:
HFP_WC = HFP_BYTE_CNT - HACT_PKT_OVERHEAD(6) - HFP_PKT_OVERHEAD(6)
- If transmission mode is burst mode and HEX_PKT_EN = 0, the formula is:
HFP_WC = HFP_BYTE_CNT + (HACT_BYTE_CNT - HACT_WC) - HACT_PKT_OVERHEAD(6) - HFP_PKT_OVERHEAD(6)
15:0CFG_VPN_HACT_WCRW0x0VPN hact packet payload data Byte Count
This parameter is equal to Active pixel RGB data total byte count
+**Offset: 0x124** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_HFP_WC | RW | 0x0 | VPN hfp packet payload data Byte Count
This parameter must be programmed if HFP_PKT_EN is 0x1, otherwise it can be kept as 0x0
- If transmission mode is non-burst mode with sync pulse, or non-burst mode with sync event, the formula is:
HFP_WC = HFP_BYTE_CNT - HACT_PKT_OVERHEAD(6) - HFP_PKT_OVERHEAD(6)
- If transmission mode is burst mode and HEX_PKT_EN = 1, the formula is:
HFP_WC = HFP_BYTE_CNT - HACT_PKT_OVERHEAD(6) - HFP_PKT_OVERHEAD(6)
- If transmission mode is burst mode and HEX_PKT_EN = 0, the formula is:
HFP_WC = HFP_BYTE_CNT + (HACT_BYTE_CNT - HACT_WC) - HACT_PKT_OVERHEAD(6) - HFP_PKT_OVERHEAD(6) | +| 15:0 | CFG_VPN_HACT_WC | RW | 0x0 | VPN hact packet payload data Byte Count
This parameter is equal to Active pixel RGB data total byte count | #### DSI_VPN_WC_2 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x128
BitsFieldTypeResetDescription
31:16
CFG_VPN_HEX_WCRW0x0VPN hex packet payload data Byte Count
This parameter must be programmed if HEX_PKT_EN is 0x1, otherwise it can be kept as 0x0
- If transmission mode is burst mode, the formula is:
HEX_WC = HACT_BYTE_CNT - HACT_WC - HEX_PKT_OVERHEAD(6)
- Otherwise HEX_WC = 0
15:0CFG_VPN_HLP_WCRW0x0VPN hlp packet payload data Byte Count
This parameter must be programmed if HLP_PKT_EN is 0x1, otherwise it can be kept as 0x0
- If transmission mode is non-burst mode with sync pulse, the formula is:
HLP_WC = HTOTAL_BYTE_CNT - HSYNC_BYTE_CNT - HSE_BYTE_CNT(4) - HLP_PKT_OVERHEAD(6)
- If transmission mode is non-burst mode with sync event or burst mode, the formula is:
HLP_WC = HTOTAL_BYTE_CNT - HSS_BYTE_CNT(4) - HLP_PKT_OVERHEAD(6)
+**Offset: 0x128** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_HEX_WC | RW | 0x0 | VPN hex packet payload data Byte Count
This parameter must be programmed if HEX_PKT_EN is 0x1, otherwise it can be kept as 0x0
- If transmission mode is burst mode, the formula is:
HEX_WC = HACT_BYTE_CNT - HACT_WC - HEX_PKT_OVERHEAD(6)
- Otherwise HEX_WC = 0 | +| 15:0 | CFG_VPN_HLP_WC | RW | 0x0 | VPN hlp packet payload data Byte Count
This parameter must be programmed if HLP_PKT_EN is 0x1, otherwise it can be kept as 0x0
- If transmission mode is non-burst mode with sync pulse, the formula is:
HLP_WC = HTOTAL_BYTE_CNT - HSYNC_BYTE_CNT - HSE_BYTE_CNT(4) - HLP_PKT_OVERHEAD(6)
- If transmission mode is non-burst mode with sync event or burst mode, the formula is:
HLP_WC = HTOTAL_BYTE_CNT - HSS_BYTE_CNT(4) - HLP_PKT_OVERHEAD(6) | #### DSI_VPN_SLOT_CNT_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x130
BitsFieldTypeResetDescription
31:16CFG_VPN_SLOT_SP_CNTRW0x0VPN Time Slot Count for Short Packet.
This parameter defines a MIN slot period for short packet transmission, which should ensure DPHY can go to low power, send the short packet, and return to HS again in time for the next active panel packet which has a strict timing requirement.
If any DSI active panel data flow is working, and CPU or smart interface wants to send short packet between the active panel packets, the internal state machine will try to find a time slot between active panel packets which has a larger period than the defined value.
DSI will only send CPU or Command Panel short packet during such slot to ensure DPHY has enough time to go to low power, send the packet, and return to HS again in time for next active panel packet which has a strict timing requirement.
The programming of this parameter is necessary only when multiple panels or data paths are working simultaneously.
15:0CFG_VPN_SLOT_LP_CNTRW0x0VPN Time Slot Count for Long Packet.
This parameter defines a minimum slot period for long packet transmission, which should ensure DPHY can enter low power mode, send the long packet, and return to HS again in time for the next active panel packet which has a strict timing requirement.
The programming of this parameter is necessary only when multiple panels or data paths are working simultaneously.
+**Offset: 0x130** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_SLOT_SP_CNT | RW | 0x0 | VPN Time Slot Count for Short Packet.
This parameter defines a MIN slot period for short packet transmission, which should ensure DPHY can go to low power, send the short packet, and return to HS again in time for the next active panel packet which has a strict timing requirement.
If any DSI active panel data flow is working, and CPU or smart interface wants to send short packet between the active panel packets, the internal state machine will try to find a time slot between active panel packets which has a larger period than the defined value.
DSI will only send CPU or Command Panel short packet during such slot to ensure DPHY has enough time to go to low power, send the packet, and return to HS again in time for next active panel packet which has a strict timing requirement.
The programming of this parameter is necessary only when multiple panels or data paths are working simultaneously. | +| 15:0 | CFG_VPN_SLOT_LP_CNT | RW | 0x0 | VPN Time Slot Count for Long Packet.
This parameter defines a minimum slot period for long packet transmission, which should ensure DPHY can enter low power mode, send the long packet, and return to HS again in time for the next active panel packet which has a strict timing requirement.
The programming of this parameter is necessary only when multiple panels or data paths are working simultaneously. | #### DSI_VPN_SLOT_CNT_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x134
BitsFieldTypeResetDescription
31:16CFG_VPN_SLOT_TXLP_CNTRW0x0VPN Time Slot Count for Low Power packet TX.
This parameter defines a minimum slot period for Low Power packet transmission, which should ensure DPHY can enter low power mode, send the Low Power packet, and return to HS again in time for the next active panel packet which has a strict timing requirement.
The programming of this parameter is necessary only when multiple panels or data paths are working simultaneously.
15:0CFG_VPN_SLOT_TN_CNTRW0x0VPN Time Slot Count for Bus Turn Around.
This parameter defines a minimum slot period for short packet transmission, which should ensure DPHY can enter low power mode, turn around the bus, and return to HS again in time for the next active panel packet which has a strict timing requirement.
+**Offset: 0x134** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_SLOT_TXLP_CNT | RW | 0x0 | VPN Time Slot Count for Low Power packet TX.
This parameter defines a minimum slot period for Low Power packet transmission, which should ensure DPHY can enter low power mode, send the Low Power packet, and return to HS again in time for the next active panel packet which has a strict timing requirement.
The programming of this parameter is necessary only when multiple panels or data paths are working simultaneously. | +| 15:0 | CFG_VPN_SLOT_TN_CNT | RW | 0x0 | VPN Time Slot Count for Bus Turn Around.
This parameter defines a minimum slot period for short packet transmission, which should ensure DPHY can enter low power mode, turn around the bus, and return to HS again in time for the next active panel packet which has a strict timing requirement. | #### DSI_VPN_SYNC_CODE REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x138
BitsFieldTypeResetDescription
31:30RSVDRO0Reserved for future use
29:24CFG_VPN_HSE_CODERW0x31MIPI DSI Hsync End Code
23:22RSVDRO0Reserved for future use
21:16CFG_VPN_HSS_CODERW0x21MIPI DSI Hsync Start Code
15:14RSVDRO0Reserved for future use
13:8CFG_VPN_VSE_CODERW0x11MIPI DSI Vsync End Code
7:6RSVDRO0Reserved for future use
5:0CFG_VPN_VSS_CODERW0x01MIPI DSI Vsync Start Code
+**Offset: 0x138** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | RSVD | RO | 0 | Reserved for future use | +| 29:24 | CFG_VPN_HSE_CODE | RW | 0x31 | MIPI DSI Hsync End Code | +| 23:22 | RSVD | RO | 0 | Reserved for future use | +| 21:16 | CFG_VPN_HSS_CODE | RW | 0x21 | MIPI DSI Hsync Start Code | +| 15:14 | RSVD | RO | 0 | Reserved for future use | +| 13:8 | CFG_VPN_VSE_CODE | RW | 0x11 | MIPI DSI Vsync End Code | +| 7:6 | RSVD | RO | 0 | Reserved for future use | +| 5:0 | CFG_VPN_VSS_CODE | RW | 0x01 | MIPI DSI Vsync Start Code | #### DSI_VPN_STATUS_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x140
BitsFieldTypeResetDescription
31CFG_VPN_RD_ERRRO0x0VPN input buffer read error
It includes
- CFG_VPN_RD_2EARLY
- CFG_VPN_LINE_MISS
- CFG_VPN_RD_UNDERRUN
30CFG_VPN_LINE_MISSRO0x0VPN input buffer line miss
This indicates a whole H line pixel data is missed.
29CFG_VPN_RD_2EARLYRO0x0VPN input buffer read too early
28CFG_VPN_RD_UNDERRUNRO0x0VPN input buffer underrun
27CFG_VPN_BF_FULLRO0x0VPN input buffer full
26CFG_VPN_RD_DELAY_ERRRO0x0VPN Request Delay Error at arbiter
25:21RSVDRO0Reserved for future use
20:0CFG_VPN_STATUS_0RO0x811DSI VPN Status Register for debug purpose
It includes the following fields:
- l1_lcd 4:0_cs
- l1_vst 6:0
- l1_hst 8:0
+**Offset: 0x140** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | CFG_VPN_RD_ERR | RO | 0x0 | VPN input buffer read error
It includes
- CFG_VPN_RD_2EARLY
- CFG_VPN_LINE_MISS
- CFG_VPN_RD_UNDERRUN | +| 30 | CFG_VPN_LINE_MISS | RO | 0x0 | VPN input buffer line miss
This indicates a whole H line pixel data is missed. | +| 29 | CFG_VPN_RD_2EARLY | RO | 0x0 | VPN input buffer read too early | +| 28 | CFG_VPN_RD_UNDERRUN | RO | 0x0 | VPN input buffer underrun | +| 27 | CFG_VPN_BF_FULL | RO | 0x0 | VPN input buffer full | +| 26 | CFG_VPN_RD_DELAY_ERR | RO | 0x0 | VPN Request Delay Error at arbiter | +| 25:21 | RSVD | RO | 0 | Reserved for future use | +| 20:0 | CFG_VPN_STATUS_0 | RO | 0x811 | DSI VPN Status Register for debug purpose
It includes the following fields:
- l1_lcd 4:0_cs
- l1_vst 6:0
- l1_hst 8:0 | #### DSI_VPN_STATUS_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x144
BitsFieldTypeResetDescription
31:16CFG_VPN_WRDONE_RDDONE_CNTRO0x0VPN Input Buffer Write Done to input buffer Read Done Clock Count
This could help to tune the vsync delay count.
15:0CFG_VPN_WR2RD_CNTRO0x0VPN Input Buffer Write to input buffer Read Clock Count.
This could help to tune the vsync delay count.
+**Offset: 0x144** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_WRDONE_RDDONE_CNT | RO | 0x0 | VPN Input Buffer Write Done to input buffer Read Done Clock Count
This could help to tune the vsync delay count. | +| 15:0 | CFG_VPN_WR2RD_CNT | RO | 0x0 | VPN Input Buffer Write to input buffer Read Clock Count.
This could help to tune the vsync delay count. | #### DSI_VPN_STATUS_2 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x148
BitsFieldTypeResetDescription
31:16CFG_VPN_UNDERRUN_CNTRO0x0VPN input buffer underrun count
15:0
CFG_VPN_RD_DATWR_CNTRO0x0VPN input buffer read to data write count
+**Offset: 0x148** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_UNDERRUN_CNT | RO | 0x0 | VPN input buffer underrun count | +| 15:0 | CFG_VPN_RD_DATWR_CNT | RO | 0x0 | VPN input buffer read to data write count | #### DSI_VPN_STATUS_3 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14c
BitsFieldTypeResetDescription
31:16CFG_VPN_REQ_ARB_DLY_CNTRO0x0VPN tx request delay count at arbiter interface
15:0CFG_VPN_REQ_PHY_DLY_CNTRO0x0VPN tx request delay count at dphy interface
+**Offset: 0x14c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_VPN_REQ_ARB_DLY_CNT | RO | 0x0 | VPN tx request delay count at arbiter interface | +| 15:0 | CFG_VPN_REQ_PHY_DLY_CNT | RO | 0x0 | VPN tx request delay count at dphy interface | #### DSI_VPN_STATUS_4 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x150
BitsFieldTypeResetDescription
31:0CFG_VPN_FRM_CNTRO0x0DSI VPN TX frame count
+**Offset: 0x150** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFG_VPN_FRM_CNT | RO | 0x0 | DSI VPN TX frame count | #### DSI_PHY_CTRL_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x180
BitsFieldTypeResetDescription
31CFG_RX_TRG_REG_DISRW0x0Disable Register for low power rx trigger signals.
Note: Internal use only
30CFG_TX_LANE_0RW0x0New packet tx start from lane
0: If two packets are transferred continuously, all data is packed and distributed to all enabled lanes. The second packet could start from any lane.
1: Transmission of every new packet starts from lane 0. If two packets are transferred continuously, and the first packet doesn't occupy all lanes, then extra byte of 0 will be inserted in at the end of first packet to ensure the second packet start from lane 0
This is an debug option and should be set to 0
29:28RSVDRO0Reserved for future use
27CFG_FCLK_NOTRW0x0Reverse Input Byte Clock from DPHY to DSI Control Logic
The output data to DPHY should be valid at the falling edge of the byte clock.
26:24RSVDRO0Reserved for future use
23:16CFG_STOP_ST_CNTRW0x10DPHY stops state count
Defines the stop state count for TXLP and PHY control
15:8CFG_RX_DLY_CNTRW0x30DPHY rx_delay count
Defines the delay state count for RX control
7:0RSVDRO0Reserved for future use
+**Offset: 0x180** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | CFG_RX_TRG_REG_DIS | RW | 0x0 | Disable Register for low power rx trigger signals.
Note: Internal use only | +| 30 | CFG_TX_LANE_0 | RW | 0x0 | New packet tx start from lane
0: If two packets are transferred continuously, all data is packed and distributed to all enabled lanes. The second packet could start from any lane.
1: Transmission of every new packet starts from lane 0. If two packets are transferred continuously, and the first packet doesn't occupy all lanes, then extra byte of 0 will be inserted in at the end of first packet to ensure the second packet start from lane 0
This is an debug option and should be set to 0 | +| 29:28 | RSVD | RO | 0 | Reserved for future use | +| 27 | CFG_FCLK_NOT | RW | 0x0 | Reverse Input Byte Clock from DPHY to DSI Control Logic
The output data to DPHY should be valid at the falling edge of the byte clock. | +| 26:24 | RSVD | RO | 0 | Reserved for future use | +| 23:16 | CFG_STOP_ST_CNT | RW | 0x10 | DPHY stops state count
Defines the stop state count for TXLP and PHY control | +| 15:8 | CFG_RX_DLY_CNT | RW | 0x30 | DPHY rx_delay count
Defines the delay state count for RX control | +| 7:0 | RSVD | RO | 0 | Reserved for future use | #### DSI_PHY_CTRL_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x184
BitsFieldTypeResetDescription
31:18RSVDRO0Reserved for future use
17CFG_VDD_ANA_VALIDRW0x1DPHY Analog VDD Valid
16CFG_VDD_DVM_VALIDRW0x1DPHY Digital VDD Valid
15:3RSVDRO0Reserved for future use
2CFG_ULPS_REQ_BYTERW0x0DPHY All Lane Force to ULPS
1CFG_TX_ULPS_CLK_ESCRW0x0DPHY clk Lane Force to ULPS
0CFG_CONT_CLK_HSRW0x0DPHY Clock Lane Continuous Clocking in HS
+**Offset: 0x184** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:18 | RSVD | RO | 0 | Reserved for future use | +| 17 | CFG_VDD_ANA_VALID | RW | 0x1 | DPHY Analog VDD Valid | +| 16 | CFG_VDD_DVM_VALID | RW | 0x1 | DPHY Digital VDD Valid | +| 15:3 | RSVD | RO | 0 | Reserved for future use | +| 2 | CFG_ULPS_REQ_BYTE | RW | 0x0 | DPHY All Lane Force to ULPS | +| 1 | CFG_TX_ULPS_CLK_ESC | RW | 0x0 | DPHY clk Lane Force to ULPS | +| 0 | CFG_CONT_CLK_HS | RW | 0x0 | DPHY Clock Lane Continuous Clocking in HS | #### DSI_PHY_CTRL_2 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x188
BitsFieldTypeResetDescription
31:15RSVDRO0Reserved for future use
14CFG_CSR_HSTX_RX_ENRW0x0RX enable when DPHY HSTX
0x0: Disable
0x1: Enable
13:12CFG_CSR_LANE_MAPRW0x0DPHY Data map to lane order
0x0: Lane0, Lane1, Lane2, Lane3
0x1: Lane0, Lane3, Lane1, lane2
0x2: Lane0, Lane2, Lane3, Lane1
0x3: Reserved
11:8CFG_CSR_LANE_RESC_ENRW0x0DPHY LP Receiver Enable
Enable the reverse escape LP receiver.
Lane immediately transmits to receive mode.
7:4CFG_CSR_LANE_ENRW0x0 DPHY Data Lane Enable
3:0CFG_CSR_LANE_TURNRW0x0DPHY Bus Turn Around
This field indicates that the protocol desires to turn the lane around, allowing the other side to begin transmitting.
+**Offset: 0x188** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:15 | RSVD | RO | 0 | Reserved for future use | +| 14 | CFG_CSR_HSTX_RX_EN | RW | 0x0 | RX enable when DPHY HSTX
0x0: Disable
0x1: Enable | +| 13:12 | CFG_CSR_LANE_MAP | RW | 0x0 | DPHY Data map to lane order
0x0: Lane0, Lane1, Lane2, Lane3
0x1: Lane0, Lane3, Lane1, lane2
0x2: Lane0, Lane2, Lane3, Lane1
0x3: Reserved | +| 11:8 | CFG_CSR_LANE_RESC_EN | RW | 0x0 | DPHY LP Receiver Enable
Enable the reverse escape LP receiver.
Lane immediately transmits to receive mode. | +| 7:4 | CFG_CSR_LANE_EN | RW | 0x0 | DPHY Data Lane Enable | +| 3:0 | CFG_CSR_LANE_TURN | RW | 0x0 | DPHY Bus Turn Around
This field indicates that the protocol desires to turn the lane around, allowing the other side to begin transmitting. | #### DSI_PHY_CTRL_3 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x18c
BitsFieldTypeResetDescription
31:10RSVDRO0Reserved for future use
9CFG_FORCECLK_HIZ_HSRW0x0DPHY clk Lane Force to High-Z in HS Mode
8CFG_FORCECLK_HIZ_LPRW0x0DPHY clk Lane Force to High-Z in LP mode
7:4CFG_FORCE_HIZ_HSRW0x0DPHY Force Data Lane to High-Z in HS Mode
3:0CFG_FORCE_HIZ_LPRW0x0DPHY Data Lane Force to High-Z in LP Mode
+**Offset: 0x18c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:10 | RSVD | RO | 0 | Reserved for future use | +| 9 | CFG_FORCECLK_HIZ_HS | RW | 0x0 | DPHY clk Lane Force to High-Z in HS Mode | +| 8 | CFG_FORCECLK_HIZ_LP | RW | 0x0 | DPHY clk Lane Force to High-Z in LP mode | +| 7:4 | CFG_FORCE_HIZ_HS | RW | 0x0 | DPHY Force Data Lane to High-Z in HS Mode | +| 3:0 | CFG_FORCE_HIZ_LP | RW | 0x0 | DPHY Data Lane Force to High-Z in LP Mode | #### DSI_PHY_STATUS_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x190
BitsFieldTypeResetDescription
31:28DPHY_RDY_HS_BYTERWC0x0DPHY HS TX ready signals
27:24TX_REQ_HS_BYTERWC0x0DPHY HS TX request signals
23:20RSVDRO0Reserved for future use
19:16DPHY_LANE_RX_LINE_ERRRWC0x0PPI ErrControl Illegal line state detected
15:12DPHY_ERR_SYNC_ESCRWC0x0PPI ErrSyncEsc Partial byte detected
11:8DPHY_ERR_ESCRWC0x0PPI ErrEsc Invalid esc command detected
7:4DPHY_ERR_CONT_LP0RWC0x0PPI ErrContentionLP0 Contention detect
3:0DPHY_ERR_CONT_LP1RWC0x0PPI ErrContentionLP0 Contention detect
+**Offset: 0x190** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | DPHY_RDY_HS_BYTE | RWC | 0x0 | DPHY HS TX ready signals | +| 27:24 | TX_REQ_HS_BYTE | RWC | 0x0 | DPHY HS TX request signals | +| 23:20 | RSVD | RO | 0 | Reserved for future use | +| 19:16 | DPHY_LANE_RX_LINE_ERR | RWC | 0x0 | PPI ErrControl Illegal line state detected | +| 15:12 | DPHY_ERR_SYNC_ESC | RWC | 0x0 | PPI ErrSyncEsc Partial byte detected | +| 11:8 | DPHY_ERR_ESC | RWC | 0x0 | PPI ErrEsc Invalid esc command detected | +| 7:4 | DPHY_ERR_CONT_LP0 | RWC | 0x0 | PPI ErrContentionLP0 Contention detect | +| 3:0 | DPHY_ERR_CONT_LP1 | RWC | 0x0 | PPI ErrContentionLP0 Contention detect | #### DSI_PHY_STATUS_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x194
BitsFieldTypeResetDescription
31DPHY_ULP_STATE_BYTERO0x1All lanes are in ULP state
30DPHY_STOP_STATE_BYTERO0x1PPI Stopstate - All lanes in stop state
29DPHY_CLK_ULPS_ACTIVE_NRO0x1PPI clock UlpsActiveNot
28DPHY_RX_CLK_ULPS_NRO0x1PPI RxUlpsClkNot
27:24DPHY_LANE_DIRRO0x0PPI Direction
23:20DPHY_ULPS_ACTIVE_NRO0xfPPI UlpsActiveNot
19:16DPHY_LANE_RX_LINE_ERRRO0x0PPI ErrControl - Illegal line state detected
15:12DPHY_ERR_ESCRO0x0PPI ErrEsc - Invalid ESC command detected
11:8DPHY_ERR_SYNC_ESCRO0x0PPI ErrSyncEsc - Partial byte detected
7:4DPHY_ERR_CONT_LP0RO0x0PPI ErrContentionLP0 - Contention detect
3:0DPHY_ERR_CONT_LP1RO0x0PPI ErrContentionLP0 - Contention detect
+**Offset: 0x194** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | DPHY_ULP_STATE_BYTE | RO | 0x1 | All lanes are in ULP state | +| 30 | DPHY_STOP_STATE_BYTE | RO | 0x1 | PPI Stopstate - All lanes in stop state | +| 29 | DPHY_CLK_ULPS_ACTIVE_N | RO | 0x1 | PPI clock UlpsActiveNot | +| 28 | DPHY_RX_CLK_ULPS_N | RO | 0x1 | PPI RxUlpsClkNot | +| 27:24 | DPHY_LANE_DIR | RO | 0x0 | PPI Direction | +| 23:20 | DPHY_ULPS_ACTIVE_N | RO | 0xf | PPI UlpsActiveNot | +| 19:16 | DPHY_LANE_RX_LINE_ERR | RO | 0x0 | PPI ErrControl - Illegal line state detected | +| 15:12 | DPHY_ERR_ESC | RO | 0x0 | PPI ErrEsc - Invalid ESC command detected | +| 11:8 | DPHY_ERR_SYNC_ESC | RO | 0x0 | PPI ErrSyncEsc - Partial byte detected | +| 7:4 | DPHY_ERR_CONT_LP0 | RO | 0x0 | PPI ErrContentionLP0 - Contention detect | +| 3:0 | DPHY_ERR_CONT_LP1 | RO | 0x0 | PPI ErrContentionLP0 - Contention detect | #### DSI_PHY_LPRX_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x198
BitsFieldTypeResetDescription
31:28DPHY_LANE_RX_TRG3RO0x0dphy_lane_rx_trg3
27:24DPHY_LANE_RX_TRG2RO0x0dphy_lane_rx_trg2
23:20DPHY_LANE_RX_TRG1RO0x0dphy_lane_rx_trg1
19:16DPHY_LANE_RX_TRG0RO0x0dphy_lane_rx_trg0
15:12DPHY_LANE_RX_ULPSRO0x0dphy_lane_rx_ulps
11:8DPHY_LANE_RX_LPDTRO0x0dphy_lane_rx_lpdt
7:4DPHY_LANE_RX_DVALIDRO0x0dphy_lane_rx_dvalid
3:0DPHY_LANE_RX_CLKRO0x0dphy_lane_rx_clk
+**Offset: 0x198** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | DPHY_LANE_RX_TRG3 | RO | 0x0 | dphy_lane_rx_trg3 | +| 27:24 | DPHY_LANE_RX_TRG2 | RO | 0x0 | dphy_lane_rx_trg2 | +| 23:20 | DPHY_LANE_RX_TRG1 | RO | 0x0 | dphy_lane_rx_trg1 | +| 19:16 | DPHY_LANE_RX_TRG0 | RO | 0x0 | dphy_lane_rx_trg0 | +| 15:12 | DPHY_LANE_RX_ULPS | RO | 0x0 | dphy_lane_rx_ulps | +| 11:8 | DPHY_LANE_RX_LPDT | RO | 0x0 | dphy_lane_rx_lpdt | +| 7:4 | DPHY_LANE_RX_DVALID | RO | 0x0 | dphy_lane_rx_dvalid | +| 3:0 | DPHY_LANE_RX_CLK | RO | 0x0 | dphy_lane_rx_clk | #### DSI_PHY_LPRX_1 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x19c
BitsFieldTypeResetDescription
31:0DPHY_LANE_DOUT_RXRO0x0dphy_lane_dout_rx
+**Offset: 0x19c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | DPHY_LANE_DOUT_RX | RO | 0x0 | dphy_lane_dout_rx | #### DSI_PHY_LPTX_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1a0
BitsFieldTypeResetDescription
31:20DPHY_TX_TRIGGER_ESC_LRO0x0tx_trigger_esc[11:0]
19:16DPHY_TX_ULPS_ESCRO0x0tx_ulps_esc
15:12DPHY_TX_LPDT_ESCRO0x0tx_lpdt_esc
11:8DPHY_TX_VALID_ESCRO0x0tx_valid_esc
7:4DPHY_TX_REQ_ESCRO0x0tx_req_esc
3:0DPHY_LANE_RDY_ESCRO0x0dphy_lane_rdy_esc
+**Offset: 0x1a0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:20 | DPHY_TX_TRIGGER_ESC_L | RO | 0x0 | tx_trigger_esc[11:0] | +| 19:16 | DPHY_TX_ULPS_ESC | RO | 0x0 | tx_ulps_esc | +| 15:12 | DPHY_TX_LPDT_ESC | RO | 0x0 | tx_lpdt_esc | +| 11:8 | DPHY_TX_VALID_ESC | RO | 0x0 | tx_valid_esc | +| 7:4 | DPHY_TX_REQ_ESC | RO | 0x0 | tx_req_esc | +| 3:0 | DPHY_LANE_RDY_ESC | RO | 0x0 | dphy_lane_rdy_esc | #### DSI_PHY_LPTX_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1a4
BitsFieldTypeResetDescription
31:4RSVDRO0Reserved for future use
3:0DPHY_TX_TRIGGER_ESC_HRO0x0tx_trigger_esc[15:12]
+**Offset: 0x1a4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | RSVD | RO | 0 | Reserved for future use | +| 3:0 | DPHY_TX_TRIGGER_ESC_H | RO | 0x0 | tx_trigger_esc[15:12] | #### DSI_PHY_LPTX_2 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1a8
BitsFieldTypeResetDescription
31:0DPHY_TX_DATA_ESCRO0x0tx_data_esc
+**Offset: 0x1a8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | DPHY_TX_DATA_ESC | RO | 0x0 | tx_data_esc | #### DSI_PHY_STATUS_2 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1ac
BitsFieldTypeResetDescription
31:16CFG_TX_REQ_CNT_RRO0x0TX previous request to ready delay count
15:0CFG_TX_REQ_CNTRO0x0TX request to ready delay count
+**Offset: 0x1ac** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | CFG_TX_REQ_CNT_R | RO | 0x0 | TX previous request to ready delay count | +| 15:0 | CFG_TX_REQ_CNT | RO | 0x0 | TX request to ready delay count | #### DSI_PHY_TIME_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1c0
BitsFieldTypeResetDescription
31:24CFG_CSR_TIME_HS_EXITRW0x0Length of HS Exit Period in tx_clk_esc Cycles
This field is used for the time to drive LP-11 after a HS burst. The HS exit period is calculated as:
HS Exit Period = (1 + CFG_CSR_HS_EXIT) / 66 MHz
By default, the DPHY escape clock frequency is 66 MHz. According to the MIPI specification, the minimum value for this period is 100 ns.
23:16CFG_CSR_TIME_HS_TRAILRW0x0DPHY HS Trail Period Length
This field is used for the time to drive the flipped differential state after the last payload data bit of a HS transmission burst. The length of the HS trail period is in tx_clk_esc cycles.
HS Trail Time = (1 + CFG_CSR_HS_TRAIL) / 66 MHz
According to the MIPI specification, the minimum value is defined by:
max(8 * UI, 60 ns + 4 * UI)
15:8CDG_CSR_TIME_HS_ZERORW0x0DPHY HS Zero State Length
This field is used for the time to drive HS-0 before the sync sequence. The length of the HS zero state is in tx_clk_esc cycles.
The HS zero state length should be:
HS Zero State Length ≥ (CFG_CSR_TIME_ZERO/ 66 MHz + 3 * Tbyte_clk
According to the MIPI specification, the minimum value for the sum of Time HS Prep and Time HS Zero is 145 ns + 10 * UI.
7:0CFG_CSR_TIME_HS_PREPRW0x0DPHY HS Prepare State Length
This field is used for the time to drive LP-00 to prepare for HS transmission.
It represents the length of the HS prepare state period in tx_clk_esc cycles.
Time HS Prep = (1 + CFG_CSR_TIME_HS_PREP) / 66 MHz
According to the MIPI specification for DPHY
- the minimum value for this parameter is 40 ns + 4 * UI, and
- the maximum value is 85 ns + 6 * UI.
+**Offset: 0x1c0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | CFG_CSR_TIME_HS_EXIT | RW | 0x0 | Length of HS Exit Period in tx_clk_esc Cycles
This field is used for the time to drive LP-11 after a HS burst. The HS exit period is calculated as:
HS Exit Period = (1 + CFG_CSR_HS_EXIT) / 66 MHz
By default, the DPHY escape clock frequency is 66 MHz. According to the MIPI specification, the minimum value for this period is 100 ns. | +| 23:16 | CFG_CSR_TIME_HS_TRAIL | RW | 0x0 | DPHY HS Trail Period Length
This field is used for the time to drive the flipped differential state after the last payload data bit of a HS transmission burst. The length of the HS trail period is in tx_clk_esc cycles.
HS Trail Time = (1 + CFG_CSR_HS_TRAIL) / 66 MHz
According to the MIPI specification, the minimum value is defined by:
max(8 * UI, 60 ns + 4 * UI) | +| 15:8 | CDG_CSR_TIME_HS_ZERO | RW | 0x0 | DPHY HS Zero State Length
This field is used for the time to drive HS-0 before the sync sequence. The length of the HS zero state is in tx_clk_esc cycles.
The HS zero state length should be:
HS Zero State Length ≥ (CFG_CSR_TIME_ZERO/ 66 MHz + 3 * Tbyte_clk
According to the MIPI specification, the minimum value for the sum of Time HS Prep and Time HS Zero is 145 ns + 10 * UI. | +| 7:0 | CFG_CSR_TIME_HS_PREP | RW | 0x0 | DPHY HS Prepare State Length
This field is used for the time to drive LP-00 to prepare for HS transmission.
It represents the length of the HS prepare state period in tx_clk_esc cycles.
Time HS Prep = (1 + CFG_CSR_TIME_HS_PREP) / 66 MHz
According to the MIPI specification for DPHY
- the minimum value for this parameter is 40 ns + 4 * UI, and
- the maximum value is 85 ns + 6 * UI. | #### DSI_PHY_TIME_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1c4
BitsFieldTypeResetDescription
31:24CFG_CSR_TIME_TA_GETRW0x0Time to Drive LP-00 by New Transmitter in tx_clk_esc cycles
TA Get Time = (1 + CFG_CSR_TIME_TA_GET)/66 MHz
According to the MIPI specification, the typical value is 5 * Tlpx, where Tlpx is the DPHY LP length:
Tlpx = (1 + CFG_CSR_TIME_LPX) / 66 MHz.
23:16CFG_CSR_TIME_TA_GORW0x0Time to Drive LP-00 after Turn Request in tx_clk_esc Cycles
TA Go Time = (1 + TA_GO)/66 MHz
According to the MIPI specification, the typical value is 4*Tlpx.
15:0CFG_CSR_TIME_WAKEUPRW0x0DPHY HS Wakeup Period Length
This field is the recovery time from Ultra-Low Power State (ULPS).
Twakeup = (1 + CFG_CSR_TIME_WAKEUP)/66 MHz
According to the MIPI specification, the minimum value is 1 ms.
+**Offset: 0x1c4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | CFG_CSR_TIME_TA_GET | RW | 0x0 | Time to Drive LP-00 by New Transmitter in tx_clk_esc cycles
TA Get Time = (1 + CFG_CSR_TIME_TA_GET)/66 MHz
According to the MIPI specification, the typical value is 5 * Tlpx, where Tlpx is the DPHY LP length:
Tlpx = (1 + CFG_CSR_TIME_LPX) / 66 MHz. | +| 23:16 | CFG_CSR_TIME_TA_GO | RW | 0x0 | Time to Drive LP-00 after Turn Request in tx_clk_esc Cycles
TA Go Time = (1 + TA_GO)/66 MHz
According to the MIPI specification, the typical value is 4*Tlpx. | +| 15:0 | CFG_CSR_TIME_WAKEUP | RW | 0x0 | DPHY HS Wakeup Period Length
This field is the recovery time from Ultra-Low Power State (ULPS).
Twakeup = (1 + CFG_CSR_TIME_WAKEUP)/66 MHz
According to the MIPI specification, the minimum value is 1 ms. | #### DSI_PHY_TIME_2 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1c8
BitsFieldTypeResetDescription
31:24CFG_CSR_TIME_CK_EXITRW0x0DPHY CLK Exit Period Length in tx_clk_esc cycles
Tck_exit = (1 + CFG_CSR_TIME_CK_EXIT)/66 MHz
This field should use the same value as CFG_CSR_TIME_HS_EXIT
23:16CFG_CSR_TIME_CK_TRAILRW0x0DPHY CLK Trail Period Length in tx_clk_esc cycles
This field is the time to drive HS differential state after the last payload clock bit of an HS transmission burst.
CLK Trail Time = (1 + CFG_CSR_TIME_CK_TRAIL)/66 MHz
According to the MIPI specification, the minimum value is 60 ns.
15:8CFG_CSR_TIME_CK_ZERORW0x0DPHY CLK Zero State Length in tx_clk_esc cycles
This field is the time for lead HS-0 drive period before starting the clock.
Tck_zero = (1 + CFG_CSR_TIME_CK_ZERO)/66 MHz
According to the MIPI specification, the minimum value for (Tck_prep+Tck_zero) is 300 ns, where in <var Product Number> Tck_prep is the same as Time HS Prep defined by CFG_CST_TIME_HS_PREP.
7:0CFG_CSR_TIME_CK_LPXRW0x0DPHY CLK LP Length
This field is the length of CLK Low Power state period in tx_clk_esc cycles.
CLK Lpx Time = Tck_lpx = (1 + CFG_CSR_TIME_CK_LPX) / 66 MHz
This field should be set to the same value as CFG_CST_TIME_LPX.
+**Offset: 0x1c8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | CFG_CSR_TIME_CK_EXIT | RW | 0x0 | DPHY CLK Exit Period Length in tx_clk_esc cycles
Tck_exit = (1 + CFG_CSR_TIME_CK_EXIT)/66 MHz
This field should use the same value as CFG_CSR_TIME_HS_EXIT | +| 23:16 | CFG_CSR_TIME_CK_TRAIL | RW | 0x0 | DPHY CLK Trail Period Length in tx_clk_esc cycles
This field is the time to drive HS differential state after the last payload clock bit of an HS transmission burst.
CLK Trail Time = (1 + CFG_CSR_TIME_CK_TRAIL)/66 MHz
According to the MIPI specification, the minimum value is 60 ns. | +| 15:8 | CFG_CSR_TIME_CK_ZERO | RW | 0x0 | DPHY CLK Zero State Length in tx_clk_esc cycles
This field is the time for lead HS-0 drive period before starting the clock.
Tck_zero = (1 + CFG_CSR_TIME_CK_ZERO)/66 MHz
According to the MIPI specification, the minimum value for (Tck_prep+Tck_zero) is 300 ns, where in <var Product Number> Tck_prep is the same as Time HS Prep defined by CFG_CST_TIME_HS_PREP. | +| 7:0 | CFG_CSR_TIME_CK_LPX | RW | 0x0 | DPHY CLK LP Length
This field is the length of CLK Low Power state period in tx_clk_esc cycles.
CLK Lpx Time = Tck_lpx = (1 + CFG_CSR_TIME_CK_LPX) / 66 MHz
This field should be set to the same value as CFG_CST_TIME_LPX. | #### DSI_PHY_TIME_3 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1cc
BitsFieldTypeResetDescription
31:16RSVDRO0Reserved for future use
15:8CFG_CSR_TIME_LPXRW0x0DPHY LP Length
This field is the length of any Low Power state period in tx_clk_esc cycles.
Lpx Time = Tlpx = (1 + CFG_CSR_TIME_LPX) / 66 MHz
According to the MIPI specification, the minimum value is 50 ns.
7:0CFG_CSR_TIME_REQRDYRW0x0DPHY HS Request to Ready Length
This field is the minimum byte clock cycles of DSI HS TX request to DPHY ready.
Sometimes it may be important for this length to be consistent to maintain precise Vertical and Horizontal timing. In most cases, this parameter should be kept at the default of 0x0.
Total cycles between DSI HS TX request to DPHY ready are composed by DPHY: clock lane timing, gap, data lane timing, and some other items inside DPHY.
- Clock lane timing = (2*(CFG_CSR_TIME_CK_LPX + 1) + (CFG_CSR_TIME_HS_PREP + 1) + (CFG_CSR_TIME_CK_ZERO + 1))/66 MHz
- Gap = (16UI +2)/66 MHz
- Data lane timing = ((2*CFG_CSR_TIME_LPX + 1) + (CFG_CSR_TIME_HS_PREP + 1) + (CFG_CSR_TIME_HS_ZERO + 1))/66 MHz
The formula to calculate the total cycles is:
(1 + CFG_CSR_TIME_REQRDY)/frequecy_byte_clk = (clock lane timing + gap + data lane timing + 10/66 MHz)
Alternative method to get the value:
- After the DSI active panel data flow is running, read the value from Bits [7:0] of the DSI_PHY_STATUS_2 register. This gives the current clock cycle delay between the DSI TX request and DPHY ready.
- Add 2 to the value obtained from the DSI_PHY_STATUS_2 register
The formula is:
CFG_CSR_TIME_REQRDY=(Value read from DSI_PHY_STATUS_2)+2
+**Offset: 0x1cc** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RSVD | RO | 0 | Reserved for future use | +| 15:8 | CFG_CSR_TIME_LPX | RW | 0x0 | DPHY LP Length
This field is the length of any Low Power state period in tx_clk_esc cycles.
Lpx Time = Tlpx = (1 + CFG_CSR_TIME_LPX) / 66 MHz
According to the MIPI specification, the minimum value is 50 ns. | +| 7:0 | CFG_CSR_TIME_REQRDY | RW | 0x0 | DPHY HS Request to Ready Length
This field is the minimum byte clock cycles of DSI HS TX request to DPHY ready.
Sometimes it may be important for this length to be consistent to maintain precise Vertical and Horizontal timing. In most cases, this parameter should be kept at the default of 0x0.
Total cycles between DSI HS TX request to DPHY ready are composed by DPHY: clock lane timing, gap, data lane timing, and some other items inside DPHY.
- Clock lane timing = (2*(CFG_CSR_TIME_CK_LPX + 1) + (CFG_CSR_TIME_HS_PREP + 1) + (CFG_CSR_TIME_CK_ZERO + 1))/66 MHz
- Gap = (16UI +2)/66 MHz
- Data lane timing = ((2*CFG_CSR_TIME_LPX + 1) + (CFG_CSR_TIME_HS_PREP + 1) + (CFG_CSR_TIME_HS_ZERO + 1))/66 MHz
The formula to calculate the total cycles is:
(1 + CFG_CSR_TIME_REQRDY)/frequecy_byte_clk = (clock lane timing + gap + data lane timing + 10/66 MHz)
Alternative method to get the value:
- After the DSI active panel data flow is running, read the value from Bits [7:0] of the DSI_PHY_STATUS_2 register. This gives the current clock cycle delay between the DSI TX request and DPHY ready.
- Add 2 to the value obtained from the DSI_PHY_STATUS_2 register
The formula is:
CFG_CSR_TIME_REQRDY=(Value read from DSI_PHY_STATUS_2)+2 | #### DSI_PHY_CODE_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1d0
BitsFieldTypeResetDescription
31:24CFG_TRIG3_CODERW0x05DPHY Trigger 3 Code
23:16CFG_TRIG2_CODERW0x84DPHY Trigger 2 Code
15:8CFG_TRIG1_CODERW0xBADPHY Trigger 1 Code
7:0CFG_TRIG0_CODERW0x46DPHY Trigger 0 Code
+**Offset: 0x1d0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | CFG_TRIG3_CODE | RW | 0x05 | DPHY Trigger 3 Code | +| 23:16 | CFG_TRIG2_CODE | RW | 0x84 | DPHY Trigger 2 Code | +| 15:8 | CFG_TRIG1_CODE | RW | 0xBA | DPHY Trigger 1 Code | +| 7:0 | CFG_TRIG0_CODE | RW | 0x46 | DPHY Trigger 0 Code | #### DSI_PHY_CODE_1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1d4
BitsFieldTypeResetDescription
31:24CFG_CSR_ULPS_CODERW0x78DPHY Ultra Low Power Code
23:16CFG_CSR_LPDT_CODERW0x87DPHY Low Power Data Transfer Code
15:0RSVDRO0Reserved for future use
+**Offset: 0x1d4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | CFG_CSR_ULPS_CODE | RW | 0x78 | DPHY Ultra Low Power Code | +| 23:16 | CFG_CSR_LPDT_CODE | RW | 0x87 | DPHY Low Power Data Transfer Code | +| 15:0 | RSVD | RO | 0 | Reserved for future use | #### DSI_PHY_ANA_PWR_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1e0
BitsFieldTypeResetDescription
31:9RSVDRO0Reserved for future use
8CFG_DPHY_ANA_RESETBRW0x1DPHY Analog reset
0: Reset DPHY analog
1: De-reset DPHY analog
7:1RSVDRO0Reserved for future use
0CFG_DPHY_ANA_PURW0x1DPHY Analog power up
0: Power down DPHY analog
1: Power up DPHY analog
+**Offset: 0x1e0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:9 | RSVD | RO | 0 | Reserved for future use | +| 8 | CFG_DPHY_ANA_RESETB | RW | 0x1 | DPHY Analog reset
0: Reset DPHY analog
1: De-reset DPHY analog | +| 7:1 | RSVD | RO | 0 | Reserved for future use | +| 0 | CFG_DPHY_ANA_PU | RW | 0x1 | DPHY Analog power up
0: Power down DPHY analog
1: Power up DPHY analog | #### DSI_PHY_ANA_CTRL0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1e4
BitsFieldTypeResetDescription
31:29CFG_DPHY_LPRX_VTTHRW0x2LPRX reference voltage high (20mV per stage)
000: 760mV
001: 780mV
010: 800mV
111: 900 mV
28:26CFG_DPHY_LPRX_VTHLRW0x3LPRX reference voltage low (20mV per stage)
000: 540mV
001: 560mV
010: 580mV
011: 600mV
111: 680 mV
25:24CFG_DPHY_LPTX_RESRW0x2LPRX driver impedance control
10: 200 Ohm
23:21CFG_DPHY_HSTX_RESRW0x4HSTX driver impedance control.
000: 120 Ohm (differential @TT)
100: 100 Ohm
111: 89 ohm
20CFG_DPHY_HSTX_LPRW0x0Low power mode for hstx drivers.
1 = Lower power
0 = Normal
19:17CFG_DPHY_ADJ_DLY_CKRW0x0Adjust delay of CH_CK hstx driver output to manage skew between channels. The delay is 30ps per stage (@tt) .
000: 0 stage
111: 7 stages
16CFG_DPHY_EN_CH_CKRW0x1Enable for CH_CK.
When disabled, CH_CK is power down mode, pad_ckp and pad_ckn are in high-z mode
0: Disable
1: Enable
15:13CFG_DPHY_ADJ_DLY3RW0x0Adjust delay of CH3 hstx driver output to manage skew between channels. The delay is 30ps per stage (@tt) .
000: 0 stage
111: 7 stages
12CFG_DPHY_EN_CH3RW0x1Enable for CH3.
When disabled, CH3 is power down mode, pad_dn3 and pad_p3 are in high-z mode
0: Disable
1: Enable
11:9CFG_DPHY_ADJ_DLY2RW0x0Adjust delay of CH2 hstx driver output to manage skew between channels. The delay is 30ps per stage (@tt) .
000: 0 stage
111: 7 stages
8CFG_DPHY_EN_CH2RW0x1Enable for CH2.
When disabled, CH2 is power down mode, pad_dn2 and pad_p2 are in high-z mode
0: Disable
1: Enable
7:5CFG_DPHY_ADJ_DLY1RW0x0Adjust delay of CH1 hstx driver output to manage skew between channels. The delay is 30ps per stage (@tt) .
000: 0 stage
111: 7 stages
4
CFG_DPHY_EN_CH1RW0x1Enable for CH1.
When disabled, CH1 is power down mode, pad_dn1 and pad_p1 are in high-z mode
0: Disable
1: Enable
3:1CFG_DPHY_ADJ_DLY0RW0x0Adjust delay of CH0 hstx driver output to manage skew between channels. The delay is 30ps per stage (@tt) .
000: 0 stage
111: 7 stages
0CFG_DPHY_EN_CH0RW0x1Enable for CH0.
When disabled, CH0 is power down mode, pad_dn0 and pad_p0 are in high-z mode
0: Disable
1: Enable
+**Offset: 0x1e4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:29 | CFG_DPHY_LPRX_VTTH | RW | 0x2 | LPRX reference voltage high (20mV per stage)
000: 760mV
001: 780mV
010: 800mV
111: 900 mV | +| 28:26 | CFG_DPHY_LPRX_VTHL | RW | 0x3 | LPRX reference voltage low (20mV per stage)
000: 540mV
001: 560mV
010: 580mV
011: 600mV
111: 680 mV | +| 25:24 | CFG_DPHY_LPTX_RES | RW | 0x2 | LPRX driver impedance control
10: 200 Ohm | +| 23:21 | CFG_DPHY_HSTX_RES | RW | 0x4 | HSTX driver impedance control.
000: 120 Ohm (differential @TT)
100: 100 Ohm
111: 89 ohm | +| 20 | CFG_DPHY_HSTX_LP | RW | 0x0 | Low power mode for hstx drivers.
1 = Lower power
0 = Normal | +| 19:17 | CFG_DPHY_ADJ_DLY_CK | RW | 0x0 | Adjust delay of CH_CK hstx driver output to manage skew between channels. The delay is 30ps per stage (@tt) .
000: 0 stage
111: 7 stages | +| 16 | CFG_DPHY_EN_CH_CK | RW | 0x1 | Enable for CH_CK.
When disabled, CH_CK is power down mode, pad_ckp and pad_ckn are in high-z mode
0: Disable
1: Enable | +| 15:13 | CFG_DPHY_ADJ_DLY3 | RW | 0x0 | Adjust delay of CH3 hstx driver output to manage skew between channels. The delay is 30ps per stage (@tt) .
000: 0 stage
111: 7 stages | +| 12 | CFG_DPHY_EN_CH3 | RW | 0x1 | Enable for CH3.
When disabled, CH3 is power down mode, pad_dn3 and pad_p3 are in high-z mode
0: Disable
1: Enable | +| 11:9 | CFG_DPHY_ADJ_DLY2 | RW | 0x0 | Adjust delay of CH2 hstx driver output to manage skew between channels. The delay is 30ps per stage (@tt) .
000: 0 stage
111: 7 stages | +| 8 | CFG_DPHY_EN_CH2 | RW | 0x1 | Enable for CH2.
When disabled, CH2 is power down mode, pad_dn2 and pad_p2 are in high-z mode
0: Disable
1: Enable | +| 7:5 | CFG_DPHY_ADJ_DLY1 | RW | 0x0 | Adjust delay of CH1 hstx driver output to manage skew between channels. The delay is 30ps per stage (@tt) .
000: 0 stage
111: 7 stages | +| 4 | CFG_DPHY_EN_CH1 | RW | 0x1 | Enable for CH1.
When disabled, CH1 is power down mode, pad_dn1 and pad_p1 are in high-z mode
0: Disable
1: Enable | +| 3:1 | CFG_DPHY_ADJ_DLY0 | RW | 0x0 | Adjust delay of CH0 hstx driver output to manage skew between channels. The delay is 30ps per stage (@tt) .
000: 0 stage
111: 7 stages | +| 0 | CFG_DPHY_EN_CH0 | RW | 0x1 | Enable for CH0.
When disabled, CH0 is power down mode, pad_dn0 and pad_p0 are in high-z mode
0: Disable
1: Enable | #### DSI_PHY_ANA_CTRL1 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1e8
BitsFieldTypeResetDescription
31:24RSVDRO0Reserved for future use
23CFG_CLK_SEL
RW0x0DPHY bit clk select
0: PLL_DIV output
1: mipi_bit_clk mux output
22:21RSVDRO0Reserved for future use
20CFG_SWAP_PN_CH3RW0x0swap pn polarity for ch3
19CFG_SWAP_PN_CH2RW0x0swap pn polarity for ch2
18CFG_SWAP_PN_CHCKRW0x0swap pn polarity for ch ck
17CFG_SWAP_PN_CH1RW0x0swap pn polarity for ch1
16CFG_SWAP_PN_CH0RW0x0swap pn polarity for ch0
15CFG_SET_TESTRW0x0Select analog phy self-test
1: enable phy self-test. At this mode, phybypass all control signal 0: disable phy self-test.
14DFG_SET_TEST_LPRW0x0Select LP or HS self-test mode. It is only valid when sel_test is high.
1: LP mode self test
0: HS mode self test
13:12DFG_TEST_PATTERNRW0x0 select self-test pattern generation
00: All 0
01: All 1
10: CK pattern (0101)
11: PRBS7
11CFG_EN_CLK_DIV2RW0x0enable half rate HSTX mode.
When enabled, PHY will work at half the data rate of PLL input clock.
1: enable
0: disable
10:8CFG_DPHY_HSTX_VREFRW0x3hstx vreg control (20mV per stage)
000: 340mV
001: 360mV
011: 400mV
111: 480 mV
7:5CFG_DPHY_LPCD_VTHHRW0x5lpcd reference voltage high (20mV per stage)
000: 300mV
001: 320mV
101: 400mV
111: 440 mV
4:2CFG_DPHY_LPCD_VTHLRW0x2lpcd reference voltage low (20mV per stage)
000: 200mV
001: 220mV
010: 240mV
111: 340 mV
1CFG_DPHY_PULL_DNRW0x1Pull down enable:
1: Enable pull down PAD IO for ch1,ch2,ch3, check when both HSTX and LPTX are not enabled.
0: Disable pull down PAD IO for ch1,ch2,ch3, check when both HSTX and LPTX are not enabled. It's high z in this state.
0CFG_DPHY_PULL_DN_CH0RW0x1Pull down enable for ch0
1: Enable pull down PAD IO when all HSTX, LPTX and LPRX are not enabled.
0: Disable pull down PAD IO when both HSTX and LPTX are not enabled. It's high z in this state.
+**Offset: 0x1e8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | RSVD | RO | 0 | Reserved for future use | +| 23 | CFG_CLK_SEL | RW | 0x0 | DPHY bit clk select
0: PLL_DIV output
1: mipi_bit_clk mux output | +| 22:21 | RSVD | RO | 0 | Reserved for future use | +| 20 | CFG_SWAP_PN_CH3 | RW | 0x0 | swap pn polarity for ch3 | +| 19 | CFG_SWAP_PN_CH2 | RW | 0x0 | swap pn polarity for ch2 | +| 18 | CFG_SWAP_PN_CHCK | RW | 0x0 | swap pn polarity for ch ck | +| 17 | CFG_SWAP_PN_CH1 | RW | 0x0 | swap pn polarity for ch1 | +| 16 | CFG_SWAP_PN_CH0 | RW | 0x0 | swap pn polarity for ch0 | +| 15 | CFG_SET_TEST | RW | 0x0 | Select analog phy self-test
1: enable phy self-test. At this mode, phybypass all control signal 0: disable phy self-test. | +| 14 | DFG_SET_TEST_LP | RW | 0x0 | Select LP or HS self-test mode. It is only valid when sel_test is high.
1: LP mode self test
0: HS mode self test | +| 13:12 | DFG_TEST_PATTERN | RW | 0x0 | select self-test pattern generation
00: All 0
01: All 1
10: CK pattern (0101)
11: PRBS7 | +| 11 | CFG_EN_CLK_DIV2 | RW | 0x0 | enable half rate HSTX mode.
When enabled, PHY will work at half the data rate of PLL input clock.
1: enable
0: disable | +| 10:8 | CFG_DPHY_HSTX_VREF | RW | 0x3 | hstx vreg control (20mV per stage)
000: 340mV
001: 360mV
011: 400mV
111: 480 mV | +| 7:5 | CFG_DPHY_LPCD_VTHH | RW | 0x5 | lpcd reference voltage high (20mV per stage)
000: 300mV
001: 320mV
101: 400mV
111: 440 mV | +| 4:2 | CFG_DPHY_LPCD_VTHL | RW | 0x2 | lpcd reference voltage low (20mV per stage)
000: 200mV
001: 220mV
010: 240mV
111: 340 mV | +| 1 | CFG_DPHY_PULL_DN | RW | 0x1 | Pull down enable:
1: Enable pull down PAD IO for ch1, ch2, ch3, check when both HSTX and LPTX are not enabled.
0: Disable pull down PAD IO for ch1, ch2, ch3, check when both HSTX and LPTX are not enabled. It's high z in this state. | +| 0 | CFG_DPHY_PULL_DN_CH0 | RW | 0x1 | Pull down enable for ch0
1: Enable pull down PAD IO when all HSTX, LPTX and LPRX are not enabled.
0: Disable pull down PAD IO when both HSTX and LPTX are not enabled. It's high z in this state. | #### DSI_PHY_DEBUG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1ec
BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0CFG_DDR_CLK_SELRW0x1DDR Clock Select
0: First bit is sent on DDR clock falling edge
1: First bit is sent on DDR clock rising edge
+**Offset: 0x1ec** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:1 | RSVD | RO | 0 | Reserved for future use | +| 0 | CFG_DDR_CLK_SEL | RW | 0x1 | DDR Clock Select
0: First bit is sent on DDR clock falling edge
1: First bit is sent on DDR clock rising edge | ## 12.4 SPI-LCD Display Interface @@ -4177,7 +1225,7 @@ To apply the image capture function, the following parameters should be configur - **startx **= X coordinate of the start point of the capture - **starty** = Y coordinate of the start point of the capture -- **width** = Width (in pixels) of the capture from (X,Y) start point +- **width** = Width (in pixels) of the capture from (X, Y) start point - **height** = Height (in pixels) of the capture from (X, Y) start point - **base_addr** = Memory start address for storing the capture - **pitch** = Distance (in bytes) between the start of two consecutive rows of pixels stored in the memory, including any padding for alignment or hardware requirements @@ -4192,252 +1240,66 @@ The process of the image capture function is depicted below. #### SHADOW_CTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x00C
BitsFieldTypeResetDescription
31SHADOW_FLAGRW0x00x0: No change
0x1: Update parameters
30:1ReservedRO0Reserved for future use
0DIS_SHADOWRW0x00x0: Shadow swap mode
0x1: Direct swap mode
+**Offset: 0x00C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | SHADOW_FLAG | RW | 0x0 | 0x0: No change
0x1: Update parameters | +| 30:1 | Reserved | RO | 0 | Reserved for future use | +| 0 | DIS_SHADOW | RW | 0x0 | 0x0: Shadow swap mode
0x1: Direct swap mode | #### LCD_TVG_START_ADDR0_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x034
BitsFieldTypeResetDescription
31:0TV Path Graphic Frame 0 Starting AddressRW0x0TV Path Graphic Frame 0 Starting Address in bytes
+**Offset: 0x034** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | TV Path Graphic Frame 0 Starting Address | RW | 0x0 | TV Path Graphic Frame 0 Starting Address in bytes | #### LCD_TVG_PITCH_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x3C
BitsFieldTypeResetDescription
31:28TV Backlight Duty Cycle ControlRW0x0Controls the duty cycle percentage of the TV path backlight clock.
- When the <TV Path Backlight Clock Divider> field (i.e., Bit[27:16]) is not 0x0, the backlight is controlled by the clock.
- This field determines the duty cycle:
1. This Field/16 of the cycle is high
2. the rest is low
27:16TV Path Backlight Clock DividerRW0x0Configures the clock divider to generate the TV path backlight control clock.
0xFFF: Generates 32 kHz divided by 4096.
0x1: Generates 32 kHz divided by 2.
If both this field and the <TV Backlight Duty Cycle Control> field (i.e., Bit[31:28]) are 0x0000
- The backlight clock function is disabled;
- The backlight is controlled by the <Dumb LCD TV GPIO Control Pin> field in the Dumb LCD TV Control Register.
15:0TV Path Graphic Memory PitchRW0x0Specifies the TV Path Graphic Memory Pitch in bytes
+**Offset: 0x3C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | TV Backlight Duty Cycle Control | RW | 0x0 | Controls the duty cycle percentage of the TV path backlight clock.
- When the <TV Path Backlight Clock Divider> field (i.e., Bit[27:16]) is not 0x0, the backlight is controlled by the clock.
- This field determines the duty cycle:
1. This Field/16 of the cycle is high
2. the rest is low | +| 27:16 | TV Path Backlight Clock Divider | RW | 0x0 | Configures the clock divider to generate the TV path backlight control clock.
0xFFF: Generates 32 kHz divided by 4096.
0x1: Generates 32 kHz divided by 2.
If both this field and the <TV Backlight Duty Cycle Control> field (i.e., Bit[31:28]) are 0x0000
- The backlight clock function is disabled;
- The backlight is controlled by the <Dumb LCD TV GPIO Control Pin> field in the Dumb LCD TV Control Register. | +| 15:0 | TV Path Graphic Memory Pitch | RW | 0x0 | Specifies the TV Path Graphic Memory Pitch in bytes | #### LCD_TVG_OVSA_HPXL_VLN_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x040
BitsFieldTypeResetDescription
31TV Path Graphic DMA Frame Selection EnableRW0x0This field enables selection of a start frame.
30:28ReservedRO0Reserved for future use
27:16TV Path Graphic Destination Starting Vertical Line on ScreenRW0x0Field Sum Constraint Formula:
This Field Value+"Graphic Vertical Line Number after Zooming" ≤ "Screen Active Vertical Lines"
Where:
- "Graphic Vertical Line Number after Zooming" is from the Graphic Destination Size (after Zooming) Register.
- "Screen Active Vertical Lines" is the value defined in the Total Screen Active Size Register
15:13ReservedRO0Reserved for future use
12TV Path Graphic DMA FrameRW0x0This field is only valid if the <TV Path Graphic DMA Frame Selection Enable> field (i.e. Bit[31])is enabled.
0x0: Select frame 0
0x1: Select frame 1
11:0TV Path Graphic Destination Starting Horizontal Pixel on ScreenRW0x0Field Sum Constraint Formula:
This Field Value+"Graphic Horizontal Pixel Number after Zooming" ≤ "Screen Horizontal Active Pixels"
Where:
- "Graphic Horizontal Pixel Number after Zooming" is from the Graphic Destination Size (after Zooming) Register..
- "Screen Horizontal Active Pixels" is the value defined in the Total Screen Active Size Register.
+**Offset: 0x040** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | TV Path Graphic DMA Frame Selection Enable | RW | 0x0 | This field enables selection of a start frame. | +| 30:28 | Reserved | RO | 0 | Reserved for future use | +| 27:16 | TV Path Graphic Destination Starting Vertical Line on Screen | RW | 0x0 | Field Sum Constraint Formula:
This Field Value+"Graphic Vertical Line Number after Zooming" ≤ "Screen Active Vertical Lines"
Where:
- "Graphic Vertical Line Number after Zooming" is from the Graphic Destination Size (after Zooming) Register.
- "Screen Active Vertical Lines" is the value defined in the Total Screen Active Size Register | +| 15:13 | Reserved | RO | 0 | Reserved for future use | +| 12 | TV Path Graphic DMA Frame | RW | 0x0 | This field is only valid if the <TV Path Graphic DMA Frame Selection Enable> field (i.e. Bit[31])is enabled.
0x0: Select frame 0
0x1: Select frame 1 | +| 11:0 | TV Path Graphic Destination Starting Horizontal Pixel on Screen | RW | 0x0 | Field Sum Constraint Formula:
This Field Value+"Graphic Horizontal Pixel Number after Zooming" ≤ "Screen Horizontal Active Pixels"
Where:
- "Graphic Horizontal Pixel Number after Zooming" is from the Graphic Destination Size (after Zooming) Register..
- "Screen Horizontal Active Pixels" is the value defined in the Total Screen Active Size Register. | #### LCD_TVG_HPXL_VLN_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x044
BitsFieldTypeResetDescription
31:28ReservedRO0Reserved for future use
27:16TV Path Graphic Source Vertical Line NumberRW0x0This field sets the source vertical size of the graphic object in memory before zooming.
15:12ReservedRO0Reserved for future use
11:0TV Path Graphic Source Horizontal Pixel NumberRW0x0This field sets the source horizontal size of the graphic object in memory before zooming.
+**Offset: 0x044** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Reserved | RO | 0 | Reserved for future use | +| 27:16 | TV Path Graphic Source Vertical Line Number | RW | 0x0 | This field sets the source vertical size of the graphic object in memory before zooming. | +| 15:12 | Reserved | RO | 0 | Reserved for future use | +| 11:0 | TV Path Graphic Source Horizontal Pixel Number | RW | 0x0 | This field sets the source horizontal size of the graphic object in memory before zooming. | #### LCD_TVGZM_HPXL_VLN_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x048
BitsFieldTypeResetDescription
31:28ReservedRO0Reserved for future use
27:16TV Path Graphic Destination Vertical Line Number after ZoomingRW0x0This field sets the vertical display size.
- Zooming Down:
If the <Graphic Vertical Line Number> field in the Graphic Source Size Register is greater than this field, the image is scaled down (made smaller).
- Zooming Up:
If the <Graphic Vertical Line Number> field in the Graphic Source Size Register is less than this field, the image is scaled up (made larger).
- No Zooming:
If the <Graphic Vertical Line Number> field in the Graphic Source Size Register is equal to this field, no zooming is performed.
15:12ReservedRO0Reserved for future use
11:0TV Path Graphic Destination Horizontal Pixel Number after ZoomingRW0x0This field sets the horizontal display size.
- Zooming Down:
If the <Graphic Horizontal Pixel Number> in the Graphic Source Size Register is greater than this field, the image is scaled down (made smaller).
- Zooming Up:
If the <Graphic Horizontal Pixel Number> in the Graphic Source Size Register is less than this field, the image is scaled up (made larger).
- No Zooming:
If the <Graphic Horizontal Pixel Number> in the Graphic Source Size Register is equal to this field, no zooming is performed.
+**Offset: 0x048** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Reserved | RO | 0 | Reserved for future use | +| 27:16 | TV Path Graphic Destination Vertical Line Number after Zooming | RW | 0x0 | This field sets the vertical display size.
- Zooming Down:
If the <Graphic Vertical Line Number> field in the Graphic Source Size Register is greater than this field, the image is scaled down (made smaller).
- Zooming Up:
If the <Graphic Vertical Line Number> field in the Graphic Source Size Register is less than this field, the image is scaled up (made larger).
- No Zooming:
If the <Graphic Vertical Line Number> field in the Graphic Source Size Register is equal to this field, no zooming is performed. | +| 15:12 | Reserved | RO | 0 | Reserved for future use | +| 11:0 | TV Path Graphic Destination Horizontal Pixel Number after Zooming | RW | 0x0 | This field sets the horizontal display size.
- Zooming Down:
If the <Graphic Horizontal Pixel Number> in the Graphic Source Size Register is greater than this field, the image is scaled down (made smaller).
- Zooming Up:
If the <Graphic Horizontal Pixel Number> in the Graphic Source Size Register is less than this field, the image is scaled up (made larger).
- No Zooming:
If the <Graphic Horizontal Pixel Number> in the Graphic Source Size Register is equal to this field, no zooming is performed. | #### LCD_TV_COLORKEY_Y_REG REGISTER @@ -4448,48 +1310,14 @@ The process of the image capture function is depicted below. > - Y2 (\): Upper threshold for color keying > - R: Red component in the RGB color model, used as a replacement if graphic color keying is enabled - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x070
BitsFieldTypeResetDescription
31:24TV Path Color Key Y2RW0x0
Defines the maximum Y value (Y2) for color keying. If a pixel’s Y component falls within Y1 to Y2, the system:
- Applies an alpha value <CFG_TV_ALPHA_Y>
- Replaces Y with <CFG_TV_CKEY_Y>
- If graphic color keying is enabled, Y is replaced with R
23:16TV Path Color Key Y1RW0x0Defines the minimum Y value (Y1) for color keying. If a pixel’s Y component falls within Y1 to Y2, the system:
- Applies an alpha value <CFG_TV_ALPHA_Y>
- Replaces Y with <CFG_TV_CKEY_Y>
- If graphic color keying is enabled, Y is replaced with R
15:8TV Path Color Key YRW0x0Specifies the replacement Y value (<CFG_TV_CKEY_Y>) used when the pixel’s Y component is within Y1 to Y2.
If graphic color keying is enabled, Y is replaced with R.
7:0TV Path Color Alpha YRW0x0Defines the alpha transparency level (<CFG_TV_ALPHA_Y>) applied when a pixel’s Y component is within Y1 to Y2.
If graphic color keying is enabled, Y is replaced with R.
+**Offset: 0x070** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | TV Path Color Key Y2 | RW | 0x0 | Defines the maximum Y value (Y2) for color keying. If a pixel’s Y component falls within Y1 to Y2, the system:
- Applies an alpha value <CFG_TV_ALPHA_Y>
- Replaces Y with <CFG_TV_CKEY_Y>
- If graphic color keying is enabled, Y is replaced with R | +| 23:16 | TV Path Color Key Y1 | RW | 0x0 | Defines the minimum Y value (Y1) for color keying. If a pixel’s Y component falls within Y1 to Y2, the system:
- Applies an alpha value <CFG_TV_ALPHA_Y>
- Replaces Y with <CFG_TV_CKEY_Y>
- If graphic color keying is enabled, Y is replaced with R | +| 15:8 | TV Path Color Key Y | RW | 0x0 | Specifies the replacement Y value (<CFG_TV_CKEY_Y>) used when the pixel’s Y component is within Y1 to Y2.
If graphic color keying is enabled, Y is replaced with R. | +| 7:0 | TV Path Color Alpha Y | RW | 0x0 | Defines the alpha transparency level (<CFG_TV_ALPHA_Y>) applied when a pixel’s Y component is within Y1 to Y2.
If graphic color keying is enabled, Y is replaced with R. | #### LCD_TV_COLORKEY_U_REG REGISTER @@ -4500,48 +1328,14 @@ The process of the image capture function is depicted below. > - U2 (\): Upper threshold for color keying > - G: Green component in the RGB color model, used as a replacement if graphic color keying is enabled - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x074
BitsFieldTypeResetDescription
31:24TV Path Color Key U2RW0x0Defines the maximum U value (U2) for color keying. If a pixel’s U component falls within U1 to U2, the system:
- Applies an alpha value <Color Alpha U>
- Replaces U with <TV Path Color Key U>
- If graphic color keying is enabled, U is replaced with G
23:16TV Path Color Key U1RW0x0Defines the minimum U value (U1) for color keying. If a pixel’s U component falls within U1 to U2, the system:
- Applies an alpha value <Color Alpha U>
- Replaces U with <TV Path Color Key U>
- If graphic color keying is enabled, U is replaced with G
15:8TV Path Color Key URW0x0Specifies the replacement U value (<TV Path Color Key U>) applied when the pixel’s U component is within U1 to U2.
If graphic color keying is enabled, U is replaced with G.
7:0TV Path Color Alpha URW0x0Defines the alpha transparency level (<Color Alpha U>) used when a pixel’s U component is within U1 to U2.
If graphic color keying is enabled, U is replaced with G.
+**Offset: 0x074** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | TV Path Color Key U2 | RW | 0x0 | Defines the maximum U value (U2) for color keying. If a pixel’s U component falls within U1 to U2, the system:
- Applies an alpha value <Color Alpha U>
- Replaces U with <TV Path Color Key U>
- If graphic color keying is enabled, U is replaced with G | +| 23:16 | TV Path Color Key U1 | RW | 0x0 | Defines the minimum U value (U1) for color keying. If a pixel’s U component falls within U1 to U2, the system:
- Applies an alpha value <Color Alpha U>
- Replaces U with <TV Path Color Key U>
- If graphic color keying is enabled, U is replaced with G | +| 15:8 | TV Path Color Key U | RW | 0x0 | Specifies the replacement U value (<TV Path Color Key U>) applied when the pixel’s U component is within U1 to U2.
If graphic color keying is enabled, U is replaced with G. | +| 7:0 | TV Path Color Alpha U | RW | 0x0 | Defines the alpha transparency level (<Color Alpha U>) used when a pixel’s U component is within U1 to U2.
If graphic color keying is enabled, U is replaced with G. | #### LCD_TV_COLORKEY_V_REG REGISTER @@ -4552,1052 +1346,258 @@ The process of the image capture function is depicted below. > - V2 (\): Upper threshold for color keying > - B: Blue component in the RGB color model, used as a replacement if graphic color keying is enabled - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x078
BitsFieldTypeResetDescription
31:24TV Path Color Key V2RW0x0Defines the maximum V value (V2) for color keying. If a pixel’s V component falls within V1 to V2, the system:
- Applies an alpha value <Color Alpha V>
- Replaces V with <TV Path Color Key V>
- If graphic color keying is enabled, V is replaced with B
23:16TV Path Color Key V1RW0x0Defines the minimum V value (V1) for color keying. If a pixel’s V component falls within V1 to V2, the system:
- Applies an alpha value <Color Alpha V>
- Replaces V with <TV Path Color Key V>
- If graphic color keying is enabled, V is replaced with B.
15:8TV Path Color Key VRW0x0Specifies the replacement V value (<TV Path Color Key V>) applied when the pixel’s V component is within V1 to V2.
If graphic color keying is enabled, V is replaced with B.
7:0TV Path Color Alpha VRW0x0Defines the alpha transparency level (<Color Alpha V>) used when a pixel’s V component is within V1 to V2.
If graphic color keying is enabled, V is replaced with B.
+**Offset: 0x078** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | TV Path Color Key V2 | RW | 0x0 | Defines the maximum V value (V2) for color keying. If a pixel’s V component falls within V1 to V2, the system:
- Applies an alpha value <Color Alpha V>
- Replaces V with <TV Path Color Key V>
- If graphic color keying is enabled, V is replaced with B | +| 23:16 | TV Path Color Key V1 | RW | 0x0 | Defines the minimum V value (V1) for color keying. If a pixel’s V component falls within V1 to V2, the system:
- Applies an alpha value <Color Alpha V>
- Replaces V with <TV Path Color Key V>
- If graphic color keying is enabled, V is replaced with B. | +| 15:8 | TV Path Color Key V | RW | 0x0 | Specifies the replacement V value (<TV Path Color Key V>) applied when the pixel’s V component is within V1 to V2.
If graphic color keying is enabled, V is replaced with B. | +| 7:0 | TV Path Color Alpha V | RW | 0x0 | Defines the alpha transparency level (<Color Alpha V>) used when a pixel’s V component is within V1 to V2.
If graphic color keying is enabled, V is replaced with B. | #### LCD_TV_CTRL0_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x80
BitsFieldTypeResetDescription
31:30ReservedRO0Reserved for future use
29TV Path Video Contrast/Saturation/Brightness/Hue Adjust EnableRW0x01: Enabled
0: Disabled
28TV Path Palette Color EnableRW0x01: Enabled
0: Disabled
This field enables the palette color SRAM table when the selected Memory Color Format is palette4bit or palette8bit.
Palette mode can be selected via video or graphic DMA.
> Note. Only one palette table in the TV path.
27:20ReservedRO0Reserved for future use
19:16TV Path Graphic DMA Memory Color FormatRW0x0Defines the graphic DMA memory color format. Options:
0x0: RGB565;
0x1: RGB1555;
0x2: RGB888;
0x3: RGB888 unpacked;
0x4: RGBA888;
0x5: YUV422packed;
0x9: Palette color 4-bit;
0xA: Palette color 8-bit;
0xB: RGB888A;
Others: Reserved.
15ReservedRO0Reserved for future use
14TV Path Graphic Horizontal Smooth EnableRW0x01: Enabled
0: Disabled
13TV Path Graphic DMA Test Mode EnableRW0x01: Enabled
0: Disabled
12TV Path Graphic DMA Swap R and BRW0x01: Swap enabled
0: Swap disabled
Swaps the red (R) and blue (B) channels in the RGB color model (e.g., RGB → BGR).
11TV Path Graphic DMA Swap U and VRW0x01: Swap enabled
0: Disabled
Swaps the U and V components in YUV color space (e.g., YUYV → YVYU).
10TV Path Graphic DMA Swap Y and U/VRW0x01: Swap enabled
0: Disabled
Swaps the Y component with U/V in YUV color space (e.g., UYVY → YUYV).
9TV Path Graphic DMA YUV to RGB Color Space ConversionRW0x0TV Path Graphic DMA YUV to RGB Color Space Conversion, 1 = Enabled; 0 = Disabled. There is only one CSC in the TV path, so either this field or the <TV Path Video DMA YUV to RGB Color Space Conversion> field can be enabled. Both cannot be enabled simultaneously.
1: Enabled
0: Disabled
Converts YUV to RGB color space.
> Note. Either this field or the <TV Path Video DMA YUV to RGB Color Space Conversion> field can be enabled at a time.
8TV Path Graphic DMA Transfer EnableRW0x01: Enable
0: Disabled
7:0ReservedRO0Reserved for future use.
+**Offset: 0x80** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | Reserved | RO | 0 | Reserved for future use | +| 29 | TV Path Video Contrast/Saturation/Brightness/Hue Adjust Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 28 | TV Path Palette Color Enable | RW | 0x0 | 1: Enabled
0: Disabled
This field enables the palette color SRAM table when the selected Memory Color Format is palette4bit or palette8bit.
Palette mode can be selected via video or graphic DMA.
**Note. Only one palette table in the TV path.** | +| 27:20 | Reserved | RO | 0 | Reserved for future use | +| 19:16 | TV Path Graphic DMA Memory Color Format | RW | 0x0 | Defines the graphic DMA memory color format. Options:
0x0: RGB565;
0x1: RGB1555;
0x2: RGB888;
0x3: RGB888 unpacked;
0x4: RGBA888;
0x5: YUV422packed;
0x9: Palette color 4-bit;
0xA: Palette color 8-bit;
0xB: RGB888A;
Others: Reserved. | +| 15 | Reserved | RO | 0 | Reserved for future use | +| 14 | TV Path Graphic Horizontal Smooth Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 13 | TV Path Graphic DMA Test Mode Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 12 | TV Path Graphic DMA Swap R and B | RW | 0x0 | 1: Swap enabled
0: Swap disabled
Swaps the red (R) and blue (B) channels in the RGB color model (e.g., RGB → BGR). | +| 11 | TV Path Graphic DMA Swap U and V | RW | 0x0 | 1: Swap enabled
0: Disabled
Swaps the U and V components in YUV color space (e.g., YUYV → YVYU). | +| 10 | TV Path Graphic DMA Swap Y and U/V | RW | 0x0 | 1: Swap enabled
0: Disabled
Swaps the Y component with U/V in YUV color space (e.g., UYVY → YUYV). | +| 9 | TV Path Graphic DMA YUV to RGB Color Space Conversion | RW | 0x0 | TV Path Graphic DMA YUV to RGB Color Space Conversion, 1 = Enabled; 0 = Disabled. There is only one CSC in the TV path, so either this field or the <TV Path Video DMA YUV to RGB Color Space Conversion> field can be enabled. Both cannot be enabled simultaneously.
1: Enabled
0: Disabled
Converts YUV to RGB color space.
**Note. Either this field or the <TV Path Video DMA YUV to RGB Color Space Conversion> field can be enabled at a time.** | +| 8 | TV Path Graphic DMA Transfer Enable | RW | 0x0 | 1: Enable
0: Disabled | +| 7:0 | Reserved | RO | 0 | Reserved for future use. | #### LCD_TV_CTRL1_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x084
BitsFieldTypeResetDescription
31:27ReservedRO0Reserved for future use
26:24TV Path Color Key ModeRW0x00x0: Disabled color key function
0x1: Video Y (or Graphic R) color key is enabled
0x2: Video U color key is enabled
0x3: Graphic RGB color key is enabled
0x4: Video V color key is enabled
0x5: Video YUV color key is enabled
0x6: Video Luma key is enabled
0x7: Graphic B color key is enabled
23TV Path Configure Low BitsRW0x01: Low bits are the extension of the maximum bit when converting RGB565/1555/4-bit color into 24-bit RGB color.
0: Fill zeros into low bits when converting RGB565/1555/4-bit color into 24-bit RGB color.
22ReservedRO0Reserved for future use
21TV Path Graphic DMA Color Key EnableRW0x01: Enabled
0: Disabled
20TV Path Video DMA Color Key EnableRW0x01: Enabled
0: Disabled
19Panel Path Graphic DMA Color Key EnableRW0x01: Enabled
0: Disabled
18Panel Path Video DMA Color Key EnableRW0x01: Enabled
0: Disabled
17ReservedRO0Reserved for future use
16TV Path Configure Video/Graphic PathRW0x0Selects the panel path graphic alpha for overlay.
0x0: Software configuration,
0x1: Pixel-based configuration.
15:8TV Path Configure AlphaRW0x0This field specifies the alpha value for blending graphics and video in the TV path when no color key alpha or alpha combined with pixel.
- 0xFF: Selects all video, no graphics.
- Other Values: Proportionally blends video and graphics.
7ReservedRO0Reserved for future use
6Re-synchronize Panel Path and TV Path TimingRW0x0This field resynchronizes both timing generation modules when Panel path and TV path are using the same clock.
1: Disable both together, no display
0: Enable both at the same time after setting to 1 and back to 0
5LCD I/O Pads Panel Signals to TVRW0x0Output on LCD I/O Signals [39:0]:
Panel pad signals connect to TV output.
- Bits [3:2]:
The entire path is swapped, including MIPI DSI1, DSI2, and HDMI.
- Bits [5:4]:
The swap only occurs on 40 digital I/O signals.
4
LCD I/O Pads TV Signals to PanelRW0x0On the LCD I/O signals [39:0], TV output signals connect to the Panel path.
- Bits [3:2]:
Swaps the entire signal path, including MIPI DSI1, DSI2, and HDMI.
- Bits [5:4]:
Swaps only 40 digital I/O signals.
3Panel Path Occupies TV InterfaceRW0x0By default, the TV interface is reserved for TV path data. However, this field allows Panel path data to use the TV interface when enabled.
1: Enable Panel path pass-through via TV interface.
0: Disabled (default).
> Note. This feature is only used for testing.
2TV Path Occupies Digital Panel InterfaceRW0x0By default, the digital panel interface is reserved for Panel path data. However, enabling this field allows TV path data to occupy the digital panel interface instead.
1: Enable TV path pass-through via the Panel interface.
0: Disabled (default).
> Note. This feature is only used for testing.
1ReservedRO0Reserved for future use.
0Enable Interlaced Mode on TV InterfaceRW0x0Enables interlaced mode on the TV interface.
1: Interlaced mode enabled,
0: Disabled.
+**Offset: 0x084** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:27 | Reserved | RO | 0 | Reserved for future use | +| 26:24 | TV Path Color Key Mode | RW | 0x0 | 0x0: Disabled color key function
0x1: Video Y (or Graphic R) color key is enabled
0x2: Video U color key is enabled
0x3: Graphic RGB color key is enabled
0x4: Video V color key is enabled
0x5: Video YUV color key is enabled
0x6: Video Luma key is enabled
0x7: Graphic B color key is enabled | +| 23 | TV Path Configure Low Bits | RW | 0x0 | 1: Low bits are the extension of the maximum bit when converting RGB565/1555/4-bit color into 24-bit RGB color.
0: Fill zeros into low bits when converting RGB565/1555/4-bit color into 24-bit RGB color. | +| 22 | Reserved | RO | 0 | Reserved for future use | +| 21 | TV Path Graphic DMA Color Key Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 20 | TV Path Video DMA Color Key Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 19 | Panel Path Graphic DMA Color Key Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 18 | Panel Path Video DMA Color Key Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 17 | Reserved | RO | 0 | Reserved for future use | +| 16 | TV Path Configure Video/Graphic Path | RW | 0x0 | Selects the panel path graphic alpha for overlay.
0x0: Software configuration,
0x1: Pixel-based configuration. | +| 15:8 | TV Path Configure Alpha | RW | 0x0 | This field specifies the alpha value for blending graphics and video in the TV path when no color key alpha or alpha combined with pixel.
- 0xFF: Selects all video, no graphics.
- Other Values: Proportionally blends video and graphics. | +| 7 | Reserved | RO | 0 | Reserved for future use | +| 6 | Re-synchronize Panel Path and TV Path Timing | RW | 0x0 | This field resynchronizes both timing generation modules when Panel path and TV path are using the same clock.
1: Disable both together, no display
0: Enable both at the same time after setting to 1 and back to 0 | +| 5 | LCD I/O Pads Panel Signals to TV | RW | 0x0 | Output on LCD I/O Signals [39:0]:
Panel pad signals connect to TV output.
- Bits [3:2]:
The entire path is swapped, including MIPI DSI1, DSI2, and HDMI.
- Bits [5:4]:
The swap only occurs on 40 digital I/O signals. | +| 4 | LCD I/O Pads TV Signals to Panel | RW | 0x0 | On the LCD I/O signals [39:0], TV output signals connect to the Panel path.
- Bits [3:2]:
Swaps the entire signal path, including MIPI DSI1, DSI2, and HDMI.
- Bits [5:4]:
Swaps only 40 digital I/O signals. | +| 3 | Panel Path Occupies TV Interface | RW | 0x0 | By default, the TV interface is reserved for TV path data. However, this field allows Panel path data to use the TV interface when enabled.
1: Enable Panel path pass-through via TV interface.
0: Disabled (default).
**Note. This feature is only used for testing.** | +| 2 | TV Path Occupies Digital Panel Interface | RW | 0x0 | By default, the digital panel interface is reserved for Panel path data. However, enabling this field allows TV path data to occupy the digital panel interface instead.
1: Enable TV path pass-through via the Panel interface.
0: Disabled (default).
**Note. This feature is only used for testing.** | +| 1 | Reserved | RO | 0 | Reserved for future use. | +| 0 | Enable Interlaced Mode on TV Interface | RW | 0x0 | Enables interlaced mode on the TV interface.
1: Interlaced mode enabled,
0: Disabled. | #### LCD_TV_CONTRAST_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x088
BitsFieldTypeResetDescription
31:16TV Path Video Brightness ControlRW0x0Bits [15:8] are used for sign extension. Bits [7:0] are used for integer brightness control. All adjustments are performed before CSC, brightness change range is +/- 0 to 255. These bits are 2's complement code.
- Bits [15:8]: Used for sign extension.
- Bits [7:0]: Define the integer brightness level.
Adjustments are applied before color space conversion (CSC).
Brightness control range: ±0 to 255 (represented in two’s complement format).
15:0TV Path Video Contrast ControlRW0x0- Bit [15]: Sign bit.
- Bit [14]: Integer part.
- Bits [13:0]: Fractional contrast value.
Contrast control is represented in two’s complement format.
Example contrast settings:
- 0x4000 → Ratio 1.0 (no change)
- 0x6000 → Ratio 1.5 (increase)
- 0x2000 → Ratio 0.5 (decrease)
+**Offset: 0x088** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | TV Path Video Brightness Control | RW | 0x0 | Bits [15:8] are used for sign extension. Bits [7:0] are used for integer brightness control. All adjustments are performed before CSC, brightness change range is +/- 0 to 255. These bits are 2's complement code.
- Bits [15:8]: Used for sign extension.
- Bits [7:0]: Define the integer brightness level.
Adjustments are applied before color space conversion (CSC).
Brightness control range: ±0 to 255 (represented in two’s complement format). | +| 15:0 | TV Path Video Contrast Control | RW | 0x0 | - Bit [15]: Sign bit.
- Bit [14]: Integer part.
- Bits [13:0]: Fractional contrast value.
Contrast control is represented in two’s complement format.
Example contrast settings:
- 0x4000 → Ratio 1.0 (no change)
- 0x6000 → Ratio 1.5 (increase)
- 0x2000 → Ratio 0.5 (decrease) | #### LCD_TV_SATURATION_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x08C
BitsFieldTypeResetDescription
31:16TV Path Configure MultiplierRW0x0- Bit [15]: Sign bit.
- Bits [14:13]: Integer part.
- Bits [12:0]: Fractional multiplier value.
Values are represented in two’s complement format.
15:0TV Path Configure SaturationRW0x0- Bit [15]: Sign bit.
- Bit [14]: Integer part.
- Bits [13:0]: Fractional saturation value.
Values are represented in two’s complement format.
+**Offset: 0x08C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | TV Path Configure Multiplier | RW | 0x0 | - Bit [15]: Sign bit.
- Bits [14:13]: Integer part.
- Bits [12:0]: Fractional multiplier value.
Values are represented in two’s complement format. | +| 15:0 | TV Path Configure Saturation | RW | 0x0 | - Bit [15]: Sign bit.
- Bit [14]: Integer part.
- Bits [13:0]: Fractional saturation value.
Values are represented in two’s complement format. | #### LCD_TV_CBSH_HUE_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x090
BitsFieldTypeResetDescription
31:16TV Path Video HUE Sine CorrectionRW0x0Adjusts the HUE of the TV path video using Sine correction.
- Bit [15]: Sign bit.
- Bit [14]: Integer part.
- Bits [13:0]: Fractional sine (delta phase).
Values are represented in two’s complement format.
Formula for Hue Correction:
- Corrected U = U × cos + V × sin
- Corrected V = V × cos - U × sin
Example:
- If CFG_SIN = 0 and CFG_COS = 0x4000, no correction is applied.
15:0TV Path Video HUE Cosine CorrectionRW0x0Adjusts the HUE of the TV path video using Cosine correction.
- Bit [15]: Sign bit.
- Bit [14]: Integer part.
- Bits [13:0]: Fractional cosine (delta phase).
Values are represented in two’s complement format.
Formula for Hue Correction:
- Corrected U = U × cos + V × sin
- Corrected V = V × cos - U × sin
Example:
- If CFG_SIN = 0x2000 and CFG_COS = 0x376D, a 30-degree HUE correction is applied.
+**Offset: 0x090** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | TV Path Video HUE Sine Correction | RW | 0x0 | Adjusts the HUE of the TV path video using Sine correction.
- Bit [15]: Sign bit.
- Bit [14]: Integer part.
- Bits [13:0]: Fractional sine (delta phase).
Values are represented in two’s complement format.
Formula for Hue Correction:
- Corrected U = U × cos + V × sin
- Corrected V = V × cos - U × sin
Example:
- If CFG_SIN = 0 and CFG_COS = 0x4000, no correction is applied. | +| 15:0 | TV Path Video HUE Cosine Correction | RW | 0x0 | Adjusts the HUE of the TV path video using Cosine correction.
- Bit [15]: Sign bit.
- Bit [14]: Integer part.
- Bits [13:0]: Fractional cosine (delta phase).
Values are represented in two’s complement format.
Formula for Hue Correction:
- Corrected U = U × cos + V × sin
- Corrected V = V × cos - U × sin
Example:
- If CFG_SIN = 0x2000 and CFG_COS = 0x376D, a 30-degree HUE correction is applied. | #### LCD_DMA_START_ADDR_Y0_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0C0
BitsFieldTypeResetDescription
31:0Panel Path Video Frame 0 Y Starting AddressRW0x0Panel Path Video Frame 0 Y Starting Address in bytes
+**Offset: 0x0C0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | Panel Path Video Frame 0 Y Starting Address | RW | 0x0 | Panel Path Video Frame 0 Y Starting Address in bytes | #### LCD_DMA_START_ADDR_U0_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0C4
BitsFieldTypeResetDescription
31:0Panel Path Video Frame 0 U Starting Address in bytesRW0x0Panel Path Video Frame 0 U Starting Address in bytes
+**Offset: 0x0C4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | Panel Path Video Frame 0 U Starting Address in bytes | RW | 0x0 | Panel Path Video Frame 0 U Starting Address in bytes | #### LCD_DMA_START_ADDR_V0_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0C8
BitsFieldTypeResetDescription
31:0Panel Path Video Frame 0 V Starting AddressRW0x0Panel Path Video Frame 0 V Starting Address in bytes
+**Offset: 0x0C8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | Panel Path Video Frame 0 V Starting Address | RW | 0x0 | Panel Path Video Frame 0 V Starting Address in bytes | #### LCD_DMA_PITCH_YC_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0E0
BitsFieldTypeResetDescription
31:16ReservedRO0Reserved for future use
15:0Panel Path Video Y PitchRW0x0Panel Path Video Y Pitch in bytes
+**Offset: 0x0E0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0 | Reserved for future use | +| 15:0 | Panel Path Video Y Pitch | RW | 0x0 | Panel Path Video Y Pitch in bytes | #### LCD_DMA_PITCH_UV_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0E4
BitsFieldTypeResetDescription
31:16Panel Path Video V PitchRW0x0Panel Path Video V Pitch in bytes
15:0Panel Path Video U PitchRW0x0Panel Path Video U Pitch in bytes
+**Offset: 0x0E4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Panel Path Video V Pitch | RW | 0x0 | Panel Path Video V Pitch in bytes | +| 15:0 | Panel Path Video U Pitch | RW | 0x0 | Panel Path Video U Pitch in bytes | #### LCD_DMA_OVSA_HPXL_VLN_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0E8
BitsFieldTypeResetDescription
31Panel Path Video DMA Frame Selection EnableRW0x0This field is used to enable Panel Path video DMA to select either frame0 or frame1.
The frame number is controlled by bits [15:13].
1: Enable to select;
0: Disable the function
30:28ReservedRO0Reserved for future use
27:16Panel Path Video Starting Vertical Line on ScreenRW0x0Defines the starting vertical line for Panel Path Video on the screen.
Valid Range: 0 to 0xFFF.
The sum of this field and <Video Vertical Line Number after Zooming> (from the Video Destination Size (After Zooming) Register) must not exceed the active display lines set in <Screen Active Vertical Lines> (from the Total Screen Active Size Register).
15Panel Path Video Y DMA FrameRW0x00: frame0
1: frame1
> Note. This field is only used if the <Panel Path Video DMA Frame Selection Enable> field is disabled.
14Panel Path video U frameRW0x00: frame0
1: frame1
> Note. This field is only used if the <Panel Path Video DMA Frame Selection Enable> field is enabled.
13Panel Path Video V DMA FrameRW0x00: frame0
1: frame1
> Note. This field is only used if the <Panel Path Video DMA Frame Selection Enable> field is enabled.
12Panel Path Smart Panel Command DMA FrameRW0x00: frame0
1: frame1
> Note. This field is only used if the <Panel Path Video DMA Frame Selection Enable> field is enabled.
11:0Panel Path Video Starting Horizontal Pixel on ScreenRW0x0Specifies the starting horizontal pixel position for Panel Path Video on the screen.
Valid Range: 0x0 to 0xFFF
The sum of this field and the <Video Horizontal Pixel Number after Zooming> field (from the Video Destination Size [After Zooming] Register) must not exceed the active display horizontal width defined in the <Screen Horizontal Active Pixels> field (from the Total Screen Active Size Register).
+**Offset: 0x0E8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Panel Path Video DMA Frame Selection Enable | RW | 0x0 | This field is used to enable Panel Path video DMA to select either frame0 or frame1.
The frame number is controlled by bits [15:13].
1: Enable to select;
0: Disable the function | +| 30:28 | Reserved | RO | 0 | Reserved for future use | +| 27:16 | Panel Path Video Starting Vertical Line on Screen | RW | 0x0 | Defines the starting vertical line for Panel Path Video on the screen.
Valid Range: 0 to 0xFFF.
The sum of this field and <Video Vertical Line Number after Zooming> (from the Video Destination Size (After Zooming) Register) must not exceed the active display lines set in <Screen Active Vertical Lines> (from the Total Screen Active Size Register). | +| 15 | Panel Path Video Y DMA Frame | RW | 0x0 | 0: frame0
1: frame1
**Note. This field is only used if the <Panel Path Video DMA Frame Selection Enable> field is disabled.** | +| 14 | Panel Path video U frame | RW | 0x0 | 0: frame0
1: frame1
**Note. This field is only used if the <Panel Path Video DMA Frame Selection Enable> field is enabled.** | +| 13 | Panel Path Video V DMA Frame | RW | 0x0 | 0: frame0
1: frame1
**Note. This field is only used if the <Panel Path Video DMA Frame Selection Enable> field is enabled.** | +| 12 | Panel Path Smart Panel Command DMA Frame | RW | 0x0 | 0: frame0
1: frame1
**Note. This field is only used if the <Panel Path Video DMA Frame Selection Enable> field is enabled.** | +| 11:0 | Panel Path Video Starting Horizontal Pixel on Screen | RW | 0x0 | Specifies the starting horizontal pixel position for Panel Path Video on the screen.
Valid Range: 0x0 to 0xFFF
The sum of this field and the <Video Horizontal Pixel Number after Zooming> field (from the Video Destination Size [After Zooming] Register) must not exceed the active display horizontal width defined in the <Screen Horizontal Active Pixels> field (from the Total Screen Active Size Register). | #### LCD_DMA_HPXL_VLN_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0EC
BitsFieldTypeResetDescription
31:28ReservedRO0Reserved for future use
27:16Panel Path Video Vertical Line NumberRW0x0This field is used for the source vertical size of the video object in memory before zooming.
15:12ReservedRO0Reserved for future use
11:0Panel Path Video Horizontal Pixel NumberRW0x0This field is used for the source horizontal size of the video object in memory before zooming.
+**Offset: 0x0EC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Reserved | RO | 0 | Reserved for future use | +| 27:16 | Panel Path Video Vertical Line Number | RW | 0x0 | This field is used for the source vertical size of the video object in memory before zooming. | +| 15:12 | Reserved | RO | 0 | Reserved for future use | +| 11:0 | Panel Path Video Horizontal Pixel Number | RW | 0x0 | This field is used for the source horizontal size of the video object in memory before zooming. | #### LCD_DMAZM_HPXL_VLN_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0F0
BitsFieldTypeResetDescription
31:28ReservedRO0Reserved for future use
27:16Panel Path Video Vertical Line Destination Number after ZoomingRW0x0Sets the vertical display size after zooming.
- Zoom Down (shrink image):
If the source vertical lines > this field
- Zoom Up (enlarge image):
If the source vertical lines < this field
- No Zoom:
If the source vertical lines = this field
Where the source vertical lines are from the <Video Vertical Line Number> field in the Video Source Size Register
15:12ReservedRO0Reserved for future use
11:0Panel Path Video Horizontal Pixel Destination Number after ZoomingRW0x0Sets the horizontal display size after zooming.
- Zoom Down (shrink image):
If the source horizontal pixels > this field
- Zoom Up (enlarge image):
If the source horizontal pixels < this field
- No Zoom:
If the source horizontal pixels = this field
Where the source horizontal pixels are from the <Video Horizontal Pixel Number> field in Video Source Size Register
+**Offset: 0x0F0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Reserved | RO | 0 | Reserved for future use | +| 27:16 | Panel Path Video Vertical Line Destination Number after Zooming | RW | 0x0 | Sets the vertical display size after zooming.
- Zoom Down (shrink image):
If the source vertical lines > this field
- Zoom Up (enlarge image):
If the source vertical lines < this field
- No Zoom:
If the source vertical lines = this field
Where the source vertical lines are from the <Video Vertical Line Number> field in the Video Source Size Register | +| 15:12 | Reserved | RO | 0 | Reserved for future use | +| 11:0 | Panel Path Video Horizontal Pixel Destination Number after Zooming | RW | 0x0 | Sets the horizontal display size after zooming.
- Zoom Down (shrink image):
If the source horizontal pixels > this field
- Zoom Up (enlarge image):
If the source horizontal pixels < this field
- No Zoom:
If the source horizontal pixels = this field
Where the source horizontal pixels are from the <Video Horizontal Pixel Number> field in Video Source Size Register | #### LCD_GRA_START_ADDR0_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0F4
BitsFieldTypeResetDescription
31:0Panel Path Graphic Frame 0 Starting AddressRW0x0Panel Path Graphic Frame 0 Starting Address in bytes.
+**Offset: 0x0F4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | Panel Path Graphic Frame 0 Starting Address | RW | 0x0 | Panel Path Graphic Frame 0 Starting Address in bytes. | #### LCD_GRA_PITCH_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0FC
BitsFieldTypeResetDescription
31:28Panel Backlight Duty Cycle ControlRW0x0When the <Dumb Panel Backlight Clock Divider> field is not 0x0, the Dumb Panel backlight is controlled by clock, and this field controls the clock duty cycle percentage. This field/16 of the cycle is high, others is low.
Controls the duty cycle percentage for the Dumb Panel backlight when the <Dumb Panel Backlight Clock Divider> field is not 0x0.
- The duty cycle is Field/16 of the cycle (high), with the rest low.
27:16Panel Backlight Clock DividerRW0x0Configures the clock divider to generate the Dumb Panel backlight control clock.
- 0xFFF: Generates 32 kHz divided by 4096.
- 0x1: Generates 32 kHz divided by 2.
If both this field and the <Duty Cycle Control> field> are 0x0000, the backlight clock function is disabled, and the backlight is controlled by the <Dumb LCD Panel GPIO Control Pin> field in the Dumb LCD Panel Control Register.
15:0Panel Path Graphic Memory PitchRW0x0Panel Path Graphic Memory Pitch in bytes
+**Offset: 0x0FC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Panel Backlight Duty Cycle Control | RW | 0x0 | When the <Dumb Panel Backlight Clock Divider> field is not 0x0, the Dumb Panel backlight is controlled by clock, and this field controls the clock duty cycle percentage. This field/16 of the cycle is high, others is low.
Controls the duty cycle percentage for the Dumb Panel backlight when the <Dumb Panel Backlight Clock Divider> field is not 0x0.
- The duty cycle is Field/16 of the cycle (high), with the rest low. | +| 27:16 | Panel Backlight Clock Divider | RW | 0x0 | Configures the clock divider to generate the Dumb Panel backlight control clock.
- 0xFFF: Generates 32 kHz divided by 4096.
- 0x1: Generates 32 kHz divided by 2.
If both this field and the <Duty Cycle Control> field> are 0x0000, the backlight clock function is disabled, and the backlight is controlled by the <Dumb LCD Panel GPIO Control Pin> field in the Dumb LCD Panel Control Register. | +| 15:0 | Panel Path Graphic Memory Pitch | RW | 0x0 | Panel Path Graphic Memory Pitch in bytes | #### LCD_GRA_OVSA_HPXL_VLN_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x100
BitsFieldTypeResetDescription
31Panel Path Graphic DMA Select Frame 0 or 1RW0x01: Enabled
0: Disabled
30:28ReservedRO0Reserved for future use
27:16Panel Path Graphic Destination Starting Vertical Line on ScreenRW0x0The sum of this field and the <Graphic Vertical Line Number after Zooming> field (from the Graphic Destination Size (after Zooming) Register) must not exceed the Screen Active Vertical Lines field (from the Total Screen Active Size Register).
15:13ReservedRO0Reserved for future use
12Panel Path Graphic DMA FrameRW0x0Specifies the frame used for DMA transfer.
1: Frame1
0: Frame0
Note: This field is only valid if the <Panel Path Graphic DMA Select Frame 0 or 1> field is enabled
11:0Panel Path Graphic Destination Starting Horizontal Pixel on ScreenRW0x0The sum of this field and the <Graphic Horizontal Pixel Number after Zooming> field (from the Graphic Destination Size (after Zooming) Register) must not exceed the <Screen Horizontal Active Pixels> field (from the Total Screen Active Size Register).
+**Offset: 0x100** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Panel Path Graphic DMA Select Frame 0 or 1 | RW | 0x0 | 1: Enabled
0: Disabled | +| 30:28 | Reserved | RO | 0 | Reserved for future use | +| 27:16 | Panel Path Graphic Destination Starting Vertical Line on Screen | RW | 0x0 | The sum of this field and the <Graphic Vertical Line Number after Zooming> field (from the Graphic Destination Size (after Zooming) Register) must not exceed the Screen Active Vertical Lines field (from the Total Screen Active Size Register). | +| 15:13 | Reserved | RO | 0 | Reserved for future use | +| 12 | Panel Path Graphic DMA Frame | RW | 0x0 | Specifies the frame used for DMA transfer.
1: Frame1
0: Frame0
Note: This field is only valid if the <Panel Path Graphic DMA Select Frame 0 or 1> field is enabled | +| 11:0 | Panel Path Graphic Destination Starting Horizontal Pixel on Screen | RW | 0x0 | The sum of this field and the <Graphic Horizontal Pixel Number after Zooming> field (from the Graphic Destination Size (after Zooming) Register) must not exceed the <Screen Horizontal Active Pixels> field (from the Total Screen Active Size Register). | #### LCD_GRA_HPXL_VLN_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x104
BitsFieldTypeResetDescription
31:28ReservedRO0Reserved for future use
27:16Panel Path Graphic Source Vertical Line NumberRW0x0This field sets the source vertical size of the graphic object in memory before zooming.
15:12ReservedRO0Reserved for future use
11:0Panel Path Graphic Source Horizontal Pixel NumberRW0x0This field sets the source horizontal size of the graphic object in memory before zooming.
+**Offset: 0x104** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Reserved | RO | 0 | Reserved for future use | +| 27:16 | Panel Path Graphic Source Vertical Line Number | RW | 0x0 | This field sets the source vertical size of the graphic object in memory before zooming. | +| 15:12 | Reserved | RO | 0 | Reserved for future use | +| 11:0 | Panel Path Graphic Source Horizontal Pixel Number | RW | 0x0 | This field sets the source horizontal size of the graphic object in memory before zooming. | #### LCD_GRAZM_HPXL_VLN_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x108
BitsFieldTypeResetDescription
31:28ReservedRO0Reserved for future use
27:16Panel Path Graphic Destination Vertical Line Number after ZoomingRW0x0Sets the vertical display size after zooming.
- Zoom Out (smaller image):
If "the graphic vertical lines" > this field
- Zoom In (larger image):
If "the graphic vertical lines" < this field
- No Zoom:
If "the graphic vertical lines" = this field
Where "the graphic vertical lines" is the <Graphic Vertical Line Number> field from the Graphic Source Size Register
15:12ReservedRO0Reserved for future use
11:0Panel Path Graphic Destination Horizontal Pixel Number after ZoomingRW0x0Sets the horizontal display size after zooming.
- Zoom Out (smaller image):
If "the pixel number" > this field
- Zoom In (larger image):
If "the pixel number" < this field
- No Zoom:
If "the pixel number" = this field
Where "the pixel number" is the <Graphic Horizontal Pixel Number> field from the Graphic Source Size Register.
+**Offset: 0x108** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Reserved | RO | 0 | Reserved for future use | +| 27:16 | Panel Path Graphic Destination Vertical Line Number after Zooming | RW | 0x0 | Sets the vertical display size after zooming.
- Zoom Out (smaller image):
If "the graphic vertical lines" > this field
- Zoom In (larger image):
If "the graphic vertical lines" < this field
- No Zoom:
If "the graphic vertical lines" = this field
Where "the graphic vertical lines" is the <Graphic Vertical Line Number> field from the Graphic Source Size Register | +| 15:12 | Reserved | RO | 0 | Reserved for future use | +| 11:0 | Panel Path Graphic Destination Horizontal Pixel Number after Zooming | RW | 0x0 | Sets the horizontal display size after zooming.
- Zoom Out (smaller image):
If "the pixel number" > this field
- Zoom In (larger image):
If "the pixel number" < this field
- No Zoom:
If "the pixel number" = this field
Where "the pixel number" is the <Graphic Horizontal Pixel Number> field from the Graphic Source Size Register. | #### LCD_PN_V_H_ACTIVE_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x118
BitsFieldTypeResetDescription
31:28ReservedRO0Reserved for future use
27:16Panel Path Screen Active Vertical LinesRW0x0This field sets the active vertical screen display size for both Dumb Panel and Smart Panel.
15:12ReservedRO0Reserved for future use
11:0Panel Path Screen Horizontal Active PixelsRW0x0This field sets the active horizontal screen display width for both Dumb Panel and Smart Panel.
+**Offset: 0x118** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Reserved | RO | 0 | Reserved for future use | +| 27:16 | Panel Path Screen Active Vertical Lines | RW | 0x0 | This field sets the active vertical screen display size for both Dumb Panel and Smart Panel. | +| 15:12 | Reserved | RO | 0 | Reserved for future use | +| 11:0 | Panel Path Screen Horizontal Active Pixels | RW | 0x0 | This field sets the active horizontal screen display width for both Dumb Panel and Smart Panel. | #### LCD_PN_BLANKCOLOR_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x124
BitsFieldTypeResetDescription
31:24ReservedRO0Reserved for future use
23:0Panel Path Background ColorRW0x0Defines the background color displayed when no objects overlay it or when no valid pixels exist within the active area.
- Bits [7:0]: Red component.
- Bits [15:8]: Green component.
- Bits [23:16]: Blue component.
+**Offset: 0x124** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Reserved | RO | 0 | Reserved for future use | +| 23:0 | Panel Path Background Color | RW | 0x0 | Defines the background color displayed when no objects overlay it or when no valid pixels exist within the active area.
- Bits [7:0]: Red component.
- Bits [15:8]: Green component.
- Bits [23:16]: Blue component. | #### LCD_PN_ALPHA_COLOR1_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x128
BitsFieldTypeResetDescription
31:24ReservedRO0Reserved for future use
23:0Panel Path Hardware Cursor Color 1RW0x0- Bits [7:0]: Red component.
- Bits [15:8]: Green component.
- Bits [23:16]: Blue component.
+**Offset: 0x128** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Reserved | RO | 0 | Reserved for future use | +| 23:0 | Panel Path Hardware Cursor Color 1 | RW | 0x0 | - Bits [7:0]: Red component.
- Bits [15:8]: Green component.
- Bits [23:16]: Blue component. | #### LCD_PN_ALPHA_COLOR2_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x12C
BitsFieldTypeResetDescription
31:24ReservedRO0Reserved for future use
23:0Panel Path Hardware Cursor Color 2RW0x0- Bits [7:0]: Red component.
- Bits [15:8]: Green component.
- Bits [23:16]: Blue component.
+**Offset: 0x12C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Reserved | RO | 0 | Reserved for future use | +| 23:0 | Panel Path Hardware Cursor Color 2 | RW | 0x0 | - Bits [7:0]: Red component.
- Bits [15:8]: Green component.
- Bits [23:16]: Blue component. | #### LCD_PN_COLORKEY_Y_REG REGISTER @@ -5608,48 +1608,14 @@ The process of the image capture function is depicted below. > - Y2 (\): Upper threshold for color keying > - R: Red component in the RGB color model, used as a replacement if graphic color keying is enabled - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x130
BitsFieldTypeResetDescription
31:24Panel Path Color Key Y2RW0x0Defines the maximum Y value (Y2) for color keying. If a pixel’s Y component falls within Y1 to Y2, the system:
- Applies an alpha value <CFG_PN_ALPHA_Y>
- Replaces Y with <CFG_PN_CKEY_Y>
- If graphic color keying is enabled, Y is replaced with R
23:16Panel Path Color Key Y1RW0x0Defines the minimum Y value (Y1) for color keying. If a pixel’s Y component falls within Y1 to Y2, the system:
- Applies an alpha value <CFG_PN_ALPHA_Y>
- Replaces Y with <CFG_PN_CKEY_Y>
- If graphic color keying is enabled, Y is replaced with R
15:8Panel Path Color Key YRW0x0Specifies the replacement Y value (<CFG_PN_CKEY_Y>) used when the pixel’s Y component is within Y1 to Y2.
If graphic color keying is enabled, Y is replaced with R.
7:0Panel Path Color Alpha YRW0x0Defines the alpha transparency level (<CFG_PN_ALPHA_Y>) applied when a pixel’s Y component is within Y1 to Y2.
If graphic color keying is enabled, Y is replaced with R.
+**Offset: 0x130** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Panel Path Color Key Y2 | RW | 0x0 | Defines the maximum Y value (Y2) for color keying. If a pixel’s Y component falls within Y1 to Y2, the system:
- Applies an alpha value <CFG_PN_ALPHA_Y>
- Replaces Y with <CFG_PN_CKEY_Y>
- If graphic color keying is enabled, Y is replaced with R | +| 23:16 | Panel Path Color Key Y1 | RW | 0x0 | Defines the minimum Y value (Y1) for color keying. If a pixel’s Y component falls within Y1 to Y2, the system:
- Applies an alpha value <CFG_PN_ALPHA_Y>
- Replaces Y with <CFG_PN_CKEY_Y>
- If graphic color keying is enabled, Y is replaced with R | +| 15:8 | Panel Path Color Key Y | RW | 0x0 | Specifies the replacement Y value (<CFG_PN_CKEY_Y>) used when the pixel’s Y component is within Y1 to Y2.
If graphic color keying is enabled, Y is replaced with R. | +| 7:0 | Panel Path Color Alpha Y | RW | 0x0 | Defines the alpha transparency level (<CFG_PN_ALPHA_Y>) applied when a pixel’s Y component is within Y1 to Y2.
If graphic color keying is enabled, Y is replaced with R. | #### LCD_PN_COLORKEY_U_REG REGISTER @@ -5660,48 +1626,14 @@ The process of the image capture function is depicted below. > - U2 (\): Upper threshold for color keying > - G: Green component in the RGB color model, used as a replacement if graphic color keying is enabled - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x134
BitsFieldTypeResetDescription
31:24Panel Path Color Key U2RW0x0Defines the maximum U value (U2) for color keying. If a pixel’s U component falls within U1 to U2, the system:
- Applies an alpha value <Color Alpha U>
- Replaces U with <Panel Path Color Key U>
- If graphic color keying is enabled, U is replaced with G
23:16Panel Path Color Key U1RW0x0Defines the minimum U value (U1) for color keying. If a pixel’s U component falls within U1 to U2, the system:
- Applies an alpha value <Color Alpha U>
- Replaces U with <Panel Path Color Key U>
- If graphic color keying is enabled, U is replaced with G
15:8Panel Path Color Key URW0x0Specifies the replacement U value (<Panel Path Color Key U>) applied when the pixel’s U component is within U1 to U2.
If graphic color keying is enabled, U is replaced with G.
7:0Panel Path Color Alpha URW0x0Defines the alpha transparency level (<Color Alpha U>) used when a pixel’s U component is within U1 to U2.
If graphic color keying is enabled, U is replaced with G.
+**Offset: 0x134** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Panel Path Color Key U2 | RW | 0x0 | Defines the maximum U value (U2) for color keying. If a pixel’s U component falls within U1 to U2, the system:
- Applies an alpha value <Color Alpha U>
- Replaces U with <Panel Path Color Key U>
- If graphic color keying is enabled, U is replaced with G | +| 23:16 | Panel Path Color Key U1 | RW | 0x0 | Defines the minimum U value (U1) for color keying. If a pixel’s U component falls within U1 to U2, the system:
- Applies an alpha value <Color Alpha U>
- Replaces U with <Panel Path Color Key U>
- If graphic color keying is enabled, U is replaced with G | +| 15:8 | Panel Path Color Key U | RW | 0x0 | Specifies the replacement U value (<Panel Path Color Key U>) applied when the pixel’s U component is within U1 to U2.
If graphic color keying is enabled, U is replaced with G. | +| 7:0 | Panel Path Color Alpha U | RW | 0x0 | Defines the alpha transparency level (<Color Alpha U>) used when a pixel’s U component is within U1 to U2.
If graphic color keying is enabled, U is replaced with G. | #### LCD_PN_COLORKEY_V_REG REGISTER @@ -5712,3149 +1644,651 @@ The process of the image capture function is depicted below. > - V2 (\): Upper threshold for color keying > - B: Blue component in the RGB color model, used as a replacement if graphic color keying is enabled - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x138
BitsFieldTypeResetDescription
31:24Panel Path Color Key V2RW0x0Defines the maximum V value (V2) for color keying. If a pixel’s V component falls within V1 to V2, the system:
- Applies an alpha value <Color Alpha V>
- Replaces V with <Panel Path Color Key V>
- If graphic color keying is enabled, V is replaced with B
23:16Panel Path Color Key V1RW0x0Defines the minimum V value (V1) for color keying. If a pixel’s V component falls within V1 to V2, the system:
- Applies an alpha value <Color Alpha V>
- Replaces V with <Panel Path Color Key V>
- If graphic color keying is enabled, V is replaced with B.
15:8Panel Path Color Key VRW0x0Specifies the replacement V value (<Panel Path Color Key V>) applied when the pixel’s V component is within V1 to V2.
If graphic color keying is enabled, V is replaced with B.
7:0Panel Path Color Alpha VRW0x0Defines the alpha transparency level (<Color Alpha V>) used when a pixel’s V component is within V1 to V2.
If graphic color keying is enabled, V is replaced with B.
+**Offset: 0x138** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Panel Path Color Key V2 | RW | 0x0 | Defines the maximum V value (V2) for color keying. If a pixel’s V component falls within V1 to V2, the system:
- Applies an alpha value <Color Alpha V>
- Replaces V with <Panel Path Color Key V>
- If graphic color keying is enabled, V is replaced with B | +| 23:16 | Panel Path Color Key V1 | RW | 0x0 | Defines the minimum V value (V1) for color keying. If a pixel’s V component falls within V1 to V2, the system:
- Applies an alpha value <Color Alpha V>
- Replaces V with <Panel Path Color Key V>
- If graphic color keying is enabled, V is replaced with B. | +| 15:8 | Panel Path Color Key V | RW | 0x0 | Specifies the replacement V value (<Panel Path Color Key V>) applied when the pixel’s V component is within V1 to V2.
If graphic color keying is enabled, V is replaced with B. | +| 7:0 | Panel Path Color Alpha V | RW | 0x0 | Defines the alpha transparency level (<Color Alpha V>) used when a pixel’s V component is within V1 to V2.
If graphic color keying is enabled, V is replaced with B. | #### LCD_PN_SEPXLCNT_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x13C
BitsFieldTypeResetDescription
31:28Debug Read IndexRW0x0Specifies the read port index for the Panel Slave Path Status and Debug Register.
0: Normal function
27:16Panel Path VSYNC Falling Edge Pixel Position of the LineRW0x0This field is used for the Panel Path horizontal pixel count from the first valid pixel to the VSYNC pulse falling edge point. VSYNC pulse is configured by both line number and pixel number.
15:12ReservedRO0Reserved for future use
11:0Panel Path VSYNC Rising Edge Pixel Position of the LineRW0x0This field is used for the Panel Path horizontal pixel count from the first valid pixel to the VSYNC pulse rising edge point. VSYNC pulse is configured by both line number and pixel number.
+**Offset: 0x13C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Debug Read Index | RW | 0x0 | Specifies the read port index for the Panel Slave Path Status and Debug Register.
0: Normal function | +| 27:16 | Panel Path VSYNC Falling Edge Pixel Position of the Line | RW | 0x0 | This field is used for the Panel Path horizontal pixel count from the first valid pixel to the VSYNC pulse falling edge point. VSYNC pulse is configured by both line number and pixel number. | +| 15:12 | Reserved | RO | 0 | Reserved for future use | +| 11:0 | Panel Path VSYNC Rising Edge Pixel Position of the Line | RW | 0x0 | This field is used for the Panel Path horizontal pixel count from the first valid pixel to the VSYNC pulse rising edge point. VSYNC pulse is configured by both line number and pixel number. | #### LCD_SPI_RXDATA_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x140
BitsFieldTypeResetDescription
31:0SPI Read DataRO0x0SPI Read Data
+**Offset: 0x140** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | SPI Read Data | RO | 0x0 | SPI Read Data | #### LCD_ISA_RXDATA_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x144
BitsFieldTypeResetDescription
31:016-bit or 8-bit Smart Panel Read DataRO0x0If the <Configure Command Format> field in the Smart Panel 8-bit Bus Control Register is set to 16-bit format:
- Bits [7:0] contain the last read data
- Bits [15:8] contain the second last read data
+**Offset: 0x144** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | 16-bit or 8-bit Smart Panel Read Data | RO | 0x0 | If the <Configure Command Format> field in the Smart Panel 8-bit Bus Control Register is set to 16-bit format:
- Bits [7:0] contain the last read data
- Bits [15:8] contain the second last read data | #### LCD_READ_IOPAD_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x148
BitsFieldTypeResetDescription
31:28ReservedRO0Reserved for future use
27:0I/O Pad Read ValueRO0x0This field contains the read value of the Digital Panel interface I/O pad [27:0].
This is useful for I/O pad checking and GPIO read data.
+**Offset: 0x148** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Reserved | RO | 0 | Reserved for future use | +| 27:0 | I/O Pad Read Value | RO | 0x0 | This field contains the read value of the Digital Panel interface I/O pad [27:0].
This is useful for I/O pad checking and GPIO read data. | #### LCD_DMAVLD_YC_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14C
BitsFieldTypeResetDescription
31Panel Video Path Y Starting Address Update FlagRO0x00: Update enabled
1: Update disabled
30Panel Video Path U Starting Address Update FlagRO0x00: Update enabled
1: Update disabled
29Panel Video Path V Starting Address Update FlagRO0x00: Update enabled
1: Update disabled
28Panel Graphic Path Starting Address Update FlagRO0x00: Update enabled
1: Update disabled
27TV Video Path Y Starting Address Update FlagRO0x00: Update enabled
1: Update disabled
26TV Video Path U Starting Address Update FlagRO0x00: Update enabled
1: Update disabled
25TV Video Path V Starting Address Update FlagRO0x00: Update enabled
1: Update disabled
24TV Graphic Path Starting Address Update FlagRO0x00: Update enabled
1: Update disabled
23Panel Path Smart Panel Command Starting Address Update FlagRO0x00: Update enabled
1: Update disabled
22tvd_sa_cflagRW0x0
21:16ReservedRO0Reserved for future use
15:0Panel Path Video Actual Y Line Length in MemoryRO0x0Panel video Path Y valid length in bytes, generated from color format and pixel number of each line
+**Offset: 0x14C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Panel Video Path Y Starting Address Update Flag | RO | 0x0 | 0: Update enabled
1: Update disabled | +| 30 | Panel Video Path U Starting Address Update Flag | RO | 0x0 | 0: Update enabled
1: Update disabled | +| 29 | Panel Video Path V Starting Address Update Flag | RO | 0x0 | 0: Update enabled
1: Update disabled | +| 28 | Panel Graphic Path Starting Address Update Flag | RO | 0x0 | 0: Update enabled
1: Update disabled | +| 27 | TV Video Path Y Starting Address Update Flag | RO | 0x0 | 0: Update enabled
1: Update disabled | +| 26 | TV Video Path U Starting Address Update Flag | RO | 0x0 | 0: Update enabled
1: Update disabled | +| 25 | TV Video Path V Starting Address Update Flag | RO | 0x0 | 0: Update enabled
1: Update disabled | +| 24 | TV Graphic Path Starting Address Update Flag | RO | 0x0 | 0: Update enabled
1: Update disabled | +| 23 | Panel Path Smart Panel Command Starting Address Update Flag | RO | 0x0 | 0: Update enabled
1: Update disabled | +| 22 | tvd_sa_cflag | RW | 0x0 | | +| 21:16 | Reserved | RO | 0 | Reserved for future use | +| 15:0 | Panel Path Video Actual Y Line Length in Memory | RO | 0x0 | Panel video Path Y valid length in bytes, generated from color format and pixel number of each line | #### LCD_DMAVLD_UV_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x150
BitsFieldTypeResetDescription
31:20ReservedRO0Reserved for future use
19:10Panel Path Video Actual V Line Length in MemoryRO0x0Panel video Path U valid length in bytes, generated from color format and pixel number of each line.
9:0Panel Path Video Actual U Line Length in MemoryRO0x0Panel video Path V valid length in bytes, generated from color format and pixel number of each line.
+**Offset: 0x150** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:20 | Reserved | RO | 0 | Reserved for future use | +| 19:10 | Panel Path Video Actual V Line Length in Memory | RO | 0x0 | Panel video Path U valid length in bytes, generated from color format and pixel number of each line. | +| 9:0 | Panel Path Video Actual U Line Length in Memory | RO | 0x0 | Panel video Path V valid length in bytes, generated from color format and pixel number of each line. | #### LCD_TVGGRAVLD_HLEN_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x154
BitsFieldTypeResetDescription
31:16TV Path Graphic Actual Line Length in MemoryRO0x0TV graphic Path Y valid length in bytes, generated from color format and pixel number of each line.
15:0Panel Path Graphic Actual Line Length in MemoryRO0x0Panel graphic Path Y valid length in bytes, generated from color format and pixel number of each line.
+**Offset: 0x154** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | TV Path Graphic Actual Line Length in Memory | RO | 0x0 | TV graphic Path Y valid length in bytes, generated from color format and pixel number of each line. | +| 15:0 | Panel Path Graphic Actual Line Length in Memory | RO | 0x0 | Panel graphic Path Y valid length in bytes, generated from color format and pixel number of each line. | #### LCD_PN_GAMMA_RDDAT_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x15C
BitsFieldTypeResetDescription
31:8ReservedRO0Reserved for future use
7:0Panel Path Gamma Table SRAM Read DataRO0x0Panel Path Gamma Table SRAM Read Data
+**Offset: 0x15C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0 | Reserved for future use | +| 7:0 | Panel Path Gamma Table SRAM Read Data | RO | 0x0 | Panel Path Gamma Table SRAM Read Data | #### LCD_PN_PALETTE_RDDAT_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x160
BitsFieldTypeResetDescription
31:24ReservedRO0Reserved for future use
23:0Panel Path Palette Table SRAM Read DataRO0x0Panel Path Palette Table SRAM Read Data
+**Offset: 0x160** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Reserved | RO | 0 | Reserved for future use | +| 23:0 | Panel Path Palette Table SRAM Read Data | RO | 0x0 | Panel Path Palette Table SRAM Read Data | #### LCD_SLV_DBG_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x164
BitsFieldTypeResetDescription
31:20ReservedRO0Reserved for future use
19:12AHB Slave Path FIFO Space CountRO0x20Indicates the available space count (in bytes) in the AHB Slave Path FIFO for the Smart Panel.
This value shows the total bytes of data can be written to the AHB Slave Path Data Port Register.
It’s recommended to check this value before writing to ensure space availability.
The maximum value is 128 bytes.
11:4AHB Slave Path FIFO Data CountRO0x0Indicates the data count (in bytes) in the AHB Slave Path FIFO for the Smart Panel.
The sum of this field and the <AHB Slave Path FIFO Space Count> should equal 0x80, which is the FIFO size.
3:0ReservedRO0Reserved for future use
+**Offset: 0x164** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:20 | Reserved | RO | 0 | Reserved for future use | +| 19:12 | AHB Slave Path FIFO Space Count | RO | 0x20 | Indicates the available space count (in bytes) in the AHB Slave Path FIFO for the Smart Panel.
This value shows the total bytes of data can be written to the AHB Slave Path Data Port Register.
It’s recommended to check this value before writing to ensure space availability.
The maximum value is 128 bytes. | +| 11:4 | AHB Slave Path FIFO Data Count | RO | 0x0 | Indicates the data count (in bytes) in the AHB Slave Path FIFO for the Smart Panel.
The sum of this field and the <AHB Slave Path FIFO Space Count> should equal 0x80, which is the FIFO size. | +| 3:0 | Reserved | RO | 0 | Reserved for future use | #### LCD_TV_GAMMA_RDDAT_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x174
BitsFieldTypeResetDescription
31:8ReservedRO0Reserved for future use
7:0TV Path Gamma Table SRAM Read DataRO0x0TV Path Gamma Table SRAM Read Data
+**Offset: 0x174** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0 | Reserved for future use | +| 7:0 | TV Path Gamma Table SRAM Read Data | RO | 0x0 | TV Path Gamma Table SRAM Read Data | #### LCD_TV_PALETTE_RDDAT_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x178
BitsFieldTypeResetDescription
31:24ReservedRO0Reserved for future use
23:0TV Path Palette Table SRAM Read DataRO0x0TV Path Palette Table SRAM Read Data
+**Offset: 0x178** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Reserved | RO | 0 | Reserved for future use | +| 23:0 | TV Path Palette Table SRAM Read Data | RO | 0x0 | TV Path Palette Table SRAM Read Data | #### LCD_FRAME_CNT_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x17C
BitsFieldTypeResetDescription
31:16ReservedRO0Reserved for future use
15:14Current IRE Frame Number for TV PathRO0x0Current IRE Frame Number for TV Path
13:12Current CCIC Frame Number for TV PathRO0x0Current CCIC Frame Number for TV Path
11:10Current IRE Frame Number for Panel PathRO0x0Current IRE Frame Number for Panel Path
9:8Current CCIC Frame Number for Panel PathRO0x0Current CCIC Frame Number for Panel Path
7:6TV Current Graphic Frame NumberRO0x0TV Path Current Graphic Frame Number
5:4TV Current Video Frame NumberRO0x0TV Path Current Video Frame Number
3:2Panel Current Graphic Frame NumberRO0x0Panel Path Current Graphic Frame Number
1:0Panel Current Video Frame NumberRO0x0Panel Path Current Video Frame Number
+**Offset: 0x17C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0 | Reserved for future use | +| 15:14 | Current IRE Frame Number for TV Path | RO | 0x0 | Current IRE Frame Number for TV Path | +| 13:12 | Current CCIC Frame Number for TV Path | RO | 0x0 | Current CCIC Frame Number for TV Path | +| 11:10 | Current IRE Frame Number for Panel Path | RO | 0x0 | Current IRE Frame Number for Panel Path | +| 9:8 | Current CCIC Frame Number for Panel Path | RO | 0x0 | Current CCIC Frame Number for Panel Path | +| 7:6 | TV Current Graphic Frame Number | RO | 0x0 | TV Path Current Graphic Frame Number | +| 5:4 | TV Current Video Frame Number | RO | 0x0 | TV Path Current Video Frame Number | +| 3:2 | Panel Current Graphic Frame Number | RO | 0x0 | Panel Path Current Graphic Frame Number | +| 1:0 | Panel Current Video Frame Number | RO | 0x0 | Panel Path Current Video Frame Number | #### LCD_SPI_CTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x180
BitsFieldTypeResetDescription
31Configure SPI dcxRW0x0Configures the dcx bit for SPI 4-wire mode, either in command or data mode.
30:24Configure SPI Clock DividerRW0x0Defines the SPI clock divider with the valid values ranging from 0xFF to 0x02, used to generate the SPI clock from the panel path pixel clock.
23:16Configure SPI ReceiveRW0x00x1F: Read/receive 32 bits
0x01: Read/receive 2 bits
0x00: Receive disabled
- If the <Configure SPI Transmit> field is set to 0x00, only receive operations are allowed. The maximum length per trigger (write 0x01 to the <Start SPI Transfer> field) is 32 bits, but unlimited read length can be achieved by triggering repeatedly when the <Configure Continuous Transfer> field is set to 0x1.
- If the <Configure SPI Transmit> field is not 0x00, it will first transmit serial bits, then receive serial bits.
15:8Configure SPI TransmitRW0x00x1F = Write/transmit 32 bits
0x01 = Write/transmit 2 bits
0x00 = Do not transfer
- If the <Configure SPI Receive> field is set to 0x00, only transmission occurs. The maximum write length is 32 bits per trigger, but unlimited write length is possible when triggering repeatedly when the <Configure Continuous Transfer> field is set to 0x1.
- If the <Configure SPI Receive> field is not 0x00, it will first transmit serial bits, and then receive incoming bits.
7Configure Clock InverseRW0x00: SPI clock rising edge samples the data, falling edge sends out data.
1: SPI clock falling edge samples the data, rising edge sends out data.
6Configure continuous TransferRW0x0When set to 1, the SPI chip select is kept low until this bit is cleared, allowing continuous shifting of bits (in or out).
5Configure Receive orderRW0x00: Receive from higher bit to bit 0.
1: Receive from bit 0 to higher bit.
4Configure Transmit orderRW0x00: Transfer from higher bit to bit 0.
1: Transfer from bit 0 to higher bit.
3Enable SPIRW0x00: Disabled
1: Enabled
2Configure SPI PortRW0x00: SPI port 0
1: SPI port 1
1Configure 3-/4-Wire SPIRW0x01: 3-wire SPI (SPI_DIN used for both transmit and receive).
0: 4-wire SPI (SPI_DIN for data from the product to the SPI panel, SPI_DOUT for data from the SPI panel to the product).
0Start SPI TransferRW0x01: Start the transfer (requires the <Enable SPI> field is set to be 1).
0: Transfer not started.
+**Offset: 0x180** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Configure SPI dcx | RW | 0x0 | Configures the dcx bit for SPI 4-wire mode, either in command or data mode. | +| 30:24 | Configure SPI Clock Divider | RW | 0x0 | Defines the SPI clock divider with the valid values ranging from 0xFF to 0x02, used to generate the SPI clock from the panel path pixel clock. | +| 23:16 | Configure SPI Receive | RW | 0x0 | 0x1F: Read/receive 32 bits
0x01: Read/receive 2 bits
0x00: Receive disabled
- If the <Configure SPI Transmit> field is set to 0x00, only receive operations are allowed. The maximum length per trigger (write 0x01 to the <Start SPI Transfer> field) is 32 bits, but unlimited read length can be achieved by triggering repeatedly when the <Configure Continuous Transfer> field is set to 0x1.
- If the <Configure SPI Transmit> field is not 0x00, it will first transmit serial bits, then receive serial bits. | +| 15:8 | Configure SPI Transmit | RW | 0x0 | 0x1F = Write/transmit 32 bits
0x01 = Write/transmit 2 bits
0x00 = Do not transfer
- If the <Configure SPI Receive> field is set to 0x00, only transmission occurs. The maximum write length is 32 bits per trigger, but unlimited write length is possible when triggering repeatedly when the <Configure Continuous Transfer> field is set to 0x1.
- If the <Configure SPI Receive> field is not 0x00, it will first transmit serial bits, and then receive incoming bits. | +| 7 | Configure Clock Inverse | RW | 0x0 | 0: SPI clock rising edge samples the data, falling edge sends out data.
1: SPI clock falling edge samples the data, rising edge sends out data. | +| 6 | Configure continuous Transfer | RW | 0x0 | When set to 1, the SPI chip select is kept low until this bit is cleared, allowing continuous shifting of bits (in or out). | +| 5 | Configure Receive order | RW | 0x0 | 0: Receive from higher bit to bit 0.
1: Receive from bit 0 to higher bit. | +| 4 | Configure Transmit order | RW | 0x0 | 0: Transfer from higher bit to bit 0.
1: Transfer from bit 0 to higher bit. | +| 3 | Enable SPI | RW | 0x0 | 0: Disabled
1: Enabled | +| 2 | Configure SPI Port | RW | 0x0 | 0: SPI port 0
1: SPI port 1 | +| 1 | Configure 3-/4-Wire SPI | RW | 0x0 | 1: 3-wire SPI (SPI_DIN used for both transmit and receive).
0: 4-wire SPI (SPI_DIN for data from the product to the SPI panel, SPI_DOUT for data from the SPI panel to the product). | +| 0 | Start SPI Transfer | RW | 0x0 | 1: Start the transfer (requires the <Enable SPI> field is set to be 1).
0: Transfer not started. | #### LCD_SPI_TXDATA_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x184
BitsFieldTypeResetDescription
31:0SPI Transfer DataRW0x0SPI Transfer Data Up to 32 bits are shifted out by each trigger. It is configurable from high to low or low to high and to shift any length. 0 = MSb to LSb; 1 = LSb to MSb.
Defines the data to be shifted out during SPI transfer.
The transfer length is configurable up to 32 bits per trigger.
The shifting direction can be set to either high to low (MSb to LSb) or low to high (LSb to MSb).
0: Shifts from MSb to LSb.
1: Shifts from LSb to MSb.
+**Offset: 0x184** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | SPI Transfer Data | RW | 0x0 | SPI Transfer Data Up to 32 bits are shifted out by each trigger. It is configurable from high to low or low to high and to shift any length. 0 = MSb to LSb; 1 = LSb to MSb.
Defines the data to be shifted out during SPI transfer.
The transfer length is configurable up to 32 bits per trigger.
The shifting direction can be set to either high to low (MSb to LSb) or low to high (LSb to MSb).
0: Shifts from MSb to LSb.
1: Shifts from LSb to MSb. | #### LCD_SMPN_CTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x188
BitsFieldTypeResetDescription
31:28Configure ISA Receive LowRW0x0This field programs the bus read active low time.
0xF: 6 clock cycles
0x0: 1 clock cycle.
27:24Configure ISA Receive HighRW0x0This field programs the bus read hold time.
0xF: 16 clock cycles
0x0: 1 clock cycle
23:20Configure ISA Transmit LowRW0x0This field programs the bus write active low time.
0xF: 16 clock cycles
0x0: 1 clock cycle
19:16Configure ISA Transmit HighRW0x0This field programs the bus read hold time.
0xF: 16 clock cycles
0x0: 1 clock cycle
15:14Select Smart Panel VSYNC TriggerRW0x0This field is used when the <Panel Path VSYNC Input Trigger Modes> field (in the Panel Path DMA Control 1 Register) is set to 0x0 or 0x1.
0x0: Parallel bus I/O pad input as Smart panel DMA VSYNC trigger signal.
0x1: MIPI DSI1 as Smart panel DMA VSYNC trigger signal.
0x2: MIPI DSI2 as Smart panel DMA VSYNC trigger signal.
All other values: Reserved
13Configure ISA iordy MaskRW0x00x0: The I/O ready signal is always active high on the Smart Panel parallel bus.
0x1: The Smart Panel parallel bus is held when the I/O ready signal is low. The I/O ready signal goes high when the bus is ready.
- Note: Set this bit to 1 when using the SPI interface to connect to a display device.
12Configure Slave Only ModeRW0x0- This field allows the Smart Panel to operate without DMA mode.
- When both the Panel Path (HDMI) and TV Path (MIPI DSI) are enabled, no extra FIFO is available for Smart Panel DMA mode.
- In slave-only mode, up to three panels can be supported simultaneously.
- When set high, the Smart Panel operates in slave mode only.
11:8Configure Pixel FormatRW0x0When in DMA transfer, this field defines the pixel format.
0x0: RGB888, 3 cycles per pixel;
0x1: RGB666, 3 cycles per pixel;
0x2: RGB565, 2 cycles per pixel;
0x3: RGB888, 1 cycle per pixel;
0x4: RGB666, 1 cycle per pixel;
0x5: RGB565 1 cycle per pixel;
0x6: RGB666_GC, 3 cycles per pixel.
7Configure Command FormatRW0x01: 32-bit command format, used for up to 24-bit bus width (I/O pins limited to 18-bit).
0: 16-bit command format, used for 8-bit bus width.
6Write Byte OrderRW0x0Configures the byte order for writing.
0: Write 8-bit bus from low byte to high byte.
1: Write 8-bit bus from high byte to low byte.
This field is used when writing one pixel across 2 or 3 byte writes.
5Smart Panel Parallel Bus Chip SelectRW0x0Selects the chip select line for the Smart Panel parallel bus.
0: CSB[0]
1: CSB[1]
4AHB Slave Path EnableRW0x00: Disabled
1: Enabled
3Smart Panel ResetRW0x00: Reset pin is high
1: Reset pin is low
2Configure 8086/6800RW0x00: 8-bit bus read/write conforming to 8086 series
1: 8-bit bus read/write conforming to 6800 series
1Configure TransferRW0x01: Force chip select to low until this bit is set to 0.
This field is useful when a Smart Panel requires the chip select to remain low during read and write.
0Smart Panel Enable
RW0x01: Enabled
0: Disabled
When both this field and the <AHB Slave Path Enable> field are high, writing a command word to the AHB Slave Path Data Port Register initiates Smart Panel parallel bus cycles.
- If the <Configure Command Format> field = 1 (High):
1. Commands are in 16-bit format.
2. Two 16-bit commands are packed into a single 32-bit word (e.g., Command 0 in bits 0–15, Command 1 in bits 16–31).
- If the <Configure Command Format> field = 0 (Low):
1. Commands are in 32-bit format.
2. Only one 32-bit command fits per 32-bit word.
+**Offset: 0x188** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Configure ISA Receive Low | RW | 0x0 | This field programs the bus read active low time.
0xF: 6 clock cycles
0x0: 1 clock cycle. | +| 27:24 | Configure ISA Receive High | RW | 0x0 | This field programs the bus read hold time.
0xF: 16 clock cycles
0x0: 1 clock cycle | +| 23:20 | Configure ISA Transmit Low | RW | 0x0 | This field programs the bus write active low time.
0xF: 16 clock cycles
0x0: 1 clock cycle | +| 19:16 | Configure ISA Transmit High | RW | 0x0 | This field programs the bus read hold time.
0xF: 16 clock cycles
0x0: 1 clock cycle | +| 15:14 | Select Smart Panel VSYNC Trigger | RW | 0x0 | This field is used when the <Panel Path VSYNC Input Trigger Modes> field (in the Panel Path DMA Control 1 Register) is set to 0x0 or 0x1.
0x0: Parallel bus I/O pad input as Smart panel DMA VSYNC trigger signal.
0x1: MIPI DSI1 as Smart panel DMA VSYNC trigger signal.
0x2: MIPI DSI2 as Smart panel DMA VSYNC trigger signal.
All other values: Reserved | +| 13 | Configure ISA iordy Mask | RW | 0x0 | 0x0: The I/O ready signal is always active high on the Smart Panel parallel bus.
0x1: The Smart Panel parallel bus is held when the I/O ready signal is low. The I/O ready signal goes high when the bus is ready.
- Note: Set this bit to 1 when using the SPI interface to connect to a display device. | +| 12 | Configure Slave Only Mode | RW | 0x0 | - This field allows the Smart Panel to operate without DMA mode.
- When both the Panel Path (HDMI) and TV Path (MIPI DSI) are enabled, no extra FIFO is available for Smart Panel DMA mode.
- In slave-only mode, up to three panels can be supported simultaneously.
- When set high, the Smart Panel operates in slave mode only. | +| 11:8 | Configure Pixel Format | RW | 0x0 | When in DMA transfer, this field defines the pixel format.
0x0: RGB888, 3 cycles per pixel;
0x1: RGB666, 3 cycles per pixel;
0x2: RGB565, 2 cycles per pixel;
0x3: RGB888, 1 cycle per pixel;
0x4: RGB666, 1 cycle per pixel;
0x5: RGB565 1 cycle per pixel;
0x6: RGB666_GC, 3 cycles per pixel. | +| 7 | Configure Command Format | RW | 0x0 | 1: 32-bit command format, used for up to 24-bit bus width (I/O pins limited to 18-bit).
0: 16-bit command format, used for 8-bit bus width. | +| 6 | Write Byte Order | RW | 0x0 | Configures the byte order for writing.
0: Write 8-bit bus from low byte to high byte.
1: Write 8-bit bus from high byte to low byte.
This field is used when writing one pixel across 2 or 3 byte writes. | +| 5 | Smart Panel Parallel Bus Chip Select | RW | 0x0 | Selects the chip select line for the Smart Panel parallel bus.
0: CSB[0]
1: CSB[1] | +| 4 | AHB Slave Path Enable | RW | 0x0 | 0: Disabled
1: Enabled | +| 3 | Smart Panel Reset | RW | 0x0 | 0: Reset pin is high
1: Reset pin is low | +| 2 | Configure 8086/6800 | RW | 0x0 | 0: 8-bit bus read/write conforming to 8086 series
1: 8-bit bus read/write conforming to 6800 series | +| 1 | Configure Transfer | RW | 0x0 | 1: Force chip select to low until this bit is set to 0.
This field is useful when a Smart Panel requires the chip select to remain low during read and write. | +| 0 | Smart Panel Enable | RW | 0x0 | 1: Enabled
0: Disabled
When both this field and the <AHB Slave Path Enable> field are high, writing a command word to the AHB Slave Path Data Port Register initiates Smart Panel parallel bus cycles.
- If the <Configure Command Format> field = 1 (High):
1. Commands are in 16-bit format.
2. Two 16-bit commands are packed into a single 32-bit word (e.g., Command 0 in bits 0–15, Command 1 in bits 16–31).
- If the <Configure Command Format> field = 0 (Low):
1. Commands are in 32-bit format.
2. Only one 32-bit command fits per 32-bit word. | #### LCD_SLV_PORT_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x18C
BitsFieldTypeResetDescription
31Command 1 A0WO0x0Command 1 A0
30:26ReservedRO0Reserved for future use
25Command 1 ReadWO0x0Command 1 Read
24Command 1 WriteWO0x0Command 1 Write
23:16Command 1 DataWO0x0- If the <Configure Command Format> field is set to 16-bit format, this field holds the 8-bit command 1 data.
- If the <Configure Command Format> field is set to 32-bit format, bits [23:0] represent Smart Panel data[23:0].
15Command 0 A0WO0x0- If the <Configure Command Format> field is set to 16-bit format, this field holds the command 0 A0.
- If the <Configure Command Format> field is set to 32-bit format, bits [23:0] represent Smart Panel data[23:0].
14:1032-bit Command Format DataWO0x0- If the <Configure Command Format> field is set to 16-bit format, this field is reserved.
- If the <Configure Command Format> field is set to 32-bit format, bits [23:0] represent Smart Panel data[23:0].
9Command 0 ReadWO0x0- If the <Configure Command Format> field is set to 16-bit format, this field holds the command 0 read.
- If the <Configure Command Format> field is set to 32-bit format, bits [23:0] represent Smart Panel data[23:0].
8Command 0 WriteWO0x0- If the <Configure Command Format> field is set to 16-bit format, this field holds the command 0 write.
- If the <Configure Command Format> field is set to 32-bit format, bits [23:0] represent Smart Panel data[23:0].
7:0Command 0 DataWO0x0- If the <Configure Command Format> field is set to 16-bit format, this field holds the command 0 data.
- If the <Configure Command Format> field is set to 32-bit format, bits [23:0] represent Smart Panel data[23:0].
+**Offset: 0x18C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Command 1 A0 | WO | 0x0 | Command 1 A0 | +| 30:26 | Reserved | RO | 0 | Reserved for future use | +| 25 | Command 1 Read | WO | 0x0 | Command 1 Read | +| 24 | Command 1 Write | WO | 0x0 | Command 1 Write | +| 23:16 | Command 1 Data | WO | 0x0 | - If the <Configure Command Format> field is set to 16-bit format, this field holds the 8-bit command 1 data.
- If the <Configure Command Format> field is set to 32-bit format, bits [23:0] represent Smart Panel data[23:0]. | +| 15 | Command 0 A0 | WO | 0x0 | - If the <Configure Command Format> field is set to 16-bit format, this field holds the command 0 A0.
- If the <Configure Command Format> field is set to 32-bit format, bits [23:0] represent Smart Panel data[23:0]. | +| 14:10 | 32-bit Command Format Data | WO | 0x0 | - If the <Configure Command Format> field is set to 16-bit format, this field is reserved.
- If the <Configure Command Format> field is set to 32-bit format, bits [23:0] represent Smart Panel data[23:0]. | +| 9 | Command 0 Read | WO | 0x0 | - If the <Configure Command Format> field is set to 16-bit format, this field holds the command 0 read.
- If the <Configure Command Format> field is set to 32-bit format, bits [23:0] represent Smart Panel data[23:0]. | +| 8 | Command 0 Write | WO | 0x0 | - If the <Configure Command Format> field is set to 16-bit format, this field holds the command 0 write.
- If the <Configure Command Format> field is set to 32-bit format, bits [23:0] represent Smart Panel data[23:0]. | +| 7:0 | Command 0 Data | WO | 0x0 | - If the <Configure Command Format> field is set to 16-bit format, this field holds the command 0 data.
- If the <Configure Command Format> field is set to 32-bit format, bits [23:0] represent Smart Panel data[23:0]. | #### LCD_PN_CTRL0_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x190
BitsFieldTypeResetDescription
31ReservedRO0Reserved for future use
30Panel Path Gamma Correction EnableRW0x01: Enabled
0: Disabled
29Panel Path Video Contrast/Saturation/Brightness/Hue Adjust EnableRW0x01: Enabled
0: Disabled
28Panel Path Palette Color EnableRW0x0This field enables the palette color SRAM table.
1: Enabled
0: Disabled
When the color format selected in the <Video Memory Color Format> field is palette4bit or palette8bit, this field should be 1. Either video or graphic DMA can select palette mode. There is only one palette table in the Panel Path.
- This field must be set to 1 when the color format selected in the <Video Memory Color Format> field is palette4bit or palette8bit.
- Either video or graphic DMA can use palette mode.
- There is only one palette table in the Panel Path, shared between video and graphic DMA.
27AXI Bus Arbiter Fast Mode EnableRW0x01: DMA AXI bus arbiter allows multiple burst requests.
0: Arbiter switches after one request is done.
For faster read, enable this bit in normal case.
26ReservedRO0Reserved for future use
25Panel Path CS Low Delay EnableRW0x01: Enabled
0: Disabled
24Panel Path Force Blank-Color EnableRW0x01: Enabled
0: Disabled
23:20Panel Path Video Memory Color FormatRW0x00x0: RGB565
0x1: RGB1555
0x2: RGB888 packed
0x3: RGB888 unpacked
0x4: RGBA888
0x5: YUV422 packed
0x6: YUV422 planar
0x7: YUV420 planar
0x8: Smart Panel command
0x9: Palette color 4-bit per pixel
0xA: Palette color 8-bit per pixel
0xB: RGB888A
All other values: Reserved
19:16Panel Path Graphic Memory Color FormatRW0x00x0: RGB565
0x1: RGB1555
0x2: RGB888 packed
0x3: RGB888 unpacked
0x4: RGBA888
0x5: YUV422 packed
0x6 to 0x8 = Reserved
0x9: Palette color 4-bit per pixel
0xA: Palette color 8-bit per pixel
0xb: RGB888A
All other values: Reserved
15ReservedRO0Reserved for future use
14Panel Path Graphic Horizontal Smooth EnableRW0x01: Enabled
0: Disabled
13Panel Path Graphic DMA Test Mode EnableRW0x01: Enabled
0: Disabled
12Panel Path graphic DMA Swap R and BRW0x0Swap R and B (e.g., RGB to BGR).
1: Swap enabled
0: Swap disabled
11Panel Path Graphic DMA Swap U and VRW0x0Swap U and V (e.g., YUYV to YVYU).
1: Swap enabled
0: Swap disabled
10Panel Path Graphic DMA Swap Y and U/VRW0x0Swap Y and U/V (e.g., UYVY to YUYV).
1: Swap enabled
0: Swap disabled
9Panel Path Graphic YUV to RGB Color Space ConversionRW0x01: Enabled
0: Disabled
Either this or the <Panel Path Video YUV to RGB Color Space Conversion> field can be enabled, but both cannot be enabled simultaneously.
8Panel Path Graphic Transfer EnableRW0x01: Enabled
0: Disabled
7ReservedRO0Reserved for future use
6Panel Path Video Horizontal Smooth EnableRW0x01: Enabled
0: Disabled
5Panel Path Video Path Test Mode EnableRW0x01: Enabled
0: Disabled
4Panel Path Video DMA Swap R and BRW0x0Swap R and B (e.g., RGB to BGR).
1: Swap enabled
0: Swap disabled
3Panel Path Video DMA Swap U and VRW0x0Swap U and V (e.g., YUYV to YVYU).
1: Swap enabled
0: Swap disabled
2Panel Path Video DMA Swap Y and U/VRW0x0Swap Y and U/V (e.g., UYVY to YUYV).
1: Swap enabled
0: Swap disabled
1Panel Path Video YUV to RGB Color Space ConversionRW0x01: Enabled
0: Disabled
Either this or the <Panel Path Graphic YUV to RGB Color Space Conversion> field can be enabled, but both cannot be enabled simultaneously.
0Panel Path Video and Command Transfer EnableRW0x01: Enabled
0: Disabled
+**Offset: 0x190** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Reserved | RO | 0 | Reserved for future use | +| 30 | Panel Path Gamma Correction Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 29 | Panel Path Video Contrast/Saturation/Brightness/Hue Adjust Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 28 | Panel Path Palette Color Enable | RW | 0x0 | This field enables the palette color SRAM table.
1: Enabled
0: Disabled
When the color format selected in the <Video Memory Color Format> field is palette4bit or palette8bit, this field should be 1. Either video or graphic DMA can select palette mode. There is only one palette table in the Panel Path.
- This field must be set to 1 when the color format selected in the <Video Memory Color Format> field is palette4bit or palette8bit.
- Either video or graphic DMA can use palette mode.
- There is only one palette table in the Panel Path, shared between video and graphic DMA. | +| 27 | AXI Bus Arbiter Fast Mode Enable | RW | 0x0 | 1: DMA AXI bus arbiter allows multiple burst requests.
0: Arbiter switches after one request is done.
For faster read, enable this bit in normal case. | +| 26 | Reserved | RO | 0 | Reserved for future use | +| 25 | Panel Path CS Low Delay Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 24 | Panel Path Force Blank-Color Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 23:20 | Panel Path Video Memory Color Format | RW | 0x0 | 0x0: RGB565
0x1: RGB1555
0x2: RGB888 packed
0x3: RGB888 unpacked
0x4: RGBA888
0x5: YUV422 packed
0x6: YUV422 planar
0x7: YUV420 planar
0x8: Smart Panel command
0x9: Palette color 4-bit per pixel
0xA: Palette color 8-bit per pixel
0xB: RGB888A
All other values: Reserved | +| 19:16 | Panel Path Graphic Memory Color Format | RW | 0x0 | 0x0: RGB565
0x1: RGB1555
0x2: RGB888 packed
0x3: RGB888 unpacked
0x4: RGBA888
0x5: YUV422 packed
0x6 to 0x8 = Reserved
0x9: Palette color 4-bit per pixel
0xA: Palette color 8-bit per pixel
0xb: RGB888A
All other values: Reserved | +| 15 | Reserved | RO | 0 | Reserved for future use | +| 14 | Panel Path Graphic Horizontal Smooth Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 13 | Panel Path Graphic DMA Test Mode Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 12 | Panel Path graphic DMA Swap R and B | RW | 0x0 | Swap R and B (e.g., RGB to BGR).
1: Swap enabled
0: Swap disabled | +| 11 | Panel Path Graphic DMA Swap U and V | RW | 0x0 | Swap U and V (e.g., YUYV to YVYU).
1: Swap enabled
0: Swap disabled | +| 10 | Panel Path Graphic DMA Swap Y and U/V | RW | 0x0 | Swap Y and U/V (e.g., UYVY to YUYV).
1: Swap enabled
0: Swap disabled | +| 9 | Panel Path Graphic YUV to RGB Color Space Conversion | RW | 0x0 | 1: Enabled
0: Disabled
Either this or the <Panel Path Video YUV to RGB Color Space Conversion> field can be enabled, but both cannot be enabled simultaneously. | +| 8 | Panel Path Graphic Transfer Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 7 | Reserved | RO | 0 | Reserved for future use | +| 6 | Panel Path Video Horizontal Smooth Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 5 | Panel Path Video Path Test Mode Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 4 | Panel Path Video DMA Swap R and B | RW | 0x0 | Swap R and B (e.g., RGB to BGR).
1: Swap enabled
0: Swap disabled | +| 3 | Panel Path Video DMA Swap U and V | RW | 0x0 | Swap U and V (e.g., YUYV to YVYU).
1: Swap enabled
0: Swap disabled | +| 2 | Panel Path Video DMA Swap Y and U/V | RW | 0x0 | Swap Y and U/V (e.g., UYVY to YUYV).
1: Swap enabled
0: Swap disabled | +| 1 | Panel Path Video YUV to RGB Color Space Conversion | RW | 0x0 | 1: Enabled
0: Disabled
Either this or the <Panel Path Graphic YUV to RGB Color Space Conversion> field can be enabled, but both cannot be enabled simultaneously. | +| 0 | Panel Path Video and Command Transfer Enable | RW | 0x0 | 1: Enabled
0: Disabled | #### LCD_PN_CTRL1_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x194
BitsFieldTypeResetDescription
31Panel Path DMA Transfer TriggerRW0x01: DMA transfer is triggered, this is equivalent to VSYNC pulse.
This field is useful when Smart Panel VSYNC input is not available.
30:28Panel Path VSYNC Input Trigger ModesRW0x00x0: Smart Panel VSYNC input triggers DMA start transfer.
0x1: Smart Panel VSYNC input triggers DMA transfer, and generates asynchronous interrupt to processor.
0x7: Write 1 to the <Panel Path DMA Transfer Trigger> field triggers DMA transfer
All other values: Reserved
27Panel Path Rising/Falling Edge Triggers DMA TransferRW0x00: Rising edge triggers
1: Falling edge
26:24Panel Path Color Key ModeRW0x00x0: Disable color key function
0x1: Video Y (or Graphic R) color key is enabled
0x2: Video U color key is enabled
0x3: Graphic RGB color key is enabled
0x4: Video V color key is enabled
0x5: Video YUV color key is enabled
0x6: Video Luma key is enabled
0x7: Graphic B color key is enabled
23Panel Path Configure Low BitsRW0x01: Low bits are the extension of the maximum bit when converting RGB565/1555/4-bit color into 24-bit RGB color.
0: Fill zeros into low bits when converting RGB565/1555/4-bit color into 24-bit RGB color.
22:20ReservedRO0Reserved for future use
19:18Configure ScalingRW0x0This field controls scaling down when Smart Panel DMA mode is enabled.
- 0x0 – No scaling down
- 0x1 – Scale down by 1/2 (in addition to any zooming applied)
- 0x2 – Scale down by 1/4 (in addition to any zooming applied)
Example:
If the original image is 160 × 120 and the target size is 80 × 60, setting this field to 0x1 will further reduce the final output to 40 × 30.
17ReservedRO0Reserved for future use
16Panel Path Alpha SelectionRW0x0This field determines how the graphic alpha is selected for the overlaid area in the Panel Path.
- 0x0: Software-configured alpha
- 0x1: Alpha is taken from the pixel data
15:8Panel Path Configure AlphaRW0x0This field configures the alpha blending in the Panel Path when neither color key alpha nor pixel-based alpha is used.
- 0xFF – Full video display, no graphics
- Other values – Blends video and graphics proportionally based on the set value
7:0Pixel CommandRW0x0This field should be set to 0x81.
All other values are reserved.
+**Offset: 0x194** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Panel Path DMA Transfer Trigger | RW | 0x0 | 1: DMA transfer is triggered, this is equivalent to VSYNC pulse.
This field is useful when Smart Panel VSYNC input is not available. | +| 30:28 | Panel Path VSYNC Input Trigger Modes | RW | 0x0 | 0x0: Smart Panel VSYNC input triggers DMA start transfer.
0x1: Smart Panel VSYNC input triggers DMA transfer, and generates asynchronous interrupt to processor.
0x7: Write 1 to the <Panel Path DMA Transfer Trigger> field triggers DMA transfer
All other values: Reserved | +| 27 | Panel Path Rising/Falling Edge Triggers DMA Transfer | RW | 0x0 | 0: Rising edge triggers
1: Falling edge | +| 26:24 | Panel Path Color Key Mode | RW | 0x0 | 0x0: Disable color key function
0x1: Video Y (or Graphic R) color key is enabled
0x2: Video U color key is enabled
0x3: Graphic RGB color key is enabled
0x4: Video V color key is enabled
0x5: Video YUV color key is enabled
0x6: Video Luma key is enabled
0x7: Graphic B color key is enabled | +| 23 | Panel Path Configure Low Bits | RW | 0x0 | 1: Low bits are the extension of the maximum bit when converting RGB565/1555/4-bit color into 24-bit RGB color.
0: Fill zeros into low bits when converting RGB565/1555/4-bit color into 24-bit RGB color. | +| 22:20 | Reserved | RO | 0 | Reserved for future use | +| 19:18 | Configure Scaling | RW | 0x0 | This field controls scaling down when Smart Panel DMA mode is enabled.
- 0x0 – No scaling down
- 0x1 – Scale down by 1/2 (in addition to any zooming applied)
- 0x2 – Scale down by 1/4 (in addition to any zooming applied)
Example:
If the original image is 160 × 120 and the target size is 80 × 60, setting this field to 0x1 will further reduce the final output to 40 × 30. | +| 17 | Reserved | RO | 0 | Reserved for future use | +| 16 | Panel Path Alpha Selection | RW | 0x0 | This field determines how the graphic alpha is selected for the overlaid area in the Panel Path.
- 0x0: Software-configured alpha
- 0x1: Alpha is taken from the pixel data | +| 15:8 | Panel Path Configure Alpha | RW | 0x0 | This field configures the alpha blending in the Panel Path when neither color key alpha nor pixel-based alpha is used.
- 0xFF – Full video display, no graphics
- Other values – Blends video and graphics proportionally based on the set value | +| 7:0 | Pixel Command | RW | 0x0 | This field should be set to 0x81.
All other values are reserved. | #### LCD_SRAM_CTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x198
BitsFieldTypeResetDescription
31:16ReservedRO0Reserved for future use
15:14SRAM Init Write/ReadRW0x00x0: Read SRAM
0x2: Write SRAM
0x3: Initialize SRAM to default value
13:12ReservedRO0Reserved for future use
11:8SRAM Address LCD IDRW0x00x0: Panel ID_gamma_yr
0x1: Panel ID_gamma_ug
0x2: Panel ID_gamma_vb
7:0SRAM Address[7:0]RW0x0SRAM Address[7:0]
+**Offset: 0x198** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0 | Reserved for future use | +| 15:14 | SRAM Init Write/Read | RW | 0x0 | 0x0: Read SRAM
0x2: Write SRAM
0x3: Initialize SRAM to default value | +| 13:12 | Reserved | RO | 0 | Reserved for future use | +| 11:8 | SRAM Address LCD ID | RW | 0x0 | 0x0: Panel ID_gamma_yr
0x1: Panel ID_gamma_ug
0x2: Panel ID_gamma_vb | +| 7:0 | SRAM Address[7:0] | RW | 0x0 | SRAM Address[7:0] | #### LCD_SRAM_WRDAT_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x19C
BitsFieldTypeResetDescription
31:0SRAM Write DataRW0x0SRAM Write Data. When generating an SRAM write command, this write data will be moved into SRAM.
+**Offset: 0x19C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | SRAM Write Data | RW | 0x0 | SRAM Write Data. When generating an SRAM write command, this write data will be moved into SRAM. | #### LCD_SCLK_DIV_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1A8
BitsFieldTypeResetDescription
31:30Panel Path Clock Source SelectRW0x0This field selects the pixel clock source
0x0: Select AXI bus clock
0x1: Select LCD Display clock 1
0x2: Select LCD Display clock 2
0x3: Select DSI PLL clock.
29ReservedRO0Reserved for future use
28Panel Path Pixel Clock DisableRW0x00: Clock enabled
1: Clock disabled.
27:16Panel Path Pixel Clock Fraction DividerRW0x0This field fine-tunes the pixel clock when the desired clock rate cannot be achieved using only an integer divider.
- Example:
To obtain 80 MHz from 83 MHz, this register should be set to (83-80)/83*4096 = <0x094>
Three clocks are suppressed and 80 clocks are used, and the duty cycle is not 50%.
> Notes.
> - This feature is useful for Smart Panels.
> - It is not recommended for Dumb Panels.
> - For basic clock adjustments, refer to the the <Clock Integer Divider> field.
15:12ReservedRO0Reserved for future use
11:8Panel Path MIPI bit Clock DividerRW0x00x0: Clock disabled
0x1: Clock bypass (no division)
0x2 to 0x15: Panel path MIPI PLL clock is divided by 2 up to 15.
7:0Panel Path Pixel Clock Integer DividerRW0x0This field sets the integer divider to generate the required pixel clock for Smart Panel and Dumb Panel after selecting the pixel clock source.
0x0: Clock disabled
0x1: Clock bypass (no division)
0x2 to 0xFF: Divides the pixel clock source by 2 to 255
> Note. For the TV path, 0x2 to 0x15 divides the MIPI PLL clock by 2 to 15.
For example, when the source AXI bus clock is 166 MHz, setting this register to 0x2 generates an 83 MHz (166 ÷ 2) clock.
+**Offset: 0x1A8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | Panel Path Clock Source Select | RW | 0x0 | This field selects the pixel clock source
0x0: Select AXI bus clock
0x1: Select LCD Display clock 1
0x2: Select LCD Display clock 2
0x3: Select DSI PLL clock. | +| 29 | Reserved | RO | 0 | Reserved for future use | +| 28 | Panel Path Pixel Clock Disable | RW | 0x0 | 0: Clock enabled
1: Clock disabled. | +| 27:16 | Panel Path Pixel Clock Fraction Divider | RW | 0x0 | This field fine-tunes the pixel clock when the desired clock rate cannot be achieved using only an integer divider.
- Example:
To obtain 80 MHz from 83 MHz, this register should be set to (83-80)/83*4096 = <0x094>
Three clocks are suppressed and 80 clocks are used, and the duty cycle is not 50%.
**Notes.**
- This feature is useful for Smart Panels.
- It is not recommended for Dumb Panels.
- For basic clock adjustments, refer to the <Clock Integer Divider> field. | +| 15:12 | Reserved | RO | 0 | Reserved for future use | +| 11:8 | Panel Path MIPI bit Clock Divider | RW | 0x0 | 0x0: Clock disabled
0x1: Clock bypass (no division)
0x2 to 0x15: Panel path MIPI PLL clock is divided by 2 up to 15. | +| 7:0 | Panel Path Pixel Clock Integer Divider | RW | 0x0 | This field sets the integer divider to generate the required pixel clock for Smart Panel and Dumb Panel after selecting the pixel clock source.
0x0: Clock disabled
0x1: Clock bypass (no division)
0x2 to 0xFF: Divides the pixel clock source by 2 to 255
**Note. For the TV path, 0x2 to 0x15 divides the MIPI PLL clock by 2 to 15.**
For example, when the source AXI bus clock is 166 MHz, setting this register to 0x2 generates an 83 MHz (166 ÷ 2) clock. | #### LCD_PN_CONTRAST_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1AC
BitsFieldTypeResetDescription
31:16Panel Path Video Brightness ControlRW0x0Bits [15:8]: Used for sign extension (for positive or negative values).
Bits [7:0]: Used for the integer value of brightness control.
- Brightness adjustments are applied before the Color Space Conversion (CSC).
- The brightness change range is +/- 0 to 255.
- The value is represented in 2's complement:
Example:
1. Set this field to 0x10 to make the video brighter.
2. Set this field to 0xFFF0 to make the video darker.
15:0Panel Path Video Contrast ControlRW0x0Bit [15]: Used for the sign (for positive or negative values).
Bit [14]: Used for the integer part.
Bits [13:0]: Used for the fractional part of contrast control.
- The value is represented in 2's complement:
Example:
1. Set this field to 0x4000 for a ratio of 1.0 (No change)
2. Set this field to 0x6000 for a ratio of 1.5 (Increase contrast)
3. Set this field to 0x2000 for a ratio of 0.5 (Decrease contrast)
+**Offset: 0x1AC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Panel Path Video Brightness Control | RW | 0x0 | Bits [15:8]: Used for sign extension (for positive or negative values).
Bits [7:0]: Used for the integer value of brightness control.
- Brightness adjustments are applied before the Color Space Conversion (CSC).
- The brightness change range is +/- 0 to 255.
- The value is represented in 2's complement:
Example:
1. Set this field to 0x10 to make the video brighter.
2. Set this field to 0xFFF0 to make the video darker. | +| 15:0 | Panel Path Video Contrast Control | RW | 0x0 | Bit [15]: Used for the sign (for positive or negative values).
Bit [14]: Used for the integer part.
Bits [13:0]: Used for the fractional part of contrast control.
- The value is represented in 2's complement:
Example:
1. Set this field to 0x4000 for a ratio of 1.0 (No change)
2. Set this field to 0x6000 for a ratio of 1.5 (Increase contrast)
3. Set this field to 0x2000 for a ratio of 0.5 (Decrease contrast) | #### LCD_PN_SATURATION_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1B0
BitsFieldTypeResetDescription
31:16Panel Path Configure MultiplierRW0x0Bit [15]: Used for the sign (for positive or negative values).
Bits [14:13]: Used for integer.
Bits [12:0] Used for fraction of multiplier of contrast and saturation.
These bits are 2's complement code.
15:0Panel Path Configure SaturationRW0x0Bit [15]: Used for the sign (for positive or negative values).
Bit [14]: Used for integer.
Bits [13:0]: Used for fraction of saturation control.
These bits are 2's complement code.
+**Offset: 0x1B0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Panel Path Configure Multiplier | RW | 0x0 | Bit [15]: Used for the sign (for positive or negative values).
Bits [14:13]: Used for integer.
Bits [12:0] Used for fraction of multiplier of contrast and saturation.
These bits are 2's complement code. | +| 15:0 | Panel Path Configure Saturation | RW | 0x0 | Bit [15]: Used for the sign (for positive or negative values).
Bit [14]: Used for integer.
Bits [13:0]: Used for fraction of saturation control.
These bits are 2's complement code. | #### LCD_PN_CBSH_HUE_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1B4
BitsFieldTypeResetDescription
31:16Panel Path Video HUE Sine CorrectionRW0x0Bit [15]: Used for the sign (positive or negative correction).
Bit [14]: Used for integer.
Bits [13:0]: Used for fraction of sine (delta phase).
These bits are 2's complement code.
Formula:
Corrected U = U * cos + V * sin
Corrected V = V * cos - U * sin
- For example,
CFG_SIN=0x0, CFG_COS=0x4000 makes no correction.
15:0Panel Path Video HUE Cosine CorrectionRW0x0Bit [15]: Used for the sign (positive or negative correction).
Bit [14]: Used for integer.
Bits [13:0]: Used for fraction of sine (delta phase).
These bits are 2's complement code.
Formula:
Corrected U = U * cos + V * sin
Corrected V = V * cos - U * sin
- For example,
CFG_SIN=0x2000, CFG_COS=0x376D makes a 30 degree correction.
+**Offset: 0x1B4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Panel Path Video HUE Sine Correction | RW | 0x0 | Bit [15]: Used for the sign (positive or negative correction).
Bit [14]: Used for integer.
Bits [13:0]: Used for fraction of sine (delta phase).
These bits are 2's complement code.
Formula:
Corrected U = U * cos + V * sin
Corrected V = V * cos - U * sin
- For example,
CFG_SIN=0x0, CFG_COS=0x4000 makes no correction. | +| 15:0 | Panel Path Video HUE Cosine Correction | RW | 0x0 | Bit [15]: Used for the sign (positive or negative correction).
Bit [14]: Used for integer.
Bits [13:0]: Used for fraction of sine (delta phase).
These bits are 2's complement code.
Formula:
Corrected U = U * cos + V * sin
Corrected V = V * cos - U * sin
- For example,
CFG_SIN=0x2000, CFG_COS=0x376D makes a 30 degree correction. | #### LCD_DUMB_CTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1B8
BitsFieldTypeResetDescription
31:28Panel Path Configure Dumb Panel Color ModeRW0x0This field is used for the Panel Path to convert internal RGB888 pixels into the destination color format.
0x0: LDD[15:0] is 16-bit RGB565;
0x1: LDD[23:8] is 16-bit RGB565;
0x2: LDD[17:0] is 18-bit RGB666;
0x3: LDD[23:6] is 18-bit RGB666;
0x4: LDD[11:0] is 12-bit RGB444;
0x5: LDD[23:12] is 12-bit RGB444;
0x6: LDD[23:0] is RGB888;
Other values: Output blank color (as set by the Panel Screen Blank Color Register) to the I/O.
27:20LCD GPIO Output DataRW0x0LCD GPIO Output Data
19:12LCD GPIO Output Data EnableRW0x0LCD GPIO Output Data Enable
11Panel Path Delay Graphic DMARW0x0- This field is used to reduce AXI bus activity by delaying graphic DMA until sufficient FIFO space is available for multiple bursts.
- It is only applicable when:
1. The graphic path is enabled.
2. The AXI bus traffic is low.
- If not used properly, FIFO underflow could occur, which would disrupt the data flow.
10ReservedRO0Reserved for future use
9Panel Path I/O Pads Output DisableRW0x01: Disabled after next VSYNC
0x0: Enabled after next VSYNC
8Panel Path Dumb LCD Panel GPIO Control PinRW0x0This field controls the backlight of a Dumb LCD Panel.
Active only when both the <Dumb Panel Backlight Clock Divider> and <Duty Cycle Control> fields in the Graphic Line Length (Pitch) Register are 0x0000.
7Panel Path Configure Reverse RGB Bit OrderRW0x01: Reverse the RGB bit order
1. For example, R[7:0] G[7:0] B[7:0] are reversed to R[0:7] G[0:7] B[0:7].
0: Do not reverse.
6Panel Path Invert Composite Blank SignalRW0x01: Invert
0: Do not invert.
5Panel Path Invert Composite Sync SignalRW0x01: Invert
0: Do not invert.
4Panel Path Invert Pixel Valid EnableRW0x01: Invert
0: Do not invert.
3Panel Path Invert VSYNCRW0x01: Invert
0: Do not invert.
2Panel Path Invert HSYNCRW0x01: Invert
0: Do not invert.
1Panel Path Invert Pixel ClockRW0x01: Invert
0: Do not invert.
0Panel Path Enable Dumb LCD PanelRW0x01: Enabled
> Note. Smart Panel should be disabled when this bit is 1
0: Disabled.
+**Offset: 0x1B8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Panel Path Configure Dumb Panel Color Mode | RW | 0x0 | This field is used for the Panel Path to convert internal RGB888 pixels into the destination color format.
0x0: LDD[15:0] is 16-bit RGB565;
0x1: LDD[23:8] is 16-bit RGB565;
0x2: LDD[17:0] is 18-bit RGB666;
0x3: LDD[23:6] is 18-bit RGB666;
0x4: LDD[11:0] is 12-bit RGB444;
0x5: LDD[23:12] is 12-bit RGB444;
0x6: LDD[23:0] is RGB888;
Other values: Output blank color (as set by the Panel Screen Blank Color Register) to the I/O. | +| 27:20 | LCD GPIO Output Data | RW | 0x0 | LCD GPIO Output Data | +| 19:12 | LCD GPIO Output Data Enable | RW | 0x0 | LCD GPIO Output Data Enable | +| 11 | Panel Path Delay Graphic DMA | RW | 0x0 | - This field is used to reduce AXI bus activity by delaying graphic DMA until sufficient FIFO space is available for multiple bursts.
- It is only applicable when:
1. The graphic path is enabled.
2. The AXI bus traffic is low.
- If not used properly, FIFO underflow could occur, which would disrupt the data flow. | +| 10 | Reserved | RO | 0 | Reserved for future use | +| 9 | Panel Path I/O Pads Output Disable | RW | 0x0 | 1: Disabled after next VSYNC
0x0: Enabled after next VSYNC | +| 8 | Panel Path Dumb LCD Panel GPIO Control Pin | RW | 0x0 | This field controls the backlight of a Dumb LCD Panel.
Active only when both the <Dumb Panel Backlight Clock Divider> and <Duty Cycle Control> fields in the Graphic Line Length (Pitch) Register are 0x0000. | +| 7 | Panel Path Configure Reverse RGB Bit Order | RW | 0x0 | 1: Reverse the RGB bit order
1. For example, R[7:0] G[7:0] B[7:0] are reversed to R[0:7] G[0:7] B[0:7].
0: Do not reverse. | +| 6 | Panel Path Invert Composite Blank Signal | RW | 0x0 | 1: Invert
0: Do not invert. | +| 5 | Panel Path Invert Composite Sync Signal | RW | 0x0 | 1: Invert
0: Do not invert. | +| 4 | Panel Path Invert Pixel Valid Enable | RW | 0x0 | 1: Invert
0: Do not invert. | +| 3 | Panel Path Invert VSYNC | RW | 0x0 | 1: Invert
0: Do not invert. | +| 2 | Panel Path Invert HSYNC | RW | 0x0 | 1: Invert
0: Do not invert. | +| 1 | Panel Path Invert Pixel Clock | RW | 0x0 | 1: Invert
0: Do not invert. | +| 0 | Panel Path Enable Dumb LCD Panel | RW | 0x0 | 1: Enabled
**Note. Smart Panel should be disabled when this bit is 1**
0: Disabled. | #### PN_IOPAD_CONTROL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1BC
BitsFieldTypeResetDescription
31Mask Panel Path Video Y SA UpdateRW0x01: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame.
30Mask Panel Path Video U SA UpdateRW0x01: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame.
29Mask Panel Path Video V SA UpdateRW0x01: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame.
28Mask Panel Path Graphic Y SA UpdateRW0x01: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame.
27Mask TV Path Video Y SA UpdateRW0x01: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame.
26Mask TV Path Video U SA UpdateRW0x01: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame.
25Mask TV Path Video V SA UpdateRW0x01: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame.
24Mask TV Path Graphic Y SA UpdateRW0x01: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame.
23Mask Panel Path Command SA UpdateRW0x01: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame.
22Mask TV Path Command SA UpdateRW0x01: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame.
21ReservedRO0Reserved for future use
20
Enable SA UpdateRW0x0- When set to 1, and the mask function is enabled, the Starting Address will be updated only once after VSYNC.
- If the mask function is disabled, this field is not used.
19TV Path Graphic Vertical Mirror EnableRW0x01: Enables vertical mirroring.
DMA fetches from the last line to the first line.
Note: The starting address for DMA must be set to the last line's starting address.
0: Disable
18ReservedRO0Reserved for future use
17TV Path Video Image Vertical Mirror EnableRW0x01: Enables vertical mirroring.
DMA fetches from the last line to the first line.
Note: The starting address for DMA must be set to the last line's starting address.
0: Disable
16ReservedRO0Reserved for future use
15Panel Path Graphic Vertical Mirror EnableRW0x01: Enables vertical mirroring.
DMA fetches from the last line to the first line.
Note: The starting address for DMA must be set to the last line's starting address.
0: Disable
14ReservedRO0Reserved for future use
13Panel Path Video Image Vertical Mirror EnableRW0x01: Enables vertical mirroring.
DMA fetches from the last line to the first line.
Note: The starting address for DMA must be set to the last line's starting address.
0: Disable
12Panel Path Command Vertical Mirror EnableRW0x01: Enables vertical mirroring.
DMA fetches from the last line to the first line.
Note: The starting address for DMA must be set to the last line's starting address.
0: Disable
11:10TV Path Configure Color Space ConversionRW0x0Configures color space conversion for TV Path:
0x0: CCIR601 YUV → Computer RGB
0x1: CCIR601 YUV → Studio RGB
0x2: CCIR709 YUV → Computer RGB
0x3: CCIR709 YUV → Studio RGB
9:8Panel Path Configure Color Space ConversionRW0x0Configures color space conversion for Panel Path:
0x0: CCIR601 YUV → Computer RGB
0x1: CCIR601 YUV → Studio RGB
0x2: CCIR709 YUV → Computer RGB
0x3: CCIR709 YUV → Studio RGB
7:6ReservedRO0Reserved for future use
5Indicates BoundaryRW0x00: No crossing 4 KB boundary
1: No crossing 1 KB boundary (usually for DDR memory).
4Indicates Cycle Burst LengthRW0x00: 8-cycle burst
1: 16-cycle burst (recommended for better performance).
3:0ReservedRO0Reserved for future use.
+**Offset: 0x1BC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Mask Panel Path Video Y SA Update | RW | 0x0 | 1: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame. | +| 30 | Mask Panel Path Video U SA Update | RW | 0x0 | 1: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame. | +| 29 | Mask Panel Path Video V SA Update | RW | 0x0 | 1: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame. | +| 28 | Mask Panel Path Graphic Y SA Update | RW | 0x0 | 1: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame. | +| 27 | Mask TV Path Video Y SA Update | RW | 0x0 | 1: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame. | +| 26 | Mask TV Path Video U SA Update | RW | 0x0 | 1: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame. | +| 25 | Mask TV Path Video V SA Update | RW | 0x0 | 1: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame. | +| 24 | Mask TV Path Graphic Y SA Update | RW | 0x0 | 1: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame. | +| 23 | Mask Panel Path Command SA Update | RW | 0x0 | 1: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame. | +| 22 | Mask TV Path Command SA Update | RW | 0x0 | 1: Masks Y Starting Address (SA) update for Panel Path Video.
Updates can occur once after writing both this bit and the <Enable SA Update> field to 1.
0 = Updates SA on each frame. | +| 21 | Reserved | RO | 0 | Reserved for future use | +| 20 | Enable SA Update | RW | 0x0 | - When set to 1, and the mask function is enabled, the Starting Address will be updated only once after VSYNC.
- If the mask function is disabled, this field is not used. | +| 19 | TV Path Graphic Vertical Mirror Enable | RW | 0x0 | 1: Enables vertical mirroring.
DMA fetches from the last line to the first line.
Note: The starting address for DMA must be set to the last line's starting address.
0: Disable | +| 18 | Reserved | RO | 0 | Reserved for future use | +| 17 | TV Path Video Image Vertical Mirror Enable | RW | 0x0 | 1: Enables vertical mirroring.
DMA fetches from the last line to the first line.
Note: The starting address for DMA must be set to the last line's starting address.
0: Disable | +| 16 | Reserved | RO | 0 | Reserved for future use | +| 15 | Panel Path Graphic Vertical Mirror Enable | RW | 0x0 | 1: Enables vertical mirroring.
DMA fetches from the last line to the first line.
Note: The starting address for DMA must be set to the last line's starting address.
0: Disable | +| 14 | Reserved | RO | 0 | Reserved for future use | +| 13 | Panel Path Video Image Vertical Mirror Enable | RW | 0x0 | 1: Enables vertical mirroring.
DMA fetches from the last line to the first line.
Note: The starting address for DMA must be set to the last line's starting address.
0: Disable | +| 12 | Panel Path Command Vertical Mirror Enable | RW | 0x0 | 1: Enables vertical mirroring.
DMA fetches from the last line to the first line.
Note: The starting address for DMA must be set to the last line's starting address.
0: Disable | +| 11:10 | TV Path Configure Color Space Conversion | RW | 0x0 | Configures color space conversion for TV Path:
0x0: CCIR601 YUV → Computer RGB
0x1: CCIR601 YUV → Studio RGB
0x2: CCIR709 YUV → Computer RGB
0x3: CCIR709 YUV → Studio RGB | +| 9:8 | Panel Path Configure Color Space Conversion | RW | 0x0 | Configures color space conversion for Panel Path:
0x0: CCIR601 YUV → Computer RGB
0x1: CCIR601 YUV → Studio RGB
0x2: CCIR709 YUV → Computer RGB
0x3: CCIR709 YUV → Studio RGB | +| 7:6 | Reserved | RO | 0 | Reserved for future use | +| 5 | Indicates Boundary | RW | 0x0 | 0: No crossing 4 KB boundary
1: No crossing 1 KB boundary (usually for DDR memory). | +| 4 | Indicates Cycle Burst Length | RW | 0x0 | 0: 8-cycle burst
1: 16-cycle burst (recommended for better performance). | +| 3:0 | Reserved | RO | 0 | Reserved for future use. | #### SPU_IRQ_ENA_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1C0
BitsFieldTypeResetDescription
31Panel Path DMA Frame 0 Done IRQ EnableRW0x01: Enabled
0: Disabled
30smt tx done IRQ EnableRW0x01: Enabled
0: Disabled
29Panel Path DMA FIFO Underflow IRQ EnableRW0x01: Enabled
0: Disabled
28AXI Bus Error IRQ EnableRW0x01: Enabled
0: Disabled
27Panel Path Graphic Frame 0 IRQ EnableRW0x01: Enabled
0: Disabled
26Panel Path Graphic Frame 1 IRQ EnableRW0x01: Enabled
0: Disabled
25Panel Path Graphic FIFO Underflow IRQ EnableRW0x01: Enabled
0: Disabled
24TV Path Hardware Cursor/OSD Frame Done IRQ EnableRW0x01: Enabled
0: Disabled
23Panel Path VSYNC Input Rising Edge IRQ EnableRW0x01: Enabled
0: Disabled
22Panel Path Dumb LCD Panel Frame Done IRQ EnableRW0x01: Enabled
0: Disabled
21Panel Path Smart Panel Frame Done IRQ EnableRW0x01: Enabled
0: Disabled
20SPI Transfer Frame Done IRQ EnableRW0x01: Enabled
0: Disabled
19AHB Slave Path All Command Empty IRQ EnableRW0x01: Enabled
0: Disabled
18SPI Bus Transfer Complete IRQ EnableRW0x01: Enabled
0: Disabled
17Power Down Request IRQ EnableRW0x01: Enabled
0: Disabled
16AXI Bus Latency Too Long IRQ EnableRW0x01: Enabled
0: Disabled
15Write Back fifo overrun EnableRW0x01: Enabled
0: Disabled
14Write Back Dma Done IRQ EnableRW0x01: Enabled
0: Disabled
13Write Back fifo underrun IRQ EnableRW0x01: Enabled
0: Disabled
12TV Path VSYNC Input Rising Edge IRQ EnableRW0x01: Enabled
0: Disabled
11TV Path Graphic Frame 0 IRQ EnableRW0x01: Enabled
0: Disabled
10TV Path Graphic Frame 1 IRQ EnableRW0x01: Enabled
0: Disabled
9TV Path Graphic FIFO Underflow IRQ EnableRW0x01: Enabled
0: Disabled
8TV Path Display Frame Done IRQ EnableRW0x01: Enabled
0: Disabled
7:0ReservedRO0Reserved for future use
+**Offset: 0x1C0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Panel Path DMA Frame 0 Done IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 30 | smt tx done IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 29 | Panel Path DMA FIFO Underflow IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 28 | AXI Bus Error IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 27 | Panel Path Graphic Frame 0 IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 26 | Panel Path Graphic Frame 1 IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 25 | Panel Path Graphic FIFO Underflow IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 24 | TV Path Hardware Cursor/OSD Frame Done IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 23 | Panel Path VSYNC Input Rising Edge IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 22 | Panel Path Dumb LCD Panel Frame Done IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 21 | Panel Path Smart Panel Frame Done IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 20 | SPI Transfer Frame Done IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 19 | AHB Slave Path All Command Empty IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 18 | SPI Bus Transfer Complete IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 17 | Power Down Request IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 16 | AXI Bus Latency Too Long IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 15 | Write Back fifo overrun Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 14 | Write Back Dma Done IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 13 | Write Back fifo underrun IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 12 | TV Path VSYNC Input Rising Edge IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 11 | TV Path Graphic Frame 0 IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 10 | TV Path Graphic Frame 1 IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 9 | TV Path Graphic FIFO Underflow IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 8 | TV Path Display Frame Done IRQ Enable | RW | 0x0 | 1: Enabled
0: Disabled | +| 7:0 | Reserved | RO | 0 | Reserved for future use | #### SPU_IRQ_ISR_RAW_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1C4
BitsFieldTypeResetDescription
31Panel Path Video Frame 0 Done Rising Edge IRQRW0x0Panel Path Video Frame 0 Done Rising Edge IRQ (before masking). 0: Clear interrupt
1: No effect
30smt tx done IRQRW0x0SMT TX Done IRQ (before masking)
0: Clear interrupt
1: No effect
29ReservedRO0Reserved for future use
28AXI Bus Error IRQRW0x0AXI Bus Error IRQ (before masking)
0: Clear interrupt
1: No effect
27Panel Path Graphic Frame 0 Done Rising Edge IRQRW0x0Panel Path Graphic Frame 0 Done Rising Edge IRQ (before masking)
0: Clear interrupt
1: No effect
26Panel Path Graphic Frame 1 Done Rising Edge IRQRW0x0Panel Path Graphic Frame 1 Done Rising Edge IRQ (before masking)
0: Clear interrupt
1: No effect
25Panel Path Graphic FIFO Underflow IRQRW0x0Panel Path Graphic FIFO Underflow IRQ (before masking)
0: Clear interrupt
1: No effect
24ReservedRO0Reserved for future use
23Panel Path VSYNC Input Rising Edge IRQRW0x0Panel Path VSYNC Input Rising Edge IRQ (before masking)
0: Clear interrupt
1: No effect
22ReservedRO0Reserved for future use
21Panel Path Smart Panel Display Area DMA Done IRQRW0x0Panel Path Smart Panel Display Area DMA Done IRQ (before masking)
0: Clear interrupt
1: No effect
20SPI Transfer Frame Done IRQRW0x0SPI Frame data Transfer Done IRQ (before masking)
0: Clear interrupt
1: No effect
19AHB Slave Path All Commands Output Done IRQRW0x0AHB Slave Path All Commands Output Done IRQ (before masking)
0: Clear interrupt
1: No effect
18SPI Bus Transfer Done IRQRW0x0SPI Bus Transfer Done IRQ (before masking)
0: Clear interrupt
1: No effect
17ReservedRO0Reserved for future use
16AXI Bus Latency Too Long IRQRW0x0AXI Bus Latency Too Long IRQ
This interrupt occurs when the response time exceeds 512 bus clocks (before masking).
0: Clear interrupt
1: No effect
15Write Back fifo overrunRW0x0Write Back FIFO underrun
14Write Back Dma DoneRW0x0Write Back DMA Done
13Write Back fifo underrunRW0x0Write Back FIFO underrun
12TV Path VSYNC Input Rising Edge IRQRW0x0TV Path VSYNC Input Rising Edge IRQ (before masking).
0: Clear interrupt
1: No effect
11TV Path Graphic Frame 0 Done Rising Edge IRQRW0x0TV Path Graphic Frame 0 Done Rising Edge IRQ (before masking)
0: Clear interrupt
1: No effect
10TV Path Graphic Frame 1 Done Rising Edge IRQRW0x0TV Path Graphic Frame 1 Done Rising Edge IRQ (before masking)
0: Clear interrupt
1: No effect
9TV Path Graphic FIFO Underflow IRQRW0x0TV Path Graphic FIFO Underflow IRQ (before masking)
0: Clear interrupt
1: No effect
8TV Path Display Screen Done IRQRW0x0TV Path Display Screen Done IRQ.
0: Clear interrupt
1: No effect
7:4ReservedRO0Reserved for future use
3Level of DMA_FF_EMPYRW0x0Level of DMA_FF_EMPY (before masking)
2Level of GRA_FF_EMPTYRW0x0Level of GRA_FF_EMPTY (before masking)
1ReservedRO0Reserved for future use
0Level of TVG_FF_EMPTYRW0x0Level of TVG_FF_EMPTY (before masking)
+**Offset: 0x1C4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Panel Path Video Frame 0 Done Rising Edge IRQ | RW | 0x0 | Panel Path Video Frame 0 Done Rising Edge IRQ (before masking). 0: Clear interrupt
1: No effect | +| 30 | smt tx done IRQ | RW | 0x0 | SMT TX Done IRQ (before masking)
0: Clear interrupt
1: No effect | +| 29 | Reserved | RO | 0 | Reserved for future use | +| 28 | AXI Bus Error IRQ | RW | 0x0 | AXI Bus Error IRQ (before masking)
0: Clear interrupt
1: No effect | +| 27 | Panel Path Graphic Frame 0 Done Rising Edge IRQ | RW | 0x0 | Panel Path Graphic Frame 0 Done Rising Edge IRQ (before masking)
0: Clear interrupt
1: No effect | +| 26 | Panel Path Graphic Frame 1 Done Rising Edge IRQ | RW | 0x0 | Panel Path Graphic Frame 1 Done Rising Edge IRQ (before masking)
0: Clear interrupt
1: No effect | +| 25 | Panel Path Graphic FIFO Underflow IRQ | RW | 0x0 | Panel Path Graphic FIFO Underflow IRQ (before masking)
0: Clear interrupt
1: No effect | +| 24 | Reserved | RO | 0 | Reserved for future use | +| 23 | Panel Path VSYNC Input Rising Edge IRQ | RW | 0x0 | Panel Path VSYNC Input Rising Edge IRQ (before masking)
0: Clear interrupt
1: No effect | +| 22 | Reserved | RO | 0 | Reserved for future use | +| 21 | Panel Path Smart Panel Display Area DMA Done IRQ | RW | 0x0 | Panel Path Smart Panel Display Area DMA Done IRQ (before masking)
0: Clear interrupt
1: No effect | +| 20 | SPI Transfer Frame Done IRQ | RW | 0x0 | SPI Frame data Transfer Done IRQ (before masking)
0: Clear interrupt
1: No effect | +| 19 | AHB Slave Path All Commands Output Done IRQ | RW | 0x0 | AHB Slave Path All Commands Output Done IRQ (before masking)
0: Clear interrupt
1: No effect | +| 18 | SPI Bus Transfer Done IRQ | RW | 0x0 | SPI Bus Transfer Done IRQ (before masking)
0: Clear interrupt
1: No effect | +| 17 | Reserved | RO | 0 | Reserved for future use | +| 16 | AXI Bus Latency Too Long IRQ | RW | 0x0 | AXI Bus Latency Too Long IRQ
This interrupt occurs when the response time exceeds 512 bus clocks (before masking).
0: Clear interrupt
1: No effect | +| 15 | Write Back fifo overrun | RW | 0x0 | Write Back FIFO underrun | +| 14 | Write Back Dma Done | RW | 0x0 | Write Back DMA Done | +| 13 | Write Back fifo underrun | RW | 0x0 | Write Back FIFO underrun | +| 12 | TV Path VSYNC Input Rising Edge IRQ | RW | 0x0 | TV Path VSYNC Input Rising Edge IRQ (before masking).
0: Clear interrupt
1: No effect | +| 11 | TV Path Graphic Frame 0 Done Rising Edge IRQ | RW | 0x0 | TV Path Graphic Frame 0 Done Rising Edge IRQ (before masking)
0: Clear interrupt
1: No effect | +| 10 | TV Path Graphic Frame 1 Done Rising Edge IRQ | RW | 0x0 | TV Path Graphic Frame 1 Done Rising Edge IRQ (before masking)
0: Clear interrupt
1: No effect | +| 9 | TV Path Graphic FIFO Underflow IRQ | RW | 0x0 | TV Path Graphic FIFO Underflow IRQ (before masking)
0: Clear interrupt
1: No effect | +| 8 | TV Path Display Screen Done IRQ | RW | 0x0 | TV Path Display Screen Done IRQ.
0: Clear interrupt
1: No effect | +| 7:4 | Reserved | RO | 0 | Reserved for future use | +| 3 | Level of DMA_FF_EMPY | RW | 0x0 | Level of DMA_FF_EMPY (before masking) | +| 2 | Level of GRA_FF_EMPTY | RW | 0x0 | Level of GRA_FF_EMPTY (before masking) | +| 1 | Reserved | RO | 0 | Reserved for future use | +| 0 | Level of TVG_FF_EMPTY | RW | 0x0 | Level of TVG_FF_EMPTY (before masking) | #### SPU_IRQ_RSR_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1C8
BitsFieldTypeResetDescription
31:8Read to Reset Status Register (Clean ISR[31:8])RW0x0- When SPU_IRQ_RSR[i] = 1:
1. Reading SPU_IRQ_ISR[i] clears the status and masks the interrupt.
2. If a new event occurs, the status is updated, but no new interrupt is triggered unless 0 is written to SPU_IRQ_ISR[i].
- When SPU_IRQ_RSR[i] = 0:
1. Reading SPU_IRQ_ISR[i] does not clear the status;
2. To clear both the status and the interrupt mask, write 0 to SPU_IRQ_ISR[i].
This mechanism is useful for systems that use status polling.
7:0ReservedRO0Reserved for future use
+**Offset: 0x1C8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Read to Reset Status Register (Clean ISR[31:8]) | RW | 0x0 | - When SPU_IRQ_RSR[i] = 1:
1. Reading SPU_IRQ_ISR[i] clears the status and masks the interrupt.
2. If a new event occurs, the status is updated, but no new interrupt is triggered unless 0 is written to SPU_IRQ_ISR[i].
- When SPU_IRQ_RSR[i] = 0:
1. Reading SPU_IRQ_ISR[i] does not clear the status;
2. To clear both the status and the interrupt mask, write 0 to SPU_IRQ_ISR[i].
This mechanism is useful for systems that use status polling. | +| 7:0 | Reserved | RO | 0 | Reserved for future use | #### LCD_GRA_CUTHPXL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1CC
BitsFieldTypeResetDescription
31:28Graphic Color [7:4]RW0x0- Defines the upper 4 bits of the Graphic Color used in the Partial Display Disable area.
- In the disabled area, the graphic is covered by video, so there is no need to read graphic memory.
- The disabled rectangle hollow area is defined by horizontal starting pixel, ending pixel and vertical starting line, ending line.
- Within the Partial Display Disable area, the pseudo 64-bit read data is formed as: {2{2{GRA_CUTCOLOR[15:0]}}}.
- This field is part of a spare area that defines the pseudo 64-bit read data color.
- By default: All bits are 0.
27:16Partial Display Disable Horizontal Ending Pixel NumberRW0x0- Specifies the horizontal ending pixel number of the Partial Display Disable area.
- This value must be less than the source graphic horizontal pixel number defined in the the <Panel Path Graphic Source Horizontal Pixel Number> field (in the Panel Graphic Source Size Register).
- The area between the starting pixel number and ending pixel number is the horizontal gap where graphic memory reads are disabled to reduce bandwidth.
15:12Graphic Color [3:0]RW0x0- Defines the lower 4 bits of the Graphic Color used in the Partial Display Disable area.
- Similar to Bits [31:28], this field is part of the pseudo 64-bit read data color definition.
11:0Partial Display Disable Horizontal Starting Pixel NumberRW0x0- Specifies the horizontal starting pixel number of the Partial Display Disable area.
- This value must be less than the source graphic horizontal pixel number defined in the the <Panel Path Graphic Source Horizontal Pixel Number> field (in the Panel Graphic Source Size Register).
- The area between the starting pixel number and ending pixel number is the horizontal gap where graphic memory reads are disabled to reduce bandwidth.
+**Offset: 0x1CC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Graphic Color [7:4] | RW | 0x0 | - Defines the upper 4 bits of the Graphic Color used in the Partial Display Disable area.
- In the disabled area, the graphic is covered by video, so there is no need to read graphic memory.
- The disabled rectangle hollow area is defined by horizontal starting pixel, ending pixel and vertical starting line, ending line.
- Within the Partial Display Disable area, the pseudo 64-bit read data is formed as: {2{2{GRA_CUTCOLOR[15:0]}}}.
- This field is part of a spare area that defines the pseudo 64-bit read data color.
- By default: All bits are 0. | +| 27:16 | Partial Display Disable Horizontal Ending Pixel Number | RW | 0x0 | - Specifies the horizontal ending pixel number of the Partial Display Disable area.
- This value must be less than the source graphic horizontal pixel number defined in the <Panel Path Graphic Source Horizontal Pixel Number> field (in the Panel Graphic Source Size Register).
- The area between the starting pixel number and ending pixel number is the horizontal gap where graphic memory reads are disabled to reduce bandwidth. | +| 15:12 | Graphic Color [3:0] | RW | 0x0 | - Defines the lower 4 bits of the Graphic Color used in the Partial Display Disable area.
- Similar to Bits [31:28], this field is part of the pseudo 64-bit read data color definition. | +| 11:0 | Partial Display Disable Horizontal Starting Pixel Number | RW | 0x0 | - Specifies the horizontal starting pixel number of the Partial Display Disable area.
- This value must be less than the source graphic horizontal pixel number defined in the <Panel Path Graphic Source Horizontal Pixel Number> field (in the Panel Graphic Source Size Register).
- The area between the starting pixel number and ending pixel number is the horizontal gap where graphic memory reads are disabled to reduce bandwidth. | #### LCD_GRA_CUTVLN_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1D0
BitsFieldTypeResetDescription
31:28Graphic Color [15:12]RW0x0- Defines bits [15:12] of the Graphic Color (GRA_CUTCOLOR[15:0]) used in the Partial Display Disable area.
- In the disabled area, the graphic is covered by video, so there is no need to read graphic memory.
- The disabled rectangle hollow area is defined by horizontal starting pixel, ending pixel and vertical starting line, ending line.
- The pseudo 64-bit read data in this area is composed of {2{2{GRA_CUTCOLOR[15:0]}}}.
- This field is part of a spare area that defines the pseudo 64-bit read data color.
- By default: All bits are 0.
27:16Partial Display Disable Vertical Ending Pixel NumberRW0x0- Specifies the vertical ending line number of the Partial Display Disable area.
- This value must be less than the source graphic vertical line number defined in the <Panel Path Graphic Source Vertical Line Number> field (in the Panel Graphic Source Size Register).
- The area between the starting line number and ending line number is the vertical gap where graphic memory reads are disabled to reduce bandwidth.
15:12Graphic Color [11:8]RW0x0- Defines bits [11:8] of the Graphic Color (GRA_CUTCOLOR[15:0]) used in the Partial Display Disable area.
- Similar to Bits 31:28, this field is part of the pseudo 64-bit read data color definition.
11:0Partial Display Disable Vertical Starting Pixel NumberRW0x0- Specifies the vertical starting line number of the Partial Display Disable area.
- This value must be less than the source graphic vertical line number defined in the <Panel Path Graphic Source Vertical Line Number> field (in the Panel Graphic Source Size Register).
- The area between the starting line number and ending line number is the vertical gap where graphic memory reads are disabled to reduce bandwidth.
+**Offset: 0x1D0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Graphic Color [15:12] | RW | 0x0 | - Defines bits [15:12] of the Graphic Color (GRA_CUTCOLOR[15:0]) used in the Partial Display Disable area.
- In the disabled area, the graphic is covered by video, so there is no need to read graphic memory.
- The disabled rectangle hollow area is defined by horizontal starting pixel, ending pixel and vertical starting line, ending line.
- The pseudo 64-bit read data in this area is composed of {2{2{GRA_CUTCOLOR[15:0]}}}.
- This field is part of a spare area that defines the pseudo 64-bit read data color.
- By default: All bits are 0. | +| 27:16 | Partial Display Disable Vertical Ending Pixel Number | RW | 0x0 | - Specifies the vertical ending line number of the Partial Display Disable area.
- This value must be less than the source graphic vertical line number defined in the <Panel Path Graphic Source Vertical Line Number> field (in the Panel Graphic Source Size Register).
- The area between the starting line number and ending line number is the vertical gap where graphic memory reads are disabled to reduce bandwidth. | +| 15:12 | Graphic Color [11:8] | RW | 0x0 | - Defines bits [11:8] of the Graphic Color (GRA_CUTCOLOR[15:0]) used in the Partial Display Disable area.
- Similar to Bits 31:28, this field is part of the pseudo 64-bit read data color definition. | +| 11:0 | Partial Display Disable Vertical Starting Pixel Number | RW | 0x0 | - Specifies the vertical starting line number of the Partial Display Disable area.
- This value must be less than the source graphic vertical line number defined in the <Panel Path Graphic Source Vertical Line Number> field (in the Panel Graphic Source Size Register).
- The area between the starting line number and ending line number is the vertical gap where graphic memory reads are disabled to reduce bandwidth. | #### LCD_TVG_CUTHPXL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1D4
BitsFieldTypeResetDescription
31:28Graphic Color [7:4]RW0x0- Defines bits [7:4] of the Graphic Color (TVG_CUTCOLOR[15:0]) used in the Partial Display Disable area.
- In the disabled area, the graphic is covered by video, so there is no need to read graphic memory.
- The disabled rectangle hollow area is defined by horizontal starting pixel, ending pixel and vertical starting line, ending line.
- The pseudo 64-bit read data in this area is composed of {2{2{TVG_CUTCOLOR[15:0]}}}.
- This field is part of a spare area that defines the pseudo 64-bit read data color.
- By default: All bits are 0.
27:16Partial Display Disable Horizontal Ending Pixel NumberRW0x0- Specifies the horizontal ending pixel number of the Partial Display Disable area.
- This value must be less than the source graphic horizontal pixel number defined in the <TV Path Graphic Source Horizontal Pixel Number> field (in the TV Graphic Source Size Register).
- The area between the starting pixel number and ending pixel number is the horizontal gap where graphic memory reads are disabled to reduce bandwidth.
15:12Graphic Color [3:0]RW0x0- Defines bits [3:0] of the Graphic Color (TVG_CUTCOLOR[15:0]) used in the Partial Display Disable area.
- Similar to Bits 31:28, this field is part of the pseudo 64-bit read data color definition.
11:0Partial Display Disable Horizontal Starting Pixel NumberRW0x0- Specifies the horizontal starting pixel number of the Partial Display Disable area.
- This value must be less than the source graphic horizontal pixel number defined in the <TV Path Graphic Source Horizontal Pixel Number> field (in the TV Graphic Source Size Register).
- The area between the starting pixel number and ending pixel number is the horizontal gap where graphic memory reads are disabled to reduce bandwidth.
+**Offset: 0x1D4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Graphic Color [7:4] | RW | 0x0 | - Defines bits [7:4] of the Graphic Color (TVG_CUTCOLOR[15:0]) used in the Partial Display Disable area.
- In the disabled area, the graphic is covered by video, so there is no need to read graphic memory.
- The disabled rectangle hollow area is defined by horizontal starting pixel, ending pixel and vertical starting line, ending line.
- The pseudo 64-bit read data in this area is composed of {2{2{TVG_CUTCOLOR[15:0]}}}.
- This field is part of a spare area that defines the pseudo 64-bit read data color.
- By default: All bits are 0. | +| 27:16 | Partial Display Disable Horizontal Ending Pixel Number | RW | 0x0 | - Specifies the horizontal ending pixel number of the Partial Display Disable area.
- This value must be less than the source graphic horizontal pixel number defined in the <TV Path Graphic Source Horizontal Pixel Number> field (in the TV Graphic Source Size Register).
- The area between the starting pixel number and ending pixel number is the horizontal gap where graphic memory reads are disabled to reduce bandwidth. | +| 15:12 | Graphic Color [3:0] | RW | 0x0 | - Defines bits [3:0] of the Graphic Color (TVG_CUTCOLOR[15:0]) used in the Partial Display Disable area.
- Similar to Bits 31:28, this field is part of the pseudo 64-bit read data color definition. | +| 11:0 | Partial Display Disable Horizontal Starting Pixel Number | RW | 0x0 | - Specifies the horizontal starting pixel number of the Partial Display Disable area.
- This value must be less than the source graphic horizontal pixel number defined in the <TV Path Graphic Source Horizontal Pixel Number> field (in the TV Graphic Source Size Register).
- The area between the starting pixel number and ending pixel number is the horizontal gap where graphic memory reads are disabled to reduce bandwidth. | #### LCD_TVG_CUTVLN_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1D8
BitsFieldTypeResetDescription
31:28Graphic Color [15:12]RW0x0- Defines bits [15:12] of the Graphic Color (GRA_CUTCOLOR[15:0]) used in the Partial Display Disable area.
- In the disabled area, the graphic is covered by video, so there is no need to read graphic memory.
- The disabled rectangle hollow area is defined by horizontal starting pixel, ending pixel and vertical starting line, ending line.
- The pseudo 64-bit read data in this area is composed of {2{2{GRA_CUTCOLOR[15:0]}}}.
- This field is part of a spare area that defines the pseudo 64-bit read data color.
27:16Partial Display Disable Vertical Ending Pixel NumberRW0x0- Specifies the vertical ending line number of the Partial Display Disable area.
- This value must be less than the source graphic vertical line number defined in the <Panel Path Graphic Source Vertical Line Number> field (in the Panel Graphic Source Size Register).
- The area between the starting line number and ending line number is the vertical gap where graphic memory reads are disabled to reduce bandwidth.
15:12Graphic Color [11:8]RW0x0- Defines bits [11:8] of the Graphic Color (GRA_CUTCOLOR[15:0]) used in the Partial Display Disable area.
- Similar to Bits 31:28, this field is part of the pseudo 64-bit read data color definition.
11:0Partial Display Disable Vertical Starting Pixel NumberRW0x0- Specifies the vertical starting line number of the Partial Display Disable area.
- This value must be less than the source graphic vertical line number defined in the in the <Source Vertical Line Number> field (in the Panel Graphic Source Size Register).
- The area between the starting line number and ending line number is the vertical gap where graphic memory reads are disabled to reduce bandwidth.
+**Offset: 0x1D8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Graphic Color [15:12] | RW | 0x0 | - Defines bits [15:12] of the Graphic Color (GRA_CUTCOLOR[15:0]) used in the Partial Display Disable area.
- In the disabled area, the graphic is covered by video, so there is no need to read graphic memory.
- The disabled rectangle hollow area is defined by horizontal starting pixel, ending pixel and vertical starting line, ending line.
- The pseudo 64-bit read data in this area is composed of {2{2{GRA_CUTCOLOR[15:0]}}}.
- This field is part of a spare area that defines the pseudo 64-bit read data color. | +| 27:16 | Partial Display Disable Vertical Ending Pixel Number | RW | 0x0 | - Specifies the vertical ending line number of the Partial Display Disable area.
- This value must be less than the source graphic vertical line number defined in the <Panel Path Graphic Source Vertical Line Number> field (in the Panel Graphic Source Size Register).
- The area between the starting line number and ending line number is the vertical gap where graphic memory reads are disabled to reduce bandwidth. | +| 15:12 | Graphic Color [11:8] | RW | 0x0 | - Defines bits [11:8] of the Graphic Color (GRA_CUTCOLOR[15:0]) used in the Partial Display Disable area.
- Similar to Bits 31:28, this field is part of the pseudo 64-bit read data color definition. | +| 11:0 | Partial Display Disable Vertical Starting Pixel Number | RW | 0x0 | - Specifies the vertical starting line number of the Partial Display Disable area.
- This value must be less than the source graphic vertical line number defined in the in the <Source Vertical Line Number> field (in the Panel Graphic Source Size Register).
- The area between the starting line number and ending line number is the vertical gap where graphic memory reads are disabled to reduce bandwidth. | #### LCD_TOP_CTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1DC
BitsFieldTypeResetDescription
31Invert I/O Pad VSYNCRW0x01: Invert dumb panel I/O pad VSYNC signal
0: No change
30Invert I/O Pad HSYNCRW0x01: Invert Dumb panel IO pad HSYNC signal
0: No change
29Invert I/O Pad PCLKRW0x01: Invert Dumb panel IO pad PCLK signal
0: No change
28Invert I/O Pad DENARW0x01: Invert Dumb panel IO pad DENA signal
0: No change
27:24Panel Path Configure MIPI DSI1 or CMU Input Color ModeRW0x0This field is used for the Panel Path to convert internal RGB888 pixels into the MIPI DSI1 color format.
0x0: 24-bit RGB88
0x1: 24-bit RGB88, but swap R and B
Others: Reserved
23:22Select All Objects for Panel or TV InterfaceRW0x0This field selects all four DMA objects to go to Panel or HDMI TV.
0x0: Auto-detect
0x1: All DMA objects go to Panel
0x2: All DMA objects go to HDMI TV
0x3: Panel path DMA to Panel, TV path DMA to TV
21Select Clock when One Clock Domain is EnabledRW0x00: Select panel clock for TV when one clock domain is enabled.
1: Select TV clock for Panel when one clock domain is enabled.
20Clock Domain SelectionRW0x0This field enables one clock domain for both TV and Panel.
1: One clock domain is selected
0: TV path and Panel path use different clock domains.
19Swap TV Path ProcessingRW0x00: TV path video processing is for video DMA, palette table is for graphic DMA.
1: TV path video processing is for graphic DMA, palette table is for video DMA.
18Swap TV Path EnableRW0x00: Auto detect TV path video processing path (<Swap TV Path Processing> field is ignored)
1: TV path video processing is selected by the <Swap TV Path Processing> field.
17Swap Panel Path ProcessingRW0x00: Panel path video processing is for video DMA, palette table is for graphic DMA.
1: Panel path video processing is for graphic DMA, palette table is for video DMA.
16Swap Panel Path EnableRW0x00: Auto detect Panel path video processing path (<Swap Panel Path Processing> field is ignored).
1: Panel path video processing is selected by the <Swap Panel Path Processing> field.
15:14Select TV Path Graphic DMA Burst LengthRW0x00x0: One burst (64 bytes)
0x1: Two bursts (128 bytes)
0x2: Three bursts (192 bytes)
0x3: Four bursts (256 bytes)
13:12Select TV Path Video DMA Burst LengthRW0x00x0: One burst (64 bytes)
0x1: Two bursts(128 bytes)
0x2: Three bursts (192 bytes)
0x3: Four bursts (256 bytes)
11:10Select Panel Path Graphic DMA Burst LengthRW0x00x0: One burst (64 bytes)
0x1: Two bursts (128 bytes)
0x2: Three bursts(192 bytes)
0x3: Four bursts (256 bytes)
9:8Select Panel Path Video DMA Burst LengthRW0x00x0: One burst (64 bytes)
0x1: Two bursts (128 bytes)
0x2: Three bursts(192 bytes)
0x3: Four bursts (256 bytes)
7:6AHB Slave Read Wait CyclesRW0x00x0: One AHB read wait cycle
0x1: Two AHB read wait cycles
0x2: Three AHB read wait cycles
0x3: Four AHB read wait cycles
5:4AHB Slave Write Wait CyclesRW0x00x0: One AHB read wait cycle
0x1: Two AHB read wait cycles
0x2: Three AHB read wait cycles
0x3: Four AHB read wait cycles
3:0ReservedRO0Reserved for future use.
+**Offset: 0x1DC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Invert I/O Pad VSYNC | RW | 0x0 | 1: Invert dumb panel I/O pad VSYNC signal
0: No change | +| 30 | Invert I/O Pad HSYNC | RW | 0x0 | 1: Invert Dumb panel IO pad HSYNC signal
0: No change | +| 29 | Invert I/O Pad PCLK | RW | 0x0 | 1: Invert Dumb panel IO pad PCLK signal
0: No change | +| 28 | Invert I/O Pad DENA | RW | 0x0 | 1: Invert Dumb panel IO pad DENA signal
0: No change | +| 27:24 | Panel Path Configure MIPI DSI1 or CMU Input Color Mode | RW | 0x0 | This field is used for the Panel Path to convert internal RGB888 pixels into the MIPI DSI1 color format.
0x0: 24-bit RGB88
0x1: 24-bit RGB88, but swap R and B
Others: Reserved | +| 23:22 | Select All Objects for Panel or TV Interface | RW | 0x0 | This field selects all four DMA objects to go to Panel or HDMI TV.
0x0: Auto-detect
0x1: All DMA objects go to Panel
0x2: All DMA objects go to HDMI TV
0x3: Panel path DMA to Panel, TV path DMA to TV | +| 21 | Select Clock when One Clock Domain is Enabled | RW | 0x0 | 0: Select panel clock for TV when one clock domain is enabled.
1: Select TV clock for Panel when one clock domain is enabled. | +| 20 | Clock Domain Selection | RW | 0x0 | This field enables one clock domain for both TV and Panel.
1: One clock domain is selected
0: TV path and Panel path use different clock domains. | +| 19 | Swap TV Path Processing | RW | 0x0 | 0: TV path video processing is for video DMA, palette table is for graphic DMA.
1: TV path video processing is for graphic DMA, palette table is for video DMA. | +| 18 | Swap TV Path Enable | RW | 0x0 | 0: Auto detect TV path video processing path (<Swap TV Path Processing> field is ignored)
1: TV path video processing is selected by the <Swap TV Path Processing> field. | +| 17 | Swap Panel Path Processing | RW | 0x0 | 0: Panel path video processing is for video DMA, palette table is for graphic DMA.
1: Panel path video processing is for graphic DMA, palette table is for video DMA. | +| 16 | Swap Panel Path Enable | RW | 0x0 | 0: Auto detect Panel path video processing path (<Swap Panel Path Processing> field is ignored).
1: Panel path video processing is selected by the <Swap Panel Path Processing> field. | +| 15:14 | Select TV Path Graphic DMA Burst Length | RW | 0x0 | 0x0: One burst (64 bytes)
0x1: Two bursts (128 bytes)
0x2: Three bursts (192 bytes)
0x3: Four bursts (256 bytes) | +| 13:12 | Select TV Path Video DMA Burst Length | RW | 0x0 | 0x0: One burst (64 bytes)
0x1: Two bursts(128 bytes)
0x2: Three bursts (192 bytes)
0x3: Four bursts (256 bytes) | +| 11:10 | Select Panel Path Graphic DMA Burst Length | RW | 0x0 | 0x0: One burst (64 bytes)
0x1: Two bursts (128 bytes)
0x2: Three bursts(192 bytes)
0x3: Four bursts (256 bytes) | +| 9:8 | Select Panel Path Video DMA Burst Length | RW | 0x0 | 0x0: One burst (64 bytes)
0x1: Two bursts (128 bytes)
0x2: Three bursts(192 bytes)
0x3: Four bursts (256 bytes) | +| 7:6 | AHB Slave Read Wait Cycles | RW | 0x0 | 0x0: One AHB read wait cycle
0x1: Two AHB read wait cycles
0x2: Three AHB read wait cycles
0x3: Four AHB read wait cycles | +| 5:4 | AHB Slave Write Wait Cycles | RW | 0x0 | 0x0: One AHB read wait cycle
0x1: Two AHB read wait cycles
0x2: Three AHB read wait cycles
0x3: Four AHB read wait cycles | +| 3:0 | Reserved | RO | 0 | Reserved for future use. | #### LCD_AFA_ALL2ONE_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1E8
BitsFieldTypeResetDescription
31:24ReservedRO0Reserved for future use
23Enable Two-Level Zoom Down in TV Path Graphic DMARW0x0Enables two-level zoom down for the TV Path Graphic DMA.
The source horizontal pixel (defined in the <TV Path Graphic Source Horizontal Pixel Number> field (in the TV Graphic Source Size Register)) must be an even number.
The zoom down is performed in two stages:
- First, the image is divided by 2.
- Then, it is further shrunk to the exact destination pixel number.
0x0: Disabled (direct zoom down, limited by 64-bit/pixel clock).
0x1: Enabled (allows higher zoom down ratios, e.g., for RGB565 mode, zoom down is limited by 4x, while two-level zoom down can make it to 8x).
22Enable Two-Level Zoom Down in TV Path Video DMARW0x0Enables two-level zoom down for the TV Path Video DMA.
Similar to Bit [23], but applies to the Video DMA.
0x0: Disabled (direct zoom down, limited by 64-bit/pixel clock).
0x1: Enabled (allows higher zoom down ratios, e.g., for RGB565 mode, zoom down is limited by 4x, while two-level zoom down can make it to 8x).
21Enable Two-Level Zoom Down in Panel Path Graphic DMARW0x0Enables two-level zoom down for the Panel Path Graphic DMA.
The source horizontal pixel (defined in the <TV Path Graphic Source Horizontal Pixel Number> field (in the TV Graphic Source Size Register)) must be an even number.
The zoom down is performed in two stages:
- First, the image is divided by 2.
- Then, it is further shrunk to the exact destination pixel number.
0x0: Disabled (direct zoom down, limited by 64-bit/pixel clock).
0x1: Enabled (allows higher zoom down ratios, e.g., for RGB565 mode, zoom down is limited by 4x, while two-level zoom down can make it to 8x).
20Enable Two-Level Zoom Down in Panel Path Video DMARW0x0Enables two-level zoom down for the Panel Path Video DMA.
Similar to Bit [21], but applies to the Video DMA.
0x0: Disabled (direct zoom down, limited by 64-bit/pixel clock).
0x1: Enabled (allows higher zoom down ratios, e.g., for RGB565 mode, zoom down is limited by 4x, while two-level zoom down can make it to 8x).
19:18Enable Graphic DMA Vertical SmoothRW0x0Enables vertical smoothing for graphic DMA.
Two graphic DMA channels are used to read two lines near the resampling line and apply smooth filtering.
0x0: Disabled (Graphic vertical smooth is not done).
0x1: Reserved.
0x2: Panel graphic vertical smooth (TV graphic DMA filters Panel graphic).
0x3: TV graphic vertical smooth (Panel graphic DMA filters TV graphic).
17:16Enable Video DMA Vertical SmoothRW0x0Enables vertical smoothing for video DMA.
Two video DMA channels are used to read two lines near the resampling line and apply smooth filtering.
0x0: Disabled (Video vertical smooth is not done).
0x1: Reserved.
0x2: Panel video vertical smooth (TV video DMA filters Panel video).
0x3: TV video vertical smooth (Panel video DMA filters TV video).
15:14Select Alpha when Panel and TV Path Graphics OverlaidRW0x0Selects the alpha blending source when Panel and TV Path graphics are overlaid.
0x0: TV path graphic DMA alpha.
0x1: Panel path graphic DMA alpha.
0x2: Panel path configured alpha.
0x3: TV path configured alpha.
13:12Select Alpha when Panel Path Graphic and TV Path Video OverlaidRW0x0Selects the alpha blending source when Panel Path graphic and TV Path video are overlaid.
0x0: TV path video DMA alpha.
0x1: Panel path graphic DMA alpha.
0x2: Panel path configured alpha.
0x3: TV path configured alpha.
11:10Select Alpha when Panel and TV Path Graphics OverlaidRW0x0Selects the alpha blending source when Panel and TV Path graphics are overlaid.
0x0: Panel path video DMA alpha.
0x1: TV path graphic DMA alpha.
0x2: Panel path configured alpha.
0x3: TV path configured alpha.
9:8Select Alpha when Panel and TV Path Videos OverlaidRW0x0Selects the alpha blending source when Panel and TV Path videos are overlaid.
0x0: Panel path video DMA alpha.
0x1: TV path video DMA alpha.
0x2: Panel path configured alpha.
0x3: TV path configured alpha.
7:5ReservedRO0Reserved for future use
4Select Hardware Cursor when Cursor OverlaidRW0x0When one path is disabled, all four objects and two cursor objects can be overlaid together.
Selects the hardware cursor when two cursors are overlaid.
0x0: Use Panel path cursor
0x1: Use TV path cursor
3:2ReservedRO0Reserved for future use
1:0Alpha Blending ModeRW0x0Alpha Blending Mode Selection. 0x0 = L0*(1-A1)+L1*A1, 0x1 = L0*(1-A1)+L1, 0x2 =L0*A1+L1, 0x3 = reserved.
Selects the alpha blending mode.
0x0: L0*(1-A1) + L1*A1
0x1: L0*(1-A1) + L1
0x2: L0*A1 + L1
0x3: Reserved
+**Offset: 0x1E8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Reserved | RO | 0 | Reserved for future use | +| 23 | Enable Two-Level Zoom Down in TV Path Graphic DMA | RW | 0x0 | Enables two-level zoom down for the TV Path Graphic DMA.
The source horizontal pixel (defined in the <TV Path Graphic Source Horizontal Pixel Number> field (in the TV Graphic Source Size Register)) must be an even number.
The zoom down is performed in two stages:
- First, the image is divided by 2.
- Then, it is further shrunk to the exact destination pixel number.
0x0: Disabled (direct zoom down, limited by 64-bit/pixel clock).
0x1: Enabled (allows higher zoom down ratios, e.g., for RGB565 mode, zoom down is limited by 4x, while two-level zoom down can make it to 8x). | +| 22 | Enable Two-Level Zoom Down in TV Path Video DMA | RW | 0x0 | Enables two-level zoom down for the TV Path Video DMA.
Similar to Bit [23], but applies to the Video DMA.
0x0: Disabled (direct zoom down, limited by 64-bit/pixel clock).
0x1: Enabled (allows higher zoom down ratios, e.g., for RGB565 mode, zoom down is limited by 4x, while two-level zoom down can make it to 8x). | +| 21 | Enable Two-Level Zoom Down in Panel Path Graphic DMA | RW | 0x0 | Enables two-level zoom down for the Panel Path Graphic DMA.
The source horizontal pixel (defined in the <TV Path Graphic Source Horizontal Pixel Number> field (in the TV Graphic Source Size Register)) must be an even number.
The zoom down is performed in two stages:
- First, the image is divided by 2.
- Then, it is further shrunk to the exact destination pixel number.
0x0: Disabled (direct zoom down, limited by 64-bit/pixel clock).
0x1: Enabled (allows higher zoom down ratios, e.g., for RGB565 mode, zoom down is limited by 4x, while two-level zoom down can make it to 8x). | +| 20 | Enable Two-Level Zoom Down in Panel Path Video DMA | RW | 0x0 | Enables two-level zoom down for the Panel Path Video DMA.
Similar to Bit [21], but applies to the Video DMA.
0x0: Disabled (direct zoom down, limited by 64-bit/pixel clock).
0x1: Enabled (allows higher zoom down ratios, e.g., for RGB565 mode, zoom down is limited by 4x, while two-level zoom down can make it to 8x). | +| 19:18 | Enable Graphic DMA Vertical Smooth | RW | 0x0 | Enables vertical smoothing for graphic DMA.
Two graphic DMA channels are used to read two lines near the resampling line and apply smooth filtering.
0x0: Disabled (Graphic vertical smooth is not done).
0x1: Reserved.
0x2: Panel graphic vertical smooth (TV graphic DMA filters Panel graphic).
0x3: TV graphic vertical smooth (Panel graphic DMA filters TV graphic). | +| 17:16 | Enable Video DMA Vertical Smooth | RW | 0x0 | Enables vertical smoothing for video DMA.
Two video DMA channels are used to read two lines near the resampling line and apply smooth filtering.
0x0: Disabled (Video vertical smooth is not done).
0x1: Reserved.
0x2: Panel video vertical smooth (TV video DMA filters Panel video).
0x3: TV video vertical smooth (Panel video DMA filters TV video). | +| 15:14 | Select Alpha when Panel and TV Path Graphics Overlaid | RW | 0x0 | Selects the alpha blending source when Panel and TV Path graphics are overlaid.
0x0: TV path graphic DMA alpha.
0x1: Panel path graphic DMA alpha.
0x2: Panel path configured alpha.
0x3: TV path configured alpha. | +| 13:12 | Select Alpha when Panel Path Graphic and TV Path Video Overlaid | RW | 0x0 | Selects the alpha blending source when Panel Path graphic and TV Path video are overlaid.
0x0: TV path video DMA alpha.
0x1: Panel path graphic DMA alpha.
0x2: Panel path configured alpha.
0x3: TV path configured alpha. | +| 11:10 | Select Alpha when Panel and TV Path Graphics Overlaid | RW | 0x0 | Selects the alpha blending source when Panel and TV Path graphics are overlaid.
0x0: Panel path video DMA alpha.
0x1: TV path graphic DMA alpha.
0x2: Panel path configured alpha.
0x3: TV path configured alpha. | +| 9:8 | Select Alpha when Panel and TV Path Videos Overlaid | RW | 0x0 | Selects the alpha blending source when Panel and TV Path videos are overlaid.
0x0: Panel path video DMA alpha.
0x1: TV path video DMA alpha.
0x2: Panel path configured alpha.
0x3: TV path configured alpha. | +| 7:5 | Reserved | RO | 0 | Reserved for future use | +| 4 | Select Hardware Cursor when Cursor Overlaid | RW | 0x0 | When one path is disabled, all four objects and two cursor objects can be overlaid together.
Selects the hardware cursor when two cursors are overlaid.
0x0: Use Panel path cursor
0x1: Use TV path cursor | +| 3:2 | Reserved | RO | 0 | Reserved for future use | +| 1:0 | Alpha Blending Mode | RW | 0x0 | Alpha Blending Mode Selection. 0x0 = L0*(1-A1)+L1*A1, 0x1 = L0*(1-A1)+L1, 0x2 =L0*A1+L1, 0x3 = reserved.
Selects the alpha blending mode.
0x0: L0*(1-A1) + L1*A1
0x1: L0*(1-A1) + L1
0x2: L0*A1 + L1
0x3: Reserved | #### LCD_DITHER_CTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1EC
BitsFieldTypeResetDescription
31:18ReservedRO0Reserved for future use
17:16Dither Table Index SelectionRW0x0Dither Table Index Selection. This field is used when software needs to read from or write to the dither table.
Selects the dither table index for software access.
0x0: Access dither table index 0.
0x1: Access dither table index 1.
0x2: Access dither table index 2.
0x3: Access dither table index 3.
15ReservedRO0Reserved for future use
14:12Dither Mode Selection For TV PathRW0x0Selects the dither mode for the TV Path.
0x0: RGB 444 mode.
0x1: RGB 565 mode.
0x2: RGB 666 mode.
11:10ReservedRO0Reserved for future use
9Dither Table 4x4 or 4x8 for TV PathRW0x0Selects the dither table size for the TV Path.
0x0: 4x4 dither table.
0x1: 4x8 dither table.
8Dither Enable for TV PathRW0x0Enables or disables dithering for the TV Path.
0x0: Disable dithering.
0x1: Enable dithering.
7ReservedRO0Reserved for future use
6:4Dither Mode Selection for Panel PathRW0x0Selects the dither mode for the Panel Path.
0x0: RGB 444 mode.
0x1: RGB 565 mode.
0x2: RGB 666 mode.
3:2ReservedRO0Reserved for future use
1Dither Table 4x4 or 4x8 for Panel PathRW0x0Selects the dither table size for the Panel Path.
0x0: 4x4 dither table.
0x1: 4x8 dither table.
0Dither Enable for Panel PathRW0x0Enables or disables dithering for the Panel Path.
0x0: Disable dithering.
0x1: Enable dithering.
+**Offset: 0x1EC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:18 | Reserved | RO | 0 | Reserved for future use | +| 17:16 | Dither Table Index Selection | RW | 0x0 | Dither Table Index Selection. This field is used when software needs to read from or write to the dither table.
Selects the dither table index for software access.
0x0: Access dither table index 0.
0x1: Access dither table index 1.
0x2: Access dither table index 2.
0x3: Access dither table index 3. | +| 15 | Reserved | RO | 0 | Reserved for future use | +| 14:12 | Dither Mode Selection For TV Path | RW | 0x0 | Selects the dither mode for the TV Path.
0x0: RGB 444 mode.
0x1: RGB 565 mode.
0x2: RGB 666 mode. | +| 11:10 | Reserved | RO | 0 | Reserved for future use | +| 9 | Dither Table 4x4 or 4x8 for TV Path | RW | 0x0 | Selects the dither table size for the TV Path.
0x0: 4x4 dither table.
0x1: 4x8 dither table. | +| 8 | Dither Enable for TV Path | RW | 0x0 | Enables or disables dithering for the TV Path.
0x0: Disable dithering.
0x1: Enable dithering. | +| 7 | Reserved | RO | 0 | Reserved for future use | +| 6:4 | Dither Mode Selection for Panel Path | RW | 0x0 | Selects the dither mode for the Panel Path.
0x0: RGB 444 mode.
0x1: RGB 565 mode.
0x2: RGB 666 mode. | +| 3:2 | Reserved | RO | 0 | Reserved for future use | +| 1 | Dither Table 4x4 or 4x8 for Panel Path | RW | 0x0 | Selects the dither table size for the Panel Path.
0x0: 4x4 dither table.
0x1: 4x8 dither table. | +| 0 | Dither Enable for Panel Path | RW | 0x0 | Enables or disables dithering for the Panel Path.
0x0: Disable dithering.
0x1: Enable dithering. | #### LCD_DITHER_TBL_DATA_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1F0
BitsFieldTypeResetDescription
31:0LCD Dither Table Data PortRW0x0There is a total of 128 bits for the dither table.
To access the dither table, use the <Dither Table Select Index> in the Dither Control Register.
- -####LCD_MISC_CTRL_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1F8
BitsFieldTypeResetDescription
31:24Configure SPI Transmit HWRW0x0hw control tx ibits, only for spi fast mode image. Configure SPI Transmit. 0x1F = Write/transmit 32 bits, 0x01 = Write/transmit 2 bits, 0x00 = Do not transfer. If the <Configure SPI Receive> field is set to 0x00, there is no receiving, only transmit. The maximum write length is 32 bits per trigger , and unlimited write length can be reached if triggering one after another and if the <Configure Continuous Transfer> field is set to 0x01. If the <Configure SPI Receive> field is not 0x00, it will first transmit serial bits, and then receive incoming bits.
Hardware-Controlled SPI Transmit (Fast Mode Only):
This field configures SPI data transmission in fast mode.
0x1F: Write/transmit 32 bits.
0x01: Write/transmit 2 bits.
0x00: Do not transfer.
- If the <Configure SPI Receive> field is set to `0x00`, only data transmission occurs without receiving.
1. The maximum write length is 32 bits per trigger.
2. Continuous transmission is possible if triggers are sent consecutively and the <Configure Continuous Transfer> field is set to 0x01.
- If the Configure SPI Receive field is not 0x00, the system will first transmit the serial bits and then receive incoming data.
23:21cfg_ch_timeRW0x0cs hold time = (cfg_ch_time+1)*period_sclk
20:19cfg_csu_timeRW0x0cs setup time = (cfg_csu_time+2)*period_sclk
18ReservedRO0Reserved for future use
17slv_fast_modeRW0x0indicate cmd in burst mode
16slv_burst_triggerRW0x0Set to 1 to trigger burst mode after command is settled (for slv_fast_mode).
15:12burst_length_hwRW0x0Hardware-controlled burst length (actual length is burst_length_hw + 1) for fast mode.
11:8burst_length_swRW0x0Software-controlled burst length (actual length is burst_length_sw + 1).
7spi cmd triggerRW0x0Write 1 before setting cmd only for fast mode
6spi_fast_modeRW0x0SPI fast mode control:
0x1: Software does not wait for SPI command completion IRQ.
0x0: Software waits.
5:4smpn2spi_modeRW0x00x0: 1 data lane mode
0x1: 2 data lane RGB888-3cycle mode
0x2: 2 data lane RGB666-3cycle mode
3Configure 3-/4-line SPIRW0x01: 3-line SPI, 9bit serial data
0: 4-line SPI, 8bit serial data+D/CX pin.
2spi_2ln_modeRW0x00x0: 1 data lane mode
0x1: 2 data lane mode.
1Smart Panel RB swapRW0x00x0: No swap
0x1: Swap RB (Set 1 for GC9305).
0SPI data path swap to hwRW0x00x0: CPU control
0x1: Hareware control
+**Offset: 0x1F0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | LCD Dither Table Data Port | RW | 0x0 | There is a total of 128 bits for the dither table.
To access the dither table, use the <Dither Table Select Index> in the Dither Control Register. | + +#### LCD_MISC_CTRL_REG REGISTER + +**Offset: 0x1F8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Configure SPI Transmit HW | RW | 0x0 | hw control tx ibits, only for spi fast mode image. Configure SPI Transmit. 0x1F = Write/transmit 32 bits, 0x01 = Write/transmit 2 bits, 0x00 = Do not transfer. If the <Configure SPI Receive> field is set to 0x00, there is no receiving, only transmit. The maximum write length is 32 bits per trigger, and unlimited write length can be reached if triggering one after another and if the <Configure Continuous Transfer> field is set to 0x01. If the <Configure SPI Receive> field is not 0x00, it will first transmit serial bits, and then receive incoming bits.
Hardware-Controlled SPI Transmit (Fast Mode Only):
This field configures SPI data transmission in fast mode.
0x1F: Write/transmit 32 bits.
0x01: Write/transmit 2 bits.
0x00: Do not transfer.
- If the <Configure SPI Receive> field is set to `0x00`, only data transmission occurs without receiving.
1. The maximum write length is 32 bits per trigger.
2. Continuous transmission is possible if triggers are sent consecutively and the <Configure Continuous Transfer> field is set to 0x01.
- If the Configure SPI Receive field is not 0x00, the system will first transmit the serial bits and then receive incoming data. | +| 23:21 | cfg_ch_time | RW | 0x0 | cs hold time = (cfg_ch_time+1)*period_sclk | +| 20:19 | cfg_csu_time | RW | 0x0 | cs setup time = (cfg_csu_time+2)*period_sclk | +| 18 | Reserved | RO | 0 | Reserved for future use | +| 17 | slv_fast_mode | RW | 0x0 | indicate cmd in burst mode | +| 16 | slv_burst_trigger | RW | 0x0 | Set to 1 to trigger burst mode after command is settled (for slv_fast_mode). | +| 15:12 | burst_length_hw | RW | 0x0 | Hardware-controlled burst length (actual length is burst_length_hw + 1) for fast mode. | +| 11:8 | burst_length_sw | RW | 0x0 | Software-controlled burst length (actual length is burst_length_sw + 1). | +| 7 | spi cmd trigger | RW | 0x0 | Write 1 before setting cmd only for fast mode | +| 6 | spi_fast_mode | RW | 0x0 | SPI fast mode control:
0x1: Software does not wait for SPI command completion IRQ.
0x0: Software waits. | +| 5:4 | smpn2spi_mode | RW | 0x0 | 0x0: 1 data lane mode
0x1: 2 data lane RGB888-3cycle mode
0x2: 2 data lane RGB666-3cycle mode | +| 3 | Configure 3-/4-line SPI | RW | 0x0 | 1: 3-line SPI, 9bit serial data
0: 4-line SPI, 8bit serial data+D/CX pin. | +| 2 | spi_2ln_mode | RW | 0x0 | 0x0: 1 data lane mode
0x1: 2 data lane mode. | +| 1 | Smart Panel RB swap | RW | 0x0 | 0x0: No swap
0x1: Swap RB (Set 1 for GC9305). | +| 0 | SPI data path swap to hw | RW | 0x0 | 0x0: CPU control
0x1: Hareware control | #### LCD_WDMA_CTRL1_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x200
BitsFieldTypeResetDescription
31:16wdma_img_pitchRW0x0wdma pitch by bytes
15:13ReservedRO0Reserved for future use
12:8wdma_burst_lenRW0x0wdma burst length by bytes
7:6ReservedRO0Reserved for future use
5:4wdma_pix_fmtRW0x00: 16bit RGB565
1: 24bit RGB888
2: 32bit ARGB8888
3: 32bit RGBA8888
3:1ReservedRO0Reserved for future use
0wdma_enaRW0x01: Valid
+**Offset: 0x200** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | wdma_img_pitch | RW | 0x0 | wdma pitch by bytes | +| 15:13 | Reserved | RO | 0 | Reserved for future use | +| 12:8 | wdma_burst_len | RW | 0x0 | wdma burst length by bytes | +| 7:6 | Reserved | RO | 0 | Reserved for future use | +| 5:4 | wdma_pix_fmt | RW | 0x0 | 0: 16bit RGB565
1: 24bit RGB888
2: 32bit ARGB8888
3: 32bit RGBA8888 | +| 3:1 | Reserved | RO | 0 | Reserved for future use | +| 0 | wdma_ena | RW | 0x0 | 1: Valid | #### LCD_WDMA_CTRL2_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x204
BitsFieldTypeResetDescription
31:28ReservedRO0Reserved for future use
27:16wdma_img_heightRW0x0wdma_img_height
15:13ReservedRO0Reserved for future use
12:0wdma_img_widthRW0x0wdma_img_width
+**Offset: 0x204** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Reserved | RO | 0 | Reserved for future use | +| 27:16 | wdma_img_height | RW | 0x0 | wdma_img_height | +| 15:13 | Reserved | RO | 0 | Reserved for future use | +| 12:0 | wdma_img_width | RW | 0x0 | wdma_img_width | #### LCD_WDMA_CTRL3_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x208
BitsFieldTypeResetDescription
31:0wdma_base_addrRW0x0wdma_base_addr
+**Offset: 0x208** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | wdma_base_addr | RW | 0x0 | wdma_base_addr | #### LCD_WDMA_CTRL4_REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x20C
BitsFieldTypeResetDescription
31:21ReservedRO0Reserved for future use
20dmac_wr_errRO0x0dmac_wr_err
19dmac_rst_n_pwrRW0x0dmac_rst_n_pwr
18dmac_rst_reqRW0x0dmac_rst_req
17dmac_wr_int_clrRW0x0dmac_wr_int_clr
16dmac_axi_secRW0x0dmac_axi_sec
15dmac_wr_post_enRW0x0dmac_wr_post_en
14:12dmac_max_req_numRW0x0dmac_max_req_num
11:8dmac_arqosRW0x0dmac_awqos
7:4dmac_awqosRW0x0dmac_awqos
3:0dmac_user_idRW0x0dmac_user_id
+**Offset: 0x20C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:21 | Reserved | RO | 0 | Reserved for future use | +| 20 | dmac_wr_err | RO | 0x0 | dmac_wr_err | +| 19 | dmac_rst_n_pwr | RW | 0x0 | dmac_rst_n_pwr | +| 18 | dmac_rst_req | RW | 0x0 | dmac_rst_req | +| 17 | dmac_wr_int_clr | RW | 0x0 | dmac_wr_int_clr | +| 16 | dmac_axi_sec | RW | 0x0 | dmac_axi_sec | +| 15 | dmac_wr_post_en | RW | 0x0 | dmac_wr_post_en | +| 14:12 | dmac_max_req_num | RW | 0x0 | dmac_max_req_num | +| 11:8 | dmac_arqos | RW | 0x0 | dmac_awqos | +| 7:4 | dmac_awqos | RW | 0x0 | dmac_awqos | +| 3:0 | dmac_user_id | RW | 0x0 | dmac_user_id | diff --git a/en/key_stone/k1/k1_docs/k1_usermanual/13.Video_Capture_Subsystem.md b/en/key_stone/k1/k1_docs/k1_usermanual/13.Video_Capture_Subsystem.md index 2e24799..c2b7f37 100644 --- a/en/key_stone/k1/k1_docs/k1_usermanual/13.Video_Capture_Subsystem.md +++ b/en/key_stone/k1/k1_docs/k1_usermanual/13.Video_Capture_Subsystem.md @@ -66,7 +66,7 @@ K1 includes a high-performance Image Signal Processor (ISP) which supports simul - Continuous video AF - Hardware 3D denoise - Multi-layer 2D YUV denoise -- Post-processing fof lens shading correction +- Post-processing for lens shading correction - Edge enhancement > **Notes**. To be highlighted the following limitations: diff --git a/en/key_stone/k1/k1_docs/k1_usermanual/14.RCPU_Subsystem.md b/en/key_stone/k1/k1_docs/k1_usermanual/14.RCPU_Subsystem.md index 2241f0f..1acd520 100644 --- a/en/key_stone/k1/k1_docs/k1_usermanual/14.RCPU_Subsystem.md +++ b/en/key_stone/k1/k1_docs/k1_usermanual/14.RCPU_Subsystem.md @@ -47,624 +47,142 @@ The applications of the RCPU subsystem can access its memory and peripherals. #### AUDIO_PMU_VOTE REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x18
BitsFieldTypeResetDescription
31:4ReservedRO0Reserved for future use
3Vote for audio PMU to enter PWR OFF modeRW0x1
1: Allow audio PMU to enter power-off mode.
0: Deny audio PMU from entering power-off mode.
2Vote for audio PMU to enter PLL OFF modeRW0x11: Allow audio PMU to enter PLL-off mode.
0: Deny audio PMU from entering PLL-off mode.
1Vote for audio PMU to enter low-power modeRW0x11: Allow audio PMU to enter low-power mode.
0: Deny audio PMU from entering low-power mode.
0ReservedRO0Reserved for future use
+**Offset: 0x18** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | Reserved | RO | 0 | Reserved for future use | +| 3 | Vote for audio PMU to enter PWR OFF mode | RW | 0x1 | 1: Allow audio PMU to enter power-off mode.
0: Deny audio PMU from entering power-off mode. | +| 2 | Vote for audio PMU to enter PLL OFF mode | RW | 0x1 | 1: Allow audio PMU to enter PLL-off mode.
0: Deny audio PMU from entering PLL-off mode. | +| 1 | Vote for audio PMU to enter low-power mode | RW | 0x1 | 1: Allow audio PMU to enter low-power mode.
0: Deny audio PMU from entering low-power mode. | +| 0 | Reserved | RO | 0 | Reserved for future use | #### AUDIO_VOTE_FOR_MAIN_PMU REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x20
BitsFieldTypeResetDescription
31:7ReservedRO0Reserved for future use
6Audio vote for AP AXI clock offRW0x11: Allow AP AXI clock off
0: Deny AP AXI clock off
5Audio vote for DDR shutdownRW0x11: Allow DDR shutdown
0: Deny DDR shutdown
4ReservedRO0Reserved for future use
3Audio vote for VCTCXO offRW0x11: Allow VCTCXO off.
0: Deny VCTCXO off.
2Audio vote for main PMU sleep stateRW0x11: Allow main PMU to enter sleep state.
0: Deny main PMU sleep state.
1Audio vote for AP standby stateRW0x11: Allow AP to go to standby state.
0: Deny AP standby state.
0ReservedRO0Reserved for future use
+**Offset: 0x20** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | Reserved | RO | 0 | Reserved for future use | +| 6 | Audio vote for AP AXI clock off | RW | 0x1 | 1: Allow AP AXI clock off
0: Deny AP AXI clock off | +| 5 | Audio vote for DDR shutdown | RW | 0x1 | 1: Allow DDR shutdown
0: Deny DDR shutdown | +| 4 | Reserved | RO | 0 | Reserved for future use | +| 3 | Audio vote for VCTCXO off | RW | 0x1 | 1: Allow VCTCXO off.
0: Deny VCTCXO off. | +| 2 | Audio vote for main PMU sleep state | RW | 0x1 | 1: Allow main PMU to enter sleep state.
0: Deny main PMU sleep state. | +| 1 | Audio vote for AP standby state | RW | 0x1 | 1: Allow AP to go to standby state.
0: Deny AP standby state. | +| 0 | Reserved | RO | 0 | Reserved for future use | #### AUDIO_WAKEUP_EN REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x28
BitsFieldTypeResetDescription
31:8ReservedRO0Reserved for future use
7ReservedRO0Reserved for future use
6ReservedRO0Reserved for future use
5ReservedRO0Reserved for future use
4timer_wkup_enRW0x0Audio timer wake up enable
1: Enable
0: Disable
3ap_wkup_enRW0x0AP wake up enable
1: Enable
0: Disable
2ReservedRO0Reserved for future use
1ipc_ap_wkup_enRW0x0Audio to AP IPC wake up enable
1: Enable
0: Disable
0shub_int_wkup_enRW0x0Audio sensor hub wake up enable
1: Enable
0: Disable
+**Offset: 0x28** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0 | Reserved for future use | +| 7 | Reserved | RO | 0 | Reserved for future use | +| 6 | Reserved | RO | 0 | Reserved for future use | +| 5 | Reserved | RO | 0 | Reserved for future use | +| 4 | timer_wkup_en | RW | 0x0 | Audio timer wake up enable
1: Enable
0: Disable | +| 3 | ap_wkup_en | RW | 0x0 | AP wake up enable
1: Enable
0: Disable | +| 2 | Reserved | RO | 0 | Reserved for future use | +| 1 | ipc_ap_wkup_en | RW | 0x0 | Audio to AP IPC wake up enable
1: Enable
0: Disable | +| 0 | shub_int_wkup_en | RW | 0x0 | Audio sensor hub wake up enable
1: Enable
0: Disable | #### AON_PER_CLK_RST_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x2C
BitsFieldTypeResetDescription
31:2Reserved
RO0Reserved for future use
1ipc2ap clk enableRW0x01: Enable
0: Disable
0aipc_ap_rstnRW0x01: Release reset
0: Reset
+**Offset: 0x2C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | RO | 0 | Reserved for future use | +| 1 | ipc2ap clk enable | RW | 0x0 | 1: Enable
0: Disable | +| 0 | aipc_ap_rstn | RW | 0x0 | 1: Release reset
0: Reset | #### MCU_EXECUTION_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x30
BitsFieldTypeResetDescription
31:1ReservedRO0Reserved for future use
0mcu_execution_ctrlRW0x01: Let MCU run
0: Halt MCU
+**Offset: 0x30** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:1 | Reserved | RO | 0 | Reserved for future use | +| 0 | mcu_execution_ctrl | RW | 0x0 | 1: Let MCU run
0: Halt MCU | #### AUDIO_BUS_CLK_DIV REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x38
BitsFieldTypeResetDescription
31:7ReservedRO0Reserved for future use
6:4apb_clk_divRW0x30: rsvd
1: div2
2: div4
3: div8
4: div16
5: rsvd
6: rsvd
7: rsvd
3:2ReservedRO0Reserved for future use
1:0axi_clk_divRW0x10: div1
1: div2
2: div4
3: div8
+**Offset: 0x38** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | Reserved | RO | 0 | Reserved for future use | +| 6:4 | apb_clk_div | RW | 0x3 | 0: rsvd
1: div2
2: div4
3: div8
4: div16
5: rsvd
6: rsvd
7: rsvd | +| 3:2 | Reserved | RO | 0 | Reserved for future use | +| 1:0 | axi_clk_div | RW | 0x1 | 0: div1
1: div2
2: div4
3: div8 | #### SHUB_GPO REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x3C
BitsFieldTypeResetDescription
31:8ReservedRO0Reserved for future use
7:0shub_gpoRW0x0Sensor hub GPIO output value
+**Offset: 0x3C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0 | Reserved for future use | +| 7:0 | shub_gpo | RW | 0x0 | Sensor hub GPIO output value | #### AUDIO_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xE0
BitsFieldTypeResetDescription
31audio ADC test interrupt statusRW0x0Audio ADC test mode interrupt status
1: Test Done
30ReservedRO0Reserved for future use
29hook key interrupt clearRW0x0Clear the latched interrupt for hook key event
1: Clear
Hook key interrupt status is stored in AUDIO_STATUS[21:14]
28:24Hook key detection debuonce clock dividerRW0xFSpecify the hook-key-detection debounce clock.
The debounce clock is divided from 32KHz clock.
23Class G right channel OCP interrupt clearRW0x0Clear the latched interrupt for Class G right channel OCP.
1: Clear
Interrupt status is stored in AUDIO_STATUS[13]
22Class G left channel OCP interrupt clearRW0x0Clear the latched interrupt for Class G left channel OCP.
1: Clear
Interrupt status is stored in AUDIO_STATUS[12]
21Class AB OCP interrupt clearRW0x0Clear the latched interrupt for Class AB OCP.
1: Clear
Interrupt status is stored in AUDIO_STATUS[11]
20:15ReservedRO0Reserved for future use
14classge_shortpwr int enableRW0x00: Disable Class G short power interrupt.
1: Enable Class G short power interrupt.
13classge_r_shortpwr_clrRW0x0Clear the classg_r_short pwr interrupt.
1: Clear interrupt
12classge_l_shortpwr_clrRW0x0Clear the classg_l_short pwr interrupt.
1: Clear interrupt
11:4ReservedRO0Reserved for future use
3plug wakeup interrupt clearRW0x0Clear the latched plug in or plug out wakeup interrupt.
1: Clear interrupt
Plug interrupt status is stored in AUDIO_STATUS[10:9]
2auto OCP reset assertionRW0x1Enable automatic generation of ocp_rst for class G and class AB.
1: Enable
0: Disable
1analog test mode interrupt maskRW0x0Enable interrupt when audio ADC test is done.
1: Enable interrupt
0analog plugin polarityRW0x00: Plugin status high indicates a plugin event.
1: Plugin status low indicates a plugin event.
+**Offset: 0xE0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | audio ADC test interrupt status | RW | 0x0 | Audio ADC test mode interrupt status
1: Test Done | +| 30 | Reserved | RO | 0 | Reserved for future use | +| 29 | hook key interrupt clear | RW | 0x0 | Clear the latched interrupt for hook key event
1: Clear
Hook key interrupt status is stored in AUDIO_STATUS[21:14] | +| 28:24 | Hook key detection debuonce clock divider | RW | 0xF | Specify the hook-key-detection debounce clock.
The debounce clock is divided from 32KHz clock. | +| 23 | Class G right channel OCP interrupt clear | RW | 0x0 | Clear the latched interrupt for Class G right channel OCP.
1: Clear
Interrupt status is stored in AUDIO_STATUS[13] | +| 22 | Class G left channel OCP interrupt clear | RW | 0x0 | Clear the latched interrupt for Class G left channel OCP.
1: Clear
Interrupt status is stored in AUDIO_STATUS[12] | +| 21 | Class AB OCP interrupt clear | RW | 0x0 | Clear the latched interrupt for Class AB OCP.
1: Clear
Interrupt status is stored in AUDIO_STATUS[11] | +| 20:15 | Reserved | RO | 0 | Reserved for future use | +| 14 | classge_shortpwr int enable | RW | 0x0 | 0: Disable Class G short power interrupt.
1: Enable Class G short power interrupt. | +| 13 | classge_r_shortpwr_clr | RW | 0x0 | Clear the classg_r_short pwr interrupt.
1: Clear interrupt | +| 12 | classge_l_shortpwr_clr | RW | 0x0 | Clear the classg_l_short pwr interrupt.
1: Clear interrupt | +| 11:4 | Reserved | RO | 0 | Reserved for future use | +| 3 | plug wakeup interrupt clear | RW | 0x0 | Clear the latched plug in or plug out wakeup interrupt.
1: Clear interrupt
Plug interrupt status is stored in AUDIO_STATUS[10:9] | +| 2 | auto OCP reset assertion | RW | 0x1 | Enable automatic generation of ocp_rst for class G and class AB.
1: Enable
0: Disable | +| 1 | analog test mode interrupt mask | RW | 0x0 | Enable interrupt when audio ADC test is done.
1: Enable interrupt | +| 0 | analog plugin polarity | RW | 0x0 | 0: Plugin status high indicates a plugin event.
1: Plugin status low indicates a plugin event. | #### AUDIO_CTRL2 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xE4
BitsFieldTypeResetDescription
31:28ReservedRO0Reserved for future use
27:19OCP length for Class GRW0xffSpecifies the number of 32KHz cycles of Class G OCP assertion before ocp_rst is automatically generated.
18:14OCP occurance times before interrupt for classgRW0x1fSpecifies the number of OCP assertions before an interrupt is generated for Class G.
13:5OCP length for rcvRW0x7Specifies the number of 32KHz cycles of RCV OCP assertion before ocp_rst is automatically generated.
4:0OCP occurance times before interrupt for rcvRW0x2Specifies the number of OCP assertions before an interrupt is generated for RCV.
+**Offset: 0xE4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Reserved | RO | 0 | Reserved for future use | +| 27:19 | OCP length for Class G | RW | 0xff | Specifies the number of 32KHz cycles of Class G OCP assertion before ocp_rst is automatically generated. | +| 18:14 | OCP occurance times before interrupt for classg | RW | 0x1f | Specifies the number of OCP assertions before an interrupt is generated for Class G. | +| 13:5 | OCP length for rcv | RW | 0x7 | Specifies the number of 32KHz cycles of RCV OCP assertion before ocp_rst is automatically generated. | +| 4:0 | OCP occurance times before interrupt for rcv | RW | 0x2 | Specifies the number of OCP assertions before an interrupt is generated for RCV. | #### AUD_DET_CLK_DIV REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xE8
BitsFieldTypeResetDescription
31:28ReservedRO0Reserved for future use
27:16hok_deb_divRW0xFFhok_deb_div
15:12ReservedRO0Reserved for future use
11:0plg_deb_divRW0xFFplg_deb_div
+**Offset: 0xE8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:28 | Reserved | RO | 0 | Reserved for future use | +| 27:16 | hok_deb_div | RW | 0xFF | hok_deb_div | +| 15:12 | Reserved | RO | 0 | Reserved for future use | +| 11:0 | plg_deb_div | RW | 0xFF | plg_deb_div | #### AUD_INT_MSK REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xF0
BitsFieldTypeResetDescription
31:3ReservedRO0Reserved for future use
2Interrupt mask for aud_ocpgr_int, aud_ocpgl_int, aud_ocpab_intRW0x00: Enable interrupt
1: Disable interrupt
1Interrupt mask for plugin/plugoutRW0x00: Enable interrupt
1: Disable interrupt
0hook_key_int_mskRW0x00: Enable interrupt
1: Disable interrupt
+**Offset: 0xF0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | Reserved | RO | 0 | Reserved for future use | +| 2 | Interrupt mask for aud_ocpgr_int, aud_ocpgl_int, aud_ocpab_int | RW | 0x0 | 0: Enable interrupt
1: Disable interrupt | +| 1 | Interrupt mask for plugin/plugout | RW | 0x0 | 0: Enable interrupt
1: Disable interrupt | +| 0 | hook_key_int_msk | RW | 0x0 | 0: Enable interrupt
1: Disable interrupt | ### 15.3.2 AUD_MCUSYSCTRL Registers @@ -672,465 +190,101 @@ The applications of the RCPU subsystem can access its memory and peripherals. #### SHUBSSP0_CLK_RES_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x28
BitsFieldTypeResetDescription
31:19ReservedRO0Reserved for future use
18:8shubssp0 clk divRW0x0Clock divider for SHub SSP0:
fclk = source_clk / (shubssp0_fclk_div + 1)
7:6ReservedRO0Reserved for future use
5:4shubssp0 fclk selRW0x0Select the SHub SSP0 frequency clock:
00: clk_62m
01: clk_24p576m
10: clk_13m
11: clk_3p25m
3ReservedRO0Reserved for future use
2shubssp0 pclk Enable/DisableRW0x0Enable bit for SHub SSP0 peripheral clock (pclk)
0: Disable
1: Enable
1shubssp0 fclk Enable/DisableRW0x0Enable bit for SHub SSP0 frequency clock (fclk)
0: Disable
1: Enable
0shubssp0 reset Enable/DisableRW0x0Enable bit for SHub SSP0 reset
0: Disable
1: Enable
+**Offset: 0x28** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | Reserved | RO | 0 | Reserved for future use | +| 18:8 | shubssp0 clk div | RW | 0x0 | Clock divider for SHub SSP0:
fclk = source_clk / (shubssp0_fclk_div + 1) | +| 7:6 | Reserved | RO | 0 | Reserved for future use | +| 5:4 | shubssp0 fclk sel | RW | 0x0 | Select the SHub SSP0 frequency clock:
00: clk_62m
01: clk_24p576m
10: clk_13m
11: clk_3p25m | +| 3 | Reserved | RO | 0 | Reserved for future use | +| 2 | shubssp0 pclk Enable/Disable | RW | 0x0 | Enable bit for SHub SSP0 peripheral clock (pclk)
0: Disable
1: Enable | +| 1 | shubssp0 fclk Enable/Disable | RW | 0x0 | Enable bit for SHub SSP0 frequency clock (fclk)
0: Disable
1: Enable | +| 0 | shubssp0 reset Enable/Disable | RW | 0x0 | Enable bit for SHub SSP0 reset
0: Disable
1: Enable | #### SHUBI2C0_CLK_RES_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x30
BitsFieldTypeResetDescription
31:19ReservedRO0Reserved for future use
18:8shubi2c0 clk divRW0x0Clock divider for SHub I²C0:
fclk= source_clk/(shubi2c0_fclk_div + 1)
7:6ReservedRO0Reserved for future use
5:4shubi2c0 fclk selRW0x0Select the SHub I²C0 frequency clock:
00: clk_62m
01: clk_26m
10: clk_13m
11: clk_3p25m
3ReservedRO0Reserved for future use
2shubi2c0 pclk Enable/DisableRW0x0Enable bit for SHub I²C0 peripheral clock (pclk)
0: Disable
1: Enable
1shubi2c0 fclk Enable/DisableRW0x0Enable bit for SHub I²C0 frequency clock (fclk)
0: Disable
1: Enable
0shubi2c0 reset Enable/DisableRW0x0Enable bit for SHub I²C0 reset
0: Disable
1: Enable
+**Offset: 0x30** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | Reserved | RO | 0 | Reserved for future use | +| 18:8 | shubi2c0 clk div | RW | 0x0 | Clock divider for SHub I虏C0:
fclk= source_clk/(shubi2c0_fclk_div + 1) | +| 7:6 | Reserved | RO | 0 | Reserved for future use | +| 5:4 | shubi2c0 fclk sel | RW | 0x0 | Select the SHub I虏C0 frequency clock:
00: clk_62m
01: clk_26m
10: clk_13m
11: clk_3p25m | +| 3 | Reserved | RO | 0 | Reserved for future use | +| 2 | shubi2c0 pclk Enable/Disable | RW | 0x0 | Enable bit for SHub I虏C0 peripheral clock (pclk)
0: Disable
1: Enable | +| 1 | shubi2c0 fclk Enable/Disable | RW | 0x0 | Enable bit for SHub I虏C0 frequency clock (fclk)
0: Disable
1: Enable | +| 0 | shubi2c0 reset Enable/Disable | RW | 0x0 | Enable bit for SHub I虏C0 reset
0: Disable
1: Enable | #### UART1_CLK_RES_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x3C
BitsFieldTypeResetDescription
31:19ReservedRO0Reserved for future use
18:8uart clk divRW0x0UART clock divider:
fclk = source_clk / (uart_fclk_div + 1)
7:6ReservedRO0Reserved for future use
5:4uart fclk selRW0x0Select the UART frequency clock:
00: clk_62m
01: clk_26m
10: clk_13m
11: clk_3p25m
3ReservedRO0Reserved for future use
2uart pclk Enable/DisableRW0x0Enable bit for UART peripheral clock (pclk)
0: Disable
1: Enable
1uart fclk Enable/DisableRW0x0Enable bit for UART frequency clock (fclk)
0: Disable
1: Enable
0uart reset Enable/DisableRW0x0Enable bit for UART reset
0: Disable
1: Enable
+**Offset: 0x3C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | Reserved | RO | 0 | Reserved for future use | +| 18:8 | uart clk div | RW | 0x0 | UART clock divider:
fclk = source_clk / (uart_fclk_div + 1) | +| 7:6 | Reserved | RO | 0 | Reserved for future use | +| 5:4 | uart fclk sel | RW | 0x0 | Select the UART frequency clock:
00: clk_62m
01: clk_26m
10: clk_13m
11: clk_3p25m | +| 3 | Reserved | RO | 0 | Reserved for future use | +| 2 | uart pclk Enable/Disable | RW | 0x0 | Enable bit for UART peripheral clock (pclk)
0: Disable
1: Enable | +| 1 | uart fclk Enable/Disable | RW | 0x0 | Enable bit for UART frequency clock (fclk)
0: Disable
1: Enable | +| 0 | uart reset Enable/Disable | RW | 0x0 | Enable bit for UART reset
0: Disable
1: Enable | #### R_CAN_CLK_RES_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x48
BitsFieldTypeResetDescription
31:19ReservedRO0Reserved for future use
18:8CAN clk divRW0x0CAN clock divider:
fclk= source_clk/(shubi2c1_fclk_div + 1)
7:6ReservedRO0Reserved for future use
5:4CAN fclk selRW0x0Select the CAN frequency clock
00: clk_62m
01: clk_26m
10: clk_13m
11: clk_3p25m
3ReservedRO0Reserved for future use
2CAN pclk Enable/DisableRW0x0Enable bit for CAN peripheral clock (pclk)
0 = disable 1 = enable
1CAN fclk Enable/DisableRW0x0Enable bit for CAN frequency clock (fclk)
0: Disable
1: Enable
0CAN reset Enable/DisableRW0x0Enable bit for CAN reset
0: Disable
1: Enable
+**Offset: 0x48** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | Reserved | RO | 0 | Reserved for future use | +| 18:8 | CAN clk div | RW | 0x0 | CAN clock divider:
fclk= source_clk/(shubi2c1_fclk_div + 1) | +| 7:6 | Reserved | RO | 0 | Reserved for future use | +| 5:4 | CAN fclk sel | RW | 0x0 | Select the CAN frequency clock
00: clk_62m
01: clk_26m
10: clk_13m
11: clk_3p25m | +| 3 | Reserved | RO | 0 | Reserved for future use | +| 2 | CAN pclk Enable/Disable | RW | 0x0 | Enable bit for CAN peripheral clock (pclk)
0 = disable 1 = enable | +| 1 | CAN fclk Enable/Disable | RW | 0x0 | Enable bit for CAN frequency clock (fclk)
0: Disable
1: Enable | +| 0 | CAN reset Enable/Disable | RW | 0x0 | Enable bit for CAN reset
0: Disable
1: Enable | #### R_R_IR_CLK_RES_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4C
BitsFieldTypeResetDescription
31:19ReservedRO0Reserved for future use
18:8ReservedRO0Reserved for future use
7:6ReservedRO0Reserved for future use
5:4ReservedRO0Reserved for future use
3ReservedRO0Reserved for future use
2R_IR pclk Enable/DisableRW0x0Enable bit for R_IR peripheral clock (pclk)
0: Disable
1: Enable
1ReservedRO0Reserved for future use
0R_IR reset Enable/DisableRW0x0Enable bit for R_IR reset
0: Disable
1: Enable
+**Offset: 0x4C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | Reserved | RO | 0 | Reserved for future use | +| 18:8 | Reserved | RO | 0 | Reserved for future use | +| 7:6 | Reserved | RO | 0 | Reserved for future use | +| 5:4 | Reserved | RO | 0 | Reserved for future use | +| 3 | Reserved | RO | 0 | Reserved for future use | +| 2 | R_IR pclk Enable/Disable | RW | 0x0 | Enable bit for R_IR peripheral clock (pclk)
0: Disable
1: Enable | +| 1 | Reserved | RO | 0 | Reserved for future use | +| 0 | R_IR reset Enable/Disable | RW | 0x0 | Enable bit for R_IR reset
0: Disable
1: Enable | #### DDR_REMAP_BASE REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0
BitsFieldTypeResetDescription
31:0ddr_remap_baseRW0x0Base address for STAR core to access DDR.
- Memory space: 0x30000000 - 0x3FFFFFFF
- Remaps to DDR address range: ddr_remap_base + 0x0 to ddr_remap_base + 0x0FFFFFFF.
+**Offset: 0xC0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | ddr_remap_base | RW | 0x0 | Base address for STAR core to access DDR.
- Memory space: 0x30000000 - 0x3FFFFFFF
- Remaps to DDR address range: ddr_remap_base + 0x0 to ddr_remap_base + 0x0FFFFFFF. | #### UART0_CLK_RES_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD8
BitsFieldTypeResetDescription
31:19ReservedRO0Reserved for future use
18:8uart clk divRW0x0UART Clock Divider:
fclk= source_clk/(shubi2c1_fclk_div + 1)
7:6ReservedRO0Reserved for future use
5:4uart fclk selRW0x0Select UART frequency clock (fclk)
00: clk_62m
01: clk_26m
10: clk_13m
11: clk_3p25m
3ReservedRO0Reserved for future use
2uart pclk Enable/DisableRW0x0Enable bit for UART peripheral clock (pclk)
0: Disable
1: Enable
1uart fclk Enable/DisableRW0x0Enable bit for UART frequency clock (fclk)
0: Disable
1: Enable
0uart reset Enable/DisableRW0x0
Enable bit for UART reset
0: Disable
1: Enable
+**Offset: 0xD8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | Reserved | RO | 0 | Reserved for future use | +| 18:8 | uart clk div | RW | 0x0 | UART Clock Divider:
fclk= source_clk/(shubi2c1_fclk_div + 1) | +| 7:6 | Reserved | RO | 0 | Reserved for future use | +| 5:4 | uart fclk sel | RW | 0x0 | Select UART frequency clock (fclk)
00: clk_62m
01: clk_26m
10: clk_13m
11: clk_3p25m | +| 3 | Reserved | RO | 0 | Reserved for future use | +| 2 | uart pclk Enable/Disable | RW | 0x0 | Enable bit for UART peripheral clock (pclk)
0: Disable
1: Enable | +| 1 | uart fclk Enable/Disable | RW | 0x0 | Enable bit for UART frequency clock (fclk)
0: Disable
1: Enable | +| 0 | uart reset Enable/Disable | RW | 0x0 | Enable bit for UART reset
0: Disable
1: Enable | ### 15.3.3 AUD_AUDCLOCK Registers @@ -1138,361 +292,77 @@ The applications of the RCPU subsystem can access its memory and peripherals. #### AUDIO_CODEC_TX_RX_CLK_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14
BitsFieldTypeResetDescription
31:18ReservedRO0Reserved for future use
17:16sspa_func_clk_source_selRW0x0Select SSPA function clock source
0: SSPA_FCLK_SRC = 245.76M
1: SSPA_FCLK_SRC = 24.576M
15ReservedRO0Reserved for future use
14:4sspa_func_clk_divRW0x9fSSPA function clock divider
SSPA_FCLK = SSPA_FCLK_SRC/(SSPA_FCLK_DIV+1)
3ReservedRO0Reserved for future use
2sspa_func_clk_enRW0x00: SSPA function clock gated
1: SSPA function clock open
1tx_rx_bus_clk_enRW0x00: bus clock gated
1: bus clock open
0tx_rx_sw_rstnRW0x0Reset control for audio SSPA and ADMA
0: Reset
1: Release reset
+**Offset: 0x14** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:18 | Reserved | RO | 0 | Reserved for future use | +| 17:16 | sspa_func_clk_source_sel | RW | 0x0 | Select SSPA function clock source
0: SSPA_FCLK_SRC = 245.76M
1: SSPA_FCLK_SRC = 24.576M | +| 15 | Reserved | RO | 0 | Reserved for future use | +| 14:4 | sspa_func_clk_div | RW | 0x9f | SSPA function clock divider
SSPA_FCLK = SSPA_FCLK_SRC/(SSPA_FCLK_DIV+1) | +| 3 | Reserved | RO | 0 | Reserved for future use | +| 2 | sspa_func_clk_en | RW | 0x0 | 0: SSPA function clock gated
1: SSPA function clock open | +| 1 | tx_rx_bus_clk_en | RW | 0x0 | 0: bus clock gated
1: bus clock open | +| 0 | tx_rx_sw_rstn | RW | 0x0 | Reset control for audio SSPA and ADMA
0: Reset
1: Release reset | #### AUDIO_DFE_CLK_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1C
BitsFieldTypeResetDescription
31:6ReservedRO0Reserved for future use
5dfe_sw_resetRW0x00: Reset
1: Release reset
4dfe_func_clk_enableRW0x00: Disble
1: Enable
3dac_sw_resetRW0x00: Reset
1: Release reset
2dac_clk_inv_enRW0x0DAC clock can use the original clock from analog or the invert clock
0: DAC uses the original clock
1: DAC uses the invert clock
1adc_sw_resetRW0x00: Reset
1: Release reset
0adc_clk_inv_enRW0x0ADC clock can use the original clock from analog or the invert clock
0: ADC uses the original clock
1: ADC uses the invert clock
+**Offset: 0x1C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:6 | Reserved | RO | 0 | Reserved for future use | +| 5 | dfe_sw_reset | RW | 0x0 | 0: Reset
1: Release reset | +| 4 | dfe_func_clk_enable | RW | 0x0 | 0: Disble
1: Enable | +| 3 | dac_sw_reset | RW | 0x0 | 0: Reset
1: Release reset | +| 2 | dac_clk_inv_en | RW | 0x0 | DAC clock can use the original clock from analog or the invert clock
0: DAC uses the original clock
1: DAC uses the invert clock | +| 1 | adc_sw_reset | RW | 0x0 | 0: Reset
1: Release reset | +| 0 | adc_clk_inv_en | RW | 0x0 | ADC clock can use the original clock from analog or the invert clock
0: ADC uses the original clock
1: ADC uses the invert clock | #### AUDIO_I2S1_TX_RX_CLK_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x40
BitsFieldTypeResetDescription
31:18ReservedRO0Reserved for future use
17:16sspa_func_clk_source_selRW0x0SSPA function clock source
0: SSPA_FCLK_SRC = 245.76M
1: SSPA_FCLK_SRC = 24.576M
15ReservedRO0Reserved for future use
14:4sspa_func_clk_divRW0x9fSSPA function clock divider
SSPA_FCLK = SSPA_FCLK_SRC/(SSPA_FCLK_DIV+1)
3ReservedRO0Reserved for future use
2sspa_func_clk_enRW0x00: SSPA function clock gated
1: SSPA function clock open
1tx_rx_bus_clk_enRW0x00: Bus clock gated
1: Bus clock open
0tx_rx_sw_rstnRW0x0Reset control for audio SSPA and ADMA
0: Reset
1: Release reset
+**Offset: 0x40** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:18 | Reserved | RO | 0 | Reserved for future use | +| 17:16 | sspa_func_clk_source_sel | RW | 0x0 | SSPA function clock source
0: SSPA_FCLK_SRC = 245.76M
1: SSPA_FCLK_SRC = 24.576M | +| 15 | Reserved | RO | 0 | Reserved for future use | +| 14:4 | sspa_func_clk_div | RW | 0x9f | SSPA function clock divider
SSPA_FCLK = SSPA_FCLK_SRC/(SSPA_FCLK_DIV+1) | +| 3 | Reserved | RO | 0 | Reserved for future use | +| 2 | sspa_func_clk_en | RW | 0x0 | 0: SSPA function clock gated
1: SSPA function clock open | +| 1 | tx_rx_bus_clk_en | RW | 0x0 | 0: Bus clock gated
1: Bus clock open | +| 0 | tx_rx_sw_rstn | RW | 0x0 | Reset control for audio SSPA and ADMA
0: Reset
1: Release reset | #### AUDIO_HDMI_CLK_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x44
BitsFieldTypeResetDescription
31:18ReservedRO0Reserved for future use
17:16sspa_func_clk_source_selRW0x0SSPA function clock source
0: SSPA_FCLK_SRC = 245.76M
1: SSPA_FCLK_SRC = 24.576M
15ReservedRO0Reserved for future use
14:4sspa_func_clk_divRW0x9fSSPA function clock divider
SSPA_FCLK = SSPA_FCLK_SRC/( SSPA_FCLK_DIV+1)
3ReservedRO0Reserved for future use
2sspa_func_clk_enRW0x00: SSPA function clock gated
1: SSPA function clock open
1tx_rx_bus_clk_enRW0x00: Bus clock gated
1: Bus clock open
0tx_rx_sw_rstnRW0x0Reset control for audio SSPA and ADMA
0: Reset
1: Release reset
+**Offset: 0x44** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:18 | Reserved | RO | 0 | Reserved for future use | +| 17:16 | sspa_func_clk_source_sel | RW | 0x0 | SSPA function clock source
0: SSPA_FCLK_SRC = 245.76M
1: SSPA_FCLK_SRC = 24.576M | +| 15 | Reserved | RO | 0 | Reserved for future use | +| 14:4 | sspa_func_clk_div | RW | 0x9f | SSPA function clock divider
SSPA_FCLK = SSPA_FCLK_SRC/( SSPA_FCLK_DIV+1) | +| 3 | Reserved | RO | 0 | Reserved for future use | +| 2 | sspa_func_clk_en | RW | 0x0 | 0: SSPA function clock gated
1: SSPA function clock open | +| 1 | tx_rx_bus_clk_en | RW | 0x0 | 0: Bus clock gated
1: Bus clock open | +| 0 | tx_rx_sw_rstn | RW | 0x0 | Reset control for audio SSPA and ADMA
0: Reset
1: Release reset | #### AUDIO_I2S0_TX_RX_CLK_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x60
BitsFieldTypeResetDescription
31:18ReservedRO0Reserved for future use
17:16sspa_func_clk_source_selRW0x0SSPA function clock source
0: SSPA_FCLK_SRC = 245.76M
1: SSPA_FCLK_SRC = 24.576M
15ReservedRO0Reserved for future use
14:4sspa_func_clk_divRW0x9fSSPA function clock divider
SSPA_FCLK = SSPA_FCLK_SRC/( SSPA_FCLK_DIV+1)
3ReservedRO0Reserved for future use
2sspa_func_clk_enRW0x00: SSPA function clock gated
1: SSPA function clock open
1tx_rx_bus_clk_enRW0x00: Bus clock gated
1: Bus clock open
0tx_rx_sw_rstnRW0x0Reset control for audio SSPA and ADMA
0: Reset
1: Release reset
+**Offset: 0x60** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:18 | Reserved | RO | 0 | Reserved for future use | +| 17:16 | sspa_func_clk_source_sel | RW | 0x0 | SSPA function clock source
0: SSPA_FCLK_SRC = 245.76M
1: SSPA_FCLK_SRC = 24.576M | +| 15 | Reserved | RO | 0 | Reserved for future use | +| 14:4 | sspa_func_clk_div | RW | 0x9f | SSPA function clock divider
SSPA_FCLK = SSPA_FCLK_SRC/( SSPA_FCLK_DIV+1) | +| 3 | Reserved | RO | 0 | Reserved for future use | +| 2 | sspa_func_clk_en | RW | 0x0 | 0: SSPA function clock gated
1: SSPA function clock open | +| 1 | tx_rx_bus_clk_en | RW | 0x0 | 0: Bus clock gated
1: Bus clock open | +| 0 | tx_rx_sw_rstn | RW | 0x0 | Reset control for audio SSPA and ADMA
0: Reset
1: Release reset | ### 15.3.4 AUD_AHBDMA Registers @@ -1500,498 +370,124 @@ The applications of the RCPU subsystem can access its memory and peripherals. #### DMA_DCR REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31:3ReservedRO0Reserved for future use
2DMA Access ModeRW0x00: Privileged access
1: User access
1DMA Soft ResetW1C0x00: No effect
1: Generates a 3-cycle reset pulse
0DMA EnableRW0x00: DMA disable
1: DMA enable
+**Offset: 0x0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | Reserved | RO | 0 | Reserved for future use | +| 2 | DMA Access Mode | RW | 0x0 | 0: Privileged access
1: User access | +| 1 | DMA Soft Reset | W1C | 0x0 | 0: No effect
1: Generates a 3-cycle reset pulse | +| 0 | DMA Enable | RW | 0x0 | 0: DMA disable
1: DMA enable | #### DMA_SR REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31:16ReservedRO0Reserved for future use
15CH15 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
14CH14 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
13CH13 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
12CH12 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
11CH11 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
10CH10 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
9CH9 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
8CH8 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
7CH7 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
6CH6 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
5CH5 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
4CH4 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
3CH3 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
2CH2 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
1CH1 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
0CH0 Int pendingW1C0x00: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt.
+**Offset: 0x4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0 | Reserved for future use | +| 15 | CH15 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 14 | CH14 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 13 | CH13 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 12 | CH12 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 11 | CH11 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 10 | CH10 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 9 | CH9 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 8 | CH8 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 7 | CH7 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 6 | CH6 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 5 | CH5 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 4 | CH4 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 3 | CH3 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 2 | CH2 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 1 | CH1 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | +| 0 | CH0 Int pending | W1C | 0x0 | 0: No interrupt
1: Interrupt is pending
Writing 1 clears the interrupt. | #### DMA_DIMR REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8
BitsFieldTypeResetDescription
31:16ReservedRO0Reserved for future use
15:0Channel n Interrupt MaskRW0xFFFFChannel n (15 ~ 0)
0: Enables interrupts
1: Disables interrupts
+**Offset: 0x8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0 | Reserved for future use | +| 15:0 | Channel n Interrupt Mask | RW | 0xFFFF | Channel n (15 ~ 0)
0: Enables interrupts
1: Disables interrupts | #### DMA_SARN REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x080+0x40*n
BitsFieldTypeResetDescription
31:0Source AddressRW0x0This register holds the source address from where data is read during a DMA transfer.
DMA does not perform misaligned accesses. The alignment behavior depends on the transfer size:
- For 32-bit transfers, the lower two bits of the address are ignored
- For 8-bit transfers, begin from the exact address specified
> Note. Software must ensure proper alignment, particularly in systems that do not support non-word-aligned accesses.
+**Offset: 0x080+0x40*n** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | Source Address | RW | 0x0 | This register holds the source address from where data is read during a DMA transfer.
DMA does not perform misaligned accesses. The alignment behavior depends on the transfer size:
- For 32-bit transfers, the lower two bits of the address are ignored
- For 8-bit transfers, begin from the exact address specified
> Note. Software must ensure proper alignment, particularly in systems that do not support non-word-aligned accesses. | #### DMA_DARN REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x084+0x40*n
BitsFieldTypeResetDescription
31:0Destination AddressRW0x0This register holds the destination address from where data is read during a DMA transfer.
DMA does not perform misaligned accesses. The alignment behavior depends on the transfer size:
- For 32-bit transfers, the lower two bits of the address are ignored
- For 8-bit transfers, begin from the exact address specified
> Note. Software must ensure proper alignment, particularly in systems that do not support non-word-aligned accesses.
+**Offset: 0x084+0x40*n** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | Destination Address | RW | 0x0 | This register holds the destination address from where data is read during a DMA transfer.
DMA does not perform misaligned accesses. The alignment behavior depends on the transfer size:
- For 32-bit transfers, the lower two bits of the address are ignored
- For 8-bit transfers, begin from the exact address specified
> Note. Software must ensure proper alignment, particularly in systems that do not support non-word-aligned accesses. | #### DMA_CNTRN REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x088+0x40*n
BitsFieldTypeResetDescription
31:24ReservedRO0Reserved for future use
23:0CountRW0x0Contains the number of bytes of data to be transferred during a DMA cycle.
+**Offset: 0x088+0x40*n** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Reserved | RO | 0 | Reserved for future use | +| 23:0 | Count | RW | 0x0 | Contains the number of bytes of data to be transferred during a DMA cycle. | #### DMA_CCRN REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x08c+0x40*n
BitsFieldTypeResetDescription
31:14ReservedRO0Reserved for future use
13:12Destination ModeRW0x0Selects the destination transfer mode
0x0: Memory
0x2: FIFO
0x1/0x3: Reserved
11:10Source ModeRW0x0Selects the destination transfer mode
0x0: Memory
0x2: FIFO
0x1/0x3: Reserved
9:8ReservedRO0Reserved for future use
7:6Destination SizeRW0x0Selects the destination size of a data transfer.
If the number of bytes to be written is less than the DSIZ setting, only that many bytes will be valid in the DMA write cycle to AHB. However, all DMA write cycles to the destination will be of DSIZ size. DMA always writes data as per DSIZ in all modes.
00: 32-bit destination port
01: 8-bit destination port
10: 16-bit destination port
11: Reserved
5:4Source SizeRW0x0Selects the source size of a data transfer.
If the number of bytes to be read is less than the SSIZ setting, only that many bytes will be used by the DMA. However, all DMA read cycles to the source will be of SSIZ size.
00: 32-bit source port
01: 8-bit source port
10: 16-bit source port
11: Reserved
3Request EnableRW0x0Enables or disables the DMA request signal.
- When REN is set, DMA burst is initiated by the dma_req signal from the I/O FIFO.
- When REN is cleared, DMA transfer is initiated by CEN (Channel Enable).
0: Disables the DMA request signal (when the peripheral asserts a DMA request, no DMA transfer is triggered).
1: Enables the DMA request signal (when the peripheral asserts a DMA request, a DMA transfer is triggered).
2:1ReservedRO0Reserved for future use
0DMA Channel EnableRW0x0> Note. Disabling CEN during an ongoing burst on the AHB will stop the burst in the middle of the transfer.
0: Disables the DMA channel
1: Enables the DMA channel
+**Offset: 0x08c+0x40*n** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:14 | Reserved | RO | 0 | Reserved for future use | +| 13:12 | Destination Mode | RW | 0x0 | Selects the destination transfer mode
0x0: Memory
0x2: FIFO
0x1/0x3: Reserved | +| 11:10 | Source Mode | RW | 0x0 | Selects the destination transfer mode
0x0: Memory
0x2: FIFO
0x1/0x3: Reserved | +| 9:8 | Reserved | RO | 0 | Reserved for future use | +| 7:6 | Destination Size | RW | 0x0 | Selects the destination size of a data transfer.
If the number of bytes to be written is less than the DSIZ setting, only that many bytes will be valid in the DMA write cycle to AHB. However, all DMA write cycles to the destination will be of DSIZ size. DMA always writes data as per DSIZ in all modes.
00: 32-bit destination port
01: 8-bit destination port
10: 16-bit destination port
11: Reserved | +| 5:4 | Source Size | RW | 0x0 | Selects the source size of a data transfer.
If the number of bytes to be read is less than the SSIZ setting, only that many bytes will be used by the DMA. However, all DMA read cycles to the source will be of SSIZ size.
00: 32-bit source port
01: 8-bit source port
10: 16-bit source port
11: Reserved | +| 3 | Request Enable | RW | 0x0 | Enables or disables the DMA request signal.
- When REN is set, DMA burst is initiated by the dma_req signal from the I/O FIFO.
- When REN is cleared, DMA transfer is initiated by CEN (Channel Enable).
0: Disables the DMA request signal (when the peripheral asserts a DMA request, no DMA transfer is triggered).
1: Enables the DMA request signal (when the peripheral asserts a DMA request, a DMA transfer is triggered). | +| 2:1 | Reserved | RO | 0 | Reserved for future use | +| 0 | DMA Channel Enable | RW | 0x0 | > Note. Disabling CEN during an ongoing burst on the AHB will stop the burst in the middle of the transfer.
0: Disables the DMA channel
1: Enables the DMA channel | #### DMA_RSSRN REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x090+0x40*n
BitsFieldTypeResetDescription
31:6ReservedRO0Reserved for future use
5:0Request Source SelectRW0x0Selects 1 of the 64 dma_req signals that initiates DMA transfer cycle for the channel.
000000: Select dma_req[0]
000001: Select dma_req [1]
...
011111: Select dma_req [31]
....
111111: Select dma_req [63]
+**Offset: 0x090+0x40*n** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:6 | Reserved | RO | 0 | Reserved for future use | +| 5:0 | Request Source Select | RW | 0x0 | Selects 1 of the 64 dma_req signals that initiates DMA transfer cycle for the channel.
000000: Select dma_req[0]
000001: Select dma_req [1]
...
011111: Select dma_req [31]
....
111111: Select dma_req [63] | #### DMA_BLRN REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x094+0x40*n
BitsFieldTypeResetDescription
31:6ReservedRO0Reserved for future use
5:0Burst LengthRW0x0Contains the number of data bytes that are transferred in a DMA burst.
000000: 64 bytes read follow 64 bytes write
000001: 1 byte read follow 1 byte write
000010: 2 bytes read follow 2 bytes write
....
111111: 63 bytes read follow 63 bytes write
+**Offset: 0x094+0x40*n** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:6 | Reserved | RO | 0 | Reserved for future use | +| 5:0 | Burst Length | RW | 0x0 | Contains the number of data bytes that are transferred in a DMA burst.
000000: 64 bytes read follow 64 bytes write
000001: 1 byte read follow 1 byte write
000010: 2 bytes read follow 2 bytes write
....
111111: 63 bytes read follow 63 bytes write | #### DMA_TRSF_CNT REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x09c+0x40*n
BitsFieldTypeResetDescription
31:24ReservedRO0Reserved for future use
23:0TRSF_CNTRO0x0Indicates the number of bytes transferred for the channel
+**Offset: 0x09c+0x40*n** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Reserved | RO | 0 | Reserved for future use | +| 23:0 | TRSF_CNT | RO | 0x0 | Indicates the number of bytes transferred for the channel | #### DMA_BTYPE REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0a0+0x40*n
BitsFieldTypeResetDescription
31:2ReservedRO0Reserved for future use
1:0Burst TypeRW0x00x0: INCR
0x2: INCR4
0x3: INCR8
0x4: INCR16
+**Offset: 0x0a0+0x40*n** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | RO | 0 | Reserved for future use | +| 1:0 | Burst Type | RW | 0x0 | 0x0: INCR
0x2: INCR4
0x3: INCR8
0x4: INCR16 | ### 15.3.5 PWM Registers @@ -2004,158 +500,46 @@ PWM Control register. This register control the behavior of the PWM module, incl - Shutdown response configuration - Clock divisor settings by adjusting the input clock frequency to the PWM control unit which determines the frequency of the scaled counter clock. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0+(n-1)*0x400
BitsFieldTypeResetDescription
31:9ReservedRO0x0Reserved for future use.
8PWM_OUTCNTenRW0x0PWM Output Counter Register enable
0: Disable
1: Enable
7ReservedRO0Reserved for future use.
6Pulse Width Modulator Shutdown ModeRW0x00: Graceful shutdown of PWM when the SoC stops the clock to the PWM.
1: Abrupt shutdown of PWM when the SoC stops the clocks to the PWM.
5:0PrescaleRW0x0The scaled counter clock frequency is:
Frequency = PSCLK_PWM / (PRESCALE + 1)
+**Offset: 0x0+(n-1) x 0x400** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:9 | Reserved | RO | 0x0 | Reserved for future use. | +| 8 | PWM_OUTCNTen | RW | 0x0 | PWM Output Counter Register enable
0: Disable
1: Enable | +| 7 | Reserved | RO | 0 | Reserved for future use. | +| 6 | Pulse Width Modulator Shutdown Mode | RW | 0x0 | 0: Graceful shutdown of PWM when the SoC stops the clock to the PWM.
1: Abrupt shutdown of PWM when the SoC stops the clocks to the PWM. | +| 5:0 | Prescale | RW | 0x0 | The scaled counter clock frequency is:
Frequency = PSCLK_PWM / (PRESCALE + 1) | #### PWM_DCR REGISTER PWM Duty Cycle register. This register configures the duty cycle of the corresponding PWM output signals (PWM_OUT). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4+(n-1)*0x400
BitsFieldTypeResetDescription
31:11ReservedRO0x0Reserved for future use.
10Full Duty CycleRW0x00: The PWM output signal (PWM_OUT) is determined by the <Duty Cycle of PWM_OUT> value.
1: The PWM output signal (PWM_OUT) is continuously asserted (i.e., it remains high).
9:0Duty Cycle of PWM_OUT
RW0x0Defines the active high period of PWM_OUT:
0: The PWM output signal (PWM_OUT) is continuously de-asserted (i.e., it remains low).
1: The PWM output signal (PWM_OUT) is high for a specific duration with the calculation formula:
High Time = (<PRESCALE> + 1) * (1 / 12.8 MHz), where <PRESCALE> is a field in the PWM Control Registers
> Note. If <Full Duty Cycle> is set to 1, this filed has no effect on the output of PWM.
+**Offset: 0x4+(n-1)*0x400** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:11 | Reserved | RO | 0x0 | Reserved for future use. | +| 10 | Full Duty Cycle | RW | 0x0 | 0: The PWM output signal (PWM_OUT) is determined by the <Duty Cycle of PWM_OUT> value.
1: The PWM output signal (PWM_OUT) is continuously asserted (i.e., it remains high). | +| 9:0 | Duty Cycle of PWM_OUT | RW | 0x0 | Defines the active high period of PWM_OUT:
0: The PWM output signal (PWM_OUT) is continuously de-asserted (i.e., it remains low).
1: The PWM output signal (PWM_OUT) is high for a specific duration with the calculation formula:
High Time = (<PRESCALE> + 1) * (1 / 12.8 MHz), where <PRESCALE> is a field in the PWM Control Registers
> Note. If <Full Duty Cycle> is set to 1, this filed has no effect on the output of PWM. | #### PWM_PCR REGISTER PWM Period Control register. This register is used to configure the cycle time of the corresponding PWM_OUT signals. When this register is set to zero (cleared), the PWM output signal (PWM_OUT) will stay in a high state. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8+(n-1)*0x400
BitsFieldTypeResetDescription
31:10ReservedRO0x0Reserved for future use.
9:0Period ValueRW0x4Defines the the cycle time of the PWM_OUT signal.
- The value written to this field specifies the number of scaled clock cycles per PWM cycle, plus one.
- Formula:
PWM Cycle Time = (Period Value+ 1) × (1 / Scaled Clock Frequency)
> Note. Writing all zeros to this field, causes the PWM_OUT signal to remain high continuously.
+**Offset: 0x8+(n-1) x 0x400** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:10 | Reserved | RO | 0x0 | Reserved for future use. | +| 9:0 | Period Value | RW | 0x4 | Defines the cycle time of the PWM_OUT signal.
- The value written to this field specifies the number of scaled clock cycles per PWM cycle, plus one.
- Formula:
PWM Cycle Time = (Period Value+ 1) 脳 (1 / Scaled Clock Frequency)
> Note. Writing all zeros to this field, causes the PWM_OUT signal to remain high continuously. | #### PWM_OUTCNT REGISTER PWM Output Counter register. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x10+(n-1)*0x400
BitsFieldTypeResetDescription
31:16ReservedRO0x0Reserved for future use.
15:0Counter ValueRW0x0Specifies the value of PWM out pulse number.
+**Offset: 0x10+(n-1) x 0x400** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0x0 | Reserved for future use. | +| 15:0 | Counter Value | RW | 0x0 | Specifies the value of PWM out pulse number. | diff --git a/en/key_stone/k1/k1_docs/k1_usermanual/15.High-Speed_Interface_System.md b/en/key_stone/k1/k1_docs/k1_usermanual/15.High-Speed_Interface_System.md index cf6bddb..98c7816 100644 --- a/en/key_stone/k1/k1_docs/k1_usermanual/15.High-Speed_Interface_System.md +++ b/en/key_stone/k1/k1_docs/k1_usermanual/15.High-Speed_Interface_System.md @@ -135,1156 +135,314 @@ The architecture of the USB port set is depicted below, where #### USB3_CTRL_CLK_CFG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31:10ReservedRO0Reserved for future use
9use_vbus_valid_extRW0x01: Routes the VBUS detection signal from GPIO to the pipe_PowerPresent signal.
8bigendian_gsRW0x0Signals connect to USB3 Controller
7:6ReservedRO0Reserved for future use
5:0fladj_30mhz_regRW0x20Signals connect to USB3 Controller
+**Offset: 0x0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:10 | Reserved | RO | 0 | Reserved for future use | +| 9 | use_vbus_valid_ext | RW | 0x0 | 1: Routes the VBUS detection signal from GPIO to the pipe_PowerPresent signal. | +| 8 | bigendian_gs | RW | 0x0 | Signals connect to USB3 Controller | +| 7:6 | Reserved | RO | 0 | Reserved for future use | +| 5:0 | fladj_30mhz_reg | RW | 0x20 | Signals connect to USB3 Controller | #### USB3_CTRL_MISC_CFG_0 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31:16gp_inRW0x0Signals connect to USB3 Controller
15:5ReservedRO0Reserved for future use
4pme_enRW0x0Signals connect to USB3 Controller
3:0bus_filter_bypassRW0x0Signals connect to USB3 Controller
+**Offset: 0x4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | gp_in | RW | 0x0 | Signals connect to USB3 Controller | +| 15:5 | Reserved | RO | 0 | Reserved for future use | +| 4 | pme_en | RW | 0x0 | Signals connect to USB3 Controller | +| 3:0 | bus_filter_bypass | RW | 0x0 | Signals connect to USB3 Controller | #### USB3_CTRL_HOST_CFG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8
BitsFieldTypeResetDescription
31:0spareRW0x0 Reserved for future use
+**Offset: 0x8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | spare | RW | 0x0 | Reserved for future use | #### USB3_CTRL_CLK_CFG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xc
BitsFieldTypeResetDescription
31:10ReservedRO0Reserved for future use
9host_msi_enableRW0x0
8host_port_power_control_presentRW0x0
7:6ReservedRO0Reserved for future use
5host_u3_port_disableRW0x0
4host_u2_port_disableRW0x0Reserved for future use
3:2hub_port_perm_attachRW0x0Signals connect to USB3 Controller
1:0hub_port_overcurrentRW0x0Signals connect to USB3 Controller
+**Offset: 0xc** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:10 | Reserved | RO | 0 | Reserved for future use | +| 9 | host_msi_enable | RW | 0x0 | | +| 8 | host_port_power_control_present | RW | 0x0 | | +| 7:6 | Reserved | RO | 0 | Reserved for future use | +| 5 | host_u3_port_disable | RW | 0x0 | | +| 4 | host_u2_port_disable | RW | 0x0 | Reserved for future use | +| 3:2 | hub_port_perm_attach | RW | 0x0 | Signals connect to USB3 Controller | +| 1:0 | hub_port_overcurrent | RW | 0x0 | Signals connect to USB3 Controller | #### USB3_CTRL_CLK_CFG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x20
BitsFieldTypeResetDescription
31bus_err_intRO0x0Bus Error Interrupt valid
30:22ReservedRO0Reserved for future use
21gsts_buserraddvld_syncRO0x0Bus access error
20host_system_err_syncRO0x0Host system error
19:16usb3_buserr_stsRO0x0Bit 0: host_system_error rise edge interrupt status
Bit 1: host_system_error fall edge interrupt status
Bit 2: gsts_buserraddvld rise edge interrupt status
Bit 3: gsts_buserraddvld fall edge interrupt status
15:8ReservedRO0Reserved for future use
7:4usb3_buserr_int_maskRW0x0Bit 0: host_system_error rise edge interrupt enable
Bit 1: host_system_error fall edge interrupt enable
Bit 2: gsts_buserraddvld rise edge interrupt enable
Bit 3: gsts_buserraddvld fall edge interrupt enable
3:1ReservedRO0Reserved for future use
0usb3_buserr_int_clrRW0x0Write 1 to clear bus_err_int
It will be clear to '0' by hardware.
+**Offset: 0x20** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | bus_err_int | RO | 0x0 | Bus Error Interrupt valid | +| 30:22 | Reserved | RO | 0 | Reserved for future use | +| 21 | gsts_buserraddvld_sync | RO | 0x0 | Bus access error | +| 20 | host_system_err_sync | RO | 0x0 | Host system error | +| 19:16 | usb3_buserr_sts | RO | 0x0 | Bit 0: host_system_error rise edge interrupt status
Bit 1: host_system_error fall edge interrupt status
Bit 2: gsts_buserraddvld rise edge interrupt status
Bit 3: gsts_buserraddvld fall edge interrupt status | +| 15:8 | Reserved | RO | 0 | Reserved for future use | +| 7:4 | usb3_buserr_int_mask | RW | 0x0 | Bit 0: host_system_error rise edge interrupt enable
Bit 1: host_system_error fall edge interrupt enable
Bit 2: gsts_buserraddvld rise edge interrupt enable
Bit 3: gsts_buserraddvld fall edge interrupt enable | +| 3:1 | Reserved | RO | 0 | Reserved for future use | +| 0 | usb3_buserr_int_clr | RW | 0x0 | Write 1 to clear bus_err_int
It will be clear to '0' by hardware. | #### P_ADDR_PUMON0 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x24
BitsFieldTypeResetDescription
31:0pumon_trigger_mask[31:0]RW0Mask for signal capture in Monitor Module
+**Offset: 0x24** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | pumon_trigger_mask[31:0] | RW | 0 | Mask for signal capture in Monitor Module | #### P_ADDR_PUMON1 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x28
BitsFieldTypeResetDescription
31:0pumon_trigger_mask[63:32]RW0Mask for signal capture in Monitor Module
+**Offset: 0x28** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | pumon_trigger_mask[63:32] | RW | 0 | Mask for signal capture in Monitor Module | #### P_ADDR_PUMON2 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x2c
BitsFieldTypeResetDescription
31:0pumon_trigger_trigger_pattern[31:0]RW
0Trigger pattern
+**Offset: 0x2c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | pumon_trigger_trigger_pattern[31:0] | RW | 0 | Trigger pattern | #### P_ADDR_PUMON3 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x30
BitsFieldTypeResetDescription
31:0pumon_trigger_trigger_pattern[63:32]RW0Trigger pattern
+**Offset: 0x30** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | pumon_trigger_trigger_pattern[63:32] | RW | 0 | Trigger pattern | #### P_ADDR_PUMON4 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x34
BitsFieldTypeResetDescription
31:10ReservedRO0Reserved for future use
9pumon_trigger_doneRW0
8pumon_trigger_ingRW0
7pumon_trigger_force_stopRW0
6pumon_trigger_startRW0
5pumon_trigger_modeRW0
4:0pumon_sample_selRW0
+**Offset: 0x34** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:10 | Reserved | RO | 0 | Reserved for future use | +| 9 | pumon_trigger_done | RW | 0 | | +| 8 | pumon_trigger_ing | RW | 0 | | +| 7 | pumon_trigger_force_stop | RW | 0 | | +| 6 | pumon_trigger_start | RW | 0 | | +| 5 | pumon_trigger_mode | RW | 0 | | +| 4:0 | pumon_sample_sel | RW | 0 | | #### P_ADDR_RO0 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x38
BitsFieldTypeResetDescription
31:0pumon_trigger_signals_ro[31:0]RO0x0Debug signal from usb3 controller
+**Offset: 0x38** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | pumon_trigger_signals_ro[31:0] | RO | 0x0 | Debug signal from usb3 controller | #### P_ADDR_RO1 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x3c
BitsFieldTypeResetDescription
31:0pumon_trigger_signals_ro[63:32]RO0x0Debug signal from usb3 controller
+**Offset: 0x3c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | pumon_trigger_signals_ro[63:32] | RO | 0x0 | Debug signal from usb3 controller | #### P_ADDR_RO2 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x40
BitsFieldTypeResetDescription
31:00pumon_monitor_ro[31:0]RW0x0Debug signal from PUPHY
+**Offset: 0x40** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:00 | pumon_monitor_ro[31:0] | RW | 0x0 | Debug signal from PUPHY | #### P_ADDR_RO3 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x44
BitsFieldTypeResetDescription
31:0pumon_monitor_ro[63:32]RO0x0Debug signal from PUPHY
+**Offset: 0x44** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | pumon_monitor_ro[63:32] | RO | 0x0 | Debug signal from PUPHY | #### 17.1.4.15 P_ADDR_RO4 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x48
BitsFieldTypeResetDescription
31:0pumon_monitor_ro[95:64]RO
0x0Pipe rx data
+**Offset: 0x48** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | pumon_monitor_ro[95:64] | RO | 0x0 | Pipe rx data | #### P_ADDR_RO5 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4c
BitsFieldTypeResetDescription
31:16ReservedRO0Reserved for future use
15:0pumon_monitor_ro[112:96]RO0x0Debug signal from USB2 PHY
+**Offset: 0x4c** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0 | Reserved for future use | +| 15:0 | pumon_monitor_ro[112:96] | RO | 0x0 | Debug signal from USB2 PHY | #### USB3_BW_CALC_CTRL REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x50
BitsFieldTypeResetDescription
31:0bw_calc_ctrlRW0x8000FFFFDedicated
> Note. Deprecated
+**Offset: 0x50** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | bw_calc_ctrl | RW | 0x8000FFFF | Dedicated
> Note. Deprecated | #### USB3_CTRL_MISC_ST REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x80
BitsFieldTypeResetDescription
31:16gp_outRO0x0Signals connect to USB3 Controller Output signals
15:8ReservedRO0Reserved for future use
7:6operational_modeRO0x0Signals connect to USB3 Controller Output signals
5pme_generationRO0x0Signals connect to USB3 Controller Output signals
4host_system_errRO0x0Signals connect to USB3 Controller Output signals
3ReservedRO0Reserved for future use
2:0clk_gate_ctrlRO0x0Signals connect to USB3 Controller Output signals
+**Offset: 0x80** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | gp_out | RO | 0x0 | Signals connect to USB3 Controller Output signals | +| 15:8 | Reserved | RO | 0 | Reserved for future use | +| 7:6 | operational_mode | RO | 0x0 | Signals connect to USB3 Controller Output signals | +| 5 | pme_generation | RO | 0x0 | Signals connect to USB3 Controller Output signals | +| 4 | host_system_err | RO | 0x0 | Signals connect to USB3 Controller Output signals | +| 3 | Reserved | RO | 0 | Reserved for future use | +| 2:0 | clk_gate_ctrl | RO | 0x0 | Signals connect to USB3 Controller Output signals | #### USB3_CTRL_HOST_ST REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x84
BitsFieldTypeResetDescription
31:12ReservedRO0Reserved for future use
11:0host_current_beltRO0x0Signals connect to USB3 Controller Output signals
+**Offset: 0x84** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:12 | Reserved | RO | 0 | Reserved for future use | +| 11:0 | host_current_belt | RO | 0x0 | Signals connect to USB3 Controller Output signals | #### IP_REVISION REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x100
BitsFieldTypeResetDescription
31:16phy_ip_revision[15:0]RO0xb112Read ip_revision[15:0]
15:0ip_revision[15:0]RO0x0252Read phy_ip_revision[15:0]
+**Offset: 0x100** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | phy_ip_revision[15:0] | RO | 0xb112 | Read ip_revision[15:0] | +| 15:0 | ip_revision[15:0] | RO | 0x0252 | Read phy_ip_revision[15:0] | #### USB_CTL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x104
BitsFieldTypeResetDescription
31:15ReservedRO0Reserved for future use
14USB2 phy reg resetRW0x0Soft reset for USB2 PHY registers.
- Set 1 to reset the USB2 PHY registers
- Clear to 0 to release the reset
Note: This reset is for backup purposes only.
13PHY suspendm enableRW0x1Controls whether the suspendm signal from the USB2 controller affects the PHY suspension.
1: PHY suspension depends on the controller's suspendm signal.
- If the controller does not indicate PHY suspension, the PHY will not suspend.
- If the controller indicates PHY suspension, the PHY may suspend based on its internal logic.
0: The USB2 PHY is not affected by the controller's suspendm signal.
12ReservedRO0Reserved for future use
11:10reg_opmodeRW0x0Provides register control for the PHY interface's op_mode.
9:8reg_xcvr_selectRW0x0Provides register control for the PHY interface's xcvr_select.
7reg_term_selectRW0x0Provides register control for the PHY interface's term_select.
6reg_selRW0x01: Bits [11:7] (reg_opmode, reg_xcvr_select, reg_term_select) take effect and control the PHY interface.
0: The controller controls the PHY interface.
5:4vbusvalid_ctlRW0x0Controls the VBUS_ON signal for the PHY.
- Bit 4:
1: Use Bit 5 to control PHY VBUS_ON.
0: Use the VBUSVALID signal from the USB2 PHY to control VBUS_ON.
- Bit 5:
When Bit 4 is 1, this bit directly controls the VBUS_ON signal.
3otg_selRW0x1Controls the OTG PHY owner.
2:0ReservedRO0Reserved for future use
+**Offset: 0x104** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:15 | Reserved | RO | 0 | Reserved for future use | +| 14 | USB2 phy reg reset | RW | 0x0 | Soft reset for USB2 PHY registers.
- Set 1 to reset the USB2 PHY registers
- Clear to 0 to release the reset
Note: This reset is for backup purposes only. | +| 13 | PHY suspendm enable | RW | 0x1 | Controls whether the suspendm signal from the USB2 controller affects the PHY suspension.
1: PHY suspension depends on the controller's suspendm signal.
- If the controller does not indicate PHY suspension, the PHY will not suspend.
- If the controller indicates PHY suspension, the PHY may suspend based on its internal logic.
0: The USB2 PHY is not affected by the controller's suspendm signal. | +| 12 | Reserved | RO | 0 | Reserved for future use | +| 11:10 | reg_opmode | RW | 0x0 | Provides register control for the PHY interface's op_mode. | +| 9:8 | reg_xcvr_select | RW | 0x0 | Provides register control for the PHY interface's xcvr_select. | +| 7 | reg_term_select | RW | 0x0 | Provides register control for the PHY interface's term_select. | +| 6 | reg_sel | RW | 0x0 | 1: Bits [11:7] (reg_opmode, reg_xcvr_select, reg_term_select) take effect and control the PHY interface.
0: The controller controls the PHY interface. | +| 5:4 | vbusvalid_ctl | RW | 0x0 | Controls the VBUS_ON signal for the PHY.
- Bit 4:
1: Use Bit 5 to control PHY VBUS_ON.
0: Use the VBUSVALID signal from the USB2 PHY to control VBUS_ON.
- Bit 5:
When Bit 4 is 1, this bit directly controls the VBUS_ON signal. | +| 3 | otg_sel | RW | 0x1 | Controls the OTG PHY owner. | +| 2:0 | Reserved | RO | 0 | Reserved for future use | #### USB_VBUS_REG REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x114
BitsFieldTypeResetDescription
31:0usb_vbus_regRW0x0> Note. Deprecated
+**Offset: 0x114** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | usb_vbus_reg | RW | 0x0 | > Note. Deprecated | #### USB2_CTRL_STATUS0 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x140
BitsFieldTypeResetDescription
31:0usb2_ctrl_status0RO0x0Provides bits [31:0] of the USB2 controller debug signal.
+**Offset: 0x140** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | usb2_ctrl_status0 | RO | 0x0 | Provides bits [31:0] of the USB2 controller debug signal. | #### USB2_CTRL_STATUS1 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x144
BitsFieldTypeResetDescription
31:0usb2_ctrl_status1RO0x0Provides bits [63:32] of the USB2 controller debug signal.
+**Offset: 0x144** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | usb2_ctrl_status1 | RO | 0x0 | Provides bits [63:32] of the USB2 controller debug signal. | #### USB2_CTRL_STATUS2 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x148
BitsFieldTypeResetDescription
31:0usb2_ctrl_status2RO0x0Provides bits [66:64] of the USB2 controller debug signal.
+**Offset: 0x148** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | usb2_ctrl_status2 | RO | 0x0 | Provides bits [66:64] of the USB2 controller debug signal. | #### USB2_CTRL_STATUS3 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14C
BitsFieldTypeResetDescription
31:0usb2_ctrl_status3RO0x0Provides bits [31:0] of the USB controller's logic_analyzer_trace signal.
+**Offset: 0x14C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | usb2_ctrl_status3 | RO | 0x0 | Provides bits [31:0] of the USB controller's logic_analyzer_trace signal. | #### USB2_CTRL_STATUS4 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x150
BitsFieldTypeResetDescription
31:0usb2_ctrl_status4RO0x0Provides bits [63:32] of the USB controller's logic_analyzer_trace signal.
+**Offset: 0x150** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | usb2_ctrl_status4 | RO | 0x0 | Provides bits [63:32] of the USB controller's logic_analyzer_trace signal. | #### USB2_CTRL_STATUS5 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x154
BitsFieldTypeResetDescription
31:0usb2_ctrl_status5RO0x0Provides USB2 PHY monitor signals.
+**Offset: 0x154** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | usb2_ctrl_status5 | RO | 0x0 | Provides USB2 PHY monitor signals. | #### USB2_CTRL_STATUS6 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x158
BitsFieldTypeResetDescription
31:0usb2_ctrl_status6RO0x0Reserved
+**Offset: 0x158** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | usb2_ctrl_status6 | RO | 0x0 | Reserved | #### USB2_CTRL_STATUS7 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x15C
BitsFieldTypeResetDescription
31:0usb2_ctrl_status7RO0x0Reserved
+**Offset: 0x15C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | usb2_ctrl_status7 | RO | 0x0 | Reserved | #### USB2_CTRL_STATUS8 REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x160
BitsFieldTypeResetDescription
31:0usb2_ctrl_status8RO0x0Reserved
+**Offset: 0x160** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | usb2_ctrl_status8 | RO | 0x0 | Reserved | #### USB2_CTRL_STATUS9 REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x164
BitsFieldTypeResetDescription
31:13ReservedRO0Reserved for future use
12chep_last_transRO0x0chep_last_trans signal
11:8chep_numberRO0x0chep_number signal
7:5ReservedRO0Reserved for future use
4int_dma_doneRO0x0int_dma_done signal
3int_dma_reqRO0x0int_dma_req signal
2sof_sent_rcvd_tglRO0x0sof_sent_rcvd_tgl signal
1sof_toggle_outRO0x0sof_toggle_out signal
0interruptRO0x0interrupt signal
+**Offset: 0x164** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:13 | Reserved | RO | 0 | Reserved for future use | +| 12 | chep_last_trans | RO | 0x0 | chep_last_trans signal | +| 11:8 | chep_number | RO | 0x0 | chep_number signal | +| 7:5 | Reserved | RO | 0 | Reserved for future use | +| 4 | int_dma_done | RO | 0x0 | int_dma_done signal | +| 3 | int_dma_req | RO | 0x0 | int_dma_req signal | +| 2 | sof_sent_rcvd_tgl | RO | 0x0 | sof_sent_rcvd_tgl signal | +| 1 | sof_toggle_out | RO | 0x0 | sof_toggle_out signal | +| 0 | interrupt | RO | 0x0 | interrupt signal | ## 16.2 PCIe @@ -1371,8 +529,8 @@ The bridge facilitates communication between AXI-embedded systems and PCIe devic Common Express Port Logic (CXPL) Module implements the basic functionality for - **PCIe Physical Layer** -- **PCIe****Link Layer** -- **PCIe****Transaction Layer** +- **PCIe Link Layer** +- **PCIe Transaction Layer** The key features are as follows: @@ -1430,14 +588,14 @@ The embedded DMA controller (EDMA) offloads data transfer tasks from the CPU and - **Channels:** 4 read channels and 4 write channels, where - - **DMA Write:**Transfers data from local (application) memory to remote (link partner) memory + - **DMA Write:** Transfers data from local (application) memory to remote (link partner) memory - **DMA Read:** Transfers data from remote (link partner) memory to local (application) memory - **Full Duplex Operation:** Supports simultaneous read and write transfers, and in parallel with normal (non-DMA) traffic - **Interrupts:** Notifies the CPU upon transfer completion or error. The DMA can - Interrupt the local CPU - Send an Interrupt Memory Write (IMWr) to the remote CPU -- **Configuration ****&**** Programming:** The DMA is highly configurable and can be programmed through +- **Configuration & Programming:** The DMA is highly configurable and can be programmed through - Local DBI (Designated Bus Interface) - PCIe wire (for remote configuration) @@ -1522,988 +680,266 @@ The EMAC core contains five sets of registers, depending on the IP configuration The DMA Configuration Register is used to program the global parameters for the DMA Controller. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0000
BitsFieldTypeResetDescription
31:17ReservedReserved for future use
20BIG_LITTLE_ENDIANRW0Big/Little Endian Bit 1
This bit should be set only when the EMAC-AHB core is configured to operate in 64-bit mode (Bit [18] is set). Together with Bit [14], this bit determines the endianness for data buffers. The following combinations of {Bit [20], Bit [14]} define the endianness:
- 2’b00: Little Endian Byte Order with in the 64-bit QWORD.
- 2’b01: Big Endian Byte Order within 32-bit DWORD in a QWORD.
- 2’b10: Reserved
- 2’b11: Big Endian Byte Order with in the 64-bit QWORD.
(Default: 1’b0)
19DESCRIPTOR_BYTE_ORDERINGRW0Descriptor Byte Order Bit (Bit 1)
This bit should be set only when the EMAC core is configured to operate in 64-bit mode (Bit [18] is set). Together with Bit [13], this bit determines the byte order for descriptors. The following combinations of {Bit [19], Bit [13]} define the descriptor byte ordering:
2’b00: Normal descriptor QWORD format.
2’b01: Big Endian byte ordering within the descriptor DWORD.
2’b10: Big Endian format for DWORDS within the QWORD.
2’b11: Big Endian format for both DWORDS and bytes within DWORDS.
(Default: 1’b0)
18
DMA_64BIT_MODERW064-bit Mode
- When this bit is set, the receive and transmit DMAs perform 64-bit data transfers for both descriptors and buffer transfers. Note that the addressing remains 32-bitIn this mode, the AHB/AXI master interface performs 64-bit data transfers by setting the size on the AHB/AXI master interface to 3’b011.
- This bit should be set only when the EMAC is interfaced to a 64-bit AHB/AXI bus and the EMAC’s host data bus width is configured to be 64-bit.
- When this bit is reset, the receive and transmit DMAs perform only 32-bit data transfers for both descriptors and buffer transfers. In this mode, the AHB/AXI master interface performs 32-bit data transfers by setting the size on the AHB/AXI master interface to 3’b010.
(Default: 1’b0)
17STRICT_BURSTRW0Strict Burst Mode
- When this bit is set, the receive and transmit DMAs operate in strict burst mode. In this mode, the DMA restricts the burst size to either the value specified in the burst length field or a single DWORD/QWORD. This is particularly useful when the AHB/AXI bus supports only specific burst sizes, such as 1, 4, 8, or 16.
- When this bit is reset, the receive and transmit DMAs can use any burst size from 1 up to the value programmed in the burst length field. This allows for optimized performance and is beneficial when the AHB bus supports bursts of any size.
(Default: 1’b0)
16WAIT_FOR_DONERW0Wait for Done
- When this bit is set, the transmit DMA waits for the Done signal from the FIFO interface before fetching the next packet’s descriptor.
- When this bit is reset, the transmit DMA does not wait for the Done signal from the FIFO interface and continuously processes transmit descriptors, provided the FIFO is not full.
(Default: 1’b0)
15TX_RX_ARBITRATIONRW0TX/RX Arbitration
This bit selects the internal bus arbitration scheme between the receive and transmit DMA state machines.
- When this bit is set, a round-robin arbitration scheme is applied, ensuring equal sharing of the bus between the receive and transmit DMAs.
- When this bit is reset, the receive DMA has priority over the transmit DMA, unless the transmit DMA controller is actively transmitting.
(Default: 1’b0)
14BIG_LITLE_ENDIANRW0Big/Little Endian Bit 0
- In 32-bit mode, setting this bit configures the DMA Controller to operate in Big Endian byte ordering mode for data buffers. When this bit is reset, the DMA Controller operates in Little Endian byte ordering mode for data buffers.
- In 64-bit mode, both this bit and Bit [20] determine the Endianness.
In 32-bit mode, the encoding of this bit is as follows when Bit [20] is reserved:
1'b0: Little Endian byte order within the DWORD.
1'b1: Big Endian byte order within the DWORD.
> Note. This is valid only for EMAC-AHB with AHB Bus Interface. The AXI Bus is inherently Little Endian, and this setting should not be enabled for the EMAC-AXI.
(Default: 1'b0)
13DESCRIPTOR_BYTE_ORDERINGRW0Descriptor Byte Ordering Bit 0
- In 64-bit mode, this bit, along with Bit [19], determines the descriptor byte ordering.
- In 32-bit mode, setting this bit causes the receive and transmit DMAs to operate in Big-Endian mode within the 32-bit DWORD for descriptors. And this bit has the following encoding values (Bit [19] is reserved):
1’b0: Normal descriptor DWORD format
1’b1: Big-Endian byte ordering within the descriptor DWORD.
(Default: 1'b0)
12:8DESCRIPTOR_SKIP_LENGTHRW0Descriptor Skip Length
This field specifies the number of 32-bit DWORDS to skip between two unchained descriptors. It applies to both transmit and receive DMAs.
Default: 5’b00000 (continuous descriptors)
7:1BURST_LENGTHRW0x4Burst Length
This field indicates the maximum number of 32-bit DWORDs or 64-bit QWORDS to be transferred to/from the host interface in a single DMA transaction. The permissible values for the burst length field are as follows:
- 7’b0000001: 1 DWORD/QWORD
- 7’b0000010: 2 DWORDS/QWORDS
- 7’b0000100: 4 DWORDS/QWORDS
- 7’b0001000: 8 DWORDS/QWORDS
- 7’b0010000: 16 DWORDS/QWORDS
- 7’b0100000: 32 DWORDS/QWORDS
- 7’b1000000: 64 DWORDS/QWORDS
Default: 7’b0000100 (4 DWORDS/QWORDS)
> Note. For EMAC-AXI with an AXI interface, the maximum burst length should be restricted to 16 DWORDS/QWORDS to comply with the AXI bus protocol.
0SOFTWARE_RESETRW0Software Reset
When this bit is set, the DMA controller is reset to its default state, clearing all internal state information. Both the receive and transmit DMAs will enter the stopped state.
When this bit is reset, the DMA controller operates in normal mode.
(Default : 1’b0)
+**Offset: 0x0000** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:17 | Reserved | | | Reserved for future use | +| 20 | BIG_LITTLE_ENDIAN | RW | 0 | Big/Little Endian Bit 1
This bit should be set only when the EMAC-AHB core is configured to operate in 64-bit mode (Bit [18] is set). Together with Bit [14], this bit determines the endianness for data buffers. The following combinations of {Bit [20], Bit [14]} define the endianness:
- 2’b00: Little Endian Byte Order with in the 64-bit QWORD.
- 2’b01: Big Endian Byte Order within 32-bit DWORD in a QWORD.
- 2’b10: Reserved
- 2’b11: Big Endian Byte Order with in the 64-bit QWORD.
(Default: 1’b0) | +| 19 | DESCRIPTOR_BYTE_ORDERING | RW | 0 | Descriptor Byte Order Bit (Bit 1)
This bit should be set only when the EMAC core is configured to operate in 64-bit mode (Bit [18] is set). Together with Bit [13], this bit determines the byte order for descriptors. The following combinations of {Bit [19], Bit [13]} define the descriptor byte ordering:
2’b00: Normal descriptor QWORD format.
2’b01: Big Endian byte ordering within the descriptor DWORD.
2’b10: Big Endian format for DWORDS within the QWORD.
2’b11: Big Endian format for both DWORDS and bytes within DWORDS.
(Default: 1’b0) | +| 18 | DMA_64BIT_MODE | RW | 0 | 64-bit Mode
- When this bit is set, the receive and transmit DMAs perform 64-bit data transfers for both descriptors and buffer transfers. Note that the addressing remains 32-bitIn this mode, the AHB/AXI master interface performs 64-bit data transfers by setting the size on the AHB/AXI master interface to 3’b011.
- This bit should be set only when the EMAC is interfaced to a 64-bit AHB/AXI bus and the EMAC’s host data bus width is configured to be 64-bit.
- When this bit is reset, the receive and transmit DMAs perform only 32-bit data transfers for both descriptors and buffer transfers. In this mode, the AHB/AXI master interface performs 32-bit data transfers by setting the size on the AHB/AXI master interface to 3’b010.
(Default: 1’b0) | +| 17 | STRICT_BURST | RW | 0 | Strict Burst Mode
- When this bit is set, the receive and transmit DMAs operate in strict burst mode. In this mode, the DMA restricts the burst size to either the value specified in the burst length field or a single DWORD/QWORD. This is particularly useful when the AHB/AXI bus supports only specific burst sizes, such as 1, 4, 8, or 16.
- When this bit is reset, the receive and transmit DMAs can use any burst size from 1 up to the value programmed in the burst length field. This allows for optimized performance and is beneficial when the AHB bus supports bursts of any size.
(Default: 1’b0) | +| 16 | WAIT_FOR_DONE | RW | 0 | Wait for Done
- When this bit is set, the transmit DMA waits for the Done signal from the FIFO interface before fetching the next packet’s descriptor.
- When this bit is reset, the transmit DMA does not wait for the Done signal from the FIFO interface and continuously processes transmit descriptors, provided the FIFO is not full.
(Default: 1’b0) | +| 15 | TX_RX_ARBITRATION | RW | 0 | TX/RX Arbitration
This bit selects the internal bus arbitration scheme between the receive and transmit DMA state machines.
- When this bit is set, a round-robin arbitration scheme is applied, ensuring equal sharing of the bus between the receive and transmit DMAs.
- When this bit is reset, the receive DMA has priority over the transmit DMA, unless the transmit DMA controller is actively transmitting.
(Default: 1’b0) | +| 14 | BIG_LITLE_ENDIAN | RW | 0 | Big/Little Endian Bit 0
- In 32-bit mode, setting this bit configures the DMA Controller to operate in Big Endian byte ordering mode for data buffers. When this bit is reset, the DMA Controller operates in Little Endian byte ordering mode for data buffers.
- In 64-bit mode, both this bit and Bit [20] determine the Endianness.
In 32-bit mode, the encoding of this bit is as follows when Bit [20] is reserved:
1'b0: Little Endian byte order within the DWORD.
1'b1: Big Endian byte order within the DWORD.
> Note. This is valid only for EMAC-AHB with AHB Bus Interface. The AXI Bus is inherently Little Endian, and this setting should not be enabled for the EMAC-AXI.
(Default: 1'b0) | +| 13 | DESCRIPTOR_BYTE_ORDERING | RW | 0 | Descriptor Byte Ordering Bit 0
- In 64-bit mode, this bit, along with Bit [19], determines the descriptor byte ordering.
- In 32-bit mode, setting this bit causes the receive and transmit DMAs to operate in Big-Endian mode within the 32-bit DWORD for descriptors. And this bit has the following encoding values (Bit [19] is reserved):
1’b0: Normal descriptor DWORD format
1’b1: Big-Endian byte ordering within the descriptor DWORD.
(Default: 1'b0) | +| 12:8 | DESCRIPTOR_SKIP_LENGTH | RW | 0 | Descriptor Skip Length
This field specifies the number of 32-bit DWORDS to skip between two unchained descriptors. It applies to both transmit and receive DMAs.
Default: 5’b00000 (continuous descriptors) | +| 7:1 | BURST_LENGTH | RW | 0x4 | Burst Length
This field indicates the maximum number of 32-bit DWORDs or 64-bit QWORDS to be transferred to/from the host interface in a single DMA transaction. The permissible values for the burst length field are as follows:
- 7’b0000001: 1 DWORD/QWORD
- 7’b0000010: 2 DWORDS/QWORDS
- 7’b0000100: 4 DWORDS/QWORDS
- 7’b0001000: 8 DWORDS/QWORDS
- 7’b0010000: 16 DWORDS/QWORDS
- 7’b0100000: 32 DWORDS/QWORDS
- 7’b1000000: 64 DWORDS/QWORDS
Default: 7’b0000100 (4 DWORDS/QWORDS)
> Note. For EMAC-AXI with an AXI interface, the maximum burst length should be restricted to 16 DWORDS/QWORDS to comply with the AXI bus protocol. | +| 0 | SOFTWARE_RESET | RW | 0 | Software Reset
When this bit is set, the DMA controller is reset to its default state, clearing all internal state information. Both the receive and transmit DMAs will enter the stopped state.
When this bit is reset, the DMA controller operates in normal mode.
(Default: 1’b0) | #### DMA Control Register The DMA Control Register is used to control the Start/Stop of the Transmit/Receive DMA. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0004
BitsFieldTypeResetDescription
31:2ReservedReserved for future use
1START_STOP_RECEIVE_DMARW0Start/Stop Receive DMA
- When set:
1. The receive DMA enters the Running state, and the EMAC core attempts to acquire a descriptor from the receive list to process incoming frames.
2. Descriptor acquisition is attempted from the current position in the list (as specified in the Receive Base Address Register) or from the position retained when the receive DMA was previously stopped.
3. If no descriptor is owned by the EMAC core, the receive DMA enters the Suspended state, and the Receive Buffer Unavailable flag is set.
4. The Start Reception command is effective only when the receive DMA is in the Stopped state.
5. If this bit is set before programming the Receive Base Address Register, the EMAC core’s behavior will be unpredictable.
- When reset:
1. The receive DMA enters the Stopped state after completing the reception of the current frame.
2. The next descriptor position in the receive list is saved and becomes the current position when the receive DMA is restarted.
3. The Stop Receive DMA command is effective only when the receive DMA is in either the Running or Suspended state.
(Default: 1’b0)
0START_STOP_TRANSMIT_DMARW0Start/Stop Transmit DMA
- When set:
1. The transmit DMA enters the Running state, and the EMAC core checks the transmit list at the current position for a frame to be transmitted.
2. Descriptor acquisition is attempted either from the current position in the list (as specified in the Transmit Base Address Register) or from the position retained when the transmit DMA was previously stopped.
3. If the current descriptor is not owned by the EMAC core, the transmit DMA enters the Suspended state, and the Transmit Buffer Unavailable flag is set.
4. The Start Transmission command is effective only when the transmit DMA is in the Stopped state. If this bit is set before programming the Transmit Base Address Register, the EMAC core’s behavior will be unpredictable.
- When reset:
1. The transmit DMA enters the Stopped state after completing the transmission of the current frame.
2. The next descriptor position in the transmit list is saved and becomes the current position when the transmit DMA is restarted.
3. The Stop Transmit DMA command is effective only when the transmit DMA is in either the Running or Suspended state.
(Default: 1’b0)
+**Offset: 0x0004** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | | | Reserved for future use | +| 1 | START_STOP_RECEIVE_DMA | RW | 0 | Start/Stop Receive DMA
- When set:
1. The receive DMA enters the Running state, and the EMAC core attempts to acquire a descriptor from the receive list to process incoming frames.
2. Descriptor acquisition is attempted from the current position in the list (as specified in the Receive Base Address Register) or from the position retained when the receive DMA was previously stopped.
3. If no descriptor is owned by the EMAC core, the receive DMA enters the Suspended state, and the Receive Buffer Unavailable flag is set.
4. The Start Reception command is effective only when the receive DMA is in the Stopped state.
5. If this bit is set before programming the Receive Base Address Register, the EMAC core’s behavior will be unpredictable.
- When reset:
1. The receive DMA enters the Stopped state after completing the reception of the current frame.
2. The next descriptor position in the receive list is saved and becomes the current position when the receive DMA is restarted.
3. The Stop Receive DMA command is effective only when the receive DMA is in either the Running or Suspended state.
(Default: 1’b0) | +| 0 | START_STOP_TRANSMIT_DMA | RW | 0 | Start/Stop Transmit DMA
- When set:
1. The transmit DMA enters the Running state, and the EMAC core checks the transmit list at the current position for a frame to be transmitted.
2. Descriptor acquisition is attempted either from the current position in the list (as specified in the Transmit Base Address Register) or from the position retained when the transmit DMA was previously stopped.
3. If the current descriptor is not owned by the EMAC core, the transmit DMA enters the Suspended state, and the Transmit Buffer Unavailable flag is set.
4. The Start Transmission command is effective only when the transmit DMA is in the Stopped state. If this bit is set before programming the Transmit Base Address Register, the EMAC core’s behavior will be unpredictable.
- When reset:
1. The transmit DMA enters the Stopped state after completing the transmission of the current frame.
2. The next descriptor position in the transmit list is saved and becomes the current position when the transmit DMA is restarted.
3. The Stop Transmit DMA command is effective only when the transmit DMA is in either the Running or Suspended state.
(Default: 1’b0) | #### DMA Status and IRQ Register The DMA Status and IRQ Register provide Status and IRQ information on various conditions that need to be monitored by the Host software. The IRQ bits are used to generate interrupts to the host. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0008
BitsFieldTypeResetDescription
31:24ReservedReserved for future use
23:20RECEIVE_DMA_STATERO0x0Receive DMA State
This field represents the current state of the Receive DMA, with values that change dynamically. The following are the encodings for the Receive DMA states:
- 4'b0000: STOPPED
- 4'b0001: FETCH_DESCRIPTOR
- 4'b0010: WAIT_FOR_END_OF_RECEIVE
- 4'b0011: WAIT_FOR_RXFRAME
- 4'b0100: SUSPENDED
- 4'b0101: CLOSE_DESCRIPTOR
- 4'b0110: FLUSH_BUFFER
- 4'b0111: PUT_BUFFER
- 4'b1000: WAIT_FOR_STATUS
(Default: 4'b0000)
19ReservedReserved for future use
18:16TRANSMIT_DMA_STATERO0x0Transmit DMA State
This field represents the current state of the Transmit DMA, with values that change dynamically. The following are the encodings for the Transmit DMA states:
- 3'b000: STOPPED
- 3'b001: FETCH_DESCRIPTOR
- 3'b010: Reserved
- 3'b011: FETCH_DATABUFFER
- 3'b100: CLOSE_DESCRIPTOR
- 3'b101: SUSPENDED
- 3'b110: Reserved
- 3'b111: Reserved
(Default: 3'b000)
15:10ReservedReserved for future use
9PTP_IRQRO01588 Interrupt
When set, this bit indicates that an interrupt has occurred from the 1588 portion of the EMAC Core. Software should read the 1588 Interrupt Register to determine the exact source of the interrupt.
This bit is cleared only when the corresponding bits in the 1588 Interrupt Register are cleared.
This behavior is valid only when the 1588 operation is enabled and configured.
8MAC_IRQRO0MAC Interrupt
When set, this bit indicates that an interrupt has occurred from the MAC portion of the EMAC Core. Software should read the MAC Interrupt Register to determine the exact source of the MAC interrupt.
This bit is cleared only when the corresponding bits in the MAC Interrupt Register are cleared.
7RECEIVE_MISSED_FRAME_IRQRW0Receive Missed Frame IRQ
When set, this bit indicates that a frame was dropped (missed) because no host receive descriptors were available. The frame is flushed from the Internal FIFO.
This bit is set only when the Receive DMA is in the Suspended state and a new frame is received. At this point, the Receive DMA attempts to fetch the descriptor again, but if the descriptor is still owned by the host, the frame is considered missed.
The IRQ is cleared by writing a 1 to this bit. (Default: 1'b0)
6RECEIVE_DMA_STOPPED_IRQRW0Receive DMA Stopped IRQ
This bit is set when the Receive DMA enters the Stopped state.
The IRQ is cleared by writing 1 to this bit. (Default: 1’b0)
5RECEIVE_DES_UNAVAILABLE_IRQRW0Receive Descriptor Unavailable IRQ
When set, this bit indicates that the next descriptor in the receive list is owned by the host and cannot be acquired by the EMAC Core, causing the Receive DMA to enter the Suspended state. To resume processing receive descriptors, the host should change the ownership of the descriptor and write to the Receive Poll Demand Register.
If no write to the Receive Poll Demand Register is issued, the Receive DMA will resume automatically when the next recognized incoming frame is received.
The IRQ is cleared by writing a 1 to this bit. (Default: 1'b0)
4RECEIVE_TRANSFER_DONE_IRQRW0Receive Transfer Done IRQ
When set, this bit indicates the completion of a frame reception and the transfer of the frame contents to host memory. Specific frame status information is posted in the descriptor (RDES0) of the Last Descriptor. The Receive DMA enters the Running state and will fetch the next descriptor.
In Receive Interrupt Mitigation Mode, the bit is set when the programmed number of frames has been transferred to host memory, or when the Receive Interrupt Timeout counter expires and at least one frame has been transferred to host memory without setting the Receive Transfer Done IRQ.
The IRQ is cleared by writing a 1 to this bit. (Default: 1'b0)
3ReservedReserved for future use
2TRANSMIT_DMA_STOPPED_IRQRW0Transmit DMA Stopped IRQ
This bit is set when the Transmit DMA enters the Stopped state.
The IRQ is cleared by writing 1 to this bit. (default: 1’b0)
1TRANSMIT_DES_UNAVAILABLE_IRQRW0Transmit Descriptor Unavailable IRQ
When set, this bit indicates that the next descriptor on the transmit list is owned by the host and cannot be acquired by the EMAC Core. In this case, the Transmit DMA enters the Suspended state. To resume processing transmit descriptors, the host software should change the ownership bit of the descriptor and then write to the Transmit Poll Demand Register, unless Transmit Auto Polling is enabled.
0TRANSMIT_TRANSFER_DONE_IRQRW0Transmit Transfer Done IRQ
When set, this bit indicates that a frame transmission has been completed, and the Interrupt On Completion (TDES1[31]) is set in the first descriptor of the frame.
- If the Wait for Done bit is not set, the IRQ is triggered when the transmit frame is enqueued into the Transmit FIFO.
- If the Wait for Done bit is set, the IRQ is triggered only when the frame is completely transmitted onto the MII/GMII interface.
The IRQ is cleared by writing a 1 to this bit. (Default: 1'b0)
+**Offset: 0x0008** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Reserved | | | Reserved for future use | +| 23:20 | RECEIVE_DMA_STATE | RO | 0x0 | Receive DMA State
This field represents the current state of the Receive DMA, with values that change dynamically. The following are the encodings for the Receive DMA states:
- 4'b0000: STOPPED
- 4'b0001: FETCH_DESCRIPTOR
- 4'b0010: WAIT_FOR_END_OF_RECEIVE
- 4'b0011: WAIT_FOR_RXFRAME
- 4'b0100: SUSPENDED
- 4'b0101: CLOSE_DESCRIPTOR
- 4'b0110: FLUSH_BUFFER
- 4'b0111: PUT_BUFFER
- 4'b1000: WAIT_FOR_STATUS
(Default: 4'b0000) | +| 19 | Reserved | | | Reserved for future use | +| 18:16 | TRANSMIT_DMA_STATE | RO | 0x0 | Transmit DMA State
This field represents the current state of the Transmit DMA, with values that change dynamically. The following are the encodings for the Transmit DMA states:
- 3'b000: STOPPED
- 3'b001: FETCH_DESCRIPTOR
- 3'b010: Reserved
- 3'b011: FETCH_DATABUFFER
- 3'b100: CLOSE_DESCRIPTOR
- 3'b101: SUSPENDED
- 3'b110: Reserved
- 3'b111: Reserved
(Default: 3'b000) | +| 15:10 | Reserved | | | Reserved for future use | +| 9 | PTP_IRQ | RO | 0 | 1588 Interrupt
When set, this bit indicates that an interrupt has occurred from the 1588 portion of the EMAC Core. Software should read the 1588 Interrupt Register to determine the exact source of the interrupt.
This bit is cleared only when the corresponding bits in the 1588 Interrupt Register are cleared.
This behavior is valid only when the 1588 operation is enabled and configured. | +| 8 | MAC_IRQ | RO | 0 | MAC Interrupt
When set, this bit indicates that an interrupt has occurred from the MAC portion of the EMAC Core. Software should read the MAC Interrupt Register to determine the exact source of the MAC interrupt.
This bit is cleared only when the corresponding bits in the MAC Interrupt Register are cleared. | +| 7 | RECEIVE_MISSED_FRAME_IRQ | RW | 0 | Receive Missed Frame IRQ
When set, this bit indicates that a frame was dropped (missed) because no host receive descriptors were available. The frame is flushed from the Internal FIFO.
This bit is set only when the Receive DMA is in the Suspended state and a new frame is received. At this point, the Receive DMA attempts to fetch the descriptor again, but if the descriptor is still owned by the host, the frame is considered missed.
The IRQ is cleared by writing a 1 to this bit. (Default: 1'b0) | +| 6 | RECEIVE_DMA_STOPPED_IRQ | RW | 0 | Receive DMA Stopped IRQ
This bit is set when the Receive DMA enters the Stopped state.
The IRQ is cleared by writing 1 to this bit. (Default: 1’b0) | +| 5 | RECEIVE_DES_UNAVAILABLE_IRQ | RW | 0 | Receive Descriptor Unavailable IRQ
When set, this bit indicates that the next descriptor in the receive list is owned by the host and cannot be acquired by the EMAC Core, causing the Receive DMA to enter the Suspended state. To resume processing receive descriptors, the host should change the ownership of the descriptor and write to the Receive Poll Demand Register.
If no write to the Receive Poll Demand Register is issued, the Receive DMA will resume automatically when the next recognized incoming frame is received.
The IRQ is cleared by writing a 1 to this bit. (Default: 1'b0) | +| 4 | RECEIVE_TRANSFER_DONE_IRQ | RW | 0 | Receive Transfer Done IRQ
When set, this bit indicates the completion of a frame reception and the transfer of the frame contents to host memory. Specific frame status information is posted in the descriptor (RDES0) of the Last Descriptor. The Receive DMA enters the Running state and will fetch the next descriptor.
In Receive Interrupt Mitigation Mode, the bit is set when the programmed number of frames has been transferred to host memory, or when the Receive Interrupt Timeout counter expires and at least one frame has been transferred to host memory without setting the Receive Transfer Done IRQ.
The IRQ is cleared by writing a 1 to this bit. (Default: 1'b0) | +| 3 | Reserved | | | Reserved for future use | +| 2 | TRANSMIT_DMA_STOPPED_IRQ | RW | 0 | Transmit DMA Stopped IRQ
This bit is set when the Transmit DMA enters the Stopped state.
The IRQ is cleared by writing 1 to this bit. (default: 1’b0) | +| 1 | TRANSMIT_DES_UNAVAILABLE_IRQ | RW | 0 | Transmit Descriptor Unavailable IRQ
When set, this bit indicates that the next descriptor on the transmit list is owned by the host and cannot be acquired by the EMAC Core. In this case, the Transmit DMA enters the Suspended state. To resume processing transmit descriptors, the host software should change the ownership bit of the descriptor and then write to the Transmit Poll Demand Register, unless Transmit Auto Polling is enabled. | +| 0 | TRANSMIT_TRANSFER_DONE_IRQ | RW | 0 | Transmit Transfer Done IRQ
When set, this bit indicates that a frame transmission has been completed, and the Interrupt On Completion (TDES1[31]) is set in the first descriptor of the frame.
- If the Wait for Done bit is not set, the IRQ is triggered when the transmit frame is enqueued into the Transmit FIFO.
- If the Wait for Done bit is set, the IRQ is triggered only when the frame is completely transmitted onto the MII/GMII interface.
The IRQ is cleared by writing a 1 to this bit. (Default: 1'b0) | #### DMA Interrupt Enable Register The DMA Interrupt Enable Register is used to enable interrupt bits for various IRQ conditions, allowing the generation of interrupts onto the AHB/AXI Bus. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x000C
BitsFieldTypeResetDescription
31:10ReservedReserved for future use
9PTP_INTR_ENABLERW01588 Interrupt Enable
- When set, this bit enables the 1588 interrupt to generate an interrupt on the AHB/AXI Bus.
- When reset, the 1588 interrupt is blocked from generating an interrupt on the AHB/AXI Bus.
(Default: 1'b0)
8MAC_INTR_ENABLERW0MAC Interrupt Enable
- When set, this bit enables the MAC interrupt to trigger an interrupt on the AHB/AXI Bus.
- When reset, the MAC interrupt is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0)
7RECEIVE_MISSED_FRAME_INTR_ENABLERW0Receive Missed Frame Interrupt Enable
- When set, this bit enables the Receive Missed Frame IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Receive Missed Frame IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0)
6RECEIVE_DMA_STOPPED_INTR_ENABLERW0Receive DMA Stopped Interrupt Enable
- When set, this bit enables the Receive DMA Stopped IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Receive DMA Stopped IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0)
5RECEIVE_DES_UNAVAILABLE_INTR_ENABLERW0Receive Descriptor Unavailable Interrupt Enable
- When set, this bit enables the Receive Descriptor Unavailable IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Receive Descriptor Unavailable IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0)
4RECEIVE_TRANSFER_DONE_INTR_ENABLERW0Receive Transfer Done Interrupt Enable
- When set, this bit enables the Receive Transfer Done IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Receive Transfer Done IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0)
3ReservedReserved for future use
2TRANSMIT_DMA_STOPPED_INTR_ENABLERW0Transmit DMA Stopped Interrupt Enable
- When set, this bit enables the Transmit DMA Stopped IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Transmit DMA Stopped IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0)
1TRANSMIT_DES_UNAVAILABLE_INTR_ENABLERW0Transmit Descriptor Unavailable Interrupt Enable
- When set, this bit enables the Transmit Descriptor Unavailable IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Transmit Descriptor Unavailable IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0)
0TRANSMIT_TRANSFER_DONE_INTR_ENABLERW0Transmit Transfer Done Interrupt Enable
- When set, this bit enables the Transmit Transfer Done IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Transmit Transfer Done IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0)
+**Offset: 0x000C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:10 | Reserved | | | Reserved for future use | +| 9 | PTP_INTR_ENABLE | RW | 0 | 1588 Interrupt Enable
- When set, this bit enables the 1588 interrupt to generate an interrupt on the AHB/AXI Bus.
- When reset, the 1588 interrupt is blocked from generating an interrupt on the AHB/AXI Bus.
(Default: 1'b0) | +| 8 | MAC_INTR_ENABLE | RW | 0 | MAC Interrupt Enable
- When set, this bit enables the MAC interrupt to trigger an interrupt on the AHB/AXI Bus.
- When reset, the MAC interrupt is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0) | +| 7 | RECEIVE_MISSED_FRAME_INTR_ENABLE | RW | 0 | Receive Missed Frame Interrupt Enable
- When set, this bit enables the Receive Missed Frame IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Receive Missed Frame IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0) | +| 6 | RECEIVE_DMA_STOPPED_INTR_ENABLE | RW | 0 | Receive DMA Stopped Interrupt Enable
- When set, this bit enables the Receive DMA Stopped IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Receive DMA Stopped IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0) | +| 5 | RECEIVE_DES_UNAVAILABLE_INTR_ENABLE | RW | 0 | Receive Descriptor Unavailable Interrupt Enable
- When set, this bit enables the Receive Descriptor Unavailable IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Receive Descriptor Unavailable IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0) | +| 4 | RECEIVE_TRANSFER_DONE_INTR_ENABLE | RW | 0 | Receive Transfer Done Interrupt Enable
- When set, this bit enables the Receive Transfer Done IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Receive Transfer Done IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0) | +| 3 | Reserved | | | Reserved for future use | +| 2 | TRANSMIT_DMA_STOPPED_INTR_ENABLE | RW | 0 | Transmit DMA Stopped Interrupt Enable
- When set, this bit enables the Transmit DMA Stopped IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Transmit DMA Stopped IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0) | +| 1 | TRANSMIT_DES_UNAVAILABLE_INTR_ENABLE | RW | 0 | Transmit Descriptor Unavailable Interrupt Enable
- When set, this bit enables the Transmit Descriptor Unavailable IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Transmit Descriptor Unavailable IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0) | +| 0 | TRANSMIT_TRANSFER_DONE_INTR_ENABLE | RW | 0 | Transmit Transfer Done Interrupt Enable
- When set, this bit enables the Transmit Transfer Done IRQ to trigger an interrupt on the AHB/AXI Bus.
- When reset, the Transmit Transfer Done IRQ is blocked from triggering an interrupt on the AHB/AXI Bus.
(Default: 1'b0) | #### DMA Transmit Auto Poll Counter Register The DMA Transmit Auto Poll Counter Register determines the polling frequency for the Transmit DMA when it is in the Suspended state. In this state, descriptor fetching is reinitiated either when the Transmit Auto Poll Counter expires or when a write is made to the Transmit Poll Demand Register. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0010
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0TRANSMIT_AUTO_POLLRW
0x0
Transmit Auto Poll Value
It defines the number of AHB/AXI clocks the system waits in the Suspended state before the Transmit DMA attempts to re-fetch the descriptor.
- If no descriptor is available, the Transmit DMA returns to the Suspended state, and the Transmit Descriptor Unavailable Interrupt is set.
- If a descriptor is available, the Transmit DMA resumes operation.
The internal Auto Poll Counter operates only when the Transmit DMA is in the Suspended state and is reset in other states. The Transmit Auto Polling feature is disabled when this value is written as all zeros.
(Default: 16'h0000)
+**Offset: 0x0010** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | TRANSMIT_AUTO_POLL | RW | 0x0 | Transmit Auto Poll Value
It defines the number of AHB/AXI clocks the system waits in the Suspended state before the Transmit DMA attempts to re-fetch the descriptor.
- If no descriptor is available, the Transmit DMA returns to the Suspended state, and the Transmit Descriptor Unavailable Interrupt is set.
- If a descriptor is available, the Transmit DMA resumes operation.
The internal Auto Poll Counter operates only when the Transmit DMA is in the Suspended state and is reset in other states. The Transmit Auto Polling feature is disabled when this value is written as all zeros.
(Default: 16'h0000) | #### DMA Transmit Poll Demand Register The DMA Transmit Poll Demand Register is used to instruct the Transmit DMA to begin fetching the descriptor again while the Transmit DMA is in the Suspended State. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0014
BitsFieldTypeResetDescription
31:0TRANSMIT_POLL_DEMANDWO0x0Transmit Poll Demand
When the Transmit DMA is in the Suspended State, writing any value to this register prompts the EMAC Core to check for frames to transmit by re-fetching the descriptor.
- If no descriptor is available, the Transmit DMA returns to the Suspended State, and the Transmit Descriptor Unavailable Interrupt is set.
- If a descriptor is available, the Transmit DMA resumes operation.
+**Offset: 0x0014** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | TRANSMIT_POLL_DEMAND | WO | 0x0 | Transmit Poll Demand
When the Transmit DMA is in the Suspended State, writing any value to this register prompts the EMAC Core to check for frames to transmit by re-fetching the descriptor.
- If no descriptor is available, the Transmit DMA returns to the Suspended State, and the Transmit Descriptor Unavailable Interrupt is set.
- If a descriptor is available, the Transmit DMA resumes operation. | #### DMA Receive Poll Demand Register The DMA Receive Poll Demand Register is used to signal the Receive DMA to begin fetching the descriptor again while the Receive DMA is in the Suspended State. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0018
BitsFieldTypeResetDescription
31:0RECEIVE_POLL_DEMANDWO0x0Receive Poll Demand
When the Transmit DMA is in the Suspended state, writing any value to this register triggers the EMAC Core to check for frames to be transmitted by re-fetching the descriptor.
- If no descriptor is available, the Transmit DMA returns to the Suspended state, and the Transmit Descriptor Unavailable Interrupt is set.
- If a descriptor is available, the Transmit DMA resumes operation.
+**Offset: 0x0018** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RECEIVE_POLL_DEMAND | WO | 0x0 | Receive Poll Demand
When the Transmit DMA is in the Suspended state, writing any value to this register triggers the EMAC Core to check for frames to be transmitted by re-fetching the descriptor.
- If no descriptor is available, the Transmit DMA returns to the Suspended state, and the Transmit Descriptor Unavailable Interrupt is set.
- If a descriptor is available, the Transmit DMA resumes operation. | #### DMA Transmit Base Address Register This register specifies the starting address of the Transmit Descriptor list in the host's memory space. The value programmed into this register must be 32-bit aligned. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x001C
BitsFieldTypeResetDescription
31:0TRANSMIT_BASE_ADDRESSRW0x0Transmit Base Address
It holds the starting address of the Transmit Descriptor list in the host memory space. When the Transmit DMA starts, it uses the value in this register to fetch descriptors (only if the register has been updated). Otherwise, it continues from the last saved address before the DMA was stopped.
- All descriptors are 32-bit aligned, so the programmed value must be 32-bit aligned.
- In 64-bit Host Bus width mode, descriptors are 64-bit aligned, requiring a 64-bit aligned programmed value.
- This register should be written only when the Transmit DMA is in the Stopped state.
(Default: 32'h0000_0000)
+**Offset: 0x001C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | TRANSMIT_BASE_ADDRESS | RW | 0x0 | Transmit Base Address
It holds the starting address of the Transmit Descriptor list in the host memory space. When the Transmit DMA starts, it uses the value in this register to fetch descriptors (only if the register has been updated). Otherwise, it continues from the last saved address before the DMA was stopped.
- All descriptors are 32-bit aligned, so the programmed value must be 32-bit aligned.
- In 64-bit Host Bus width mode, descriptors are 64-bit aligned, requiring a 64-bit aligned programmed value.
- This register should be written only when the Transmit DMA is in the Stopped state.
(Default: 32'h0000_0000) | #### DMA Receive Base Address Register The DMA Receive Base Address Register is used to point to the Start of Receive Descriptor list in the Host’s Memory Space. The value programmed in this register should be 32-bit aligned value. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0020
BitsFieldTypeResetDescription
31:0RECEIVE_BASE_ADDRESSRW0x0Receive Base Address
It holds the starting address of the Receive Descriptor list in the host memory space. When the Receive DMA starts, it uses the value in this register to fetch descriptors (only if the register has been updated). Otherwise, it continues from the last saved address before the DMA was stopped.
- All descriptors are 32-bit aligned, so the programmed value must be 32-bit aligned.
- In 64-bit mode, descriptors are 64-bit aligned, requiring a 64-bit aligned programmed value.
- This register should be written only when the Receive DMA is in the Stopped state.
(Default: 32'h0000_0000)
+**Offset: 0x0020** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RECEIVE_BASE_ADDRESS | RW | 0x0 | Receive Base Address
It holds the starting address of the Receive Descriptor list in the host memory space. When the Receive DMA starts, it uses the value in this register to fetch descriptors (only if the register has been updated). Otherwise, it continues from the last saved address before the DMA was stopped.
- All descriptors are 32-bit aligned, so the programmed value must be 32-bit aligned.
- In 64-bit mode, descriptors are 64-bit aligned, requiring a 64-bit aligned programmed value.
- This register should be written only when the Receive DMA is in the Stopped state.
(Default: 32'h0000_0000) | #### DMA Missed Frame Counter Register The DMA Missed Frame Counter Register tracks the number of frames missed due to the unavailability of a receive descriptor. When the Receive DMA is suspended and a new receive frame is received, it attempts to fetch a descriptor. If the descriptor is unavailable (i.e. owned by the host), the frame is flushed from the receive FIFO. This counter represents the total number of frames missed since the counter was last read. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0024
BitsFieldTypeResetDescription
31MISSED_FRAME_COUNTER_OVERFLOW_IRQRW0Missed Frame Counter Overflow IRQ
This bit is set when the Missed Frame Counter overflows.
> Note. Setting this bit does not trigger an interrupt.
The bit is cleared when this register is read by the host.
(Default: 1'b0)
30:0MISSED_FRAME_COUNTERRW0x0Missed Frame Counter
It tracks the number of frames missed due to the unavailability of a receive descriptor. When the Receive DMA is suspended and a new receive frame is received, it attempts to fetch a descriptor. If the descriptor is unavailable (i.e., owned by the host), the frame is flushed from the receive FIFO.
This counter represents the total number of such frames missed since the counter was last read.
The counter is cleared when it is read.
(Default: 31'h0000_0000)
+**Offset: 0x0024** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | MISSED_FRAME_COUNTER_OVERFLOW_IRQ | RW | 0 | Missed Frame Counter Overflow IRQ
This bit is set when the Missed Frame Counter overflows.
> Note. Setting this bit does not trigger an interrupt.
The bit is cleared when this register is read by the host.
(Default: 1'b0) | +| 30:0 | MISSED_FRAME_COUNTER | RW | 0x0 | Missed Frame Counter
It tracks the number of frames missed due to the unavailability of a receive descriptor. When the Receive DMA is suspended and a new receive frame is received, it attempts to fetch a descriptor. If the descriptor is unavailable (i.e., owned by the host), the frame is flushed from the receive FIFO.
This counter represents the total number of such frames missed since the counter was last read.
The counter is cleared when it is read.
(Default: 31'h0000_0000) | #### DMA Stop Flush Counter Register The DMA Stop Flush Counter Register tracks the number of frames that were flushed because the Receive DMA is in Stopped State, since the counter was last read. An interrupt is generated when the counter overflows. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0028
BitsFieldTypeResetDescription
31STOP_COUNTER_OVERFLOW_IRQRW0Stop Counter Overflow IRQ
This bit is set when the Stop Flush Counter overflows.
Setting this bit does not trigger an interrupt.
The bit is cleared when this register is read by the Host.
(Default: 1'b0)
30:0STOP_FLUSH_COUNTER
RW0x0Stop Flush Counter
It tracks the number of frames that were flushed from the Receive FIFO due to the Receive DMA being in the Stopped State.
This counter represents the total number of frames flushed since the counter was last read.
The counter is cleared upon reading.
(Default: 31'h0000_0000)
+**Offset: 0x0028** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | STOP_COUNTER_OVERFLOW_IRQ | RW | 0 | Stop Counter Overflow IRQ
This bit is set when the Stop Flush Counter overflows.
Setting this bit does not trigger an interrupt.
The bit is cleared when this register is read by the Host.
(Default: 1'b0) | +| 30:0 | STOP_FLUSH_COUNTER | RW | 0x0 | Stop Flush Counter
It tracks the number of frames that were flushed from the Receive FIFO due to the Receive DMA being in the Stopped State.
This counter represents the total number of frames flushed since the counter was last read.
The counter is cleared upon reading.
(Default: 31'h0000_0000) | #### DMA Receive Transfer Done Interrupt Mitigation Control The DMA Receive Transfer Done Interrupt Control Register governs the behavior of interrupt generation when a packet is received and successfully transferred to Host Memory (Receive Transfer Done Interrupt). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x002C
BitsFieldTypeResetDescription
31RECEIVE_IRQ_MITIGATION_ENABLERW
0Receive Transfer Done Interrupt Mitigation Control Enable
- When set:
Enables Receive Transfer Done Interrupt Mitigation Control using the packet/timer counter.
- When reset:
Disables interrupt mitigation, and the Receive Transfer Done Interrupt is asserted for each packet transferred to host memory. The DMA Interrupt Register will reflect this interrupt.
(Default Value: 1'b0)
30RECEIVE_IRQ_FRAME_COUNTER_MODERW0Receive Interrupt Frame Counter Mode
- When set:
The Receive Interrupt Frame Counter is reset to 8'h01 after the Receive Transfer Done Interrupt is generated when operating in Receive Interrupt Mitigation Mode.
- When reset:
The Receive Interrupt Frame Counter is not modified internally and retains the value programmed by the software.
29:28ReservedReserved for future use
27:8RECEIVE_IRQ_TIMEOUT_COUNTER
RW0xFFFFReceive Interrupt Timeout Counter
These bits define the maximum time (in AHB/AXI clock periods) between the last Receive Transfer Done Interrupt and the assertion of a new Receive Transfer Done Interrupt, provided that at least one frame has been transferred to Host Memory.
When Interrupt Mitigation is enabled, the Receive Transfer Done Interrupt is asserted after every 'n' frames, where 'n' is determined by the Receive Interrupt Frame Counter. The Receive Transfer Done Interrupt is asserted when either:
- 'n' frames have been transferred to Host Memory, or
- The internal Timeout Counter exceeds the value programmed in these bits, and at least one frame has been transferred to Host Memory.
(Default Value: 20'h0_FFFF)
7:0RECEIVE_IRQ_FRAME_COUNTERRW0x1Receive Interrupt Frame Counter
These bits specify the number of frames to be counted before asserting the Receive Transfer Done Interrupt.
The value in this register is only valid when Bit [31] is set.
When Bit [31] is set, the Receive DMA will assert the Receive Transfer Done Interrupt after every 'n' frames, where 'n' is the value programmed in this register.
Legal values: 1 - 255
Default Value: 8'b0000_0001
+**Offset: 0x002C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | RECEIVE_IRQ_MITIGATION_ENABLE | RW | 0 | Receive Transfer Done Interrupt Mitigation Control Enable
- When set:
Enables Receive Transfer Done Interrupt Mitigation Control using the packet/timer counter.
- When reset:
Disables interrupt mitigation, and the Receive Transfer Done Interrupt is asserted for each packet transferred to host memory. The DMA Interrupt Register will reflect this interrupt.
(Default Value: 1'b0) | +| 30 | RECEIVE_IRQ_FRAME_COUNTER_MODE | RW | 0 | Receive Interrupt Frame Counter Mode
- When set:
The Receive Interrupt Frame Counter is reset to 8'h01 after the Receive Transfer Done Interrupt is generated when operating in Receive Interrupt Mitigation Mode.
- When reset:
The Receive Interrupt Frame Counter is not modified internally and retains the value programmed by the software. | +| 29:28 | Reserved | | | Reserved for future use | +| 27:8 | RECEIVE_IRQ_TIMEOUT_COUNTER | RW | 0xFFFF | Receive Interrupt Timeout Counter
These bits define the maximum time (in AHB/AXI clock periods) between the last Receive Transfer Done Interrupt and the assertion of a new Receive Transfer Done Interrupt, provided that at least one frame has been transferred to Host Memory.
When Interrupt Mitigation is enabled, the Receive Transfer Done Interrupt is asserted after every 'n' frames, where 'n' is determined by the Receive Interrupt Frame Counter. The Receive Transfer Done Interrupt is asserted when either:
- 'n' frames have been transferred to Host Memory, or
- The internal Timeout Counter exceeds the value programmed in these bits, and at least one frame has been transferred to Host Memory.
(Default Value: 20'h0_FFFF) | +| 7:0 | RECEIVE_IRQ_FRAME_COUNTER | RW | 0x1 | Receive Interrupt Frame Counter
These bits specify the number of frames to be counted before asserting the Receive Transfer Done Interrupt.
The value in this register is only valid when Bit [31] is set.
When Bit [31] is set, the Receive DMA will assert the Receive Transfer Done Interrupt after every 'n' frames, where 'n' is the value programmed in this register.
Legal values: 1 - 255
Default Value: 8'b0000_0001 | #### DMA Current Tx. Descriptor Pointer Register This register holds the pointer to the current descriptor that the Transmit DMA is using. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0030
BitsFieldTypeResetDescription
31:0CURRENT_TRANSMIT_DES_POINTERRO0x0Current Transmit Descriptor Pointer
This field holds the current descriptor pointer being used by the Transmit DMA.
The value is aligned according to the configured bus width of the DMA, either 32-bit or 64-bit.
> Note. This is a read-only value, typically used for debugging purposes.
(Default: 32’h0000_0000)
+**Offset: 0x0030** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CURRENT_TRANSMIT_DES_POINTER | RO | 0x0 | Current Transmit Descriptor Pointer
This field holds the current descriptor pointer being used by the Transmit DMA.
The value is aligned according to the configured bus width of the DMA, either 32-bit or 64-bit.
> Note. This is a read-only value, typically used for debugging purposes.
(Default: 32’h0000_0000) | #### DMA Current Tx. Buffer Pointer Register This register contains the current buffer pointer being used by the Transmit DMA. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0034
BitsFieldTypeResetDescription
31:0CURRENT_TRANSMIT_BUFER_POINTERRO0x0Current Transmit Buffer Pointer
This field contains the current buffer pointer the Transmit DMA is using.
> Note. This is a Read only value used for debugging purposes.
(Default: 32’h0000_0000)
+**Offset: 0x0034** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CURRENT_TRANSMIT_BUFER_POINTER | RO | 0x0 | Current Transmit Buffer Pointer
This field contains the current buffer pointer the Transmit DMA is using.
> Note. This is a Read only value used for debugging purposes.
(Default: 32’h0000_0000) | #### DMA Current Rx. Descriptor Pointer Register This register contains the current descriptor pointer being used by the Receive DMA. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0038
BitsFieldTypeResetDescription
31:0CURRENT_RECEIVE_DES_POINTERRO0x0Current Receive Descriptor Pointer
This field contains the current descriptor pointer the Receive DMA is using. This is a 32-bit aligned value or 64-bit aligned value based on the configured bus width of the DMA.
> Note. This is a read-only value used for debugging purposes.
(Default: 32’h0000_0000)
+**Offset: 0x0038** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CURRENT_RECEIVE_DES_POINTER | RO | 0x0 | Current Receive Descriptor Pointer
This field contains the current descriptor pointer the Receive DMA is using. This is a 32-bit aligned value or 64-bit aligned value based on the configured bus width of the DMA.
> Note. This is a read-only value used for debugging purposes.
(Default: 32’h0000_0000) | #### DMA Current Rx. Buffer Pointer Register This register contains the current buffer pointer being used by Receive DMA. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x003C
BitsFieldTypeResetDescription
31:0CURRENT_RECEIVE_BUFFER_POINTERRO0x0Current Receive Buffer Pointer
This field contains the current buffer pointer the Receive DMA is using.
> Note. This is a read-only value used for debugging purposes.
(Default: 32’h0000_0000)
+**Offset: 0x003C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CURRENT_RECEIVE_BUFFER_POINTER | RO | 0x0 | Current Receive Buffer Pointer
This field contains the current buffer pointer the Receive DMA is using.
> Note. This is a read-only value used for debugging purposes.
(Default: 32’h0000_0000) | #### MAC Global Control Register The MAC Global Control Register is used to program the global parameters for the MAC in the EMAC Core. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0100
BitsFieldTypeResetDescription
31:10ReservedReserved for future use
9MAGIC_PACKET_WAKEUP_MODERW0Magic Packet Wakeup Mode
When set, the EMAC Core operates in Wakeup Mode, preventing received frames from being written into the RXFIFO of the MAC. A wakeup event is triggered when a Magic Packet, whose Destination Address (DA) passes address filtering, contains a valid Magic Packet Signature in the packet contents.
(Default: 1’b0)
8
UNICAST_WAKEUP_MODERW0Unicast Wakeup Mode
When set, the EMAC Core operates in Wakeup Mode, preventing received frames from being written into the RXFIFO of the MAC.
A wakeup event is triggered when a unicast frame, whose destination address (DA) matches the value programmed in the MAC Address #0 Registers, is received.
(Default: 1’b0)
> Note. This register bit is reserved if Wakeup Mode is not supported in the current configuration.
7:5ReservedReserved for future use
4RESET_TX_STAT_COUNTERSRW0Reset Tx. Stat. Counters
When set, this field initiates the resetting of all Statistic Counters related to the Transmit path in the EMAC Core.
The actual reset process begins after this bit is cleared.
(Default: 1’b0)
3RESET_RX_STAT_COUNTERSRW0Reset Rx. Stat. Counters
When set, this field initiates the resetting of all Statistic Counters related to the Receive path in the EMAC Core.
The actual reset process begins after this bit is cleared.
(Default: 1’b0)
2DUPLEX_MODERW0Duplex Mode
- When set:
The EMAC core operates in Full-Duplex mode, enabling simultaneous transmission and reception of data.
- When reset:
The EMAC core operates in Half-Duplex mode, implementing the CSMA/CD protocol to monitor collisions and apply back-off mechanisms in case of collisions.
Default Value: 1’b0
1’b0: Half-Duplex Mode
1’b1: Full-Duplex Mode
> Note.
> - Changing the Full-Duplex bit is permitted only if the transmitter and receiver are disabled.
> - When the Speed variable is set to 2’b10 (1000 Mbps), the EMAC core must be configured for Full-Duplex mode, as it does not support Half-Duplex mode in Gigabit operation.
1:0SPEEDRW0x0Speed
This field determines the Ethernet interface speed of the EMAC Core.
Based on the configured speed, the EMAC Core selects either the GMII or MII interface. The txclk and rxclk frequencies should match the selected speed.
Permissible values:
- 2’b00 (10 Mbps) – Default
- 2’b01 (100 Mbps)
- 2’b10 (1000 Mbps)
- 2’b11 (Reserved)
+**Offset: 0x0100** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:10 | Reserved | | | Reserved for future use | +| 9 | MAGIC_PACKET_WAKEUP_MODE | RW | 0 | Magic Packet Wakeup Mode
When set, the EMAC Core operates in Wakeup Mode, preventing received frames from being written into the RXFIFO of the MAC. A wakeup event is triggered when a Magic Packet, whose Destination Address (DA) passes address filtering, contains a valid Magic Packet Signature in the packet contents.
(Default: 1’b0) | +| 8 | UNICAST_WAKEUP_MODE | RW | 0 | Unicast Wakeup Mode
When set, the EMAC Core operates in Wakeup Mode, preventing received frames from being written into the RXFIFO of the MAC.
A wakeup event is triggered when a unicast frame, whose destination address (DA) matches the value programmed in the MAC Address #0 Registers, is received.
(Default: 1’b0)
> Note. This register bit is reserved if Wakeup Mode is not supported in the current configuration. | +| 7:5 | Reserved | | | Reserved for future use | +| 4 | RESET_TX_STAT_COUNTERS | RW | 0 | Reset Tx. Stat. Counters
When set, this field initiates the resetting of all Statistic Counters related to the Transmit path in the EMAC Core.
The actual reset process begins after this bit is cleared.
(Default: 1’b0) | +| 3 | RESET_RX_STAT_COUNTERS | RW | 0 | Reset Rx. Stat. Counters
When set, this field initiates the resetting of all Statistic Counters related to the Receive path in the EMAC Core.
The actual reset process begins after this bit is cleared.
(Default: 1’b0) | +| 2 | DUPLEX_MODE | RW | 0 | Duplex Mode
- When set:
The EMAC core operates in Full-Duplex mode, enabling simultaneous transmission and reception of data.
- When reset:
The EMAC core operates in Half-Duplex mode, implementing the CSMA/CD protocol to monitor collisions and apply back-off mechanisms in case of collisions.
Default Value: 1’b0
1’b0: Half-Duplex Mode
1’b1: Full-Duplex Mode
> Note.
> - Changing the Full-Duplex bit is permitted only if the transmitter and receiver are disabled.
> - When the Speed variable is set to 2’b10 (1000 Mbps), the EMAC core must be configured for Full-Duplex mode, as it does not support Half-Duplex mode in Gigabit operation. | +| 1:0 | SPEED | RW | 0x0 | Speed
This field determines the Ethernet interface speed of the EMAC Core.
Based on the configured speed, the EMAC Core selects either the GMII or MII interface. The txclk and rxclk frequencies should match the selected speed.
Permissible values:
- 2’b00 (10 Mbps) – Default
- 2’b01 (100 Mbps)
- 2’b10 (1000 Mbps)
- 2’b11 (Reserved) | #### MAC Transmit Control Register The MAC Transmit Control Register is used to configure the parameters for the transmit portion of the MAC in the EMAC Core. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0104
BitsFieldTypeResetDescription
31:0ReservedReserved for future use
9:7PREAMBLE_LENGTHRW0x0Preamble Length
It determines the number of Preamble Bytes followed by SFD to be prepended to outgoing frames. According to the IEEE 802.3 specification, each frame must have 7 bytes of Preamble followed by 1 byte of SFD at the beginning. The permissible values for the Preamble Length field are as follows:
- 3'b000: 7 Bytes of Preamble (Default)
- 3'b001: 1 Byte of Preamble
- 3'b010: 2 Bytes of Preamble
- 3'b011: 3 Bytes of Preamble
- 3'b100: 4 Bytes of Preamble
- 3'b101: 5 Bytes of Preamble
- 3'b110: 6 Bytes of Preamble
- 3'b111: 7 Bytes of Preamble
> Note. Programming the Preamble Length to anything other than 3'b000 (7 Bytes of Preamble) violates the IEEE 802.3 specification and may cause interoperability issues with peer network devices. This field only controls the length of the Preamble; each outgoing frame will automatically have the SFD added after the Preamble and before the Destination Address field.
6:4IFG_LENRW0x0IFG Length
It determines the minimum Inter-Packet Gap (IPG) or Inter-Frame Gap (IFG) to be inserted between outgoing frames when the transmit FIFO has back-to-back data. The IEEE 802.3 specification requires a minimum IPG of 96 bit-times between frames.
The permissible values for the IFG Length field are as follows:
- 3’b000: 96 Bit Times of IFG
- 3’b001: 64 Bit Times of IFG
- 3’b010: 128 Bit Times of IFG
- 3’b011: 256 Bit Times of IFG
- 3’b100: 24 Bit Times of IFG
- 3’b101: 32 Bit Times of IFG
- 3’b110: 40 Bit Times of IFG
- 3’b111: 48 Bit Times of IFG
Default: 3’b000 (96 bit-times)
> Note.
> - Programming the IFG Length to less than 96 bit-times may cause interoperability issues with peer network devices.
> - Programming the IFG Length to 3’b010 or 3’b011 (128 or 256 bit-times) may result in performance degradation.
3TRANSMIT_AUTO_RETRYRW0Transmit Auto Retry
- When set:
The EMAC core automatically retries frame transmission on collision in Half-Duplex mode. The frame contents remain in the transmit FIFO until the collision window has passed.
- When reset:
The host is expected to retransmit the frame manually on collision.
(Default: 1’b0)
> Note. This field must be set to 1’b1 for proper operation of the EMAC core in Half-Duplex mode.
2DISABLE_FCS_INSERTRW0Disable FCS Insertion
- When set:
The FCS calculation and insertion logic is disabled in the transmit path. FCS insertion is disabled for all frames.
- When reset:
The FCS is calculated for all frames and inserted at the end of the outgoing frame, provided the per-frame FCS insertion is disabled (TDES1[28]).
> Note.
> When Disable FCS Insertion is enabled, it is expected that frames from the host memory will:
> - Meet the 64-byte minimum frame size requirement, and
> - Include the FCS field to ensure compliance with the IEEE 802.3 specification.
(Default: 1'b0)
1INVERT_FCSRW0Invert FCS
- When set:
The EMAC Core inverts the FCS field being inserted into the outgoing frame.
- When reset:
The EMAC Core performs normal FCS insertion without inversion.
> Note.
> - According to the IEEE 802.3 specification, the FCS is calculated from the first byte of the DA field to the last byte of the DATA/PAD field. The calculated FCS is then inverted and transmitted in MSB first.
> - In normal mode, the FCS is inverted before being inserted into the outgoing frame.
> - When the Invert FCS is set, the FCS field is double-inverted (effectively no inversion occurs).
(Default: 1'b0)
0TRANSMIT_ENABLERW0Transmit Enable
- When set
The EMAC Core’s transmitter is enabled and will transmit frames from the Transmit FIFO onto the MII/GMII Interface.
- When reset
The EMAC Core’s transmitter is disabled and will not transmit any frames.
(Default: 1'b0)
+**Offset: 0x0104** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | Reserved | | | Reserved for future use | +| 9:7 | PREAMBLE_LENGTH | RW | 0x0 | Preamble Length
It determines the number of Preamble Bytes followed by SFD to be prepended to outgoing frames. According to the IEEE 802.3 specification, each frame must have 7 bytes of Preamble followed by 1 byte of SFD at the beginning. The permissible values for the Preamble Length field are as follows:
- 3'b000: 7 Bytes of Preamble (Default)
- 3'b001: 1 Byte of Preamble
- 3'b010: 2 Bytes of Preamble
- 3'b011: 3 Bytes of Preamble
- 3'b100: 4 Bytes of Preamble
- 3'b101: 5 Bytes of Preamble
- 3'b110: 6 Bytes of Preamble
- 3'b111: 7 Bytes of Preamble
> Note. Programming the Preamble Length to anything other than 3'b000 (7 Bytes of Preamble) violates the IEEE 802.3 specification and may cause interoperability issues with peer network devices. This field only controls the length of the Preamble; each outgoing frame will automatically have the SFD added after the Preamble and before the Destination Address field. | +| 6:4 | IFG_LEN | RW | 0x0 | IFG Length
It determines the minimum Inter-Packet Gap (IPG) or Inter-Frame Gap (IFG) to be inserted between outgoing frames when the transmit FIFO has back-to-back data. The IEEE 802.3 specification requires a minimum IPG of 96 bit-times between frames.
The permissible values for the IFG Length field are as follows:
- 3’b000: 96 Bit Times of IFG
- 3’b001: 64 Bit Times of IFG
- 3’b010: 128 Bit Times of IFG
- 3’b011: 256 Bit Times of IFG
- 3’b100: 24 Bit Times of IFG
- 3’b101: 32 Bit Times of IFG
- 3’b110: 40 Bit Times of IFG
- 3’b111: 48 Bit Times of IFG
Default: 3’b000 (96 bit-times)
> Note.
> - Programming the IFG Length to less than 96 bit-times may cause interoperability issues with peer network devices.
> - Programming the IFG Length to 3’b010 or 3’b011 (128 or 256 bit-times) may result in performance degradation. | +| 3 | TRANSMIT_AUTO_RETRY | RW | 0 | Transmit Auto Retry
- When set:
The EMAC core automatically retries frame transmission on collision in Half-Duplex mode. The frame contents remain in the transmit FIFO until the collision window has passed.
- When reset:
The host is expected to retransmit the frame manually on collision.
(Default: 1’b0)
> Note. This field must be set to 1’b1 for proper operation of the EMAC core in Half-Duplex mode. | +| 2 | DISABLE_FCS_INSERT | RW | 0 | Disable FCS Insertion
- When set:
The FCS calculation and insertion logic is disabled in the transmit path. FCS insertion is disabled for all frames.
- When reset:
The FCS is calculated for all frames and inserted at the end of the outgoing frame, provided the per-frame FCS insertion is disabled (TDES1[28]).
> Note.
> When Disable FCS Insertion is enabled, it is expected that frames from the host memory will:
> - Meet the 64-byte minimum frame size requirement, and
> - Include the FCS field to ensure compliance with the IEEE 802.3 specification.
(Default: 1'b0) | +| 1 | INVERT_FCS | RW | 0 | Invert FCS
- When set:
The EMAC Core inverts the FCS field being inserted into the outgoing frame.
- When reset:
The EMAC Core performs normal FCS insertion without inversion.
> Note.
> - According to the IEEE 802.3 specification, the FCS is calculated from the first byte of the DA field to the last byte of the DATA/PAD field. The calculated FCS is then inverted and transmitted in MSB first.
> - In normal mode, the FCS is inverted before being inserted into the outgoing frame.
> - When the Invert FCS is set, the FCS field is double-inverted (effectively no inversion occurs).
(Default: 1'b0) | +| 0 | TRANSMIT_ENABLE | RW | 0 | Transmit Enable
- When set
The EMAC Core’s transmitter is enabled and will transmit frames from the Transmit FIFO onto the MII/GMII Interface.
- When reset
The EMAC Core’s transmitter is disabled and will not transmit any frames.
(Default: 1'b0) | #### MAC Receive Control Register The MAC Receive Control Register is used to program the parameters for the Receive portion of the MAC in the EMAC Core. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0108
BitsFieldTypeResetDescription
31:7ReservedReserved for future use
6ACOOUNT_VLANRW0Account VLANs
According to the IEEE 802.3 specification:
- The minimum frame size (minFrameSize) for untagged frames is 64 bytes.
- The maximum frame size (maxFrameSize) for untagged frames is 1518 bytes.
For VLAN-tagged frames, the frame size values are adjusted to account for the 4-byte VLAN tag, increasing the maxFrameSize to 1522 bytes.
The EMAC core supports up to 3 VLAN tags per frame. It can dynamically adjust the maxFrameSize field to accommodate up to 12 bytes (3 VLAN tags) based on the number of VLAN tags present in the incoming frame. This prevents false maxFrameSize violation reporting for VLAN-tagged frames that exceed 1518 bytes but are within the adjusted limit (1518 + tag bytes).
- When set:
The maxFrameSize field is dynamically adjusted to account for up to 3 VLAN tags (12 bytes) based on the number of VLAN tags in the incoming frame.
- When reset:
The maxFrameSize field is not adjusted and remains fixed at the value programmed in the Maximum Frame Size Register.
(Default: 1’b0)
5PASS_BAD_FRAMESRW0Pass Bad Frames
When the EMAC core operates in Store-and-Forward mode, frames with errors (e.g., CRC errors, minimum frame length errors, fragments, maximum frame length errors, receive errors, etc.) are typically flushed from the receive FIFO and not transferred to host memory.
- When set:
Frames with errors are transferred to host memory, and the appropriate error status is indicated in the Frame Status field (written back in the TDES0 of the last descriptor).
- When reset:
Frames with errors are not transferred to host memory and are flushed from the receive FIFO.
(Default: 1’b0)
4STATUS_FIRSTRW0Status First
When the EMAC core operates in Store-and-Forward mode, a frame is sent from the internal MAC to the DMA only after the entire frame is stored in the receive FIFO.
- When set:
The status field is transferred before the start of the packet (SOP).
- When reset:
The status field is transferred after the end of the packet (EOP).
For proper operation of the EMAC core, this bit should always be reset (1’b0).
3STORE_FORWARDRW0Store and Forward
- When set:
The EMAC core operates in store-and-forward mode in the receive direction. A frame is transferred to host memory only after the entire frame is stored in the receive FIFO. Frames with errors (e.g., CRC errors, minimum frame length errors, fragments, maximum frame length errors, receive errors, etc.) are flushed from the receive FIFO and not transferred to host memory.
- When reset:
The EMAC core operates in cut-through mode in the receive direction. Frames are transferred without waiting for the end of the frame.
(Default: 1’b0)
When operating in store-and-forward mode, the receive FIFO should be large enough to store at least one full-length frame. If jumbo frames are supported, the receive FIFO must accommodate one full jumbo frame.
2STRIP_FCSRW0Strip FCS
- When set:
The FCS field is stripped from the frame before it is transferred to host memory. The frame length field is updated to reflect the new length (excluding the FCS field).
- When reset:
The FCS field is not stripped and remains part of the frame transferred to host memory.
Regardless of the Strip FCS setting, FCS checking is performed on every frame unless Disable FCS Check is set. If the FCS field is checked, CRC error status is reported for every frame.
(Default: 1’b0)
1DISABLE_FCS_CHECKRW0Disable FCS Checking
- When set:
The EMAC core does not perform FCS checking on incoming frames, and the CRC error status is not set for any frames.
- When reset:
The EMAC core performs FCS checking on every incoming frame. Frames with CRC errors are reported and may be dropped.
(Default: 1’b0)
0RECEIVE_ENABLERW0Receive Enable
- When set:
The EMAC core’s receiver is enabled, allowing it to receive frames from the MII/GMII interface and transfer them into the receive FIFO.
- When reset:
The EMAC core’s receiver is disabled and does not receive any frames.
(Default: 1’b0)
+**Offset: 0x0108** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | Reserved | | | Reserved for future use | +| 6 | ACOOUNT_VLAN | RW | 0 | Account VLANs
According to the IEEE 802.3 specification:
- The minimum frame size (minFrameSize) for untagged frames is 64 bytes.
- The maximum frame size (maxFrameSize) for untagged frames is 1518 bytes.
For VLAN-tagged frames, the frame size values are adjusted to account for the 4-byte VLAN tag, increasing the maxFrameSize to 1522 bytes.
The EMAC core supports up to 3 VLAN tags per frame. It can dynamically adjust the maxFrameSize field to accommodate up to 12 bytes (3 VLAN tags) based on the number of VLAN tags present in the incoming frame. This prevents false maxFrameSize violation reporting for VLAN-tagged frames that exceed 1518 bytes but are within the adjusted limit (1518 + tag bytes).
- When set:
The maxFrameSize field is dynamically adjusted to account for up to 3 VLAN tags (12 bytes) based on the number of VLAN tags in the incoming frame.
- When reset:
The maxFrameSize field is not adjusted and remains fixed at the value programmed in the Maximum Frame Size Register.
(Default: 1’b0) | +| 5 | PASS_BAD_FRAMES | RW | 0 | Pass Bad Frames
When the EMAC core operates in Store-and-Forward mode, frames with errors (e.g., CRC errors, minimum frame length errors, fragments, maximum frame length errors, receive errors, etc.) are typically flushed from the receive FIFO and not transferred to host memory.
- When set:
Frames with errors are transferred to host memory, and the appropriate error status is indicated in the Frame Status field (written back in the TDES0 of the last descriptor).
- When reset:
Frames with errors are not transferred to host memory and are flushed from the receive FIFO.
(Default: 1’b0) | +| 4 | STATUS_FIRST | RW | 0 | Status First
When the EMAC core operates in Store-and-Forward mode, a frame is sent from the internal MAC to the DMA only after the entire frame is stored in the receive FIFO.
- When set:
The status field is transferred before the start of the packet (SOP).
- When reset:
The status field is transferred after the end of the packet (EOP).
For proper operation of the EMAC core, this bit should always be reset (1’b0). | +| 3 | STORE_FORWARD | RW | 0 | Store and Forward
- When set:
The EMAC core operates in store-and-forward mode in the receive direction. A frame is transferred to host memory only after the entire frame is stored in the receive FIFO. Frames with errors (e.g., CRC errors, minimum frame length errors, fragments, maximum frame length errors, receive errors, etc.) are flushed from the receive FIFO and not transferred to host memory.
- When reset:
The EMAC core operates in cut-through mode in the receive direction. Frames are transferred without waiting for the end of the frame.
(Default: 1’b0)
When operating in store-and-forward mode, the receive FIFO should be large enough to store at least one full-length frame. If jumbo frames are supported, the receive FIFO must accommodate one full jumbo frame. | +| 2 | STRIP_FCS | RW | 0 | Strip FCS
- When set:
The FCS field is stripped from the frame before it is transferred to host memory. The frame length field is updated to reflect the new length (excluding the FCS field).
- When reset:
The FCS field is not stripped and remains part of the frame transferred to host memory.
Regardless of the Strip FCS setting, FCS checking is performed on every frame unless Disable FCS Check is set. If the FCS field is checked, CRC error status is reported for every frame.
(Default: 1’b0) | +| 1 | DISABLE_FCS_CHECK | RW | 0 | Disable FCS Checking
- When set:
The EMAC core does not perform FCS checking on incoming frames, and the CRC error status is not set for any frames.
- When reset:
The EMAC core performs FCS checking on every incoming frame. Frames with CRC errors are reported and may be dropped.
(Default: 1’b0) | +| 0 | RECEIVE_ENABLE | RW | 0 | Receive Enable
- When set:
The EMAC core’s receiver is enabled, allowing it to receive frames from the MII/GMII interface and transfer them into the receive FIFO.
- When reset:
The EMAC core’s receiver is disabled and does not receive any frames.
(Default: 1’b0) | #### MAC Maximum Frame Size Register The MAC Maximum Frame Size Register is used to set the value of the MaxFrameSize field to check for MaxFrameLength violations. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x010C
BitsFieldTypeResetDescription
31:14ReservedReserved for future use
13:0
MAX_FRAME_SIZERW0x5EEMaximum Frame Size
This field defines the maximum frame size for untagged frames used to check MaxFrameLength violations.
- In store-and-forward mode:
Any frame exceeding this value is flushed from the receive FIFO unless Pass Bad Frames is set.
- When Pass Bad Frames is set:
Frames larger than this value are transferred to host memory with the MaxFrameLength Error bit set in the Frame Status, which is written back in RDES0 of the last descriptor.
(Default: 14’h05EE)
+**Offset: 0x010C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:14 | Reserved | | | Reserved for future use | +| 13:0 | MAX_FRAME_SIZE | RW | 0x5EE | Maximum Frame Size
This field defines the maximum frame size for untagged frames used to check MaxFrameLength violations.
- In store-and-forward mode:
Any frame exceeding this value is flushed from the receive FIFO unless Pass Bad Frames is set.
- When Pass Bad Frames is set:
Frames larger than this value are transferred to host memory with the MaxFrameLength Error bit set in the Frame Status, which is written back in RDES0 of the last descriptor.
(Default: 14’h05EE) | #### MAC Transmit Jabber Size Register @@ -2511,34 +947,12 @@ This register sets the jabber size limit for outgoing frames: - If an outgoing frame exceeds this size, it is truncated and marked with EOP-ERROR. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0110
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0TRANSMIT_JABBER_SIZERW0x600Transmit Jabber Size
This field defines the jabber size for outgoing (transmit) frames.
- If an outgoing frame exceeds this size, it is considered a Jabber Frame and is truncated at that point with EOP-ERROR.
- The PHY will then force an error code onto the line, preventing excessive frame transmission due to programming errors.
(Default: 16’h0600)
+**Offset: 0x0110** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | TRANSMIT_JABBER_SIZE | RW | 0x600 | Transmit Jabber Size
This field defines the jabber size for outgoing (transmit) frames.
- If an outgoing frame exceeds this size, it is considered a Jabber Frame and is truncated at that point with EOP-ERROR.
- The PHY will then force an error code onto the line, preventing excessive frame transmission due to programming errors.
(Default: 16’h0600) | #### MAC Receive Jabber Size Register @@ -2547,34 +961,12 @@ This register sets the jabber size limit for incoming frames: - If an incoming frame exceeds this size, it is truncated, and the Jabber Error is set in the Frame Status. - The remaining portion of the jabbered frame is received but ignored. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0114
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0RECEIVE_JABBER_SIZERW0x600Receive Jabber Size
This field defines the jabber size for incoming (receive) frames.
- If an incoming frame exceeds this size, it is considered a Jabber Frame and is truncated at that point.
- The Frame Status is updated with a Jabber Error, and the remaining portion of the frame is ignored.
- In store-and-forward mode: The frame is flushed from the receive FIFO unless Pass Bad Frames is set.
(Default: 16’h0600)
+**Offset: 0x0114** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | RECEIVE_JABBER_SIZE | RW | 0x600 | Receive Jabber Size
This field defines the jabber size for incoming (receive) frames.
- If an incoming frame exceeds this size, it is considered a Jabber Frame and is truncated at that point.
- The Frame Status is updated with a Jabber Error, and the remaining portion of the frame is ignored.
- In store-and-forward mode: The frame is flushed from the receive FIFO unless Pass Bad Frames is set.
(Default: 16’h0600) | #### MAC Address Control Register @@ -2594,123 +986,31 @@ This register controls MAC address checking for all incoming frames: - All frames, regardless of whether they pass or fail address filtering, are transferred to host memory. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0118
BitsFieldTypeResetDescription
31:9ReservedReserved for future use
8PROMISCUOUS_MODERW0Promiscuous Mode
- When set, the EMAC transfers all frames to host memory, regardless of the Destination Address.
- The Packet Status field will still reflect the result of the address filtering process.
(Default: 1’b0)
7INVERSE_MAC_ADDRESS4_ENABLERW0Inverse MAC Address #4 Enable
- When set:
Inverse filtering is performed on the Destination Address field using the value in MAC Address Register #4. Inverse filtering is only enabled when the MAC Address #4 Enable bit is set.
- When reset:
Normal address filtering is performed using MAC Address Register #4.
(Default: 1’b0)
6INVERSE_MAC_ADDRESS3_ENABLERW0Inverse MAC Address #3 Enable
- When set:
Inverse filtering is performed on the Destination Address field using the value in MAC Address Register #3. Inverse filtering is enabled only when the MAC Address #3 Enable bit is set.
- When reset:
Normal address filtering is performed using MAC Address Register #3.
(Default: 1’b0)
5INVERSE_MAC_ADDRESS2_ENABLERW0Inverse MAC Address #2 Enable
- When set:
Inverse filtering is performed on the Destination Address field using the value in MAC Address Register #2. Inverse filtering is enabled only when the MAC Address #2 Enable bit is set.
- When reset:
Normal address filtering is performed using MAC Address Register #2.
(Default: 1’b0)
4INVERSE_MAC_ADDRESS1_ENABLERW0Inverse MAC Address #1 Enable
- When set:
Inverse filtering is performed on the Destination Address field using the value in MAC Address Register #1. Inverse filtering is enabled only when the MAC Address #1 Enable bit is set.
- When reset:
Normal address filtering is performed using MAC Address Register #1.
(Default: 1’b0)
3MAC_ADDRESS4_ENABLERW0MAC Address #4 Enable
- When set:
The MAC Address Register #4 is used to perform address filtering on the Destination Address field of all incoming frames.
- When reset:
The MAC Address Register #4 is not used for address filtering.
(Default: 1’b0)
2MAC_ADDRESS3_ENABLERW0MAC Address #3 Enable
- When set:
The MAC Address Register #3 is used to perform address filtering on the Destination Address field of all incoming frames.
- When reset:
The MAC Address Register #3 is not used for address filtering.
(Default: 1’b0)
1MAC_ADDRESS2_ENABLERW0MAC Address #2 Enable
- When set:
The MAC Address Register #2 is used to perform address filtering on the Destination Address field of all incoming frames.
- When reset:
The MAC Address Register #2 is not used for address filtering.
(Default: 1’b0)
0MAC_ADDRESS1_ENABLERW0MAC Address #1 Enable
- When set:
The MAC Address Register #1 is used to perform address filtering on the Destination Address field of all incoming frames.
- When reset:
The MAC Address Register #1 is not used for address filtering.
(Default: 1’b0)
+**Offset: 0x0118** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:9 | Reserved | | | Reserved for future use | +| 8 | PROMISCUOUS_MODE | RW | 0 | Promiscuous Mode
- When set, the EMAC transfers all frames to host memory, regardless of the Destination Address.
- The Packet Status field will still reflect the result of the address filtering process.
(Default: 1’b0) | +| 7 | INVERSE_MAC_ADDRESS4_ENABLE | RW | 0 | Inverse MAC Address #4 Enable
- When set:
Inverse filtering is performed on the Destination Address field using the value in MAC Address Register #4. Inverse filtering is only enabled when the MAC Address #4 Enable bit is set.
- When reset:
Normal address filtering is performed using MAC Address Register #4.
(Default: 1’b0) | +| 6 | INVERSE_MAC_ADDRESS3_ENABLE | RW | 0 | Inverse MAC Address #3 Enable
- When set:
Inverse filtering is performed on the Destination Address field using the value in MAC Address Register #3. Inverse filtering is enabled only when the MAC Address #3 Enable bit is set.
- When reset:
Normal address filtering is performed using MAC Address Register #3.
(Default: 1’b0) | +| 5 | INVERSE_MAC_ADDRESS2_ENABLE | RW | 0 | Inverse MAC Address #2 Enable
- When set:
Inverse filtering is performed on the Destination Address field using the value in MAC Address Register #2. Inverse filtering is enabled only when the MAC Address #2 Enable bit is set.
- When reset:
Normal address filtering is performed using MAC Address Register #2.
(Default: 1’b0) | +| 4 | INVERSE_MAC_ADDRESS1_ENABLE | RW | 0 | Inverse MAC Address #1 Enable
- When set:
Inverse filtering is performed on the Destination Address field using the value in MAC Address Register #1. Inverse filtering is enabled only when the MAC Address #1 Enable bit is set.
- When reset:
Normal address filtering is performed using MAC Address Register #1.
(Default: 1’b0) | +| 3 | MAC_ADDRESS4_ENABLE | RW | 0 | MAC Address #4 Enable
- When set:
The MAC Address Register #4 is used to perform address filtering on the Destination Address field of all incoming frames.
- When reset:
The MAC Address Register #4 is not used for address filtering.
(Default: 1’b0) | +| 2 | MAC_ADDRESS3_ENABLE | RW | 0 | MAC Address #3 Enable
- When set:
The MAC Address Register #3 is used to perform address filtering on the Destination Address field of all incoming frames.
- When reset:
The MAC Address Register #3 is not used for address filtering.
(Default: 1’b0) | +| 1 | MAC_ADDRESS2_ENABLE | RW | 0 | MAC Address #2 Enable
- When set:
The MAC Address Register #2 is used to perform address filtering on the Destination Address field of all incoming frames.
- When reset:
The MAC Address Register #2 is not used for address filtering.
(Default: 1’b0) | +| 0 | MAC_ADDRESS1_ENABLE | RW | 0 | MAC Address #1 Enable
- When set:
The MAC Address Register #1 is used to perform address filtering on the Destination Address field of all incoming frames.
- When reset:
The MAC Address Register #1 is not used for address filtering.
(Default: 1’b0) | #### MAC MDIO Clock Division Control Register This register adjusts the ratio between the MDC (Management Data Clock) and the host clock, which can either be the AHB clock or the AXI clock. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x011C
BitsFieldTypeResetDescription
31:8ReservedReserved for future use
7:0MDC_CLK_DIV_CONTROLRW0x40MDC Clock Division Control
This field defines the ratio between the MDC Clock and the host clock.
- For the default value of 64, the MDC Clock is high for 32 host clock periods and low for 32 host clock periods.
- Only even values are supported for this field, with a maximum value of 8’hFE.
(Default: 8’h40)
+**Offset: 0x011C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | | | Reserved for future use | +| 7:0 | MDC_CLK_DIV_CONTROL | RW | 0x40 | MDC Clock Division Control
This field defines the ratio between the MDC Clock and the host clock.
- For the default value of 64, the MDC Clock is high for 32 host clock periods and low for 32 host clock periods.
- Only even values are supported for this field, with a maximum value of 8’hFE.
(Default: 8’h40) | #### MAC Address#1 High Register @@ -2721,41 +1021,13 @@ The remaining bytes of the 48-bit MAC Address #1 are stored in the: - MAC Address #1 Medium Register - MAC Address #1 Low Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0120
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_ADDRESS1_02_BYTERW0x0MAC Address #1 Second Byte
This field contains the second byte of MAC Address #1 in Canonical Format.
It is the second byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
7:0MAC_ADDRESS1_01_BYTERW0x0MAC Address #1 First Byte
This field contains the first byte of MAC Address #1 in Canonical Format.
It is the first byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
+**Offset: 0x0120** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_ADDRESS1_02_BYTE | RW | 0x0 | MAC Address #1 Second Byte
This field contains the second byte of MAC Address #1 in Canonical Format.
It is the second byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | +| 7:0 | MAC_ADDRESS1_01_BYTE | RW | 0x0 | MAC Address #1 First Byte
This field contains the first byte of MAC Address #1 in Canonical Format.
It is the first byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | #### MAC Address#1 Med Register @@ -2766,41 +1038,13 @@ The remaining bytes of the 48-bit MAC Address #1 are stored in the: - MAC Address#1 High Register - MAC Address#1 Low Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0124
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_ADDRESS1_04_BYTERW0x0MAC Address#1 Fourth Byte
This byte contains the fourth byte of MAC Address #1 in Canonical Format.
It is the fourth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
7:0MAC_ADDRESS1_03_BYTERW0x0MAC Address#1 Third Byte
This byte contains the third byte of MAC Address #1 in Canonical Format.
It is the third byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
+**Offset: 0x0124** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_ADDRESS1_04_BYTE | RW | 0x0 | MAC Address#1 Fourth Byte
This byte contains the fourth byte of MAC Address #1 in Canonical Format.
It is the fourth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | +| 7:0 | MAC_ADDRESS1_03_BYTE | RW | 0x0 | MAC Address#1 Third Byte
This byte contains the third byte of MAC Address #1 in Canonical Format.
It is the third byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | #### MAC Address#1 Low Register @@ -2811,41 +1055,13 @@ The remaining bytes of the 48-bit MAC Address#1 are stored in the: - MAC Address#1 High Register - MAC Address#1 Medium Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0128
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_ADDRESS1_05_BYTERW0x0MAC Address#1 Fifth Byte
This byte contains the fifth byte of MAC Address#1 in Canonical Format.
It is the fifth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
7:0MAC_ADDRESS_06_SIXTH_BYTERW0x0MAC Address#1 Sixth Byte
This byte contains the sixth byte of MAC Address#1 in Canonical Format.
It is the sixth (last) byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
+**Offset: 0x0128** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_ADDRESS1_05_BYTE | RW | 0x0 | MAC Address#1 Fifth Byte
This byte contains the fifth byte of MAC Address#1 in Canonical Format.
It is the fifth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | +| 7:0 | MAC_ADDRESS_06_SIXTH_BYTE | RW | 0x0 | MAC Address#1 Sixth Byte
This byte contains the sixth byte of MAC Address#1 in Canonical Format.
It is the sixth (last) byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | #### MAC Address#2 High Register @@ -2856,41 +1072,13 @@ The remaining bytes of the 48-bit MAC Address#2 are stored in the: - MAC Address#2 Medium Register - MAC Address#2 Low Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x012C
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_ADDRESS2_02_BYTERW
0x0MAC Address#2 Second Byte
This field contains the second byte of MAC Address#2 in Canonical Format.
It is the second byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
7:0MAC_ADDRESS2_01_BYTERW0x0MAC Address#2 First Byte
This field contains the first byte of MAC Address#2 in Canonical Format.
It is the first byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
+**Offset: 0x012C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_ADDRESS2_02_BYTE | RW | 0x0 | MAC Address#2 Second Byte
This field contains the second byte of MAC Address#2 in Canonical Format.
It is the second byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | +| 7:0 | MAC_ADDRESS2_01_BYTE | RW | 0x0 | MAC Address#2 First Byte
This field contains the first byte of MAC Address#2 in Canonical Format.
It is the first byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | #### MAC Address#2 Med Register @@ -2901,41 +1089,13 @@ The remaining bytes of the 48-bit MAC Address#2 are stored in the: - MAC Address#2 High Register - MAC Address#2 Low Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0130
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_ADDRESS2_04_BYTERW
0x0MAC Address#2 Fourth Byte
This byte contains the fourth byte of MAC Address#2 in Canonical Format.
It is the fourth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
7:0MAC_ADDRESS2_03_BYTERW0x0MAC Address#2 Third Byte
This byte contains the third byte of MAC Address#2 in Canonical Format.
It is the third byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
+**Offset: 0x0130** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_ADDRESS2_04_BYTE | RW | 0x0 | MAC Address#2 Fourth Byte
This byte contains the fourth byte of MAC Address#2 in Canonical Format.
It is the fourth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | +| 7:0 | MAC_ADDRESS2_03_BYTE | RW | 0x0 | MAC Address#2 Third Byte
This byte contains the third byte of MAC Address#2 in Canonical Format.
It is the third byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | #### MAC Address#2 Low Register @@ -2946,41 +1106,13 @@ The remaining bytes of the 48-bit MAC Address #2 are stored in the: - MAC Address#2 High Register - MAC Address#2 Medium Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0134
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_ADDRESS2_05_BYTE
RW0x0MAC Address#2 Fifth Byte
This byte contains the fifth byte of MAC Address#2 in Canonical Format.
It is the fifth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
7:0MAC_ADDRESS2_06_BYTERW0x0MAC Address#2 Sixth Byte
This byte contains the sixth byte of MAC Address#2 in Canonical Format.
It is the sixth (last) byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
+**Offset: 0x0134** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_ADDRESS2_05_BYTE | RW | 0x0 | MAC Address#2 Fifth Byte
This byte contains the fifth byte of MAC Address#2 in Canonical Format.
It is the fifth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | +| 7:0 | MAC_ADDRESS2_06_BYTE | RW | 0x0 | MAC Address#2 Sixth Byte
This byte contains the sixth byte of MAC Address#2 in Canonical Format.
It is the sixth (last) byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | #### MAC Address#3 High Register @@ -2991,41 +1123,13 @@ The remaining bytes of the 48-bit MAC Address#3 are stored in the: - MAC Address#3 Medium Register - MAC Address#3 Low Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0138
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_ADDRESS3_02_BYTERW
0x0MAC Address#3 Second Byte
This field contains the second byte of MAC Address#3 in Canonical Format.
It is the second byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
7:0MAC_ADDRESS3_01_BYTERW0x0
MAC Address#3 First Byte
This field contains the first byte of MAC Address#3 in Canonical Format.
It is the first byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
+**Offset: 0x0138** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_ADDRESS3_02_BYTE | RW | 0x0 | MAC Address#3 Second Byte
This field contains the second byte of MAC Address#3 in Canonical Format.
It is the second byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | +| 7:0 | MAC_ADDRESS3_01_BYTE | RW | 0x0 | MAC Address#3 First Byte
This field contains the first byte of MAC Address#3 in Canonical Format.
It is the first byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | #### MAC Address#3 Med Register @@ -3036,41 +1140,13 @@ The remaining bytes of the 48-bit MAC Address#3 are stored in the: - MAC Address#3 High Register - MAC Address#3 Low Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x013C
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_ADDRESS3_04_BYTERW0x0MAC Address#3 Fourth Byte
This byte contains the fourth byte of MAC Address#3 in Canonical Format.
It is the fourth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
7:0MAC_ADDRESS3_03_BYTERW0x0MAC Address#3 Third Byte
This byte contains the third byte of MAC Address#3 in Canonical Format.
It is the third byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
+**Offset: 0x013C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_ADDRESS3_04_BYTE | RW | 0x0 | MAC Address#3 Fourth Byte
This byte contains the fourth byte of MAC Address#3 in Canonical Format.
It is the fourth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | +| 7:0 | MAC_ADDRESS3_03_BYTE | RW | 0x0 | MAC Address#3 Third Byte
This byte contains the third byte of MAC Address#3 in Canonical Format.
It is the third byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | #### MAC Address#3 Low Register @@ -3081,41 +1157,13 @@ The remaining bytes of the 48-bit MAC Address#3 are stored in the: - MAC Address#3 High Register - MAC Address#3 Medium Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0140
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_ADDRESS3_05_BYTERW0x0MAC Address#3 Fifth Byte
This byte contains the fifth byte of MAC Address#3 in Canonical Format.
It is the fifth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
7:0MAC_ADDRESS3_06_BYTERW0x0MAC Address#3 Sixth Byte
This byte contains the sixth byte of MAC Address#3 in Canonical Format.
It is the sixth (last) byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
+**Offset: 0x0140** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_ADDRESS3_05_BYTE | RW | 0x0 | MAC Address#3 Fifth Byte
This byte contains the fifth byte of MAC Address#3 in Canonical Format.
It is the fifth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | +| 7:0 | MAC_ADDRESS3_06_BYTE | RW | 0x0 | MAC Address#3 Sixth Byte
This byte contains the sixth byte of MAC Address#3 in Canonical Format.
It is the sixth (last) byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | #### MAC Address#4 High Register @@ -3126,41 +1174,13 @@ The remaining bytes of the 48-bit MAC Address #4 are stored in the: - MAC Address#4 Medium Register - MAC Address#4 Low Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0144
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_ADDRESS4_02_BYTERW0x0
MAC Address#4 Second Byte
This field contains the second byte of MAC Address#4 in Canonical Format.
It is the second byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
7:0MAC_ADDRESS4_01_BYTERW0x0MAC Address #4 First Byte
This field contains the first byte of MAC Address#4 in Canonical Format.
It is the first byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
+**Offset: 0x0144** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_ADDRESS4_02_BYTE | RW | 0x0 | MAC Address#4 Second Byte
This field contains the second byte of MAC Address#4 in Canonical Format.
It is the second byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | +| 7:0 | MAC_ADDRESS4_01_BYTE | RW | 0x0 | MAC Address #4 First Byte
This field contains the first byte of MAC Address#4 in Canonical Format.
It is the first byte transmitted on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | #### MAC Address#4 Med Register @@ -3171,41 +1191,13 @@ The remaining bytes of the 48-bit MAC Address#4 are stored in the: - MAC Address#4 High Register - MAC Address#4 Low Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0148
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_ADDRESS4_04_BYTERW0x0MAC Address#4 Fourth Byte
This byte contains the fourth byte of MAC Address#4 in Canonical Format.
It is the fourth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
7:0MAC_ADDRESS4_03_BYTERW0x0MAC Address#4 Third Byte
This byte contains the third byte of MAC Address#4 in Canonical Format.
It is the third byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
+**Offset: 0x0148** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_ADDRESS4_04_BYTE | RW | 0x0 | MAC Address#4 Fourth Byte
This byte contains the fourth byte of MAC Address#4 in Canonical Format.
It is the fourth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | +| 7:0 | MAC_ADDRESS4_03_BYTE | RW | 0x0 | MAC Address#4 Third Byte
This byte contains the third byte of MAC Address#4 in Canonical Format.
It is the third byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | #### MAC Address#4 Low Register @@ -3216,41 +1208,13 @@ The remaining bytes of the 48-bit MAC Address#4 are stored in the: - MAC Address#4 High Register - MAC Address#4 Medium Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x014C
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_ADDRESS4_05_BYTERW0x0MAC Address#4 Fifth Byte
This byte contains the fifth byte of MAC Address#4 in Canonical Format.
It is the fifth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
7:0MAC_ADDRESS4_06_BYTERW0x0
MAC Address#4 Sixth Byte
This byte contains the sixth byte of MAC Address#4 in Canonical Format.
It is the sixth (last) byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0)
+**Offset: 0x014C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_ADDRESS4_05_BYTE | RW | 0x0 | MAC Address#4 Fifth Byte
This byte contains the fifth byte of MAC Address#4 in Canonical Format.
It is the fifth byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | +| 7:0 | MAC_ADDRESS4_06_BYTE | RW | 0x0 | MAC Address#4 Sixth Byte
This byte contains the sixth byte of MAC Address#4 in Canonical Format.
It is the sixth (last) byte that goes out on the line as part of the Destination Address (DA) field.
(Default: 8’b0) | #### MAC Multicast Hash Table#1 Register @@ -3265,34 +1229,12 @@ Hash Filtering Process: - A value of 6’b111111 selects bit [63] of the hash table. - When a multicast frame is hashed into the table, if the corresponding bit is '1', the frame is accepted. If it is '0', the frame is rejected. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0150
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0HASH_TABLE_15_TO_0RW0x0Hash Table Bits [15:0]
These bits represent the lower 16 bits of the Multi-Cast Hash Table.
- When a bit is set to '1', the corresponding multicast frame hashed to that bit is accepted and forwarded to the host.
- If the bit is set to '0', the multicast frame is dropped.
(Default: 16'b0)
+**Offset: 0x0150** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | HASH_TABLE_15_TO_0 | RW | 0x0 | Hash Table Bits [15:0]
These bits represent the lower 16 bits of the Multi-Cast Hash Table.
- When a bit is set to '1', the corresponding multicast frame hashed to that bit is accepted and forwarded to the host.
- If the bit is set to '0', the multicast frame is dropped.
(Default: 16'b0) | #### MAC Multicast Hash Table#2 Register @@ -3307,34 +1249,12 @@ Hash Filtering Process: - A value of 6’b111111 selects bit [63] of the hash table. - When a multicast frame is hashed into the table, if the corresponding bit is '1', the frame is accepted. If it is '0', the frame is rejected. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0154
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0HASH_TABLE_31_TO_16RW0x0Hash Table Bits [31:16]
These bits represent the lower 16 bits of the Multi-Cast Hash Table.
- When a bit is set to '1', the corresponding multicast frame hashed to that bit is accepted and forwarded to the host.
- If the bit is set to '0', the multicast frame is dropped.
(Default: 16'b0)
+**Offset: 0x0154** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | HASH_TABLE_31_TO_16 | RW | 0x0 | Hash Table Bits [31:16]
These bits represent the lower 16 bits of the Multi-Cast Hash Table.
- When a bit is set to '1', the corresponding multicast frame hashed to that bit is accepted and forwarded to the host.
- If the bit is set to '0', the multicast frame is dropped.
(Default: 16'b0) | #### MAC Multicast Hash Table#3 Register @@ -3349,34 +1269,12 @@ Hash Filtering Process: - A value of 6’b111111 selects bit [63] of the hash table. - When a multicast frame is hashed into the table, if the corresponding bit is '1', the frame is accepted. If it is '0', the frame is rejected. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0158
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0HASH_TABLE_47_TO_32RW0x0Hash Table Bits [47:32]
These bits represent the lower 16 bits of the Multi-Cast Hash Table.
- When a bit is set to '1', the corresponding multicast frame hashed to that bit is accepted and forwarded to the host.
- If the bit is set to '0', the multicast frame is dropped.
(Default: 16'b0)
+**Offset: 0x0158** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | HASH_TABLE_47_TO_32 | RW | 0x0 | Hash Table Bits [47:32]
These bits represent the lower 16 bits of the Multi-Cast Hash Table.
- When a bit is set to '1', the corresponding multicast frame hashed to that bit is accepted and forwarded to the host.
- If the bit is set to '0', the multicast frame is dropped.
(Default: 16'b0) | #### MAC Multicast Hash Table#4 Register @@ -3391,34 +1289,12 @@ Hash Filtering Process: - A value of 6’b111111 selects bit [63] of the hash table. - When a multicast frame is hashed into the table, if the corresponding bit is '1', the frame is accepted. If it is '0', the frame is rejected. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x015C
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0HASH_TABLE_63_TO_48Hash Table Bits [63:48]
These bits represent the lower 16 bits of the Multi-Cast Hash Table.
- When a bit is set to '1', the corresponding multicast frame hashed to that bit is accepted and forwarded to the host.
- If the bit is set to '0', the multicast frame is dropped.
(Default: 16'b0)
+**Offset: 0x015C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | HASH_TABLE_63_TO_48 | | | Hash Table Bits [63:48]
These bits represent the lower 16 bits of the Multi-Cast Hash Table.
- When a bit is set to '1', the corresponding multicast frame hashed to that bit is accepted and forwarded to the host.
- If the bit is set to '0', the multicast frame is dropped.
(Default: 16'b0) | #### MAC Flow-Control Register @@ -3427,83 +1303,19 @@ This register manages Flow-Control features, including PAUSE frame generation an - In **Full-Duplex mode**, Flow-Control is enabled. - In **Half-Duplex mode**, Flow-Control is disabled, and received PAUSE frames are treated as normal data frames without decoding. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0160
BitsFieldTypeResetDescription
15:8ENABLE_PRIORITIESRW0x0Enabled Priorities
This field specifies which priorities are active for Priority PAUSE flow control generation and detection.
- The XOFF/XON control signals from user logic are monitored only for the enabled priorities.
- During reception, only the enabled priorities are considered for the Time-Vector field.
(Default: 8'b0)
7ReservedReserved for future use
6PRIORITY_PAUSE_DECODE_ENABLERW0Priority PAUSE Decode Enable
This field enables or disables Priority PAUSE Flow-Control in the EMAC Core.
- When enabled (set to '1'):
1. The EMAC Core decodes incoming frames for Priority PAUSE Control Frames, as per IEEE 802.3.
2. If a valid Priority PAUSE Control Frame is received, the timers for enabled priorities are extracted.
3. A corresponding XOFF notification is sent to the user logic while the counter remains nonzero.
- When disabled (reset to '0'):
1. The EMAC Core does not decode Priority PAUSE Control Frames.
> Note. This bit is valid only in Full-Duplex mode.
(Default: 1’b0)
5PRIORITY_FC_GENERATION_ENABLERW0Priority Flow-Control Generation Enable
This field enables or disables the transmission of Priority PAUSE Control Frames by the EMAC Core.
- When enabled (set to '1'):
1. The EMAC Core transmits Priority PAUSE Control Frames, which can be triggered either by software control or external Priority XON/XOFF controls.
2. The parameters for the generated Priority PAUSE Frame are controlled independently.
- When disabled (reset to '0'):
1. The EMAC Core does not generate any Priority PAUSE Control Frames.
> Note.
> - This bit is valid only in Full-Duplex mode.
> - PAUSE and Priority PAUSE functionalities are mutually exclusive, so only one should be enabled at a time.
(Default: 1’b0)
4BLOCK_PAUSE_FRAMESRW0Block Pause Frames
This field controls whether received PAUSE Control Frames are forwarded to the Host Memory.
- When enabled (set to '1'):
1. The EMAC Core decodes the received PAUSE Control Frames but does not forward them to Host Memory.
2. These frames are purged from the Receive FIFO.
- When disabled (reset to '0'):
1. The received PAUSE Control Frames are decoded and transmitted to the Host Memory like normal data frames.
(Default: 1’b0)
3MULTICAST_MODERW0Flow-Control Multi-Cast Mode
This field determines the Destination Address (DA) used in generated PAUSE Flow Control frames.
- When set:
1. The DA field in the PAUSE Flow Control frames is set to the reserved multicast address: 01:80:C2:00:00:01
- When reset:
1. The DA field uses the MAC Flow-Control Destination Address stored in the High/Med/Low Registers.
2. This address is typically the unicast address of the device at the other end of the cable.
(Default: 1’b0)
2AUTO_FC_GENERATION_ENABLERW0Auto Flow Control Generation Enable
- When set:
The EMAC core generates automatic PAUSE control frames when the receive FIFO fill level crosses the configured high or low threshold values (after debouncing).
1. If the receive FIFO fill level exceeds the high threshold, a PAUSE control frame is generated with the PauseTime value set to the MAC Auto High Pause Time Register.
2. If the receive FIFO fill level falls below the low threshold, a PAUSE control frame is generated with the PauseTime value set to the MAC Auto Low Pause Time Register.
- When reset:
Automatic generation of PAUSE control frames is disabled.
(Default: 1’b0)
1FC_GENERATION_ENABLERW0Flow-Control Generation Enable
This field controls whether the EMAC Core can transmit PAUSE Control frames.
- When set:
1. The EMAC Core transmits PAUSE Control frames in one of the following ways:
- Software control
- Auto-generation mode (when the Receive FIFO fill level crosses the High or Low Threshold)
- External XON/XOFF controls
2. The parameters for PAUSE frame generation are managed separately.
- When reset:
1. The EMAC Core does not generate PAUSE Control frames.
> Note. This feature is only valid in Full-Duplex mode.
(Default: 1’b0)
0FC_DECODE_ENABLERW0Flow-Control Decode Enable
This field controls whether the EMAC Core processes incoming PAUSE Control frames.
- When set:
1. The EMAC Core decodes PAUSE Control frames according to the IEEE 802.3 Specification.
2. If a valid PAUSE Control frame is received, the EMAC Core halts user data transmission for the duration specified in the PAUSE_TIME field.
- When reset:
1. The Flow-Control Operation in the EMAC Core is disabled and the Core does not decode the frames for PAUSE Control Frames
> Note. This feature is only valid in Full-Duplex mode.
(Default: 1’b0)
+**Offset: 0x0160** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 15:8 | ENABLE_PRIORITIES | RW | 0x0 | Enabled Priorities
This field specifies which priorities are active for Priority PAUSE flow control generation and detection.
- The XOFF/XON control signals from user logic are monitored only for the enabled priorities.
- During reception, only the enabled priorities are considered for the Time-Vector field.
(Default: 8'b0) | +| 7 | Reserved | | | Reserved for future use | +| 6 | PRIORITY_PAUSE_DECODE_ENABLE | RW | 0 | Priority PAUSE Decode Enable
This field enables or disables Priority PAUSE Flow-Control in the EMAC Core.
- When enabled (set to '1'):
1. The EMAC Core decodes incoming frames for Priority PAUSE Control Frames, as per IEEE 802.3.
2. If a valid Priority PAUSE Control Frame is received, the timers for enabled priorities are extracted.
3. A corresponding XOFF notification is sent to the user logic while the counter remains nonzero.
- When disabled (reset to '0'):
1. The EMAC Core does not decode Priority PAUSE Control Frames.
> Note. This bit is valid only in Full-Duplex mode.
(Default: 1’b0) | +| 5 | PRIORITY_FC_GENERATION_ENABLE | RW | 0 | Priority Flow-Control Generation Enable
This field enables or disables the transmission of Priority PAUSE Control Frames by the EMAC Core.
- When enabled (set to '1'):
1. The EMAC Core transmits Priority PAUSE Control Frames, which can be triggered either by software control or external Priority XON/XOFF controls.
2. The parameters for the generated Priority PAUSE Frame are controlled independently.
- When disabled (reset to '0'):
1. The EMAC Core does not generate any Priority PAUSE Control Frames.
> Note.
> - This bit is valid only in Full-Duplex mode.
> - PAUSE and Priority PAUSE functionalities are mutually exclusive, so only one should be enabled at a time.
(Default: 1’b0) | +| 4 | BLOCK_PAUSE_FRAMES | RW | 0 | Block Pause Frames
This field controls whether received PAUSE Control Frames are forwarded to the Host Memory.
- When enabled (set to '1'):
1. The EMAC Core decodes the received PAUSE Control Frames but does not forward them to Host Memory.
2. These frames are purged from the Receive FIFO.
- When disabled (reset to '0'):
1. The received PAUSE Control Frames are decoded and transmitted to the Host Memory like normal data frames.
(Default: 1’b0) | +| 3 | MULTICAST_MODE | RW | 0 | Flow-Control Multi-Cast Mode
This field determines the Destination Address (DA) used in generated PAUSE Flow Control frames.
- When set:
1. The DA field in the PAUSE Flow Control frames is set to the reserved multicast address: 01:80:C2:00:00:01
- When reset:
1. The DA field uses the MAC Flow-Control Destination Address stored in the High/Med/Low Registers.
2. This address is typically the unicast address of the device at the other end of the cable.
(Default: 1’b0) | +| 2 | AUTO_FC_GENERATION_ENABLE | RW | 0 | Auto Flow Control Generation Enable
- When set:
The EMAC core generates automatic PAUSE control frames when the receive FIFO fill level crosses the configured high or low threshold values (after debouncing).
1. If the receive FIFO fill level exceeds the high threshold, a PAUSE control frame is generated with the PauseTime value set to the MAC Auto High Pause Time Register.
2. If the receive FIFO fill level falls below the low threshold, a PAUSE control frame is generated with the PauseTime value set to the MAC Auto Low Pause Time Register.
- When reset:
Automatic generation of PAUSE control frames is disabled.
(Default: 1’b0) | +| 1 | FC_GENERATION_ENABLE | RW | 0 | Flow-Control Generation Enable
This field controls whether the EMAC Core can transmit PAUSE Control frames.
- When set:
1. The EMAC Core transmits PAUSE Control frames in one of the following ways:
- Software control
- Auto-generation mode (when the Receive FIFO fill level crosses the High or Low Threshold)
- External XON/XOFF controls
2. The parameters for PAUSE frame generation are managed separately.
- When reset:
1. The EMAC Core does not generate PAUSE Control frames.
> Note. This feature is only valid in Full-Duplex mode.
(Default: 1’b0) | +| 0 | FC_DECODE_ENABLE | RW | 0 | Flow-Control Decode Enable
This field controls whether the EMAC Core processes incoming PAUSE Control frames.
- When set:
1. The EMAC Core decodes PAUSE Control frames according to the IEEE 802.3 Specification.
2. If a valid PAUSE Control frame is received, the EMAC Core halts user data transmission for the duration specified in the PAUSE_TIME field.
- When reset:
1. The Flow-Control Operation in the EMAC Core is disabled and the Core does not decode the frames for PAUSE Control Frames
> Note. This feature is only valid in Full-Duplex mode.
(Default: 1’b0) | #### MAC Flow-Control PAUSE Frame Generate Register @@ -3515,41 +1327,13 @@ This register allows to trigger the generation of **PAUSE Control Frames**. - **Initiates the creation of a PAUSE Control Frame** - **Indicate** when the PAUSE Frame generation is complete. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0164
BitsFieldTypeResetDescription
31:2ReservedReserved for future use
1GENERATE_PRIORITY_PAUSE_FRAMERW0Generate Priority PAUSE Frame
This bit is set by the software to instruct the EMAC Core to generate a Priority PAUSE Control Frame.
- Before setting this bit, software must ensure it is cleared.
- Once set, the EMAC Core attempts to generate the frame immediately:
1. If the MAC Transmitter is idle, the frame is generated right away.
2. If the MAC Transmitter is busy transmitting a user data frame, the Priority PAUSE Control Frame is queued. It will be transmitted once the current frame completes and the IFG is met.
- The software must continuously monitor this bit to check if the Priority PAUSE Frame transmission is complete.
- Once the frame is successfully transmitted, the EMAC Core automatically clears this bit.
> Note.
> - The generated Priority PAUSE Frame is based on the Enabled Priorities.
> - This bit is valid only in Full-Duplex mode and when the Priority PAUSE Flow-Control Generation Enable bit in the MAC Flow-Control Register is set.
(Default: 1’b0)
0GENERATE_PAUSE_FRAME
RW
0Generate PAUSE Frame
This bit is set by the software to instruct the EMAC Core to generate a PAUSE Control Frame.
- Before setting this bit, the software must ensure it is cleared.
- Once set, the EMAC Core attempts to generate the frame immediately:
1. If the MAC Transmitter is idle, the frame is generated right away.
2. If the MAC Transmitter is busy transmitting a user data frame, the PAUSE Control Frame is queued. It will be transmitted once the current frame completes and the IFG is met.
- The software must continuously monitor this bit to check if the PAUSE Frame transmission is complete.
- Once the frame is successfully transmitted, the EMAC Core automatically clears this bit.
> Note.
> This bit is valid only in Full-Duplex mode and when the Flow-Control Generation Enable bit in the MAC Flow-Control Register is set.
(Default: 1’b0)
+**Offset: 0x0164** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | | | Reserved for future use | +| 1 | GENERATE_PRIORITY_PAUSE_FRAME | RW | 0 | Generate Priority PAUSE Frame
This bit is set by the software to instruct the EMAC Core to generate a Priority PAUSE Control Frame.
- Before setting this bit, software must ensure it is cleared.
- Once set, the EMAC Core attempts to generate the frame immediately:
1. If the MAC Transmitter is idle, the frame is generated right away.
2. If the MAC Transmitter is busy transmitting a user data frame, the Priority PAUSE Control Frame is queued. It will be transmitted once the current frame completes and the IFG is met.
- The software must continuously monitor this bit to check if the Priority PAUSE Frame transmission is complete.
- Once the frame is successfully transmitted, the EMAC Core automatically clears this bit.
> Note.
> - The generated Priority PAUSE Frame is based on the Enabled Priorities.
> - This bit is valid only in Full-Duplex mode and when the Priority PAUSE Flow-Control Generation Enable bit in the MAC Flow-Control Register is set.
(Default: 1’b0) | +| 0 | GENERATE_PAUSE_FRAME | RW | 0 | Generate PAUSE Frame
This bit is set by the software to instruct the EMAC Core to generate a PAUSE Control Frame.
- Before setting this bit, the software must ensure it is cleared.
- Once set, the EMAC Core attempts to generate the frame immediately:
1. If the MAC Transmitter is idle, the frame is generated right away.
2. If the MAC Transmitter is busy transmitting a user data frame, the PAUSE Control Frame is queued. It will be transmitted once the current frame completes and the IFG is met.
- The software must continuously monitor this bit to check if the PAUSE Frame transmission is complete.
- Once the frame is successfully transmitted, the EMAC Core automatically clears this bit.
> Note.
> This bit is valid only in Full-Duplex mode and when the Flow-Control Generation Enable bit in the MAC Flow-Control Register is set.
(Default: 1’b0) | #### MAC Flow-Control Source Address High Register @@ -3561,41 +1345,13 @@ The MAC Flow-Control Source Address High Register stores the first two bytes of - MAC Flow-Control Source Address Med Register (middle two bytes). - MAC Flow-Control Source Address Low Register (last two bytes). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0168
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_FC_SOURCE_ADDRESS_02_BYTERW0x0MAC Flow-Control Source Address Second Byte
This register holds the second byte of the Source Address in Canonical Format, used in generated PAUSE and Priority PAUSE Control Frames.
- It represents the second byte transmitted on the Ethernet line as part of the Source Address (SA) field in Flow-Control Frames.
(Default : 8’b0)
7:0MAC_FC_SOURCE_ADDRESS_01_BYTERW0x0MAC Flow-Control Source Address First Byte
This register holds the first byte of the Source Address in Canonical Format, used in generated PAUSE and Priority PAUSE Control Frames.
- It represents the first byte transmitted on the Ethernet line as part of the Source Address (SA) field in Flow-Control Frames.
(Default : 8’b0)
+**Offset: 0x0168** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_FC_SOURCE_ADDRESS_02_BYTE | RW | 0x0 | MAC Flow-Control Source Address Second Byte
This register holds the second byte of the Source Address in Canonical Format, used in generated PAUSE and Priority PAUSE Control Frames.
- It represents the second byte transmitted on the Ethernet line as part of the Source Address (SA) field in Flow-Control Frames.
(Default: 8’b0) | +| 7:0 | MAC_FC_SOURCE_ADDRESS_01_BYTE | RW | 0x0 | MAC Flow-Control Source Address First Byte
This register holds the first byte of the Source Address in Canonical Format, used in generated PAUSE and Priority PAUSE Control Frames.
- It represents the first byte transmitted on the Ethernet line as part of the Source Address (SA) field in Flow-Control Frames.
(Default: 8’b0) | #### MAC Flow-Control Source Address Med Register @@ -3607,41 +1363,13 @@ The MAC Flow-Control Source Address Med Register stores the first two bytes of t - MAC Flow-Control Source Address High Register (first two bytes). - MAC Flow-Control Source Address Low Register (last two bytes). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x016C
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_FC_SOURCE_ADDRESS_04_BYTERW0x0MAC Flow-Control Source Address Fourth Byte
This register holds the fourth byte of the Source Address in Canonical Format, used in generated PAUSE and Priority PAUSE Control Frames.
- It represents the fourth byte transmitted on the Ethernet line as part of the Source Address (SA) field in Flow-Control Frames.
(Default : 8’b0)
7:0MAC_FC_SOURCE_ADDRESS_03_BYTERW0x0MAC Flow-Control Source Address Third Byte
This register holds the third byte of the Source Address in Canonical Format, used in generated PAUSE and Priority PAUSE Control Frames.
- It represents the third byte transmitted on the Ethernet line as part of the Source Address (SA) field in Flow-Control Frames.
(Default : 8’b0)
+**Offset: 0x016C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_FC_SOURCE_ADDRESS_04_BYTE | RW | 0x0 | MAC Flow-Control Source Address Fourth Byte
This register holds the fourth byte of the Source Address in Canonical Format, used in generated PAUSE and Priority PAUSE Control Frames.
- It represents the fourth byte transmitted on the Ethernet line as part of the Source Address (SA) field in Flow-Control Frames.
(Default: 8’b0) | +| 7:0 | MAC_FC_SOURCE_ADDRESS_03_BYTE | RW | 0x0 | MAC Flow-Control Source Address Third Byte
This register holds the third byte of the Source Address in Canonical Format, used in generated PAUSE and Priority PAUSE Control Frames.
- It represents the third byte transmitted on the Ethernet line as part of the Source Address (SA) field in Flow-Control Frames.
(Default: 8’b0) | #### MAC Flow-Control Source Address Low Register @@ -3653,41 +1381,13 @@ The MAC Flow-Control Source Address High Register stores the last two bytes of t - MAC Flow-Control Source Address High Register (first two bytes). - MAC Flow-Control Source Address Med Register (middle two bytes). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0170
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_FC_SOURCE_ADDRESS_06_BYTERW0x0MAC Flow-Control Source Address Sixth Byte
This register holds the sixth byte of the Source Address in Canonical Format, used in generated PAUSE and Priority PAUSE Control Frames.
- It represents the sixth byte transmitted on the Ethernet line as part of the Source Address (SA) field in Flow-Control Frames.
(Default : 8’b0)
7:0MAC_FC_SOURCE_ADDRESS_05_BYTERW0x0MAC Flow-Control Source Address Fifth Byte
This register holds the fifth byte of the Source Address in Canonical Format, used in generated PAUSE and Priority PAUSE Control Frames.
- It represents the fifth byte transmitted on the Ethernet line as part of the Source Address (SA) field in Flow-Control Frames.
(Default : 8’b0)
+**Offset: 0x0170** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_FC_SOURCE_ADDRESS_06_BYTE | RW | 0x0 | MAC Flow-Control Source Address Sixth Byte
This register holds the sixth byte of the Source Address in Canonical Format, used in generated PAUSE and Priority PAUSE Control Frames.
- It represents the sixth byte transmitted on the Ethernet line as part of the Source Address (SA) field in Flow-Control Frames.
(Default: 8’b0) | +| 7:0 | MAC_FC_SOURCE_ADDRESS_05_BYTE | RW | 0x0 | MAC Flow-Control Source Address Fifth Byte
This register holds the fifth byte of the Source Address in Canonical Format, used in generated PAUSE and Priority PAUSE Control Frames.
- It represents the fifth byte transmitted on the Ethernet line as part of the Source Address (SA) field in Flow-Control Frames.
(Default: 8’b0) | #### MAC Flow-Control Dst. Address High Register @@ -3699,41 +1399,13 @@ The MAC Flow-Control Destination Address High Register stores the first two byte - MAC Flow-Control Destination Address Med Register (middle two bytes). - MAC Flow-Control Destination Address Low Register (last two bytes). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0174
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_FC_DESTINATION_ADDRESS_02_BYTERW0x0MAC Flow-Control Destination Address Second Byte
The register stores the second byte of the Destination Address (in Canonical Format) used in generated PAUSE Control Frames.
- This is the second byte transmitted on the Ethernet line as part of the DA field in PAUSE Control Frames.
(Default : 8’b0)
7:0MAC_FC_DESTINATION_ADDRESS_01_BYTERW0x0MAC Flow-Control Destination Address First Byte
The register stores the first byte of the Destination Address (in Canonical Format) used in generated PAUSE Control Frames.
- This is the first byte transmitted on the Ethernet line as part of the DA field in PAUSE Control Frames.
(Default : 8’b0)
+**Offset: 0x0174** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_FC_DESTINATION_ADDRESS_02_BYTE | RW | 0x0 | MAC Flow-Control Destination Address Second Byte
The register stores the second byte of the Destination Address (in Canonical Format) used in generated PAUSE Control Frames.
- This is the second byte transmitted on the Ethernet line as part of the DA field in PAUSE Control Frames.
(Default: 8’b0) | +| 7:0 | MAC_FC_DESTINATION_ADDRESS_01_BYTE | RW | 0x0 | MAC Flow-Control Destination Address First Byte
The register stores the first byte of the Destination Address (in Canonical Format) used in generated PAUSE Control Frames.
- This is the first byte transmitted on the Ethernet line as part of the DA field in PAUSE Control Frames.
(Default: 8’b0) | #### MAC Flow-Control Dst. Address Med Register @@ -3745,41 +1417,13 @@ The MAC Flow-Control Destination Address Med Register stores the middle two byte - MAC Flow-Control Destination Address High Register (first two bytes). - MAC Flow-Control Destination Address Low Register (last two bytes). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0178
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8
MAC_FC_DESTINATION_ADDRESS_04_BYTERW
0x0MAC Flow-Control Destination Address Fourth Byte
The register stores the fourth byte of the Destination Address (in Canonical Format) used in generated PAUSE Control Frames.
- This is the fourth byte transmitted on the Ethernet line as part of the DA field in PAUSE Control Frames.
(Default : 8’b0)
7:0MAC_FC_DESTINATION_ADDRESS_03_BYTERW0x0
MAC Flow-Control Destination Address Third Byte
The register stores the third byte of the Destination Address (in Canonical Format) used in generated PAUSE Control Frames.
- This is the third byte transmitted on the Ethernet line as part of the DA field in PAUSE Control Frames.
(Default : 8’b0)
+**Offset: 0x0178** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_FC_DESTINATION_ADDRESS_04_BYTE | RW | 0x0 | MAC Flow-Control Destination Address Fourth Byte
The register stores the fourth byte of the Destination Address (in Canonical Format) used in generated PAUSE Control Frames.
- This is the fourth byte transmitted on the Ethernet line as part of the DA field in PAUSE Control Frames.
(Default: 8’b0) | +| 7:0 | MAC_FC_DESTINATION_ADDRESS_03_BYTE | RW | 0x0 | MAC Flow-Control Destination Address Third Byte
The register stores the third byte of the Destination Address (in Canonical Format) used in generated PAUSE Control Frames.
- This is the third byte transmitted on the Ethernet line as part of the DA field in PAUSE Control Frames.
(Default: 8’b0) | #### MAC Flow-Control Dst. Address Low Register @@ -3791,41 +1435,13 @@ The MAC Flow-Control Destination Address High Register stores the last two bytes - MAC Flow-Control Destination Address High Register (first two bytes). - MAC Flow-Control Destination Address Med Register (middle two bytes). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x017C
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8MAC_FC_DESTINATION_ADDRESS_06_BYTERW0x0MAC Flow-Control Destination Address Sixth Byte
The register stores the sixth byte of the Destination Address (in Canonical Format) used in generated PAUSE Control Frames.
- This is the sixth byte transmitted on the Ethernet line as part of the DA field in PAUSE Control Frames.
(Default : 8’b0)
7:0MAC_FC_DESTINATION_ADDRESS_05_BYTERW0x0
MAC Flow-Control Destination Address Fifth Byte
The register stores the fifth byte of the Destination Address (in Canonical Format) used in generated PAUSE Control Frames.
- This is the fifth byte transmitted on the Ethernet line as part of the DA field in PAUSE Control Frames.
(Default : 8’b0)
+**Offset: 0x017C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | MAC_FC_DESTINATION_ADDRESS_06_BYTE | RW | 0x0 | MAC Flow-Control Destination Address Sixth Byte
The register stores the sixth byte of the Destination Address (in Canonical Format) used in generated PAUSE Control Frames.
- This is the sixth byte transmitted on the Ethernet line as part of the DA field in PAUSE Control Frames.
(Default: 8’b0) | +| 7:0 | MAC_FC_DESTINATION_ADDRESS_05_BYTE | RW | 0x0 | MAC Flow-Control Destination Address Fifth Byte
The register stores the fifth byte of the Destination Address (in Canonical Format) used in generated PAUSE Control Frames.
- This is the fifth byte transmitted on the Ethernet line as part of the DA field in PAUSE Control Frames.
(Default: 8’b0) | #### MAC Flow-Control Pause Time Value Register @@ -3833,100 +1449,34 @@ This register contains the **Pause-Time** value used in the generated **PAUSE Co - The value is used when the **Generate (Priority) PAUSE Frame** bit in the **MAC Flow-Control (Priority) PAUSE Frame Generate Register** is set. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0180
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0MAC_FC_PAUSE_TIMERW0x0MAC Flow-Control Time
This field stores the Pause-Time value used in the generated (Priority) PAUSE Control Frame.
- The 16-bit value is transmitted as per the IEEE 802.3 specification, with the most significant byte first, followed by the least significant byte.
(Default: 16'b0)
+**Offset: 0x0180** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | MAC_FC_PAUSE_TIME | RW | 0x0 | MAC Flow-Control Time
This field stores the Pause-Time value used in the generated (Priority) PAUSE Control Frame.
- The 16-bit value is transmitted as per the IEEE 802.3 specification, with the most significant byte first, followed by the least significant byte.
(Default: 16'b0) | #### MAC Flow-Control Auto Gen Hi Pause Time Value Register This register contains the Pause-Time value used in the generated PAUSE Control Frame when the Receive FIFO fill level exceeds the threshold set in the Receive FIFO Auto Gen Hi Threshold Register. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0184
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0MAC_FC_HIGH_PAUSE_TIMERW
0x0MAC Flow-Control Auto Gen High Pause Time
This field stores the Pause-Time value used in the generated PAUSE control frame when the Receive FIFO Fill Level exceeds the programmed high threshold value.
- The 16-bit value is transmitted as per the IEEE 802.3 specification, with the most significant byte first, followed by the least significant byte.
(Default: 16'b0)
+**Offset: 0x0184** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | MAC_FC_HIGH_PAUSE_TIME | RW | 0x0 | MAC Flow-Control Auto Gen High Pause Time
This field stores the Pause-Time value used in the generated PAUSE control frame when the Receive FIFO Fill Level exceeds the programmed high threshold value.
- The 16-bit value is transmitted as per the IEEE 802.3 specification, with the most significant byte first, followed by the least significant byte.
(Default: 16'b0) | #### MAC Flow-Control Auto Lo Pause Time Value Register This register contains the **Pause-Time** value used in the generated **PAUSE Control Frame** when the **Receive FIFO** fill level falls below the programmed **Low Threshold** value, which had previously crossed the **High Threshold** value. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0188
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0MAC_FC_LOW_PAUSE_TIMERW0x0MAC Flow-Control Pause Time
This field stores the Pause-Time value used in the generated PAUSE Control Frame when the Receive FIFO Fill Level drops below the programmed Low Threshold value, after previously crossing the programmed High Threshold value.
- The 16-bit value is transmitted as per the IEEE 802.3 specification, with the most significant byte first, followed by the least significant byte.
(Default: 16'b0)
+**Offset: 0x0188** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | MAC_FC_LOW_PAUSE_TIME | RW | 0x0 | MAC Flow-Control Pause Time
This field stores the Pause-Time value used in the generated PAUSE Control Frame when the Receive FIFO Fill Level drops below the programmed Low Threshold value, after previously crossing the programmed High Threshold value.
- The 16-bit value is transmitted as per the IEEE 802.3 specification, with the most significant byte first, followed by the least significant byte.
(Default: 16'b0) | #### MAC Flow-Control Auto Pause Frame Gen Hi Threshold Register @@ -3935,34 +1485,12 @@ This register stores the high threshold value for the Receive FIFO Fill Level. - When the Receive FIFO Fill Level reaches or exceeds this threshold value, a PAUSE control frame is generated. - The Pause-Time value used in the generated PAUSE control frame is the value programmed in the MAC Flow-Control Auto Gen High Pause Time Register. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x018C
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0MAC_FC_PAUSE_HIGH_THRESHOLDRW0xFFFFThis field stores the High Threshold value for the Receive FIFO Fill Level. When the fill level reaches or exceeds this threshold, a PAUSE Control Frame is generated using the Pause-Time value programmed in the MAC Flow-Control Auto Gen Hi Pause Time Value Register.
- The value represents the MAC Receive FIFO fill level.
- Each location corresponds to either an 8-byte-wide FIFO or a 16-byte-wide FIFO.
(Default: 16'hFFFF)
+**Offset: 0x018C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | MAC_FC_PAUSE_HIGH_THRESHOLD | RW | 0xFFFF | This field stores the High Threshold value for the Receive FIFO Fill Level. When the fill level reaches or exceeds this threshold, a PAUSE Control Frame is generated using the Pause-Time value programmed in the MAC Flow-Control Auto Gen Hi Pause Time Value Register.
- The value represents the MAC Receive FIFO fill level.
- Each location corresponds to either an 8-byte-wide FIFO or a 16-byte-wide FIFO.
(Default: 16'hFFFF) | #### MAC Flow-Control Auto Pause Frame Gen Lo Threshold Register @@ -3971,34 +1499,12 @@ This register stores the low threshold value for the Receive FIFO Fill Level. - When the Receive FIFO Fill Level falls below this threshold value, a PAUSE control frame is generated. - The Pause-Time value used in the generated PAUSE control frame is the value programmed in the MAC Flow-Control Auto Gen High Pause Time Register. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0190
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0MAC_FC_PAUSE_LOW_THRESHOLDRW0x0MAC Flow-Control Auto Pause Low Threshold
This field contains the Receive FIFO Low Threshold value used to generate the PAUSE Control Frame when the Receive FIFO Fill Level falls below this threshold. When this happens, the PAUSE Control Frame is generated using the Pause Time value programmed in the MAC Flow-Control Auto Gen Lo Pause Time Value Register.
- The threshold value is based on the MAC Receive FIFO fill level.
- Each location corresponds to either an 8-byte wide FIFO or a 16-byte wide FIFO.
(Default: 16'b0)
+**Offset: 0x0190** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | MAC_FC_PAUSE_LOW_THRESHOLD | RW | 0x0 | MAC Flow-Control Auto Pause Low Threshold
This field contains the Receive FIFO Low Threshold value used to generate the PAUSE Control Frame when the Receive FIFO Fill Level falls below this threshold. When this happens, the PAUSE Control Frame is generated using the Pause Time value programmed in the MAC Flow-Control Auto Gen Lo Pause Time Value Register.
- The threshold value is based on the MAC Receive FIFO fill level.
- Each location corresponds to either an 8-byte wide FIFO or a 16-byte wide FIFO.
(Default: 16'b0) | #### MAC MDIO Control Register @@ -4008,62 +1514,16 @@ The MAC MDIO Control Register is used to control and generate MDIO frames to the - Register Address - etc - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01A0
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15START_MDIO_TRANSRW0
Start MDIO Transaction
This bit is set by the software to instruct the EMAC Core to generate an MDIO frame.
- Before setting this bit, the software must ensure it is cleared.
- Once set, the EMAC Core generates the MDIO frame based on the register fields:
1. For write transactions, the data from the MDIO Data Register is used.
2. For read transactions, the data read from the PHY is written into the MDIO Data Register.
- The software must continuously poll this bit to check if the MDIO frame transmission is completed.
- After the MDIO frame transmission is complete, the EMAC Core automatically clears this bit.
> Note.
> For read transactions, the software should read from the MDIO Data Register after the EMAC clears this bit.
(Default: 1’b0)
14:11ReservedReserved for future use
10MDIO_READ_WRITERW0MDIO Read/Write
This bit determines the type of MDIO transaction to be performed.
- Encodings:
1. 1’b1: Read transaction
2. 1’b0: Write transaction (Default)
9:5REGISTER_ADDRESSRW0x0Register Address
This field contains the Register Address field that is used in the MDIO Frame.
It can address up to 32 registers in the addressed PHY device. (Default: 5’b0)
4:0PHY_ADDRESSRW0x0PHY Address
This field contains the PHY Address field that is used in the MDIO Frame.
It can address up to 32 PHY devices.
(Default: 5’b0)
+**Offset: 0x01A0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15 | START_MDIO_TRANS | RW | 0 | Start MDIO Transaction
This bit is set by the software to instruct the EMAC Core to generate an MDIO frame.
- Before setting this bit, the software must ensure it is cleared.
- Once set, the EMAC Core generates the MDIO frame based on the register fields:
1. For write transactions, the data from the MDIO Data Register is used.
2. For read transactions, the data read from the PHY is written into the MDIO Data Register.
- The software must continuously poll this bit to check if the MDIO frame transmission is completed.
- After the MDIO frame transmission is complete, the EMAC Core automatically clears this bit.
> Note.
> For read transactions, the software should read from the MDIO Data Register after the EMAC clears this bit.
(Default: 1’b0) | +| 14:11 | Reserved | | | Reserved for future use | +| 10 | MDIO_READ_WRITE | RW | 0 | MDIO Read/Write
This bit determines the type of MDIO transaction to be performed.
- Encodings:
1. 1’b1: Read transaction
2. 1’b0: Write transaction (Default) | +| 9:5 | REGISTER_ADDRESS | RW | 0x0 | Register Address
This field contains the Register Address field that is used in the MDIO Frame.
It can address up to 32 registers in the addressed PHY device. (Default: 5’b0) | +| 4:0 | PHY_ADDRESS | RW | 0x0 | PHY Address
This field contains the PHY Address field that is used in the MDIO Frame.
It can address up to 32 PHY devices.
(Default: 5’b0) | #### MAC MDIO Data Register @@ -4072,34 +1532,12 @@ The register stores the 16-bit data used in MDIO transfers: - For **MDIO write transfers**, it contains the 16-bit data to be written to the addressed PHY register. - For **MDIO read transfers**, it holds the 16-bit data read from the addressed PHY register. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01A4
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0MDIO_DATARW0x0MDIO Data
This field holds the 16-bit value:
- In MDIO read transfers, it contains the data read from the PHY.
- In MDIO write transfers, it contains the data to be written to the PHY.
(Default: 16'b0)
+**Offset: 0x01A4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | MDIO_DATA | RW | 0x0 | MDIO Data
This field holds the 16-bit value:
- In MDIO read transfers, it contains the data read from the PHY.
- In MDIO write transfers, it contains the data to be written to the PHY.
(Default: 16'b0) | #### MAC Receive StatCtr. Control Register @@ -4108,114 +1546,36 @@ This register is used to initiate the reading of the Receive Statistic Counters - The specific counter to be read is programmed through this register. - After the counter read operation is complete, the resulting data is provided in the MAC Receive StatCtr. Data High/Low Registers for further processing. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01A8
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15START_RX_COUNTER_READRW0x0Start Receive Counter Read
This bit is set by the software to instruct the EMAC Core to read the specified Receive Statistic Counter from the internal memory.
- Before setting this bit, software must ensure that it is cleared.
- Once set, the EMAC Core immediately attempts to read the addressed counter.
- The software should continuously poll this bit to determine when the counter read operation is complete.
- Once the operation is finished, the EMAC Core automatically clears this bit.
- After the bit is cleared, software should read the MAC Receive StatCtr. Data High/Low Registers to retrieve the counter value.
(Default: 1'b0)
14:5ReservedReserved for future use
4:0RX_COUNTER_NUMBERRO0x0Receive Counter Number
This field contains the Receive Statistic Counter Number that is to be read.
- The Counter is a 32-bit rollover counter.
(Default: 5’b0)
+**Offset: 0x01A8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15 | START_RX_COUNTER_READ | RW | 0x0 | Start Receive Counter Read
This bit is set by the software to instruct the EMAC Core to read the specified Receive Statistic Counter from the internal memory.
- Before setting this bit, software must ensure that it is cleared.
- Once set, the EMAC Core immediately attempts to read the addressed counter.
- The software should continuously poll this bit to determine when the counter read operation is complete.
- Once the operation is finished, the EMAC Core automatically clears this bit.
- After the bit is cleared, software should read the MAC Receive StatCtr. Data High/Low Registers to retrieve the counter value.
(Default: 1'b0) | +| 14:5 | Reserved | | | Reserved for future use | +| 4:0 | RX_COUNTER_NUMBER | RO | 0x0 | Receive Counter Number
This field contains the Receive Statistic Counter Number that is to be read.
- The Counter is a 32-bit rollover counter.
(Default: 5’b0) | #### MAC Receive StatCtr. Data High Register This register contains the upper 16-bits of the 32-bit counter data that was read in the previous read operation. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01AC
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0RX_STATCTR_DATA_HIGHRO
0x0Receive StatCtr. Data High
This field contains the upper 16-bits of the 32-bit Receive Counter that was read in the previous operation.
(Default: 16’b0)
+**Offset: 0x01AC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | RX_STATCTR_DATA_HIGH | RO | 0x0 | Receive StatCtr. Data High
This field contains the upper 16-bits of the 32-bit Receive Counter that was read in the previous operation.
(Default: 16’b0) | #### MAC Receive StatCtr. Data Low Register This register contains the lower 16-bits of the 32-bit counter data that was read in the previous read operation. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01B0
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0RX_STATCTR_DATA_LOWRO0x0Receive StatCtr. Data Low
This field contains the lower 16-bits of the 32-bit Receive Counter that was read in the previous operation.
(Default: 16’b0)
+**Offset: 0x01B0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | RX_STATCTR_DATA_LOW | RO | 0x0 | Receive StatCtr. Data Low
This field contains the lower 16-bits of the 32-bit Receive Counter that was read in the previous operation.
(Default: 16’b0) | #### MAC Transmit StatCtr. Control Register @@ -4224,114 +1584,36 @@ This register is used to initiate the reading of the Transmit Statistic Counters - The specific counter to be read is programmed through this register. - After the counter read operation is complete, the resulting data is provided in the MAC Transmit StatCtr. Data High/Low Registers for further processing. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01B4
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15START_TX_COUNTER_READRW0Start Transmit Counter Read
This bit is set by the software to instruct the EMAC Core to read the specified Transmit Statistic Counter from the internal memory.
- Before setting this bit, software must ensure that it is cleared.
- Once set, the EMAC Core immediately attempts to read the addressed counter.
- The software should continuously poll this bit to determine when the counter read operation is complete.
- Once the operation is finished, the EMAC Core automatically clears this bit.
- After the bit is cleared, software should read the MAC Transmit StatCtr. Data High/Low Registers to retrieve the counter value.
(Default: 1'b0)
14:5ReservedReserved for future use
4:0TX_COUNTER_NUMBERRO0x0Transmit Counter Number
This field contains the Transmit Statistic Counter Number that is to be read.
- The Counter is a 32-bit rollover counter.
(Default: 5’b0)
+**Offset: 0x01B4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15 | START_TX_COUNTER_READ | RW | 0 | Start Transmit Counter Read
This bit is set by the software to instruct the EMAC Core to read the specified Transmit Statistic Counter from the internal memory.
- Before setting this bit, software must ensure that it is cleared.
- Once set, the EMAC Core immediately attempts to read the addressed counter.
- The software should continuously poll this bit to determine when the counter read operation is complete.
- Once the operation is finished, the EMAC Core automatically clears this bit.
- After the bit is cleared, software should read the MAC Transmit StatCtr. Data High/Low Registers to retrieve the counter value.
(Default: 1'b0) | +| 14:5 | Reserved | | | Reserved for future use | +| 4:0 | TX_COUNTER_NUMBER | RO | 0x0 | Transmit Counter Number
This field contains the Transmit Statistic Counter Number that is to be read.
- The Counter is a 32-bit rollover counter.
(Default: 5’b0) | #### MAC Transmit StatCtr. Data High Register This register contains the upper 16-bits of the 32-bit counter data that was read in the previous read operation. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01B8
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0TX_STATCTR_DATA_HIGHRO0x0Transmit StatCtr. Data High
This field contains the upper 16-bits of the 32-bit Receive Counter that was read in the previous operation.
(Default: 16’b0)
+**Offset: 0x01B8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | TX_STATCTR_DATA_HIGH | RO | 0x0 | Transmit StatCtr. Data High
This field contains the upper 16-bits of the 32-bit Receive Counter that was read in the previous operation.
(Default: 16’b0) | #### MAC Transmit StatCtr. Data Low Register This register contains the lower 16-bits of the 32-bit counter data that was read in the previous read operation. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01B0
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0TX_STATCTR_DATA_LOWRO0x0Transmit StatCtr. Data Low
This field contains the lower 16-bits of the 32-bit Receive Counter that was read in the previous operation.
(Default: 16’b0)
+**Offset: 0x01B0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | TX_STATCTR_DATA_LOW | RO | 0x0 | Transmit StatCtr. Data Low
This field contains the lower 16-bits of the 32-bit Receive Counter that was read in the previous operation.
(Default: 16’b0) | #### MAC Transmit FIFO AlmostFull Threshold Register @@ -4340,34 +1622,12 @@ This register contains the threshold value used by the Transmit FIFO in the EMAC - When the Transmit FIFO reaches this threshold, it signals the DMA to stop fetching the next burst of data from the Host Memory, as the FIFO is nearing full capacity. - The value programmed in this register represents the number of empty FIFO locations that must remain before the "Almost Full" condition is declared. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01C0
BitsFieldTypeResetDescription
31:14ReservedReserved for future use
13:0TX_FIFO_AFRW0x0Transmit FIFO AlmostFull Threshold
This field specifies the number of occupied locations (each 32-bit wide) in the Transmit FIFO that triggers the "Almost Full" condition within the EMAC Core.
- Once the threshold is reached, the Transmit FIFO asserts the Almost Full condition, signaling the Transmit DMA to stop fetching the next burst of data from Host Memory.
- For proper operation of the EMAC Core, the value programmed in this field should be
FIFO_SIZE - 14'h0008
where, FIFO_SIZE represents the depth of the Transmit FIFO in 32-bit words.
(Default: 14'b0)
+**Offset: 0x01C0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:14 | Reserved | | | Reserved for future use | +| 13:0 | TX_FIFO_AF | RW | 0x0 | Transmit FIFO AlmostFull Threshold
This field specifies the number of occupied locations (each 32-bit wide) in the Transmit FIFO that triggers the "Almost Full" condition within the EMAC Core.
- Once the threshold is reached, the Transmit FIFO asserts the Almost Full condition, signaling the Transmit DMA to stop fetching the next burst of data from Host Memory.
- For proper operation of the EMAC Core, the value programmed in this field should be
FIFO_SIZE - 14'h0008
where, FIFO_SIZE represents the depth of the Transmit FIFO in 32-bit words.
(Default: 14'b0) | #### MAC Transmit Packet Start Threshold Register @@ -4376,34 +1636,12 @@ This field specifies the threshold value for the number of bytes in the Transmit - The EMAC Core waits for at least the specified number of bytes or the end of the packet in the Transmit FIFO before initiating transmission. - Setting an appropriate value in this register helps reduce Transmit Underflow conditions, particularly when the Host Bus has high bandwidth demands. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01C4
BitsFieldTypeResetDescription
31:14ReservedReserved for future use
13:0TX_PACKET_START_THRESHOLDRW0x0Transmit Packet Start Threshold
This field specifies the number of bytes that must be present in the Transmit FIFO before the packet is transmitted onto the MII/GMII Interface.
- The EMAC Core waits until the Transmit FIFO contains at least the specified number of bytes of data, or the End of Packet is in the FIFO, before initiating transmission.
- Setting a higher value helps reduce Transmit Underflow situations, particularly when the DMA cannot fetch data from the Host Memory fast enough.
Suggested values based on Ethernet Interface Speed (assuming the Host bandwidth is sufficiently available for DMA to fetch data from Host Memory):
- 10 Mbps: 64 Bytes
- 100 Mbps: 128 Bytes
- 1000 Mbps: 1024 Bytes
A value of 1518 sets the Transmit MAC to operate in Store and Forward mode for all packets, regardless of the Ethernet speed.
(Default: 14'b0)
+**Offset: 0x01C4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:14 | Reserved | | | Reserved for future use | +| 13:0 | TX_PACKET_START_THRESHOLD | RW | 0x0 | Transmit Packet Start Threshold
This field specifies the number of bytes that must be present in the Transmit FIFO before the packet is transmitted onto the MII/GMII Interface.
- The EMAC Core waits until the Transmit FIFO contains at least the specified number of bytes of data, or the End of Packet is in the FIFO, before initiating transmission.
- Setting a higher value helps reduce Transmit Underflow situations, particularly when the DMA cannot fetch data from the Host Memory fast enough.
Suggested values based on Ethernet Interface Speed (assuming the Host bandwidth is sufficiently available for DMA to fetch data from Host Memory):
- 10 Mbps: 64 Bytes
- 100 Mbps: 128 Bytes
- 1000 Mbps: 1024 Bytes
A value of 1518 sets the Transmit MAC to operate in Store and Forward mode for all packets, regardless of the Ethernet speed.
(Default: 14'b0) | #### MAC Receive Packet Start Threshold Register @@ -4412,34 +1650,12 @@ This field specifies the number of bytes that must be present in the Receive FIF - If the packet is smaller than the value programmed in this register, it will be dropped from the Receive FIFO and not transferred to Host Memory. - This mechanism helps prevent the transfer of small packets, such as Runts and Fragments, optimizing CPU resources by ensuring only valid, sufficiently-sized packets are passed to the Host. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01C8
BitsFieldTypeResetDescription
31:14ReservedReserved for future use
13:0RX_PACKET_START_THRESHOLDRW0xEReceive Packet Start Threshold
This field defines the minimum number of bytes required in a received packet before it is transferred from the MII/GMII Interface to Host Memory.
- If the packet size is smaller than the programmed value, it is treated as a Runt/Fragment and dropped from the Receive FIFO without being transferred.
- A value of 64 in this field ensures that all Runt frames are filtered out and not transferred to Host Memory.
- A value of 0 configures the EMAC Core to transfer all frames, regardless of size or DA field, to Host Memory.
- A minimum value of 12 is necessary for the Address Filtering logic to function and filter out frames not addressed to this device. Setting a value less than 12 disables the Address Filtering logic.
- If the "Store And Forward" bit in the MAC Receive Control Register is set, this register’s value is ignored, and the EMAC operates in store-and-forward mode for packet reception.
(Default: 14’h000E)
+**Offset: 0x01C8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:14 | Reserved | | | Reserved for future use | +| 13:0 | RX_PACKET_START_THRESHOLD | RW | 0xE | Receive Packet Start Threshold
This field defines the minimum number of bytes required in a received packet before it is transferred from the MII/GMII Interface to Host Memory.
- If the packet size is smaller than the programmed value, it is treated as a Runt/Fragment and dropped from the Receive FIFO without being transferred.
- A value of 64 in this field ensures that all Runt frames are filtered out and not transferred to Host Memory.
- A value of 0 configures the EMAC Core to transfer all frames, regardless of size or DA field, to Host Memory.
- A minimum value of 12 is necessary for the Address Filtering logic to function and filter out frames not addressed to this device. Setting a value less than 12 disables the Address Filtering logic.
- If the "Store And Forward" bit in the MAC Receive Control Register is set, this register’s value is ignored, and the EMAC operates in store-and-forward mode for packet reception.
(Default: 14’h000E) | #### MAC Transmit FIFO AlmostEmpty Threshold Register @@ -4447,34 +1663,12 @@ This register contains the threshold value used by the Transmit FIFO in the EMAC - When the number of occupied locations in the Transmit FIFO is less than or equal to the programmed threshold value, the Almost Empty condition is triggered. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01CC
BitsFieldTypeResetDescription
31:8ReservedReserved for future use
7:0TX_FIFO_AERW0x10Transmit FIFO AlmostEmpty Threshold
This field contains the threshold value for the Transmit FIFO in the EMAC Core.
- When the number of occupied locations (each 32-bit or 64-bit wide) in the Transmit FIFO equals or falls below this threshold, the Transmit FIFO Almost Empty signal is generated to the DMA.
(Default: 8'h10)
+**Offset: 0x01CC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | | | Reserved for future use | +| 7:0 | TX_FIFO_AE | RW | 0x10 | Transmit FIFO AlmostEmpty Threshold
This field contains the threshold value for the Transmit FIFO in the EMAC Core.
- When the number of occupied locations (each 32-bit or 64-bit wide) in the Transmit FIFO equals or falls below this threshold, the Transmit FIFO Almost Empty signal is generated to the DMA.
(Default: 8'h10) | #### MAC Transmit FIFO Space Available Hi Threshold Register @@ -4482,34 +1676,12 @@ This register holds the threshold value used by the Transmit FIFO in the EMAC Co - When the FIFO fill level reaches or exceeds this value, the Space Available indication to the DMA is deasserted, signaling that there is insufficient space for additional data - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01D0
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0TX_FIFO_SPACE_AVAILABLE_HIGH_THRESHOLDRW0x100Transmit FIFO Space Available Hi Threshold
This field contains the threshold value. When the number of locations (each 32-bit or 64-bit wide) occupied in the Transmit FIFO equals or exceeds this value, the Space Available signal is deasserted.
(Default: 16’h0100)
+**Offset: 0x01D0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | TX_FIFO_SPACE_AVAILABLE_HIGH_THRESHOLD | RW | 0x100 | Transmit FIFO Space Available Hi Threshold
This field contains the threshold value. When the number of locations (each 32-bit or 64-bit wide) occupied in the Transmit FIFO equals or exceeds this value, the Space Available signal is deasserted.
(Default: 16’h0100) | #### MAC Transmit FIFO Space Available Lo Threshold Register @@ -4519,473 +1691,145 @@ This register contains the threshold value used by the Transmit FIFO in the EMAC - When the FIFO fill level equals or dips below this value, the Space Available indication is asserted to the DMA, signaling that there is available space for more data. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01D4
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0TX_FIFO_SPACE_AVAILABLE_LOW_THRESHOLDRW0x10Transmit FIFO Space Available Lo Threshold
This field contains the threshold value. When the number of locations (each 32-bit or 64-bit wide) occupied in the Transmit FIFO equals or dips below this value, the Space Available signal is deasserted.
(Default: 16’h0010)
+**Offset: 0x01D4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | TX_FIFO_SPACE_AVAILABLE_LOW_THRESHOLD | RW | 0x10 | Transmit FIFO Space Available Lo Threshold
This field contains the threshold value. When the number of locations (each 32-bit or 64-bit wide) occupied in the Transmit FIFO equals or dips below this value, the Space Available signal is deasserted.
(Default: 16’h0010) | #### MAC Receive FIFO Packet Available Threshold#1 Register This register contains the threshold values used by the Receive FIFO in the EMAC Core to assert the Packet Available indication to DMA when the Fill level equals to or exceeds the selected threshold value. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01D8
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8RX_FIFO_PACKET_AVAILABLE_THRESHOLD2RW0x20Receive FIFO Packet Available Threshold2
This field specifies the threshold value for the receive FIFO.
When the number of occupied locations (each 32-bit or 64-bit wide) in the receive FIFO equals or exceeds this value, the Receive Packet Available signal is generated (provided that Threshold Selection is set to Threshold2).
(Default: 8’20)
7:0RX_FIFO_PACKET_AVAILABLE_THRESHOLD1RW0x10Receive FIFO Packet Available Threshold1
This field specifies the threshold value for the receive FIFO.
When the number of occupied locations (each 32-bit or 64-bit wide) in the receive FIFO equals or exceeds this value, the Receive Packet Available signal is generated (provided that Threshold Selection is set to Threshold1).
(Default: 8’10)
+**Offset: 0x01D8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | RX_FIFO_PACKET_AVAILABLE_THRESHOLD2 | RW | 0x20 | Receive FIFO Packet Available Threshold2
This field specifies the threshold value for the receive FIFO.
When the number of occupied locations (each 32-bit or 64-bit wide) in the receive FIFO equals or exceeds this value, the Receive Packet Available signal is generated (provided that Threshold Selection is set to Threshold2).
(Default: 8’20) | +| 7:0 | RX_FIFO_PACKET_AVAILABLE_THRESHOLD1 | RW | 0x10 | Receive FIFO Packet Available Threshold1
This field specifies the threshold value for the receive FIFO.
When the number of occupied locations (each 32-bit or 64-bit wide) in the receive FIFO equals or exceeds this value, the Receive Packet Available signal is generated (provided that Threshold Selection is set to Threshold1).
(Default: 8’10) | #### MAC Receive FIFO Packet Available Threshold#2 Register This register contains the threshold values used by the Receive FIFO in the EMAC Core to assert the Packet Available indication to DMA when the Fill level equals to or exceeds the selected threshold value - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01DC
BitsFieldTypeResetDescription
31:5ReservedReserved for future use
4RX_FIFO_PACKET_AVAILABLE_THRESHOLD_SELECTIONRW0Receive FIFO Packet Available Threshold Selection
This bit selects one of the two Receive FIFO Packet Available Threshold values for generating the Receive Packet Available signal. (Default: 8'b0)
- 1'b0: Receive FIFO Packet Available Threshold1 Selected
- 1'b1: Receive FIFO Packet Available Threshold2 Selected
Currently, this value is not used by the DMA and does not need to be programmed.
3:0RX_FIFO_PACKET_COUNT_THRESHOLDRW0x1Receive FIFO Packet Count Threshold
This field contains a threshold value.
When the number of packets in the Receive FIFO equals to or
Exceeds this value, the Receive packet available signal is
generated.
(Default: 4'b0001)
+**Offset: 0x01DC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:5 | Reserved | | | Reserved for future use | +| 4 | RX_FIFO_PACKET_AVAILABLE_THRESHOLD_SELECTION | RW | 0 | Receive FIFO Packet Available Threshold Selection
This bit selects one of the two Receive FIFO Packet Available Threshold values for generating the Receive Packet Available signal. (Default: 8'b0)
- 1'b0: Receive FIFO Packet Available Threshold1 Selected
- 1'b1: Receive FIFO Packet Available Threshold2 Selected
Currently, this value is not used by the DMA and does not need to be programmed. | +| 3:0 | RX_FIFO_PACKET_COUNT_THRESHOLD | RW | 0x1 | Receive FIFO Packet Count Threshold
This field contains a threshold value.
When the number of packets in the Receive FIFO equals to or
Exceeds this value, the Receive packet available signal is
generated.
(Default: 4'b0001) | #### MAC Status and IRQ Register This register provides status and interrupt request (IRQ) information on various conditions that need to be monitored by the host software, which results from the MAC module in the EMAC Core. The IRQ bits are used to generate interrupts for the host. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01E0
BitsFieldTypeResetDescription
31:2ReservedReserved for future use
1MAC_JABBER_IRQRW0
MAC Jabber IRQ
- When set:
Indicates that a jabber condition has been detected while transferring a frame to the MII/GMII interface. This occurs when the frame length exceeds the value programmed in the Transmit Jabber Count Register.
1. The MAC truncates the frame at this point and forces EOP/ERR onto the MII/GMII interface.
2. Any remaining data bytes received from the host are ignored.
- The interrupt is cleared by writing 1 to this bit.
(Default: 1’b0)
0MAC_UNDERRUN_IRQRW0MAC Underrun IRQ
- When set:
Indicates that an underrun condition has occurred while transferring a frame to the MII/GMII interface. This happens when the DMA is unable to sustain the data transfer rate required by the MAC.
1. The MAC forces EOP/ERR onto the MII/GMII interface.
2. Any remaining data bytes received from the host are ignored.
- The interrupt is cleared by writing 1 to this bit.
(Default: 1’b0)
+**Offset: 0x01E0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | | | Reserved for future use | +| 1 | MAC_JABBER_IRQ | RW | 0 | MAC Jabber IRQ
- When set:
Indicates that a jabber condition has been detected while transferring a frame to the MII/GMII interface. This occurs when the frame length exceeds the value programmed in the Transmit Jabber Count Register.
1. The MAC truncates the frame at this point and forces EOP/ERR onto the MII/GMII interface.
2. Any remaining data bytes received from the host are ignored.
- The interrupt is cleared by writing 1 to this bit.
(Default: 1’b0) | +| 0 | MAC_UNDERRUN_IRQ | RW | 0 | MAC Underrun IRQ
- When set:
Indicates that an underrun condition has occurred while transferring a frame to the MII/GMII interface. This happens when the DMA is unable to sustain the data transfer rate required by the MAC.
1. The MAC forces EOP/ERR onto the MII/GMII interface.
2. Any remaining data bytes received from the host are ignored.
- The interrupt is cleared by writing 1 to this bit.
(Default: 1’b0) | #### MAC Interrupt Enable Register This register is used to enable interrupts for various conditions in the MAC module that need to be monitored by the host software in the EMAC Core. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01E4
BitsFieldTypeResetDescription
31:2ReservedReserved for future use
1JABBER_INTERRUPT_ENABLERW0Jabber Interrupt Enable
- When set:
The MAC Jabber IRQ will trigger an interrupt on the AHB/AXI Bus.
- When cleared:
The MAC Jabber IRQ will be blocked and will not generate an interrupt.
(Default: 1'b0)
0MAC_UNDERRUN_INTERRUPT_ENABLERW0MAC Underrun Interrupt Enable
- When set:
The MAC Underrun IRQ will trigger an interrupt on the AHB/AXI Bus.
- When cleared:
The MAC Underrun IRQ will be blocked and will not generate an interrupt.
(Default: 1'b0)
+**Offset: 0x01E4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | | | Reserved for future use | +| 1 | JABBER_INTERRUPT_ENABLE | RW | 0 | Jabber Interrupt Enable
- When set:
The MAC Jabber IRQ will trigger an interrupt on the AHB/AXI Bus.
- When cleared:
The MAC Jabber IRQ will be blocked and will not generate an interrupt.
(Default: 1'b0) | +| 0 | MAC_UNDERRUN_INTERRUPT_ENABLE | RW | 0 | MAC Underrun Interrupt Enable
- When set:
The MAC Underrun IRQ will trigger an interrupt on the AHB/AXI Bus.
- When cleared:
The MAC Underrun IRQ will be blocked and will not generate an interrupt.
(Default: 1'b0) | #### MAC VLAN TPID#1 Register - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01E8
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0MAC_VLAN_TPID1RW0x8100MAC VLAN TPID#1
This field contains the 1st of the three custom TPID values that are used to detect VLAN fields.
(Default: 16’h8100)
+**Offset: 0x01E8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | MAC_VLAN_TPID1 | RW | 0x8100 | MAC VLAN TPID#1
This field contains the 1st of the three custom TPID values that are used to detect VLAN fields.
(Default: 16’h8100) | #### MAC VLAN TPID#2 Register - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01EC
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0MAC_VLAN_TPID2RW0x9100MAC VLAN TPID#2
This field contains the 2nd of the three custom TPID values that are used to detect VLAN fields.
(Default: 16’h9100)
+**Offset: 0x01EC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | MAC_VLAN_TPID2 | RW | 0x9100 | MAC VLAN TPID#2
This field contains the 2nd of the three custom TPID values that are used to detect VLAN fields.
(Default: 16’h9100) | #### MAC VLAN TPID#3 Register - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x01F0
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0MAC_VLAN_TPID3RW0x88A8MAC VLAN TPID#3
This field contains the 3rd of the three custom TPID values that are used to detect VLAN fields.
(Default: 16’h88A8)
+**Offset: 0x01F0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | MAC_VLAN_TPID3 | RW | 0x88A8 | MAC VLAN TPID#3
This field contains the 3rd of the three custom TPID values that are used to detect VLAN fields.
(Default: 16’h88A8) | #### 1588 Control Register Tis register is used to control the main features of the 1588 Module and the Timestamping of the packets. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0300
BitsFieldTypeResetDescription
31:6ReservedReserved for future use
5:3RX_PTP_PKT_TYPERW0x0RX PTP Packet Type
This field controls the selection of packets for timestamping on the receive path. A packet is timestamped and reported to software only if it is received error-free and matches all the programmed criteria.
The following PTP packet types are monitored:
- 3'b000:
Timestamp Version #2 PTP packets in L2 encapsulation (PTP packets as L2 payload) only. This includes Sync or Delay_Req packet types based on the PTP MessageID.
- 3'b001:
Timestamp Version #1 PTP packets in L4 encapsulation (PTP packets as UDP payload) only. This includes Sync or Delay_Req packet types based on the PTP MessageID.
- 3'b010:
Timestamp Version #2 PTP packets in either L2 or L4 encapsulation (PTP packets as L2 payload or UDP payload).
- 3'b011 – 3'b111:
Reserved.
(Default: 3'b000)
2RX_TIMESTAMP_ENRW0RX Timestamping Enable
- When set:
Enables timestamping for incoming PTP packets that match the programmed criteria (such as MessageID, PTP EtherType, UDP Port, Version, etc.).
- When cleared:
Disables the timestamping feature for receive packets.
(Default: 1'b0)
1TX_TIMESTAMP_ENRW0TX Timestamping Enable
- When set:
Enables timestamping for outgoing PTP packets under software control via the descriptor bit.
- When cleared:
Disables the timestamping feature for transmit packets.
(Default: 1'b0)
0ReservedReserved for future use
+**Offset: 0x0300** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:6 | Reserved | | | Reserved for future use | +| 5:3 | RX_PTP_PKT_TYPE | RW | 0x0 | RX PTP Packet Type
This field controls the selection of packets for timestamping on the receive path. A packet is timestamped and reported to software only if it is received error-free and matches all the programmed criteria.
The following PTP packet types are monitored:
- 3'b000:
Timestamp Version #2 PTP packets in L2 encapsulation (PTP packets as L2 payload) only. This includes Sync or Delay_Req packet types based on the PTP MessageID.
- 3'b001:
Timestamp Version #1 PTP packets in L4 encapsulation (PTP packets as UDP payload) only. This includes Sync or Delay_Req packet types based on the PTP MessageID.
- 3'b010:
Timestamp Version #2 PTP packets in either L2 or L4 encapsulation (PTP packets as L2 payload or UDP payload).
- 3'b011 – 3'b111:
Reserved.
(Default: 3'b000) | +| 2 | RX_TIMESTAMP_EN | RW | 0 | RX Timestamping Enable
- When set:
Enables timestamping for incoming PTP packets that match the programmed criteria (such as MessageID, PTP EtherType, UDP Port, Version, etc.).
- When cleared:
Disables the timestamping feature for receive packets.
(Default: 1'b0) | +| 1 | TX_TIMESTAMP_EN | RW | 0 | TX Timestamping Enable
- When set:
Enables timestamping for outgoing PTP packets under software control via the descriptor bit.
- When cleared:
Disables the timestamping feature for transmit packets.
(Default: 1'b0) | +| 0 | Reserved | | | Reserved for future use | #### Increment Attributes Register This register is used to control incrementing of the System Timer. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0304
BitsFieldTypeResetDescription
31:24INCR_PERIODRW0x0Increment Period
- This field sets the period for performing the Increment operation on the System Timer. It defines the number of clk_1588 clock cycles between each Increment operation.
- When the value is 0x00, the increment operation is disabled.
(Default: 8'h00)
23:0INRC_VALRW0x0Increment Value
- This field specifies the value to be added to the System Timer during each increment operation. The value is determined by the granularity and accuracy of the implemented System Timer.
(Default: 24'h000000)
+**Offset: 0x0304** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | INCR_PERIOD | RW | 0x0 | Increment Period
- This field sets the period for performing the Increment operation on the System Timer. It defines the number of clk_1588 clock cycles between each Increment operation.
- When the value is 0x00, the increment operation is disabled.
(Default: 8'h00) | +| 23:0 | INRC_VAL | RW | 0x0 | Increment Value
- This field specifies the value to be added to the System Timer during each increment operation. The value is determined by the granularity and accuracy of the implemented System Timer.
(Default: 24'h000000) | #### PTP Ethertype Register This register is used to determine the Ethertype of the packets when the PTP message is using L2 Encapsulation - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0308
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0PTP_ETH_TYPERW0x0PTP Ethertype
- Specifies the Ethertype in incoming packets for PTP message detection.
- Applies when V2 PTP Packets use Layer 2 (L2) Encapsulation.
- The register value is programmed or read in network order.
- Typical Ethertype for PTP messages: 16'h88F7 (in network order).
(Default: 16'h0000)
+**Offset: 0x0308** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | PTP_ETH_TYPE | RW | 0x0 | PTP Ethertype
- Specifies the Ethertype in incoming packets for PTP message detection.
- Applies when V2 PTP Packets use Layer 2 (L2) Encapsulation.
- The register value is programmed or read in network order.
- Typical Ethertype for PTP messages: 16'h88F7 (in network order).
(Default: 16'h0000) | #### PTP Message ID Register This register is used to define the PTP Message ID of the incoming PTP Packets that will be selected for timestamping. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x030C
BitsFieldTypeResetDescription
31:8ReservedReserved for future use
7:0PTP_MSG_IDRW0x0PTP Message ID
- Defines the PTP Message ID (or PTP Control for V1) for timestamping.
- Used to select SYNC or DELAY_REQ packets based on device role (Master/Slave).
- For monitoring V1 PTP messages, this field corresponds to PTP Control.
- For monitoring V2 PTP messages, this field corresponds to PTP Message ID.
(Default: 8’h00)
+**Offset: 0x030C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | | | Reserved for future use | +| 7:0 | PTP_MSG_ID | RW | 0x0 | PTP Message ID
- Defines the PTP Message ID (or PTP Control for V1) for timestamping.
- Used to select SYNC or DELAY_REQ packets based on device role (Master/Slave).
- For monitoring V1 PTP messages, this field corresponds to PTP Control.
- For monitoring V2 PTP messages, this field corresponds to PTP Message ID.
(Default: 8’h00) | #### PTP UDP Port Register This register is used to determine the destination UDP Port number of the packets when the PTP message is using L4 Encapsulation. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0310
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:0PTP_UDP_PORTRW0x0PTP UDP Port
- Specifies the destination UDP port in incoming packets for monitoring PTP messages.
- Applies when V1/V2 PTP Packets use L4 Encapsulation.
- The register value is programmed/read in Network order.
- Typical PTP UDP ports: 16’h0319 or 16’h0320 (in network order).
- Default: 16’h0000.
+**Offset: 0x0310** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:0 | PTP_UDP_PORT | RW | 0x0 | PTP UDP Port
- Specifies the destination UDP port in incoming packets for monitoring PTP messages.
- Applies when V1/V2 PTP Packets use L4 Encapsulation.
- The register value is programmed/read in Network order.
- Typical PTP UDP ports: 16’h0319 or 16’h0320 (in network order).
- Default: 16’h0000. | #### System Time Value (Lower) Register @@ -4994,27 +1838,11 @@ The System Time Value (Lower & Upper) Registers are used to read the current val - The first register contains the lower 32 bits of the System Timer. - The second register contains the upper 32 bits of the System Timer. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0320
BitsFieldTypeResetDescription
31:0SYS_TIME_LOWRO0x0System Time Value (Lower)
- This field holds the lower 32 bits of the System Timer value.
- Read this register first before reading the System Time Value (Upper) register.
- Reading this register latches the upper 32 bits into the upper register.
(Default: 32’h0000_0000)
+**Offset: 0x0320** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | SYS_TIME_LOW | RO | 0x0 | System Time Value (Lower)
- This field holds the lower 32 bits of the System Timer value.
- Read this register first before reading the System Time Value (Upper) register.
- Reading this register latches the upper 32 bits into the upper register.
(Default: 32’h0000_0000) | #### System Time Value (Upper) Register @@ -5023,27 +1851,11 @@ The System Time Value (Lower & Upper) Registers are used to read the current val - The first register contains the lower 32 bits of the System Timer. - The second register contains the upper 32 bits of the System Timer. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0324
BitsFieldTypeResetDescription
31:0SYSTEM_TIME_HIRO0x0System Time Value (Upper)
- This field holds the upper 32 bits of the System Timer value.
- Read this register after reading the System Time Value (Lower) register.
(Default: 32’h0000_0000)
+**Offset: 0x0324** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | SYSTEM_TIME_HI | RO | 0x0 | System Time Value (Upper)
- This field holds the upper 32 bits of the System Timer value.
- Read this register after reading the System Time Value (Lower) register.
(Default: 32’h0000_0000) | #### System Time Adjust Control (Lower) Register @@ -5051,27 +1863,11 @@ The System Time Adjust Control (Lower & Upper) Registers are used to read and ad - Software should first program the System Timer Adjust Control Lower Register with the adjustment parameters, and then, program the Upper Register to apply the adjustment. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0328
BitsFieldTypeResetDescription
31:0SYS_TIME_ADJ_LOWRW0x0System Time Adjust Value (Lower)
- This field defines the 32-bit adjustment value for the System Timer.
- The type (positive or negative) and the magnitude of the adjustment are controlled by the System Time Adjust Control Upper Register.
(Default: 32’h0000_0000)
+**Offset: 0x0328** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | SYS_TIME_ADJ_LOW | RW | 0x0 | System Time Adjust Value (Lower)
- This field defines the 32-bit adjustment value for the System Timer.
- The type (positive or negative) and the magnitude of the adjustment are controlled by the System Time Adjust Control Upper Register.
(Default: 32’h0000_0000) | #### System Time Adjust Control (Upper) Register @@ -5079,27 +1875,11 @@ The System Time Adjust Control (Lower & Upper) Registers are used to read and ad - Software should first program the System Timer Adjust Control Lower Register with the adjustment parameters, and then, program the Upper Register to apply the adjustment. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x032C
BitsFieldTypeResetDescription
31:0SYS_TIME_ADJ_HIRW
0x0System Time Adjust Control (Upper)
- This Write-only register is used to adjust the System Timer.
- Adjustment occurs when software writes to this register.
- Bit[31] determines the adjustment type:
1. 0 (Positive Adjustment): Adds the System Time Adjust Value to the current System Timer.
2. 1 (Negative Adjustment): Subtracts the System Time Adjust Value from the current System Timer.
+**Offset: 0x032C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | SYS_TIME_ADJ_HI | RW | 0x0 | System Time Adjust Control (Upper)
- This Write-only register is used to adjust the System Timer.
- Adjustment occurs when software writes to this register.
- Bit[31] determines the adjustment type:
1. 0 (Positive Adjustment): Adds the System Time Adjust Value to the current System Timer.
2. 1 (Negative Adjustment): Subtracts the System Time Adjust Value from the current System Timer. | #### Transmit Timestamp (Lower) Register @@ -5111,27 +1891,11 @@ The Transmit Timestamp (Lower & Upper) Registers are used to read the current ti - The first register contains the lower 32 bits of the transmit timestamp value. - The second register contains the upper 32 bits of the transmit timestamp value. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0330
BitsFieldTypeResetDescription
31:0TX_TIMESTAMP_LOWRO0x0Transmit Timestamp (Lower)
- This field contains the lower 32-bits of the Transmit Timestamp value.
- This register is read first before reading the Transmit Timestamp (Upper) Register
(Default: 32’h0000_0000)
+**Offset: 0x0330** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | TX_TIMESTAMP_LOW | RO | 0x0 | Transmit Timestamp (Lower)
- This field contains the lower 32-bits of the Transmit Timestamp value.
- This register is read first before reading the Transmit Timestamp (Upper) Register
(Default: 32’h0000_0000) | #### Transmit Timestamp (Upper) Registers @@ -5143,27 +1907,11 @@ The Transmit Timestamp (Lower & Upper) Registers are used to read the current ti - The first register contains the lower 32 bits of the transmit timestamp value. - The second register contains the upper 32 bits of the transmit timestamp value. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0334
BitsFieldTypeResetDescription
31:0TX_TIMESTAMP_HIRO
0x0Transmit Timestamp (Upper)
- This field contains the upper 32-bits of the Transmit Timestamp value.
- This register is read after the Transmit Timestamp (Lower) Register has been read.
(Default: 32’h0000_0000)
+**Offset: 0x0334** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | TX_TIMESTAMP_HI | RO | 0x0 | Transmit Timestamp (Upper)
- This field contains the upper 32-bits of the Transmit Timestamp value.
- This register is read after the Transmit Timestamp (Lower) Register has been read.
(Default: 32’h0000_0000) | #### Receive Timestamp (Lower) Registers @@ -5175,31 +1923,15 @@ The Receive Timestamp (Lower & Upper) Registers are used to read the current tim - The first register contains the lower 32 bits of the receive timestamp value. - The second register contains the upper 32 bits of the receive timestamp value. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0340
BitsFieldTypeResetDescription
31:0RX_TIMESTAMP_LOWRO0x0Receive Timestamp (Lower)
- This field contains the lower 32-bits of the Receive Timestamp value. Software
- This register is read first before reading the Receive Timestamp (Upper) Register
(Default: 32’h0000_0000)
+**Offset: 0x0340** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RX_TIMESTAMP_LOW | RO | 0x0 | Receive Timestamp (Lower)
- This field contains the lower 32-bits of the Receive Timestamp value. Software
- This register is read first before reading the Receive Timestamp (Upper) Register
(Default: 32’h0000_0000) | #### Receive Timestamp (Upper) Registers -The Receive Timestamp (Lower & Upper) Registers are used to read the current timestamp for the indicated receive packet. +The Receive Timestamp (Lower & Upper) Registers are used to read the current timestamp for the indicated receive packet. - The logic will not update this value (i.e., it will not perform timestamping on another packet) until these registers are read. - These registers are read-only. @@ -5207,27 +1939,11 @@ The Receive Timestamp (Lower & Upper) Registers are used to read the current ti - The first register contains the lower 32 bits of the receive timestamp value. - The second register contains the upper 32 bits of the receive timestamp value. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0344
BitsFieldTypeResetDescription
31:0RX_TIMESTAMP_HIRO0x0Transmit Timestamp (Upper)
- This field contains the upper 32-bits of the Receive Timestamp value.
- This register is read after the Receive Timestamp (Lower) Register has been read.
(Default: 32’h0000_0000)
+**Offset: 0x0344** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RX_TIMESTAMP_HI | RO | 0x0 | Transmit Timestamp (Upper)
- This field contains the upper 32-bits of the Receive Timestamp value.
- This register is read after the Receive Timestamp (Lower) Register has been read.
(Default: 32’h0000_0000) | #### Receive PTP Packet Attribute (Lower) Registers @@ -5235,34 +1951,12 @@ The Receive PTP Packet Attributes (Lower/Middle/Upper) Registers are used to rea - The SrcID corresponds to the byte offset 20 to 29 in the PTP message. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0348
BitsFieldTypeResetDescription
31:16PTP_SRC_ID_LOWRO0x0SrcID (Lower)
- This field contains the lower 16-bits of the SrcID from the timestamped Receive PTP Packet.
- The SrcID is extracted from Byte Offset 28-29 in the PTP message packet.
(Default: 32'h0000_0000)
15:0PTP_SEQ_IDRO0x0SeqID
This field contains the 16-bit SeqID extracted from the timestamped Receive PTP Packet.
(Default: 16’h0000)
+**Offset: 0x0348** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | PTP_SRC_ID_LOW | RO | 0x0 | SrcID (Lower)
- This field contains the lower 16-bits of the SrcID from the timestamped Receive PTP Packet.
- The SrcID is extracted from Byte Offset 28-29 in the PTP message packet.
(Default: 32'h0000_0000) | +| 15:0 | PTP_SEQ_ID | RO | 0x0 | SeqID
This field contains the 16-bit SeqID extracted from the timestamped Receive PTP Packet.
(Default: 16’h0000) | #### Receive PTP Packet Attribute (Middle) Registers @@ -5270,27 +1964,11 @@ The Receive PTP Packet Attributes (Lower/Middle/Upper) Registers are used to rea - The SrcID corresponds to the byte offset 20 to 29 in the PTP message. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x034C
BitsFieldTypeResetDescription
31:0PTP_SRC_ID_MIDRO0x0SrcID (Middle)
- This field contains the middle 32-bits of the SrcID from the timestamped Receive PTP Packet.
- The SrcID is extracted from Byte Offset 24-27 in the PTP message packet.
(Default: 32'h0000_0000)
+**Offset: 0x034C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | PTP_SRC_ID_MID | RO | 0x0 | SrcID (Middle)
- This field contains the middle 32-bits of the SrcID from the timestamped Receive PTP Packet.
- The SrcID is extracted from Byte Offset 24-27 in the PTP message packet.
(Default: 32'h0000_0000) | #### Receive PTP Packet Attribute (Upper) Registers @@ -5298,27 +1976,11 @@ The Receive PTP Packet Attributes (Lower/Middle/Upper) Registers are used to rea - The SrcID corresponds to the byte offset 20 to 29 in the PTP message. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0350
BitsFieldTypeResetDescription
31:0TP_SRC_ID_HIRO0x0SrcID (Upper)
- This field contains the upper 32-bits of the SrcID from the timestamped Receive PTP Packet.
- The SrcID is extracted from Byte Offset 20-23 in the PTP message packet.
(Default: 16'h0000_0000)
+**Offset: 0x0350** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | TP_SRC_ID_HI | RO | 0x0 | SrcID (Upper)
- This field contains the upper 32-bits of the SrcID from the timestamped Receive PTP Packet.
- The SrcID is extracted from Byte Offset 20-23 in the PTP message packet.
(Default: 16'h0000_0000) | #### 1588 IRQ Register @@ -5326,142 +1988,40 @@ The 1588 IRQ Register provides interrupt (IRQ) information related to receive an - The IRQ bits in this register are used to generate interrupts to the host. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0360
BitsFieldTypeResetDescription
31:2ReservedReserved for future use
1RX_TIMESTAMP_IRQRW0Receive Timestamp Valid IRQ
- When set, it indicates that a valid PTP Packet that matches the programmed parameters has been received and timestamped.
- The value is available to read in the Receive Timestamp (Lower/Upper) Registers
- The IRQ is cleared by writing 1 to this bit.
(Default: 1’b0)
0TX_TIMESTAMP_IRQRW0Transmit Timestamp Valid IRQ
- When set, it indicates that a Transmit Packet has been timestamped
- The value is available to read in the Transmit Timestamp (Lower/Upper) Registers.
- The IRQ is cleared by writing 1 to this bit.
(Default: 1’b0)
+**Offset: 0x0360** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | | | Reserved for future use | +| 1 | RX_TIMESTAMP_IRQ | RW | 0 | Receive Timestamp Valid IRQ
- When set, it indicates that a valid PTP Packet that matches the programmed parameters has been received and timestamped.
- The value is available to read in the Receive Timestamp (Lower/Upper) Registers
- The IRQ is cleared by writing 1 to this bit.
(Default: 1’b0) | +| 0 | TX_TIMESTAMP_IRQ | RW | 0 | Transmit Timestamp Valid IRQ
- When set, it indicates that a Transmit Packet has been timestamped
- The value is available to read in the Transmit Timestamp (Lower/Upper) Registers.
- The IRQ is cleared by writing 1 to this bit.
(Default: 1’b0) | #### 1588 Interrupt Enable Register The 1588 Interrupt Enable Register is used to enable the generation of 1588 interrupts for various conditions that need to be monitored by the Host software. These conditions arise from the 1588 module in the EMAC Core. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0340
BitsFieldTypeResetDescription
31:2ReservedReserved for future use
1RX_TIMESTAMP_IRQ_ENABLERW0Receive Timestamp Interrupt Enable
- When set, enables the Receive Timestamp IRQ to trigger an interrupt on the AHB/AXI Bus.
- When cleared, the Receive Timestamp Valid IRQ is blocked from generating an interrupt.
(Default: 1’b0)
0TX_TIMESTAMP_IRQ_ENABLERW
0
Transmit Timestamp Interrupt Enable
- When set, enables the Transmit Timestamp IRQ to trigger an interrupt on the AHB/AXI Bus.
- When cleared, the Transmit Timestamp Valid IRQ is blocked from generating an interrupt.
(Default: 1’b0)
+**Offset: 0x0340** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | | | Reserved for future use | +| 1 | RX_TIMESTAMP_IRQ_ENABLE | RW | 0 | Receive Timestamp Interrupt Enable
- When set, enables the Receive Timestamp IRQ to trigger an interrupt on the AHB/AXI Bus.
- When cleared, the Receive Timestamp Valid IRQ is blocked from generating an interrupt.
(Default: 1’b0) | +| 0 | TX_TIMESTAMP_IRQ_ENABLE | RW | 0 | Transmit Timestamp Interrupt Enable
- When set, enables the Transmit Timestamp IRQ to trigger an interrupt on the AHB/AXI Bus.
- When cleared, the Transmit Timestamp Valid IRQ is blocked from generating an interrupt.
(Default: 1’b0) | #### AVB Control Register The AVB Control Register configures and controls the operation of the AVB Transmit and Receive interface. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0400
BitsFieldTypeResetDescription
31:16ReservedReserved for future use
15:8AVB_TX_THRESHOLDRW0x0AVB Transmit Threshold Register
- This register defines the transmit threshold for the AVB Transmit interface.
- It sets the txavb_afull signal based on empty locations in the transmit buffer.
- The programmed value determines the number of txavb_vld strobes that can be asserted after txavb_afull is triggered.
(Default: 8’h00)
7:5ReservedReserved for future use
4AVB_RX_INTF_ENABLERW0Enable AVB Receive Interface
- When set, the AVB Receive Interface is activated to process AVB frames.
- Received AVB frames are forwarded to the AVB receive interface.
- When cleared, the AVB Receive Interface is disabled, and no frames are identified.
- For proper operation, enable this bit before receiving traffic.
(Default: 1’b0)
3:1ReservedReserved for future use
0AVB_TX_INTF_ENABLERW0Enable AVB Transmit Interface
- When set:
1. The AVB Transmit Interface is activated, prioritizing frames for transmission via TX_FIFO.
2. Frames are transmitted using the Credit-Based Shaper Algorithm.
- When cleared:
1. The AVB Transmit Interface is disabled, and no frames are dequeued.
2. The Transmit FIFO on the AVB interface is cleared.
For proper operation, enable this bit before sending traffic.
(Default: 1’b0)
+**Offset: 0x0400** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | | | Reserved for future use | +| 15:8 | AVB_TX_THRESHOLD | RW | 0x0 | AVB Transmit Threshold Register
- This register defines the transmit threshold for the AVB Transmit interface.
- It sets the txavb_afull signal based on empty locations in the transmit buffer.
- The programmed value determines the number of txavb_vld strobes that can be asserted after txavb_afull is triggered.
(Default: 8’h00) | +| 7:5 | Reserved | | | Reserved for future use | +| 4 | AVB_RX_INTF_ENABLE | RW | 0 | Enable AVB Receive Interface
- When set, the AVB Receive Interface is activated to process AVB frames.
- Received AVB frames are forwarded to the AVB receive interface.
- When cleared, the AVB Receive Interface is disabled, and no frames are identified.
- For proper operation, enable this bit before receiving traffic.
(Default: 1’b0) | +| 3:1 | Reserved | | | Reserved for future use | +| 0 | AVB_TX_INTF_ENABLE | RW | 0 | Enable AVB Transmit Interface
- When set:
1. The AVB Transmit Interface is activated, prioritizing frames for transmission via TX_FIFO.
2. Frames are transmitted using the Credit-Based Shaper Algorithm.
- When cleared:
1. The AVB Transmit Interface is disabled, and no frames are dequeued.
2. The Transmit FIFO on the AVB interface is cleared.
For proper operation, enable this bit before sending traffic.
(Default: 1’b0) | #### AVB Transmit SendSlope Register @@ -5469,34 +2029,12 @@ This register configures the _SendSlope_ variable, as defined by IEEE 802.1Qav. It is used by the Rate Shaper to control the credit decrease rate. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0404
BitsFieldTypeResetDescription
31:20ReservedReserved for future use
19:0SEND_SLOPERW0x800SendSlope
- The SendSlope variable, defined in IEEE 802.1Qav, represents the credit decrease rate in bits per second.
- It is used by the Traffic Shaper to decrement the bucket value when AVB traffic is transmitted.
(Default: 20’h00800)
+**Offset: 0x0404** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:20 | Reserved | | | Reserved for future use | +| 19:0 | SEND_SLOPE | RW | 0x800 | SendSlope
- The SendSlope variable, defined in IEEE 802.1Qav, represents the credit decrease rate in bits per second.
- It is used by the Traffic Shaper to decrement the bucket value when AVB traffic is transmitted.
(Default: 20’h00800) | #### AVB Transmit IdleSlope Register @@ -5504,60 +2042,22 @@ This register configures the _IdleSlope_ variable, as defined by IEEE 802.1Qav. It is used by the Rate Shaper to control the idle rate. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0408
BitsFieldTypeResetDescription
31:20ReservedReserved for future use
19:0IDLE_SLOPERW0x1800IdleSlope
- The IdleSlope variable, defined in IEEE 802.1Qav, represents the credit increase rate in bits per second.
- It is used by the Traffic Shaper to decrement the bucket value when legacy traffic is transmitted and AVB traffic is queued.
(Default: 20’h01800)
+**Offset: 0x0408** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:20 | Reserved | | | Reserved for future use | +| 19:0 | IDLE_SLOPE | RW | 0x1800 | IdleSlope
- The IdleSlope variable, defined in IEEE 802.1Qav, represents the credit increase rate in bits per second.
- It is used by the Traffic Shaper to decrement the bucket value when legacy traffic is transmitted and AVB traffic is queued.
(Default: 20’h01800) | #### AVB RxPacket Filter1 Register This register is used to program the filter value that is used to identify AVB traffic on the receive path. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0410
BitsFieldTypeResetDescription
31:0RX_FILTER1RW0x0Filter1
- The value programmed in this register is compared against the extracted VLAN_TAG and ID fields. It helps identify AVB traffic on the receive path.
- When the corresponding bit in the Mask register is 1, that bit is used for comparison with the received value.
- For example,
1. To identify packets with a PCP (Priority Code Point) of 2 and a VLAN_ID of 2, program the value 0x8100_4002 in this register.
(Default: 0x0000_0000)
+**Offset: 0x0410** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RX_FILTER1 | RW | 0x0 | Filter1
- The value programmed in this register is compared against the extracted VLAN_TAG and ID fields. It helps identify AVB traffic on the receive path.
- When the corresponding bit in the Mask register is 1, that bit is used for comparison with the received value.
- For example,
1. To identify packets with a PCP (Priority Code Point) of 2 and a VLAN_ID of 2, program the value 0x8100_4002 in this register.
(Default: 0x0000_0000) | #### AVB RxPacket Mask1 Register @@ -5565,53 +2065,21 @@ This register is used to program the mask value. - This mask enables the Filter1 value for identifying AVB traffic on the receive path - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0414
BitsFieldTypeResetDescription
31:0RX_MASK1RW0x0Mask1
- The Mask1 register is a bit-to-bit mask for the Filter1 register.
- When the Mask bit is 1, the corresponding bit in the Filter1 register is used for comparison against the received VLAN TAG/ID field.
- When the Mask bit is 0, the corresponding bit in Filter1 is ignored.
- To compare the full 32-bit VLAN_TAG/ID field, program this register to 0xFFFF_FFFF.
(Default: 0x0000_0000)
+**Offset: 0x0414** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RX_MASK1 | RW | 0x0 | Mask1
- The Mask1 register is a bit-to-bit mask for the Filter1 register.
- When the Mask bit is 1, the corresponding bit in the Filter1 register is used for comparison against the received VLAN TAG/ID field.
- When the Mask bit is 0, the corresponding bit in Filter1 is ignored.
- To compare the full 32-bit VLAN_TAG/ID field, program this register to 0xFFFF_FFFF.
(Default: 0x0000_0000) | #### AVB RxPacket Filter2 Register This register is used to program the filter value that is used to identify AVB traffic on the receive path. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0418
BitsFieldTypeResetDescription
31:0RX_FILTER2RW0x0Filter2
- The value programmed in this register is compared against the extracted VLAN_TAG and ID fields. It helps identify AVB traffic on the receive path.
- When the corresponding bit in the Mask register is 1, that bit is used for comparison with the received value.
- For example,
1. To identify packets with a PCP (Priority Code Point) of 3 and a VLAN_ID of 2, program the value 0x8100_6002 in this register.
(Default: 0x0000_0000)
+**Offset: 0x0418** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RX_FILTER2 | RW | 0x0 | Filter2
- The value programmed in this register is compared against the extracted VLAN_TAG and ID fields. It helps identify AVB traffic on the receive path.
- When the corresponding bit in the Mask register is 1, that bit is used for comparison with the received value.
- For example,
1. To identify packets with a PCP (Priority Code Point) of 3 and a VLAN_ID of 2, program the value 0x8100_6002 in this register.
(Default: 0x0000_0000) | #### AVB RxPacket Mask2 Register @@ -5619,50 +2087,18 @@ This register is used to program the mask value. - This mask enables the Filter2 value for identifying AVB traffic on the receive path - - - - - - - - - - - - - - - - - - - - -
Offset: 0x041C
BitsFieldTypeResetDescription
31:0RX_MASK2RW0x0Mask2
- The Mask2 register is a bit-to-bit mask for the Filter2 register.
- When the Mask bit is 1, the corresponding bit in the Filter2 register is used for comparison against the received VLAN TAG/ID field.
- When the Mask bit is 0, the corresponding bit in Filter12 is ignored.
- To compare the full 32-bit VLAN_TAG/ID field, program this register to 0xFFFF_FFFF.
(Default: 0x0000_0000)
+**Offset: 0x041C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RX_MASK2 | RW | 0x0 | Mask2
- The Mask2 register is a bit-to-bit mask for the Filter2 register.
- When the Mask bit is 1, the corresponding bit in the Filter2 register is used for comparison against the received VLAN TAG/ID field.
- When the Mask bit is 0, the corresponding bit in Filter12 is ignored.
- To compare the full 32-bit VLAN_TAG/ID field, program this register to 0xFFFF_FFFF.
(Default: 0x0000_0000) | #### AVB HiLimit Register This register is used to program the High Limit value for the credits that are accumulated when the legacy traffic is transmitted. This value is determined based on the MaxFrameSize of the Legacy Traffic. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0420
BitsFieldTypeResetDescription
31:0HI_LIMTRW0xF0000000HiLimit
- This field defines the maximum accumulated credits when legacy traffic is transmitted.
- It limits AV frame bursts.
- It is based on the MaxFrameSize of legacy frames.
(Default: 0xF000_0000, based on 2000-byte Max Frame Size)
+**Offset: 0x0420** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | HI_LIMT | RW | 0xF0000000 | HiLimit
- This field defines the maximum accumulated credits when legacy traffic is transmitted.
- It limits AV frame bursts.
- It is based on the MaxFrameSize of legacy frames.
(Default: 0xF000_0000, based on 2000-byte Max Frame Size) | diff --git a/en/key_stone/k1/k1_docs/k1_usermanual/16.Low-Speed_Interface_System.md b/en/key_stone/k1/k1_docs/k1_usermanual/16.Low-Speed_Interface_System.md index 7d4e5c3..6e86f83 100644 --- a/en/key_stone/k1/k1_docs/k1_usermanual/16.Low-Speed_Interface_System.md +++ b/en/key_stone/k1/k1_docs/k1_usermanual/16.Low-Speed_Interface_System.md @@ -49,50 +49,17 @@ Each device on the I2C bus is identified by a unique 7-bit address and can funct The key I2C terminology is tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
I2C terminologyDefinition
TransmitterSends data over the I2C bus
ReceiverReceives data over the I2C bus
MasterInitiates transfers, generates clock signals, and terminates transactions
SlaveResponds to the master's requests by transmitting or receiving data
Multi-masterAllows multiple masters to control the bus without corrupting messages
ArbitrationEnsures that only one master controls the bus when multiple masters compete. This technique avoids message corruption
AcknowledgeA response by the receiver to the master’s acknowledge clock pulse on SCL
The acknowledge can be either positive (ACK) or negative (NAK)
ACKPositive Acknowledge: The receiver pulls SDA low during the clock pulse
NAKNegative Acknowledge: The receiver keeps SDA high during the clock pulse
+| I2C terminology | Definition | +| --- | --- | +| Transmitter | Sends data over the I2C bus | +| Receiver | Receives data over the I2C bus | +| Master | Initiates transfers, generates clock signals, and terminates transactions | +| Slave | Responds to the master's requests by transmitting or receiving data | +| Multi-master | Allows multiple masters to control the bus without corrupting messages | +| Arbitration | Ensures that only one master controls the bus when multiple masters compete. This technique avoids message corruption | +| Acknowledge | A response by the receiver to the master’s acknowledge clock pulse on SCL
The acknowledge can be either positive (ACK) or negative (NAK) | +| ACK | Positive Acknowledge: The receiver pulls SDA low during the clock pulse | +| NAK | Negative Acknowledge: The receiver keeps SDA high during the clock pulse | #### Block Diagram @@ -186,30 +153,12 @@ I2C transactions can be initiated by the I2C as a master or received by the I2C The I2C unit can accomplish a transfer in different operational modes as summarized below. - - - - - - - - - - - - - - - - - - - - - - - -
Mode Description
Master-Transmit- I2C acts as a master
- Used to transmit operations
- I2C sends the data
- I2C generates the clock
- Slave device is in Slave-Receive mode
Master-Receive- I2C acts as a master
- Used to receive operations
- I2C receives the data
- I2C generates the clock
- Slave device is in Slave-Transmit mode
Slave-Transmit- I2C acts as a slave
- Responds to a master Read operation
- I2C sends the data
- Master device is in Master-Receive mode
Slave-Receive (default)- I2C acts as a slave
- Responds to a master Write operation
- I2C receives the data
- Master device is in Master-Transmit mode
+| Mode | Description | +| --- | --- | +| Master-Transmit | - I2C acts as a master
- Used to transmit operations
- I2C sends the data
- I2C generates the clock
- Slave device is in Slave-Receive mode | +| Master-Receive | - I2C acts as a master
- Used to receive operations
- I2C receives the data
- I2C generates the clock
- Slave device is in Slave-Transmit mode | +| Slave-Transmit | - I2C acts as a slave
- Responds to a master Read operation
- I2C sends the data
- Master device is in Master-Receive mode | +| Slave-Receive (default) | - I2C acts as a slave
- Responds to a master Write operation
- I2C receives the data
- Master device is in Master-Transmit mode | ##### Default Mode: Slave-Receive @@ -263,34 +212,11 @@ The I2C unit uses the ICR[START] and ICR[STOP] bits to: The definitions of the START and STOP bits in the ICR are tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
STOP BitSTART BitCondition Notes
00No Start or Stop- Used for continuous data transfer without sending a Start or Stop condition.
01Start condition and repeated StartStarting condition:
- The I2C sends a Start condition and transmits the IDBR 8-bit contents.
- IDBR must contain the 7-bit slave address and the R/nW bit before a Start is initiated.
For a repeated start:
- The IDBR contains the target slave address and the R/nW bit.
- Allows the master to perform multiple transfers to different slaves without releasing the bus.
- The interface stays in Master-Transmit mode for Writes and switches to Master-Receive mode for Reads.
1XStop conditionIn Master-Transmit mode:
- the I2C transmits the IDBR 8-bit contents and sends a Stop condition on the I2C bus.
In Master-Receive mode:
- ICR[ACKNAK] must be set to define a Negative-Acknowledge (NAK) pulse.
- The I2C transmits the NAK pulse, places the received data byte into the IDBR, and sends a Stop condition on the I2C bus.
+| STOP Bit | START Bit | Condition | Notes | +| --- | --- | --- | --- | +| 0 | 0 | No Start or Stop | - Used for continuous data transfer without sending a Start or Stop condition. | +| 0 | 1 | Start condition and repeated Start | Starting condition:
- The I2C sends a Start condition and transmits the IDBR 8-bit contents.
- IDBR must contain the 7-bit slave address and the R/nW bit before a Start is initiated.
For a repeated start:
- The IDBR contains the target slave address and the R/nW bit.
- Allows the master to perform multiple transfers to different slaves without releasing the bus.
- The interface stays in Master-Transmit mode for Writes and switches to Master-Receive mode for Reads. | +| 1 | X | Stop condition | In Master-Transmit mode:
- the I2C transmits the IDBR 8-bit contents and sends a Stop condition on the I2C bus.
In Master-Receive mode:
- ICR[ACKNAK] must be set to define a Negative-Acknowledge (NAK) pulse.
- The I2C transmits the NAK pulse, places the received data byte into the IDBR, and sends a Stop condition on the I2C bus. | The Start and Stop Conditions of I2C are depicted below. @@ -311,14 +237,14 @@ The Start and Stop Conditions of I2C are depicted below. - **Software Preparation**: - Load the target slave address and the R/nW bit into the IDBR. - + - **Transmission:** - Set ICR[TB] to transmit the Start condition and the IDBR contents on the I2C bus. - + - **Mode Transition:** - For Write requests: The I2C bus remains in Master-Transmit mode. - For Read requests: The I2C bus switches to Master-Receive mode. - + - **Repeated Start:** - Used to change the R/nW bit or the target slave address without releasing the bus. - The IDBR must contain the updated slave address and R/nW bit. @@ -347,16 +273,16 @@ The Start and Stop Conditions of I2C are depicted below. - **Data Transfer:** - Software writes a data byte to the IDBR. - The I2C sets ISR[ITE] and clears ICR[TB]. - + - **Next Byte:** - Software writes the next byte to the IDBR and sets ICR[TB] to initiate the next byte transmission. - + - **Continuation:** - This process repeats until software sets ICR[START] or ICR[STOP]. - + - **Acknowledge Pulse:** - The I2C issues an ACK/NAK as defined by ICR[ACKNAK]. - + - **Wait States:** - After each byte transfer (including the acknowledge pulse), the I2C holds the SCL line low to insert wait states until ICR[TB] is set. - This allows software to prepare the next byte for transmission. @@ -383,7 +309,7 @@ The Stop condition (ICR[START]=X, ICR[STOP]=1) terminates a data transfer. In Ma - **Master-Transmit Mode:** - Set ICR[STOP] and ICR[TB] to initiate the last byte transfer. - The I2C transmits the IDBR contents and sends a Stop condition. - + - **Master-Receive Mode:** - Set ICR[ACKNAK] to define a Negative-Acknowledge (NAK) pulse. - Set ICR[STOP] and ICR[TB] to initiate the last transfer. @@ -420,17 +346,17 @@ The I2C Data Buffer register (IDBR) and the I2C Slave Address register (ISAR) ar ##### Master or Slave Transmit Mode - **Data Transmission:** - + - **Software Writes Data:** - Software writes data to the IDBR over the internal bus - This initiates a master transaction or sends the next data byte after ISR[ITE] is set - + - **I2C Transmits Data:** - The I2C transmits data from the IDBR when ICR[TB] is set - + - **Interrupts:** - If ICR[ITEIE] is set, an IDBR transmit-empty interrupt is signaled when a byte is transferred and the acknowledge cycle is complete - + - **Wait States:** - If the I2C is ready to transfer the next byte but the CPU has not written to the IDBR, the I2C inserts wait states until the CPU writes a new value to the IDBR and sets ICR[TB] @@ -443,11 +369,11 @@ In FIFO mode, software writes control + data information to the TX FIFO instead - **Data Reception:** - **Software Reads Data**: Software reads data from the IDBR over the internal bus after the IDBR receive-full interrupt is signaled (if ICR[DRFIE] is set) - + - **I2C Transfers Data:** The I2C transfers data from the Shift register to the IDBR after the acknowledge cycle completes - + - **Wait States: **The I2C inserts wait states until the IDBR is read by the CPU - + - **Next Byte Transfer:** After the CPU reads the IDBR, the I2C unit updates the ICR[ACKNAK] and ICR[TB] bits, allowing the next byte transfer to proceed - **FIFO Mode:** @@ -535,12 +461,12 @@ Every I2C byte transfer must be accompanied by an acknowledge (ACK) pulse that t - The I2C sends a negative-acknowledge (NAK) pulse to signal the slave transmitter to stop sending data - The ICR[ACKNAK] bit controls the ACK/NAK pulse value driven onto the I2C bus -**Procedure: ** +**Procedure:** - The master receives a byte from the slave - The I2C automatically transmits the ACK pulse after receiving each byte from the serial bus, unless it is the last bytes - Before receiving the last byte, software must set ICR[ACKNAK] to generate a NAK -- The NAK pulse is sent after the last byte has been sent, to signals the end of data reception (and to stop sending data) +- The NAK pulse is sent after the last byte has been sent, to signals the end of data reception (and to stop sending data) > **Note****. **As required by the I2C bus protocol, ISR[BED] is not set for a Master-Receive mode NAK @@ -600,7 +526,7 @@ Clock Synchronization Mechanism (as depicted below)**:** - Clock synchronization is achieved through the **wired-AND connection** of the I2C devices to the SCL line. - **High to Low Transition**: When a master's clock transitions from **high to low**, it holds the SCL line for its own clock period. -- **Low to High Transition**: A clock cannot switch from **low to high** until all masters complete their low periods. +- **Low to High Transition**: A clock cannot switch from **low to high** until all masters complete their low periods. - The master with the **longest** low period holds the SCL line low. Masters with shorter low periods enter a **high wait-state** until the master with the longest low period completes. - Once the master with the longest low period completes, the **SCL line** transitions to high, and other masters with shorter periods can continue their data cycles. The master with the longest clock period controls the SCL line, ensuring synchronized data transfer. @@ -615,7 +541,7 @@ Arbitration on the **SDA (Serial Data Line)** can extend over a significant dura ###### Address & R/nW Checking -- **Condition 1:**,If the **address** and **R/nW bit** transmitted by multiple masters are identical, arbitration proceeds to the **data bits**. +- **Condition 1:** If the **address** and **R/nW bit** transmitted by multiple masters are identical, arbitration proceeds to the **data bits**. - Due to the **wired-AND nature** of the I2C bus, no data is lost if multiple masters signal the same bus states. - **Condition 2:** If the **address**, **R/nW bit**, or **data** differ, the master that transmits the first **high data bit** loses arbitration. @@ -724,7 +650,7 @@ After the master receives an ACK, the I2C enters 1 of 2 Master modes: When transmitting the master code, the master should receive a NAK and then enter HS-mode. The 7-bit slave address and the R/nW bit follow a repeated Start condition. The master receives an ACK and the I2C unit enters 1 of 2 Master modes listed above. -The CPU writes to the ICR register to initiate a master transaction. Data is read and written from the I2C unit through the memory-mapped registers. The I2C unit responsibilities as a master device are tabled below. +The CPU writes to the ICR register to initiate a master transaction. Data is read and written from the I2C unit through the memory-mapped registers. The I2C unit responsibilities as a master device are tabled below. | I2C Master Action | Mode of Operation | Definition | |--------------------------------------|----------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| @@ -739,7 +665,7 @@ The CPU writes to the ICR register to initiate a master transaction. Data is rea | Read one byte of I2C data from the IDBR | Master-receive only | Eight bits are read from the serial bus, collected in the Shift register, then transferred to the IDBR after the ICR[ACKNAK] bit is read.
- The CPU reads the IDBR when ISR[IRF] is set and ICR[TB] is clear. If the IDBR receive-full interrupt is enabled, it is signalled to the CPU.
- When the IDBR is read, if ISR[ACKNAK] is clear (indicating ACK), the software must clear the ICR[ACKNAK] bit and set ICR[TB] to initiate the next byte Read.
- If ISR[ACKNAK] is set (indicating NAK), ICR[TB] is clear, ICR[STOP] is set, and ISR[UB] is set, then the last data byte has been read into the IDBR, and the I2C is sending the Stop.
- If ISR[ACKNAK] is set (indicating NAK) and ICR[TB] is clear, but ICR[STOP] is clear, then the software has 2 options:
 1. Set ICR[START], write a new target address to the IDBR, and set ICR[TB], which sends a repeated Start.
 2. Set ICR[MA] and leave ICR[TB] clear, which sends a Stop only. | | Transmit acknowledge to slave transmitter | Master-receive only | - As a master receiver, the JINDIE I2C generates the clock for the acknowledge pulse and drives the SDA line during the acknowledge cycle.
- If the next data byte is to be the last transaction, the user software sets ICR[ACKNAK] for NAK generation.
See Section [I2C Acknowledge](#i2c-acknowledge). | | Generate a repeated Start to chain I2C transactions | Master-transmit Master-receive | Data chaining takes place by using a repeated Start condition instead of a Stop condition.
- The repeated Start is generated after the last data byte of a transaction has been transmitted on the I2C bus, as described in Section [Data Transfer Sequence](#data-transfer-sequence).
- The software must write the next target slave address and the R/nW bit to the IDBR, sets ICR[START], and sets ICR[TB].
See Section [Start and Stop Bus States](#start--stop-bus-states) in this chapter | -| Generate a Stop | Master-transmit Master-receive | - A Stop is generated after the last data byte of a transaction has been transmitted on the I2C bus, as described in Section [Data Transfer Sequence](#data-transfer-sequence).
- ICR[STOP] must be set in order to generate the Stop condition.
See See Section [Start and Stop Bus States](#start--stop-bus-states) in this chapter. | +| Generate a Stop | Master-transmit Master-receive | - A Stop is generated after the last data byte of a transaction has been transmitted on the I2C bus, as described in Section [Data Transfer Sequence](#data-transfer-sequence).
- ICR[STOP] must be set in order to generate the Stop condition.
See Section [Start and Stop Bus States](#start--stop-bus-states) in this chapter. | #### FIFO mode @@ -980,8 +906,8 @@ Before each of the I2C modules has been initialized, set the clock: 10. If the RX FIFO ever becomes half full during this sequence it sends a RX FIFO Half Full DMA request to the DMA 11. DMA reads the RX FIFO contents 12. After receiving a TXDONE interrupt, if there are any trailing bytes (Only for Read Transactions) it is up to the software to handle them. The hardware does not handle trailing bytes. -13. Each entry in the Tx FIFO has the format as shown in Figure-9 - . The LSB 8 bits are for data and the MSB 4 bits are for control bits. For a Write transaction, data consists of the Slave address followed by actual Write data.The control bits are nothing but ICR[3:0] bits. -14. For a Read transaction, Data consists of the Slave address followed by dummy data (actual Read data from the slave goes into the Rx FIFO). Again, the control bits are ICR[3:0] bits. +13. Each entry in the Tx FIFO has the format as shown in Figure-9 - . The LSB 8 bits are for data and the MSB 4 bits are for control bits. For a Write transaction, data consists of the Slave address followed by actual Write data. The control bits are nothing but ICR[3:0] bits. +14. For a Read transaction, Data consists of the Slave address followed by dummy data (actual Read data from the slave goes into the Rx FIFO). Again, the control bits are ICR[3:0] bits. ##### FIFO Programming Examples @@ -1015,7 +941,7 @@ Each entry in the Tx FIFO has a control word concatenated with Address/Data byte 2. The core/DMA then writes 1 Addr + 7 Data Bytes to the TX FIFO (control word + dummy data since it is a Read transaction). 3. After the address is sent out on the bus, for each control word, a Read byte is received and saved off in the Rx FIFO. Once the Tx FIFO is empty (mote that there are 7 bytes in the Rx FIFO by now), an interrupt/DMA request is made and the remaining bytes (1 data byte from Read transaction and 3 bytes from the next Write transaction) are loaded into the Tx FIFO. 4. After the 8 byte is received into the Rx FIFO, the Rx FIFO Half full interrupt/DMA request is set. This Read data now needs to be read out of the FIFO. -5. By now, the Read transaction is also done. But since there is NO stop bit after the Read and instead Repeated Start is used for the Write Transaction, the ISR[TX_DONE] status bit is NOT set as it would have normally been set at the end of a transaction. +5. By now, the Read transaction is also done. But since there is NO stop bit after the Read and instead Repeated Start is used for the Write Transaction, the ISR[TX_DONE] status bit is NOT set as it would have normally been set at the end of a transaction. 6. I2C now starts the Write transaction by sending out the Address followed by the 2 Write bytes. 7. Once the Write transaction is done, ICR[TX_BEGIN] is automatically cleared and ISR[TX_DONE] bit is set, which generates an interrupt to the core. @@ -1157,296 +1083,64 @@ To reset the I2C unit using the **ICR** register, follow these steps: > **Note.** The base address of I2C registers are tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameAddress
SHUB_I2C_BASE 0xC0887000
I2C0_BASE0xD4010800
I2C1_BASE0xD4011000
I2C2_BASE 0xD4012000
I2C3_BASE(SEC_I2C)0xF0614000
I2C4_BASE 0xD4012800
I2C5_BASE 0xD4013800
I2C6_BASE 0xD4018800
I2C7_BASE 0xD401d000
I2C8_BASE (PWR_I2C)0xD401d800
+| Name | Address | +| --- | --- | +| SHUB_I2C_BASE | 0xC0887000 | +| I2C0_BASE | 0xD4010800 | +| I2C1_BASE | 0xD4011000 | +| I2C2_BASE | 0xD4012000 | +| I2C3_BASE(SEC_I2C) | 0xF0614000 | +| I2C4_BASE | 0xD4012800 | +| I2C5_BASE | 0xD4013800 | +| I2C6_BASE | 0xD4018800 | +| I2C7_BASE | 0xD401d000 | +| I2C8_BASE (PWR_I2C) | 0xD401d800 | #### ICR REGISTER The bits in the I2C Control register (ICR) are used to control the I2C unit. These are read/write registers. Ignore reads from reserved bits. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31RXOV_IER/W
0x0Receive FIFO overrun Interrupt Enable.
0: Receive FIFO overrun (ISR[RXOV]) interrupt is not enabled;
1: Receive FIFO overrun (ISR[RXOV]) interrupt is enabled.
30RXF_IER/W0x0Receive FIFO full Interrupt Enable.
0: Receive FIFO full (ISR[RXF]) interrupt is not enabled;
1: Receive FIFO full (ISR[RXF]) interrupt is enabled.
29RXHF_IER/W0x0Receive FIFO half full Interrupt Enable.
0: Receive FIFO half full (ISR[RXHF]) interrupt is not enabled;
1: Receive FIFO half full (ISR[RXHF]) interrupt is enabled.
28TXE_IER/W0x0Transmit FIFO empty Interrupt Enable.
0: Transmit FIFO empty (ISR[TXE]) interrupt is not enabled;
1: Transmit FIFO empty (ISR[TXE]) interrupt is enabled.
27TXDONE_IER/W0x0Transaction Done Interrupt Enable.
0: Transaction done (ISR[TXD]) interrupt is not enabled.;
1: Transaction done (ISR[TXD]) interrupt is enabled.
26MSDER/W0x0Master Stop Detected Enable:
0: Master Stop Detect (ISR[MSD]) status is not enabled.
1: Master Stop Detect (ISR[MSD]) status is enabled.
25MSDIER/W0x0Master Stop Detected Interrupt Enable:
0: Disable interrupt.
1: Enables the I2C unit to interrupt the upon detecting a Master Stop sent by the I2C unit.
24SSDIER/W0x0Slave Stop Detected Interrupt Enable:
0: Disable interrupt.
1: Enables the I2C to interrupt the when it detects a Stop condition while in slave mode.
23SADIER/W0x0Slave Address Detected Interrupt Enable:
0: Disable interrupt.
1: Enables the I2C to interrupt the upon detecting a slave address match or a general call address.
22BEIER/W0x0Bus Error Interrupt Enable:
0: Disable interrupt.
1: Enables the I2C to interrupt the for the following I2C bus errors:
21GCDR/W0x0General Call Disable:
0: Enable the I2C to respond to general call messages.
1: Disable I2C response to general call messages as a slave.
This bit must be set when sending a master mode general call message from the I2C.
20DRFIER/W0x0DBR Receive Full Interrupt Enable:
0: Disable interrupt.
1: Enables the I2C to interrupt the when the IDBR has received a data byte from the I2C bus.
19ITEIER/W0x0IDBR Transmit Empty Interrupt Enable:
0: Disable interrupt
1: Enables the I2C to interrupt the after transmitting a byte onto the I2C bus
18ALDIER/W0x0Arbitration Loss Detected Interrupt Enable:
0: Disable interrupt.
1: Enables the I2C to interrupt the upon losing arbitration while in master mode.
17CURSRC_FIX_BYPASSR/W0x0Bypass the cursrc fix :
0: cursrc fix effective
1: bypass the cursrc fix
16HS_STRETCH_FIX_BYPASSR/W0x0Bypass the hs stretch fix :
0: hs stretch fix effective
1: bypass the hs stretch fix
15RSVDR0Reserved for future use
14IUER/W0x0I2C Unit Enable:
0: Disables the unit and does not master any transactions or respond to any slave transactions.
1: Enables the I2C (defaults to slave-receive mode).
Software must ensure the I2C bus is idle before setting this bit. Software must ensure that the internal clock to the I2C unit is enabled (D0CKEN_B[4] must be set) before setting or clearing this bit.
13SCLER/W0x0SCL Enable:
0: Disables the I2C from driving the SCL line.
1: Enables the I2C clock output for master-mode operation.
12MAR/W0x0Master Abort:
Used by the I2C in master mode to generate a Stop without transmitting another data byte:
0: The I2C transmits Stop on if ICR[STOP] is set.
1: The I2C sends Stop without data transmission.
In Master-Transmit Mode:
- After transmitting a data byte:
1. The ICR[TB] bit is cleared.
2. The IDBR[ITE] bit is set.
- When no more data needs to be sent:
1. Set the Master Abort (MA) bit to send a Stop condition.
2. Ensure the ICR[TB] bit remains clear during this operation.
In Master-Receive Mode:
- If a NAK is sent without a Stop (because ICR[STOP] was not set) and the unit does not send a repeated Start:
1. Setting the MA bit forces a Stop.
2. Again, the ICR[TB] bit must remain clear.
11I2C_BUS_RESET_REQ_R/W0x0 The I2C will do bus reset upon this bit set.this bit is self-cleared
10URR/W0x0Unit Reset
0: No reset
1: Reset the I2C only
9:8MODER/W0x2Bus Mode (Master operation):
00: Standard-mode: Supports up to 100 Kbps
01: Fast-mode: Supports up to 400 Kbps
10: High-speed (HS) mode: Supports up to 3.3 Mbps in master mode and 3.4 Mbps in slave mode; operates in Standard mode when not performing a high-speed transfer.
11: High-speed (HS) mode: Supports up to 3.3 Mbps in master mode and 3.4 Mbps in slave mode; operates in Fast mode when not performing a high-speed transfer.

Bus Mode (Slave operation):
0X: HS-mode Disabled: I2C unit uses Standard/Fast mode timing on the SDA pin.
1X: HS-mode Enabled: I2C unit uses HS-mode timing on the SDA pin when a master code is received.
7DMA_ENR/W0x0DMA Enable for both TX and RX FIFOs:
0: DMA mode is NOT enabled;
1: DMA mode enabled;
6GPIOENR/W0x0GPIO mode Enable for SCL during HS mode.
0: GPIO mode disabled: SCL operates as an open-collector output.
1: GPIO mode enabled: SCL is directly driven by the I2C unit.
5FIFOENR/W0x0FIFO mode:
0: FIFO mode disabled; Data is read from or written to the IDBR directly.
1: FIFO mode enabled; Data is managed through the Transmit and Receive FIFOs.
4TXBEGINR/W0x0Transaction Begin
Set this for a new Transaction only after ISR[TXDONE] is set:
0: No transaction starting;
1: A new transaction begins.
This is cleared by the hardware at the end of each transaction after a STOP bit is sent out.
The software has to set it again to start a new transaction.
3TBR/W0x0Transfer Byte:
Used to send or receive a byte on the I2C bus:
0: Cleared by I2C when the byte is sent/received.
1: Send/receive a byte.
Monitoring this bit can determine when the byte transfer has completed.
In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set.
2ACKNAKR/W0x0The positive/negative acknowledge control bit, ACK/NAK, defines the type of acknowledge pulse sent by the I2C when in master receive mode:
0: Send a positive acknowledge (ACK) pulse after receiving a data byte;
1: Send a negative acknowledge (NAK) pulse after receiving a data byte.
The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the ACKNAK control-bit setting.
1STOPR/W0x0Stop
Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode.
In master-receive mode, the ACKNAK control bit must be set in conjunction with the STOP bit.
0: Do not send a Stop.
1: Send a Stop.
0STARTR/W0x0Start
Used to initiate a Start condition to the I2C unit when in master mode.
0: Do not send a Start pulse.
1: Send a Start pulse.
+**Offset: 0x0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | RXOV_IE | R/W | 0x0 | Receive FIFO overrun Interrupt Enable.
0: Receive FIFO overrun (ISR[RXOV]) interrupt is not enabled;
1: Receive FIFO overrun (ISR[RXOV]) interrupt is enabled. | +| 30 | RXF_IE | R/W | 0x0 | Receive FIFO full Interrupt Enable.
0: Receive FIFO full (ISR[RXF]) interrupt is not enabled;
1: Receive FIFO full (ISR[RXF]) interrupt is enabled. | +| 29 | RXHF_IE | R/W | 0x0 | Receive FIFO half full Interrupt Enable.
0: Receive FIFO half full (ISR[RXHF]) interrupt is not enabled;
1: Receive FIFO half full (ISR[RXHF]) interrupt is enabled. | +| 28 | TXE_IE | R/W | 0x0 | Transmit FIFO empty Interrupt Enable.
0: Transmit FIFO empty (ISR[TXE]) interrupt is not enabled;
1: Transmit FIFO empty (ISR[TXE]) interrupt is enabled. | +| 27 | TXDONE_IE | R/W | 0x0 | Transaction Done Interrupt Enable.
0: Transaction done (ISR[TXD]) interrupt is not enabled.;
1: Transaction done (ISR[TXD]) interrupt is enabled. | +| 26 | MSDE | R/W | 0x0 | Master Stop Detected Enable:
0: Master Stop Detect (ISR[MSD]) status is not enabled.
1: Master Stop Detect (ISR[MSD]) status is enabled. | +| 25 | MSDIE | R/W | 0x0 | Master Stop Detected Interrupt Enable:
0: Disable interrupt.
1: Enables the I2C unit to interrupt the upon detecting a Master Stop sent by the I2C unit. | +| 24 | SSDIE | R/W | 0x0 | Slave Stop Detected Interrupt Enable:
0: Disable interrupt.
1: Enables the I2C to interrupt the when it detects a Stop condition while in slave mode. | +| 23 | SADIE | R/W | 0x0 | Slave Address Detected Interrupt Enable:
0: Disable interrupt.
1: Enables the I2C to interrupt the upon detecting a slave address match or a general call address. | +| 22 | BEIE | R/W | 0x0 | Bus Error Interrupt Enable:
0: Disable interrupt.
1: Enables the I2C to interrupt the for the following I2C bus errors: | +| 21 | GCD | R/W | 0x0 | General Call Disable:
0: Enable the I2C to respond to general call messages.
1: Disable I2C response to general call messages as a slave.
This bit must be set when sending a master mode general call message from the I2C. | +| 20 | DRFIE | R/W | 0x0 | DBR Receive Full Interrupt Enable:
0: Disable interrupt.
1: Enables the I2C to interrupt the when the IDBR has received a data byte from the I2C bus. | +| 19 | ITEIE | R/W | 0x0 | IDBR Transmit Empty Interrupt Enable:
0: Disable interrupt
1: Enables the I2C to interrupt the after transmitting a byte onto the I2C bus | +| 18 | ALDIE | R/W | 0x0 | Arbitration Loss Detected Interrupt Enable:
0: Disable interrupt.
1: Enables the I2C to interrupt the upon losing arbitration while in master mode. | +| 17 | CURSRC_FIX_BYPASS | R/W | 0x0 | Bypass the cursrc fix:
0: cursrc fix effective
1: bypass the cursrc fix | +| 16 | HS_STRETCH_FIX_BYPASS | R/W | 0x0 | Bypass the hs stretch fix:
0: hs stretch fix effective
1: bypass the hs stretch fix | +| 15 | RSVD | R | 0 | Reserved for future use | +| 14 | IUE | R/W | 0x0 | I2C Unit Enable:
0: Disables the unit and does not master any transactions or respond to any slave transactions.
1: Enables the I2C (defaults to slave-receive mode).
Software must ensure the I2C bus is idle before setting this bit. Software must ensure that the internal clock to the I2C unit is enabled (D0CKEN_B[4] must be set) before setting or clearing this bit. | +| 13 | SCLE | R/W | 0x0 | SCL Enable:
0: Disables the I2C from driving the SCL line.
1: Enables the I2C clock output for master-mode operation. | +| 12 | MA | R/W | 0x0 | Master Abort:
Used by the I2C in master mode to generate a Stop without transmitting another data byte:
0: The I2C transmits Stop on if ICR[STOP] is set.
1: The I2C sends Stop without data transmission.
In Master-Transmit Mode:
- After transmitting a data byte:
1. The ICR[TB] bit is cleared.
2. The IDBR[ITE] bit is set.
- When no more data needs to be sent:
1. Set the Master Abort (MA) bit to send a Stop condition.
2. Ensure the ICR[TB] bit remains clear during this operation.
In Master-Receive Mode:
- If a NAK is sent without a Stop (because ICR[STOP] was not set) and the unit does not send a repeated Start:
1. Setting the MA bit forces a Stop.
2. Again, the ICR[TB] bit must remain clear. | +| 11 | I2C_BUS_RESET_REQ_ | R/W | 0x0 | The I2C will do bus reset upon this bit set.this bit is self-cleared | +| 10 | UR | R/W | 0x0 | Unit Reset
0: No reset
1: Reset the I2C only | +| 9:8 | MODE | R/W | 0x2 | Bus Mode (Master operation):
00: Standard-mode: Supports up to 100 Kbps
01: Fast-mode: Supports up to 400 Kbps
10: High-speed (HS) mode: Supports up to 3.3 Mbps in master mode and 3.4 Mbps in slave mode; operates in Standard mode when not performing a high-speed transfer.
11: High-speed (HS) mode: Supports up to 3.3 Mbps in master mode and 3.4 Mbps in slave mode; operates in Fast mode when not performing a high-speed transfer.

Bus Mode (Slave operation):
0X: HS-mode Disabled: I2C unit uses Standard/Fast mode timing on the SDA pin.
1X: HS-mode Enabled: I2C unit uses HS-mode timing on the SDA pin when a master code is received. | +| 7 | DMA_EN | R/W | 0x0 | DMA Enable for both TX and RX FIFOs:
0: DMA mode is NOT enabled;
1: DMA mode enabled; | +| 6 | GPIOEN | R/W | 0x0 | GPIO mode Enable for SCL during HS mode.
0: GPIO mode disabled: SCL operates as an open-collector output.
1: GPIO mode enabled: SCL is directly driven by the I2C unit. | +| 5 | FIFOEN | R/W | 0x0 | FIFO mode:
0: FIFO mode disabled; Data is read from or written to the IDBR directly.
1: FIFO mode enabled; Data is managed through the Transmit and Receive FIFOs. | +| 4 | TXBEGIN | R/W | 0x0 | Transaction Begin
Set this for a new Transaction only after ISR[TXDONE] is set:
0: No transaction starting;
1: A new transaction begins.
This is cleared by the hardware at the end of each transaction after a STOP bit is sent out.
The software has to set it again to start a new transaction. | +| 3 | TB | R/W | 0x0 | Transfer Byte:
Used to send or receive a byte on the I2C bus:
0: Cleared by I2C when the byte is sent/received.
1: Send/receive a byte.
Monitoring this bit can determine when the byte transfer has completed.
In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set. | +| 2 | ACKNAK | R/W | 0x0 | The positive/negative acknowledge control bit, ACK/NAK, defines the type of acknowledge pulse sent by the I2C when in master receive mode:
0: Send a positive acknowledge (ACK) pulse after receiving a data byte;
1: Send a negative acknowledge (NAK) pulse after receiving a data byte.
The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the ACKNAK control-bit setting. | +| 1 | STOP | R/W | 0x0 | Stop
Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode.
In master-receive mode, the ACKNAK control bit must be set in conjunction with the STOP bit.
0: Do not send a Stop.
1: Send a Stop. | +| 0 | START | R/W | 0x0 | Start
Used to initiate a Start condition to the I2C unit when in master mode.
0: Do not send a Start pulse.
1: Send a Start pulse. | #### ISR REGISTER -I2C interrupts are signaled to the interrupt controller by the I2C Interrupt Status register. Software uses the ISR bits to check the status of the I2C unit and bus. ISR bits (bits 9-5) are updated after the ACK/NAK bit has completed on the I2C bus. +I2C interrupts are signaled to the interrupt controller by the I2C Interrupt Status register. Software uses the ISR bits to check the status of the I2C unit and bus. ISR bits (bits 9-5) are updated after the ACK/NAK bit has completed on the I2C bus. -The I2C has transmitted a STOP signal when configured as a master when : +The I2C has transmitted a STOP signal when configured as a master when: - IDBR receive full - IDBR transmit empty @@ -1455,160 +1149,30 @@ The I2C has transmitted a STOP signal when configured as a master when : - Stop condition detect - Arbitration lost - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31RXOVR/W1C0x0Receive FIFO Overrun (Used in FIFO mode) .
0: Transmit FIFO NOT overrun;
1: Transmit FIFO overrun happened.
30RXFR/W1C0x0Receive FIFO Full (Used in FIFO mode).
0: Receive FIFO in NOT full;
1: Receive FIFO is full;
29RXHFR/W1C0x0Receive FIFO Half Full (Used in FIFO mode):
0: Receive FIFO in NOT half full;
1: Receive FIFO is half full.
28TXER/W1C0x0Transmit FIFO Empty (Used in FIFO mode).
0: Transmit FIFO is NOT empty;
1: Transmit FIFO is empty.
27TXDONER/W1C0x0Transaction Done (Used in FIFO mode):
0: Transaction is NOT done.
1: Transaction is done.
26MSDR/W1C0x0Master Stop Detected:
0: No Master Stop Detected.
1: Set when the I2C detects a Stop while in master-receive or master-transmit mode.
25RSVDR0Reserved for future use
24SSDR/W1C0x0Slave Stop Detected:
0: No Stop detected.
1: Set when the I2C detects a Stop while in slave-receive or slave-transmit mode.
23SADR/W1C0x0Slave Address Detected:
0: No slave address was detected.
1: The I2C detected a seven-bit address that matches the general call address or ISAR. An interrupt is signaled when enabled in the ICR.
22BEDR/W1C0x0Bus Error Detected:
0: No error detected.
1: The I2C sets this bit when it detects one of the following error conditions:
- As a master transmitter, no ACK is detected on the interface after a byte is sent.
- As a slave receiver, the I2C generates a NAK pulse.
21GCADR/W1C0x0General Call Address Detected:
0: No general call address received.
1: I2C received a general call address.
20IRFR/W1C0x0IDBR Receive Full:
0: The IDBR has not received a new data byte or the I2C is idle.
1: The IDBR register received a new data byte from the I2C bus. An interrupt is signaled when enabled in the ICR.
19ITER/W1C0x0IDBR Transmit Empty:
0: The data byte is still being transmitted.
1: The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signaled when enabled in the ICR.
18ALDR/W1C0x0Arbitration Loss Detected: Used during multi-master operation:
0: Cleared when arbitration is won or never took place.
1: Set when the I2C loses arbitration.
17EBBR0x0Early Bus Busy:
0: Bus is idle or the I2C unit is actively using the bus (unit busy).
1: Early Bus Busy: SCL or SDA is low without detecting a START condition.
Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set.
16IBBR0x0I2C Bus Busy:
0: I2C bus is idle or the I2C unit is actively using the bus (unit busy).
1: Bus is busy due to external activity (another master using the bus).
15UBR0x0Unit Busy
0: I2C not busy.
1: I2C is busy. This is defined as the time between the first Start and Stop.
14ACKNAKR0x0
ACK/NACK Status:
0: The I2C received or sent an ACK on the bus.
1: The I2C received or sent a NAK.
On the bus, this bit is used in slave-transmit mode to determine when the byte transferred is the last one.
This bit is updated after each byte and ACK/NAK information is received.
13RWMR0x0Read/write Mode:
0: The I2C is in master-transmit or slave-receive mode.
1: The I2C is in master-receive or slave-transmit mode.
This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state.
12:0RSVDR0Reserved for future use
+**Offset: 0x4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | RXOV | R/W1C | 0x0 | Receive FIFO Overrun (Used in FIFO mode) .
0: Transmit FIFO NOT overrun;
1: Transmit FIFO overrun happened. | +| 30 | RXF | R/W1C | 0x0 | Receive FIFO Full (Used in FIFO mode).
0: Receive FIFO in NOT full;
1: Receive FIFO is full; | +| 29 | RXHF | R/W1C | 0x0 | Receive FIFO Half Full (Used in FIFO mode):
0: Receive FIFO in NOT half full;
1: Receive FIFO is half full. | +| 28 | TXE | R/W1C | 0x0 | Transmit FIFO Empty (Used in FIFO mode).
0: Transmit FIFO is NOT empty;
1: Transmit FIFO is empty. | +| 27 | TXDONE | R/W1C | 0x0 | Transaction Done (Used in FIFO mode):
0: Transaction is NOT done.
1: Transaction is done. | +| 26 | MSD | R/W1C | 0x0 | Master Stop Detected:
0: No Master Stop Detected.
1: Set when the I2C detects a Stop while in master-receive or master-transmit mode. | +| 25 | RSVD | R | 0 | Reserved for future use | +| 24 | SSD | R/W1C | 0x0 | Slave Stop Detected:
0: No Stop detected.
1: Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. | +| 23 | SAD | R/W1C | 0x0 | Slave Address Detected:
0: No slave address was detected.
1: The I2C detected a seven-bit address that matches the general call address or ISAR. An interrupt is signaled when enabled in the ICR. | +| 22 | BED | R/W1C | 0x0 | Bus Error Detected:
0: No error detected.
1: The I2C sets this bit when it detects one of the following error conditions:
- As a master transmitter, no ACK is detected on the interface after a byte is sent.
- As a slave receiver, the I2C generates a NAK pulse. | +| 21 | GCAD | R/W1C | 0x0 | General Call Address Detected:
0: No general call address received.
1: I2C received a general call address. | +| 20 | IRF | R/W1C | 0x0 | IDBR Receive Full:
0: The IDBR has not received a new data byte or the I2C is idle.
1: The IDBR register received a new data byte from the I2C bus. An interrupt is signaled when enabled in the ICR. | +| 19 | ITE | R/W1C | 0x0 | IDBR Transmit Empty:
0: The data byte is still being transmitted.
1: The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signaled when enabled in the ICR. | +| 18 | ALD | R/W1C | 0x0 | Arbitration Loss Detected: Used during multi-master operation:
0: Cleared when arbitration is won or never took place.
1: Set when the I2C loses arbitration. | +| 17 | EBB | R | 0x0 | Early Bus Busy:
0: Bus is idle or the I2C unit is actively using the bus (unit busy).
1: Early Bus Busy: SCL or SDA is low without detecting a START condition.
Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set. | +| 16 | IBB | R | 0x0 | I2C Bus Busy:
0: I2C bus is idle or the I2C unit is actively using the bus (unit busy).
1: Bus is busy due to external activity (another master using the bus). | +| 15 | UB | R | 0x0 | Unit Busy
0: I2C not busy.
1: I2C is busy. This is defined as the time between the first Start and Stop. | +| 14 | ACKNAK | R | 0x0 | ACK/NACK Status:
0: The I2C received or sent an ACK on the bus.
1: The I2C received or sent a NAK.
On the bus, this bit is used in slave-transmit mode to determine when the byte transferred is the last one.
This bit is updated after each byte and ACK/NAK information is received. | +| 13 | RWM | R | 0x0 | Read/write Mode:
0: The I2C is in master-transmit or slave-receive mode.
1: The I2C is in master-receive or slave-transmit mode.
This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state. | +| 12:0 | RSVD | R | 0 | Reserved for future use | #### ISAR REGISTER @@ -1619,34 +1183,12 @@ The I2C has transmitted a STOP signal when configured as a master when : These are read/write registers. Ignore reads from reserved bits. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8
BitsFieldTypeResetDescription
31:7RSVDR0Reserved for future use
6:0SLAVE_ADDRESSR/W0x0The seven-bit address to which the I2C responds when in slave-receive mode
+**Offset: 0x8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | R | 0 | Reserved for future use | +| 6:0 | SLAVE_ADDRESS | R/W | 0x0 | The seven-bit address to which the I2C responds when in slave-receive mode | #### IDBR REGISTER @@ -1707,34 +1249,12 @@ The I2C Data Buffer Register (IDBR) is used to transmit and receive data from th These are read/write registers. Ignore reads from reserved bits. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC
BitsFieldTypeResetDescription
31:8RSVDR0Reserved for future use
7:0DATA_BUFFERR/W0x0 Buffer for I2C bus send/receive data.
+**Offset: 0xC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | RSVD | R | 0 | Reserved for future use | +| 7:0 | DATA_BUFFER | R/W | 0x0 | Buffer for I2C bus send/receive data. | #### ILCR REGISTER @@ -1765,48 +1285,14 @@ Reset values are designed to allow the highest possible SCL frequency while meet **Extreme caution** is required when modifying this register to avoid disrupting I2C operations. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x10
BitsFieldTypeResetDescription
31:27HLVLR/W0x1- Load value for High-Speed Mode SCL (master mode) – Low phase.
- With the reset value, the I2C in master mode generates an SCL supporting data rates up to 1.8 Mbps.
26:18HLVHR/W0xb- Load value for High-Speed Mode SCL (master mode) – High phase.
- With the reset value, the I2C in master mode generates an SCL supporting data rates up to 1.8 Mbps.
17:9FLVR/W0x5d- Load value for Fast Mode SCL (master mode) – Both high and low phases.
- With the reset value, the I2C in master mode generates an SCL supporting data rates up to 400 Kbps.
8:0SLVR/W0x156- Load value for Standard Mode SCL (master mode) – Both high and low phases.
- With the reset value, the I2C in master mode generates an SCL supporting data rates up to 100 Kbps.
+**Offset: 0x10** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:27 | HLVL | R/W | 0x1 | - Load value for High-Speed Mode SCL (master mode) – Low phase.
- With the reset value, the I2C in master mode generates an SCL supporting data rates up to 1.8 Mbps. | +| 26:18 | HLVH | R/W | 0xb | - Load value for High-Speed Mode SCL (master mode) – High phase.
- With the reset value, the I2C in master mode generates an SCL supporting data rates up to 1.8 Mbps. | +| 17:9 | FLV | R/W | 0x5d | - Load value for Fast Mode SCL (master mode) – Both high and low phases.
- With the reset value, the I2C in master mode generates an SCL supporting data rates up to 400 Kbps. | +| 8:0 | SLV | R/W | 0x156 | - Load value for Standard Mode SCL (master mode) – Both high and low phases.
- With the reset value, the I2C in master mode generates an SCL supporting data rates up to 100 Kbps. | #### IWCR REGISTER @@ -1814,109 +1300,29 @@ The I2C Wait Count register controls the setup and hold times during slave mode This register works together with the ILCR register control the setup and hold times for all modes. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14
BitsFieldTypeResetDescription
31:15RSVDR0Reserved for future use
14:10HS_COUNT2R/W0x5Count value for defining high speed mode STOP bit setup and hold times.
Default: Decimal 5
9:5HS_COUNT1R/W0x01Count value for defining high speed mode START bit setup and hold times.
Default: Decimal 1
4:0COUNTR/W0x1AControls the counter values defining the setup and hold times in standard and fast mode.
Recommended values:
01010 => 33 MHz I2C functional clock;
10100 => 66 MHz I2C functional clock;
Default: Decimal 26.
+**Offset: 0x14** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:15 | RSVD | R | 0 | Reserved for future use | +| 14:10 | HS_COUNT2 | R/W | 0x5 | Count value for defining high speed mode STOP bit setup and hold times.
Default: Decimal 5 | +| 9:5 | HS_COUNT1 | R/W | 0x01 | Count value for defining high speed mode START bit setup and hold times.
Default: Decimal 1 | +| 4:0 | COUNT | R/W | 0x1A | Controls the counter values defining the setup and hold times in standard and fast mode.
Recommended values:
01010 => 33 MHz I2C functional clock;
10100 => 66 MHz I2C functional clock;
Default: Decimal 26. | #### IRCR REGISTER -The I2C bus reset cycle counter defines the cycles of SCL during bus reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x18
BitsFieldTypeResetDescription
31:8RSVDR0Reserved for future use
7I2C_SDA_GLITCH_FIX_BYPASSR/W0x0Bypass the SDA glitch fix:
0: The SDA glitch fix effective;
1: Bypass the SDA glitch fix.
6I2C_READ_HANG_FIX_BYPASSR/W0x0Bypass the read hang fix.
0: The read hang fix effective;
1: Bypass the read hang fix.
5SCL_SW_CTRLR/W0x01: The SCL output is controlled by SW_SCL
4SW_SCLR/W0x00: SCL output set to 0;
1: SCL output set to 1;
3:0RST_CYCR/W0x9The cycles of SCL during bus reset.
+The I2C bus reset cycle counter defines the cycles of SCL during bus reset + +**Offset: 0x18** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | RSVD | R | 0 | Reserved for future use | +| 7 | I2C_SDA_GLITCH_FIX_BYPASS | R/W | 0x0 | Bypass the SDA glitch fix:
0: The SDA glitch fix effective;
1: Bypass the SDA glitch fix. | +| 6 | I2C_READ_HANG_FIX_BYPASS | R/W | 0x0 | Bypass the read hang fix.
0: The read hang fix effective;
1: Bypass the read hang fix. | +| 5 | SCL_SW_CTRL | R/W | 0x0 | 1: The SCL output is controlled by SW_SCL | +| 4 | SW_SCL | R/W | 0x0 | 0: SCL output set to 0;
1: SCL output set to 1; | +| 3:0 | RST_CYC | R/W | 0x9 | The cycles of SCL during bus reset. | #### IBMR REGISTER @@ -1924,41 +1330,13 @@ The I2C Bus Monitor register (IBMR) tracks the status of the SCL and SDA pins. T This a read-only register. Ignore reads from reserved bits. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1C
BitsFieldTypeResetDescription
31:2RSVDR0Reserved for future use
1SCLR0x1 IBMR[SCL] continuously reflects the value of the SCL pin.
0SDAR0x1 IBMR[SDA] continuously reflects the value of the SDA pin.
+**Offset: 0x1C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | RSVD | R | 0 | Reserved for future use | +| 1 | SCL | R | 0x1 | IBMR[SCL] continuously reflects the value of the SCL pin. | +| 0 | SDA | R | 0x1 | IBMR[SDA] continuously reflects the value of the SDA pin. | #### WFIFO REGISTER @@ -1968,41 +1346,13 @@ This FIFO can be filled up in PIO or DMA mode. If this FIFO is empty, an interrupt or a DMA request is generated. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x20
BitsFieldTypeResetDescription
31:12RSVDR0Reserved for future use
11:8CONTROLR0x0I2C Bus send/receive data control bits.
These control bits are essential for ICR[3:0] bits.
7:0DATAR0x00I2C Bus send data for Write Transactions and dummy data for Read Transactions
+**Offset: 0x20** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:12 | RSVD | R | 0 | Reserved for future use | +| 11:8 | CONTROL | R | 0x0 | I2C Bus send/receive data control bits.
These control bits are essential for ICR[3:0] bits. | +| 7:0 | DATA | R | 0x00 | I2C Bus send data for Write Transactions and dummy data for Read Transactions | #### WFIFO_WPTR REGISTER @@ -2012,34 +1362,12 @@ This is a read/write register. Software can write '0' to this register to flush the FIFO after handling interrupts like Bus error, Arbitration loss, etc. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x24
BitsFieldTypeResetDescription
31:4RSVDR0Reserved for future use
3:0DATAR/W0x0This is the location in the TX FIFO where the next entry will be written to by the software.
+**Offset: 0x24** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | RSVD | R | 0 | Reserved for future use | +| 3:0 | DATA | R/W | 0x0 | This is the location in the TX FIFO where the next entry will be written to by the software. | #### WFIFO_RPTR REGISTER @@ -2049,34 +1377,12 @@ This is a read/write register. Software can write '0' to this register to flush the FIFO after an interrupt. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x28
BitsFieldTypeResetDescription
31:4RSVDR0Reserved for future use
3:0DATAR/W0x0This is the location in the TX FIFO where the next entry will be read from by the hardware.
+**Offset: 0x28** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | RSVD | R | 0 | Reserved for future use | +| 3:0 | DATA | R/W | 0x0 | This is the location in the TX FIFO where the next entry will be read from by the hardware. | #### RFIFO REGISTER @@ -2086,41 +1392,13 @@ This FIFO can be emptied in PIO or DMA mode. If this FIFO is half full, an interrupt or a DMA request is generated. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x2C
BitsFieldTypeResetDescription
31:12RSVDR0Reserved for future use
11:8CONTROLR0x0I2C Bus send/receive data control bits.
These control bits are essential for ICR[3:0] bits.
7:0DATAR0x00 I2C Bus send data for Write Transactions and dummy data for Read Transactions
+**Offset: 0x2C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:12 | RSVD | R | 0 | Reserved for future use | +| 11:8 | CONTROL | R | 0x0 | I2C Bus send/receive data control bits.
These control bits are essential for ICR[3:0] bits. | +| 7:0 | DATA | R | 0x00 | I2C Bus send data for Write Transactions and dummy data for Read Transactions | #### RFIFO_WPTR REGISTER @@ -2130,34 +1408,12 @@ This is a read/write register. Software can write '0' to this register to flush the FIFO after handling interrupts like Bus error, Arbitration loss, etc. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x30
BitsFieldTypeResetDescription
31:4RSVDR0Reserved for future use
3:0DATAR/W0x0This is the location in the TX FIFO where the next entry will be written to by the software.
+**Offset: 0x30** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | RSVD | R | 0 | Reserved for future use | +| 3:0 | DATA | R/W | 0x0 | This is the location in the TX FIFO where the next entry will be written to by the software. | #### RFIFO_RPTR REGISTER @@ -2167,34 +1423,12 @@ This is a read/write register. Software can write '0' to this register to flush the FIFO after an interrupt. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x34
BitsFieldTypeResetDescription
31:4RSVDR0Reserved for future use
3:0DATAR/W0x0This is the location in the TX FIFO where the next entry will be read from by the hardware.
+**Offset: 0x34** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | RSVD | R | 0 | Reserved for future use | +| 3:0 | DATA | R/W | 0x0 | This is the location in the TX FIFO where the next entry will be read from by the hardware. | ## 17.2 SPI/I2S @@ -2294,7 +1528,7 @@ When the Trailing Byte SSCR[TRAIL] bit is set, trailing bytes left in the RXFIFO A DMA service request is issued automatically after the SSCR[TRAIL] field is set and a timeout occurs, SSSR[TINT]=1. The DMA empties the RXFIFO unless the DMA reaches the end of its Descriptor chain. When handling trailing bytes using the DMA, if a timeout occurs and the RXFIFO is empty (SSSR[RNE]=0), an end-of-receive (EOR) is sent to the DMA. -If a DMA EOC occurs (SSSR[EOC]=1) at the time that the last sample is read out of the RXFIFO (the DMA Descriptor chain was just exactly long enough) and the timeout counter is still running (that is, a timeout has not occurred and SSTO[TIMEOUT] is non-zero), then, when the timeout does occur, the SPI/I2S generates a DMA request. When this occurs, re-initialize the DMA registers and re-enable the channel for the SPI/I2S to send its EOR to the DMA controller. +If a DMA EOC occurs (SSSR[EOC]=1) at the time that the last sample is read out of the RXFIFO (the DMA Descriptor chain was just exactly long enough) and the timeout counter is still running (that is, a timeout has not occurred and SSTO[TIMEOUT] is non-zero), then, when the timeout does occur, the SPI/I2S generates a DMA request. When this occurs, re-initialize the DMA registers and re-enable the channel for the SPI/I2S to send its EOR to the DMA controller. > **Notes.** > @@ -2336,13 +1570,13 @@ The SPI format has four possible sub-modes depending on the SS_SCLK edges select When the SPI/I2S is disabled or in idle mode, SS_SCLK and SS_TX are low and SS_FRM is high. When Transmit data is ready to be sent, SS_FRM goes low (one clock period before the first rising edge of SS_SCLK) and stays low for the remainder of the frame. The most significant bit of the serial data is driven onto SS_TX one half-cycle later. Halfway into the first bit period, SS_SCLK asserts high and continues toggling for the remaining data bits. Data transitions on the falling edge of SS_SCLK and is sampled on the rising edge of SS_SCLK. 8, 16, 18, or 32 bits can be transferred per frame. -With the assertion of SS_FRM, Receive data is driven simultaneously from the peripheral on SS_RX , MSb first. Data transitions on SS_SCLK falling edges and is sampled by the controller on SS_SCLK rising edges. At the end of the frame, SS_FRM is de-asserted high one clock period (one half clock cycle after the last falling edge of SS_SCLK) after the last bit has been latched at its destination and the completed incoming word is shifted into the “incoming” FIFO. The peripheral can drive SS_RX to a high-impedance state after sending the last bit of the frame. +With the assertion of SS_FRM, Receive data is driven simultaneously from the peripheral on SS_RX, MSb first. Data transitions on SS_SCLK falling edges and is sampled by the controller on SS_SCLK rising edges. At the end of the frame, SS_FRM is de-asserted high one clock period (one half clock cycle after the last falling edge of SS_SCLK) after the last bit has been latched at its destination and the completed incoming word is shifted into the “incoming” FIFO. The peripheral can drive SS_RX to a high-impedance state after sending the last bit of the frame. SS_TX retains the last value transmitted when the controller goes into Idle mode, unless the SPI/I2S is disabled or reset (which forces SS_TX to zero). For back-to-back transfers, start and completion are like those of a single transfer, but SS_FRM does not de-assert between words. Both transmitter and receiver are configured for the word length and internally track the start and end of frames. There are no “dead” bits; the LSb of one frame is followed immediately by the MSb of the next. -When in Motorola\* SPI format, the SPI/I2S can be either a master or a slave device, but the clock and frame direction must be the same. For example, the Serial Bit Rate Clock Direction, SSCR[SCLKDIR], and the Frame Direction, SSCR[SFRMDIR], fields must either both be set or cleared. +When in Motorola\* SPI format, the SPI/I2S can be either a master or a slave device, but the clock and frame direction must be the same. For example, the Serial Bit Rate Clock Direction, SSCR[SCLKDIR], and the Frame Direction, SSCR[SFRMDIR], fields must either both be set or cleared. When in Motorola\* SPI format, if the SPI/I2S is the master and SSPSP[ETDS] is cleared, the end-of-transfer data state for SS_TX is low. If the SPI/I2S is the master and SSPSP[ETDS] is set, the end-of-transfer data state for SS_TX remains at the last bit transmitted (LSB). If the SPI/I2S is the slave, then the SSPSP[ETDS] is undefined. SS_RX is undefined before the frame is active and after the LSB is received. SS_RX must not float. When the SPI/I2S is configured as a master and SSCR[TTE] is set, SSPSP[ETDS] is ignored and SS_TX becomes high impedance between active transfers. @@ -2374,70 +1608,17 @@ In general, because of the programmable nature of the PSP protocol, this protoco The programmable protocol parameters of SPI/I2S are tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Symbol DefinitionRange Units
- Serial clock mode (SSPSP[SCMODE])(Drive, Sample, SS_ SCLK Idle)
0 = Fall, rise, low
1 = Rise, fall, low
2 = Rise, fall, high
3 = Fall, rise, high		-
- Serial frame polarity
(SSPSP[SFRMP])		High or low-
T1Start delay
(SSPSP[STRTDLY])		0 to 7Clock period
T2Dummy start
(SSPSP[EDMYSTRT] + SSPSP[DMYSTRT])		0 to 15Clock period
T3Data size
(SSCR[DSS])		4 to 32Clock period
T4 Dummy stop(SSPSP[EDMYSTOP] + SSPSP[DMYSTOP])0 to 31Clock period
T5SS_FRM delay (SSPSP[SFRMDLY])0 to 127Half-clock period
T6SS_FRM width (SSPSP[SFRMWDTH])1 to 63Clock period
-End of transfer data state (SSPSP[ETDS])Low or bit 0-
+| Symbol | Definition | Range | Units | +| --- | --- | --- | --- | +| - | Serial clock mode (SSPSP[SCMODE]) | (Drive, Sample, SS_ SCLK Idle)
0 = Fall, rise, low
1 = Rise, fall, low
2 = Rise, fall, high
3 = Fall, rise, high | - | +| - | Serial frame polarity
(SSPSP[SFRMP]) | High or low | - | +| T1 | Start delay
(SSPSP[STRTDLY]) | 0 to 7 | Clock period | +| T2 | Dummy start
(SSPSP[EDMYSTRT] + SSPSP[DMYSTRT]) | 0 to 15 | Clock period | +| T3 | Data size
(SSCR[DSS]) | 4 to 32 | Clock period | +| T4 | Dummy stop(SSPSP[EDMYSTOP] + SSPSP[DMYSTOP]) | 0 to 31 | Clock period | +| T5 | SS_FRM delay (SSPSP[SFRMDLY]) | 0 to 127 | Half-clock period | +| T6 | SS_FRM width (SSPSP[SFRMWDTH]) | 1 to 63 | Clock period | +| - | End of transfer data state (SSPSP[ETDS]) | Low or bit 0 | - | The SS_FRM delay (T5) must not extend beyond the end of T4. The SS_FRM width (T6) must be asserted for at least one SS_SCLK period and should be de-asserted before the end of T4 (for example, in terms of time, not bit values @@ -2549,343 +1730,76 @@ Wait two SS_SCLK cycles before writing new data to the TXFIFO. The SPI/I2S Baud > **Note.** The base address of SPI/I2S registers are tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameAddress
SHUB_SSP0_BASE0xC0885000
SSP3_BASE0xD401C000
SSPA0_BASE0xD4026000
SSPA1_BASE0xD4026800
SSP2_BASE0xF0613000
+| Name | Address | +| --- | --- | +| SHUB_SSP0_BASE | 0xC0885000 | +| SSP3_BASE | 0xD401C000 | +| SSPA0_BASE | 0xD4026000 | +| SSPA1_BASE | 0xD4026800 | +| SSP2_BASE | 0xF0613000 | #### SSCR REGISTER SPI/I2S top control register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31:19RSVDR0Reserved for future use
18TTELPR/W0x0TXD Three-state Enable On Last Phase
0 = SS_TX is three-stated 1/2 clock cycle after the beginning of the LSB
1 = SS_TX output signal is three-stated on the clock edge that ends the LSB
17TTER/W0x0TXD Three-State Enable
0 = SS_TX output signal is not three-stated
1 = SS_TX is three-stated when not transmitting data
16SCFRR/W0x0Slave Clock Free Running
0 = Clock input to SS_CLK is continuously running
1 = Clock input to SS_CLK is only active during data transfers.
15IFSR/W0x0Invert Frame Signal
0 = SS_FRM polarity is determined by the PSP polarity bits
1 = SS_FRM will be inverted from normal-SS_FRM (as defined by the PSP polarity bits). (Works in all frame formats: SPI and PSP)
14HOLD_FRAME_LOWR/W0x0Hold Frame Low Control
1=After this field is set to 1 and the SPI/I2S is operating in master mode. Used for SPI Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there's no bit clock, or the data transfers before the stop clock will be discarded.
13TRAILR/W0x0Trailing Byte
0 = Trailing bytes are handled by the CPU
1 = Trailing bytes are handled by DMA bursts
12LBMR/W0x0Loopback Mode (Test Mode Bit)
0 = Normal serial port operation is enabled
1 = Output of TX serial shifter is internally connected to input of RX serial shifter
11SPHR/W0x0Motorola SPI SS_SCLK phase setting
0 = SS_SCLK is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame
1 = SS_SCLK is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame
10SPOR/W0x0Motorola SPI SS_SCLK Polarity Setting
0 = The inactive or idle state of SS_SCLK is low
1 = The inactive or idle state of SS_SCLK is high
9:5DSSR/W0x0SPI/I2S Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits
4SFRMDIRR/W0x0SS_FRM Direction
0 = Master mode, SPI/I2S port drives SS_FRM
1 = Slave mode, SPI/I2S port receives SS_FRM
3SCLKDIRR/W0x0SS_SCLK Direction
0 = Master mode, SPI/I2S port drives SS_SCLK
1 = Slave mode, SPI/I2S port receives SS_SCLK
2:1FRFR/W0x0Frame Format
0x0 = Motorola* Serial Peripheral Interface (SPI)
0x3 = Programmable Serial Protocol (PSP)
Others = reserved
0SSER/W0x0SPI/I2S Enable
0 = SPI/I2S port is disabled
1 = SPI/I2S port is enabled
+**Offset: 0x0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | RSVD | R | 0 | Reserved for future use | +| 18 | TTELP | R/W | 0x0 | TXD Three-state Enable On Last Phase
0 = SS_TX is three-stated 1/2 clock cycle after the beginning of the LSB
1 = SS_TX output signal is three-stated on the clock edge that ends the LSB | +| 17 | TTE | R/W | 0x0 | TXD Three-State Enable
0 = SS_TX output signal is not three-stated
1 = SS_TX is three-stated when not transmitting data | +| 16 | SCFR | R/W | 0x0 | Slave Clock Free Running
0 = Clock input to SS_CLK is continuously running
1 = Clock input to SS_CLK is only active during data transfers. | +| 15 | IFS | R/W | 0x0 | Invert Frame Signal
0 = SS_FRM polarity is determined by the PSP polarity bits
1 = SS_FRM will be inverted from normal-SS_FRM (as defined by the PSP polarity bits). (Works in all frame formats: SPI and PSP) | +| 14 | HOLD_FRAME_LOW | R/W | 0x0 | Hold Frame Low Control
1=After this field is set to 1 and the SPI/I2S is operating in master mode. Used for SPI Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there's no bit clock, or the data transfers before the stop clock will be discarded. | +| 13 | TRAIL | R/W | 0x0 | Trailing Byte
0 = Trailing bytes are handled by the CPU
1 = Trailing bytes are handled by DMA bursts | +| 12 | LBM | R/W | 0x0 | Loopback Mode (Test Mode Bit)
0 = Normal serial port operation is enabled
1 = Output of TX serial shifter is internally connected to input of RX serial shifter | +| 11 | SPH | R/W | 0x0 | Motorola SPI SS_SCLK phase setting
0 = SS_SCLK is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame
1 = SS_SCLK is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame | +| 10 | SPO | R/W | 0x0 | Motorola SPI SS_SCLK Polarity Setting
0 = The inactive or idle state of SS_SCLK is low
1 = The inactive or idle state of SS_SCLK is high | +| 9:5 | DSS | R/W | 0x0 | SPI/I2S Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits | +| 4 | SFRMDIR | R/W | 0x0 | SS_FRM Direction
0 = Master mode, SPI/I2S port drives SS_FRM
1 = Slave mode, SPI/I2S port receives SS_FRM | +| 3 | SCLKDIR | R/W | 0x0 | SS_SCLK Direction
0 = Master mode, SPI/I2S port drives SS_SCLK
1 = Slave mode, SPI/I2S port receives SS_SCLK | +| 2:1 | FRF | R/W | 0x0 | Frame Format
0x0 = Motorola* Serial Peripheral Interface (SPI)
0x3 = Programmable Serial Protocol (PSP)
Others = reserved | +| 0 | SSE | R/W | 0x0 | SPI/I2S Enable
0 = SPI/I2S port is disabled
1 = SPI/I2S port is enabled | #### SSFCR REGISTER SPI/I2S FIFO control register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31:22RSVDR0Reserved for future use
21RXENDIANR/W0x0select the big endian or little endian for RX transfer
0 = big endian
1 = little endian
20TXENDIANR/W0x0select the big endian or little endian for TX transfer
0 = big endian
1 = little endian
19STRFR/W0x0Select FIFO For Test Mode Bit
0 = TXFIFO is selected for both writes and reads through the SPI/I2S Data Register
1 = RXFIFO is selected for both writes and reads through the SPI/I2S Data Register
18EFWRR/W0x0Enable FIFO Write/read (Test Mode Bit)
0 = FIFO write/read special function is disabled
1 = FIFO write/read special function is enabled
17RXFIFO_AUTO_FULL_CTRLR/W0x0Rx FIFO Auto Full Control
After this field is set to 1 and the SPI/I2S is operating in master mode, the SS_FSM returns to IDLE state and stops the SS_SCLK. When Rx FIFO is full, the SS_FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue.
1= Enable Rx FIFO auto full control
0= Disable Rx FIFO auto full control
16FPCKER/W0x0FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled
15:14TXFIFO_WR_ENDIANR/W0x0apb_pwdata Write to Tx FIFO Endian
0x0 = txfifo_wdata[31:0] = apb_pwdata[31:0]
0x1 = fifo_wdata[31:0] = {apb_pwdata[15:0], apb_pwdata[31:16]}
0x2 = txfifo_wdata[31:0] = {apb_pwdata[7:0], apb_pwdata[15:8], apb_pwdata[23:16], apb_pwdata[31:24]}
0x3 = txfifo_wdata[31:0] = {apb_pwdata[23:16], apb_pwdata[31:24], apb_pwdata[7:0], apb_pwdata[15:8]}
13:12RXFIFO_RD_ENDIANR/W0x0apb_prdata Read from Rx FIFO Endian
0x0 = apb_prdata[31:0] = rxfifo_wdata[31:0]
0x1 = apb_prdata[31:0] = {rxfifo_wdata[15:0], rxfifo_wdata[31:16]}
0x2 = apb_prdata[31:0]= {rxfifo_wdata[7:0], rxfifo_wdata[15:8], rxfifo_wdata[23:16], rxfifo_wdata[31:24]}
0x3 = apb_prdata[31:0]= {rxfifo_wdata[23:16], rxfifo_wdata[31:24], rxfifo_wdata[7:0], rxfifo_wdata[15:8]}
11RSRER/W0x0Receive Service Request Enable
0 = DMA service request is disabled
1 = DMA service request is enabled
10TSRER/W0x0Transmit Service Request Enable
0 = DMA service request is disabled
1 = DMA service request is enabled
9:5RFTR/W0x0RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1.
4:0TFTR/W0x0TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1.
+**Offset: 0x4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:22 | RSVD | R | 0 | Reserved for future use | +| 21 | RXENDIAN | R/W | 0x0 | select the big endian or little endian for RX transfer
0 = big endian
1 = little endian | +| 20 | TXENDIAN | R/W | 0x0 | select the big endian or little endian for TX transfer
0 = big endian
1 = little endian | +| 19 | STRF | R/W | 0x0 | Select FIFO For Test Mode Bit
0 = TXFIFO is selected for both writes and reads through the SPI/I2S Data Register
1 = RXFIFO is selected for both writes and reads through the SPI/I2S Data Register | +| 18 | EFWR | R/W | 0x0 | Enable FIFO Write/read (Test Mode Bit)
0 = FIFO write/read special function is disabled
1 = FIFO write/read special function is enabled | +| 17 | RXFIFO_AUTO_FULL_CTRL | R/W | 0x0 | Rx FIFO Auto Full Control
After this field is set to 1 and the SPI/I2S is operating in master mode, the SS_FSM returns to IDLE state and stops the SS_SCLK. When Rx FIFO is full, the SS_FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue.
1= Enable Rx FIFO auto full control
0= Disable Rx FIFO auto full control | +| 16 | FPCKE | R/W | 0x0 | FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled | +| 15:14 | TXFIFO_WR_ENDIAN | R/W | 0x0 | apb_pwdata Write to Tx FIFO Endian
0x0 = txfifo_wdata[31:0] = apb_pwdata[31:0]
0x1 = fifo_wdata[31:0] = {apb_pwdata[15:0], apb_pwdata[31:16]}
0x2 = txfifo_wdata[31:0] = {apb_pwdata[7:0], apb_pwdata[15:8], apb_pwdata[23:16], apb_pwdata[31:24]}
0x3 = txfifo_wdata[31:0] = {apb_pwdata[23:16], apb_pwdata[31:24], apb_pwdata[7:0], apb_pwdata[15:8]} | +| 13:12 | RXFIFO_RD_ENDIAN | R/W | 0x0 | apb_prdata Read from Rx FIFO Endian
0x0 = apb_prdata[31:0] = rxfifo_wdata[31:0]
0x1 = apb_prdata[31:0] = {rxfifo_wdata[15:0], rxfifo_wdata[31:16]}
0x2 = apb_prdata[31:0]= {rxfifo_wdata[7:0], rxfifo_wdata[15:8], rxfifo_wdata[23:16], rxfifo_wdata[31:24]}
0x3 = apb_prdata[31:0]= {rxfifo_wdata[23:16], rxfifo_wdata[31:24], rxfifo_wdata[7:0], rxfifo_wdata[15:8]} | +| 11 | RSRE | R/W | 0x0 | Receive Service Request Enable
0 = DMA service request is disabled
1 = DMA service request is enabled | +| 10 | TSRE | R/W | 0x0 | Transmit Service Request Enable
0 = DMA service request is disabled
1 = DMA service request is enabled | +| 9:5 | RFT | R/W | 0x0 | RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1. | +| 4:0 | TFT | R/W | 0x0 | TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1. | #### SSINTEN REGISTER SPI/I2S interrupt enable register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8
BitsFieldTypeResetDescription
31:7RSVDR0Reserved for future use
6EBCEIR/W0x0Enable Bit Count Error Interrupt
0 = Interrupt due to a bit count error is disabled
1 = Interrupt due to a bit count error is enabled
5TIMR/W0x1Transmit FIFO Underrun Interrupt Mask
0 = TUR events generate an interrupt
1 = TUR events do NOT generate an interrupt
4RIMR/W0x1Receive FIFO Overrun Interrupt Mask
0 = ROR events generate an interrupt
1 = ROR events do NOT generate an interrupt
3TIER/W0x0Transmit FIFO Interrupt Enable
0 = TXFIFO threshold-level-reached interrupt is disabled
1 = TXFIFO threshold-level-reached interrupt is enabled
2RIER/W0x0Receive FIFO Interrupt Enable
0 = RXFIFO threshold-level-reached interrupt is disabled
1 = RXFIFO threshold-level-reached interrupt is enabled
1TINTER/W0x0Receiver Time-out Interrupt Enable
0 = Receiver time-out interrupt is disabled
1 = Receiver time-out interrupt is enabled
0PINTER/W0x0Peripheral Trailing Byte Interrupt Enable
0 = Peripheral trailing byte interrupt is disabled
1 = Peripheral trailing byte interrupt is enabled
+**Offset: 0x8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | R | 0 | Reserved for future use | +| 6 | EBCEI | R/W | 0x0 | Enable Bit Count Error Interrupt
0 = Interrupt due to a bit count error is disabled
1 = Interrupt due to a bit count error is enabled | +| 5 | TIM | R/W | 0x1 | Transmit FIFO Underrun Interrupt Mask
0 = TUR events generate an interrupt
1 = TUR events do NOT generate an interrupt | +| 4 | RIM | R/W | 0x1 | Receive FIFO Overrun Interrupt Mask
0 = ROR events generate an interrupt
1 = ROR events do NOT generate an interrupt | +| 3 | TIE | R/W | 0x0 | Transmit FIFO Interrupt Enable
0 = TXFIFO threshold-level-reached interrupt is disabled
1 = TXFIFO threshold-level-reached interrupt is enabled | +| 2 | RIE | R/W | 0x0 | Receive FIFO Interrupt Enable
0 = RXFIFO threshold-level-reached interrupt is disabled
1 = RXFIFO threshold-level-reached interrupt is enabled | +| 1 | TINTE | R/W | 0x0 | Receiver Time-out Interrupt Enable
0 = Receiver time-out interrupt is disabled
1 = Receiver time-out interrupt is enabled | +| 0 | PINTE | R/W | 0x0 | Peripheral Trailing Byte Interrupt Enable
0 = Peripheral trailing byte interrupt is disabled
1 = Peripheral trailing byte interrupt is enabled | #### SSTO REGISTER @@ -2893,508 +1807,130 @@ SPI/I2S time out register. These registers specify the timeout (TIMEOUT) value u TimeOut Interval = SSTO [TIMEOUT] / APB Clock Frequency, APB Clock Frequency = 25.6 MHz OR 51.2MHz. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC
BitsFieldTypeResetDescription
31:24RSVDR0Reserved for future use
23:0TIMEOUTR/W0x0Timeout Value TIMEOUT value is the value that defines the time-out interval. The time-out interval is given by the equation shown in the TIMEOUT Interval Equation.
+**Offset: 0xC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | RSVD | R | 0 | Reserved for future use | +| 23:0 | TIMEOUT | R/W | 0x0 | Timeout Value TIMEOUT value is the value that defines the time-out interval. The time-out interval is given by the equation shown in the TIMEOUT Interval Equation. | #### SSDATR REGISTER SPI/I2S data register. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x10
BitsFieldTypeResetDescription
31:0DATAR/W0x0DATA This field is used for data to be written to the TXFIFO read from the RXFIFO.
+**Offset: 0x10** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | DATA | R/W | 0x0 | DATA This field is used for data to be written to the TXFIFO read from the RXFIFO. | #### SSSR REGISTER SPI/I2S status register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14
BitsFieldTypeResetDescription
31:24RSVDR0Reserved for future use
23OSSR0x0Odd Sample Status
0 = RxFIFO entry has two samples
1 = RxFIFO entry has one sample
> Note. This bit needs to be looked at only when FIFO Packing is enabled (SSFCR[FPCKE] field is set). Otherwise, this bit is zero. When SPI/I2S port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that SSSR[RNE] = 1 AND this field = 0 before it attempts to read the RxFIFO.
22TX_OSSR0x0TX FIFO Odd Sample Status
0 = TxFIFO entry has an even number of samples
1 = TxFIFO entry has an odd number of samples
> Note. This bit needs to be read only when FIFO Packing is enabled (SSFCR[FPCKE] field is set). Otherwise, this bit is zero.
21BCER/W1C0x0Bit Count Error
0 = The SPI/I2S port has not experienced a bit count error
1 = The SS_FRM signal was asserted when the bit counter was not zero
20RORR/W1C0x0Receive FIFO Overrun
0 = RXFIFO has not experienced an overrun
1 = Attempted data write to full RXFIFO, causes an interrupt request
19:15RFLR0x1FReceive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the SSSR[RNE] field.
14RNER0x0Receive FIFO Not Empty
0 = RXFIFO is empty
1 = RXFIFO is not empty
13RFSR0x0Receive FIFO Service Request
0 = RXFIFO level is at or below RFT threshold (RFT) or SPI/I2S port is disabled
1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request
12TURR/W1C0x0Transmit FIFO Underrun
0 = The TXFIFO has not experienced an underrun
1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causing an interrupt if it is enabled
11:7TFLR0x0Transmit FIFO Level This field is the number of entries in TXFIFO. When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the SSSR[TNF] field.
6TNFR0x1Transmit FIFO Not Full
0 = TXFIFO is full
1 = TXFIFO is not full
5TFSR0x0Transmit FIFO Service Request
0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SPI/I2S port disabled
1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request
4EOCR/W1C0x0End Of Chain
0 = DMA has not signaled an end of chain condition
1 = DMA has signaled an end of chain condition
3TINTR/W1C0x0Receiver Time-out Interrupt
0 = No receiver time-out is pending
1 = Receiver time-out pending, causes an interrupt request
2PINTR/W1C0x0Peripheral Trailing Byte Interrupt
0 = No peripheral trailing byte interrupt is pending
1 = Peripheral trailing byte interrupt is pending
1CSSR0x0Clock Synchronization Status
0 = The SPI/I2S port is ready for slave clock operations
1 = The SPI/I2S port is currently busy synchronizing slave mode signals
0BSYR0x0SPI/I2S Busy
0 = SPI/I2S port is idle or disabled
1 = SPI/I2S port is currently transmitting or receiving framed data
+**Offset: 0x14** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | RSVD | R | 0 | Reserved for future use | +| 23 | OSS | R | 0x0 | Odd Sample Status
0 = RxFIFO entry has two samples
1 = RxFIFO entry has one sample
> Note. This bit needs to be looked at only when FIFO Packing is enabled (SSFCR[FPCKE] field is set). Otherwise, this bit is zero. When SPI/I2S port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that SSSR[RNE] = 1 AND this field = 0 before it attempts to read the RxFIFO. | +| 22 | TX_OSS | R | 0x0 | TX FIFO Odd Sample Status
0 = TxFIFO entry has an even number of samples
1 = TxFIFO entry has an odd number of samples
> Note. This bit needs to be read only when FIFO Packing is enabled (SSFCR[FPCKE] field is set). Otherwise, this bit is zero. | +| 21 | BCE | R/W1C | 0x0 | Bit Count Error
0 = The SPI/I2S port has not experienced a bit count error
1 = The SS_FRM signal was asserted when the bit counter was not zero | +| 20 | ROR | R/W1C | 0x0 | Receive FIFO Overrun
0 = RXFIFO has not experienced an overrun
1 = Attempted data write to full RXFIFO, causes an interrupt request | +| 19:15 | RFL | R | 0x1F | Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the SSSR[RNE] field. | +| 14 | RNE | R | 0x0 | Receive FIFO Not Empty
0 = RXFIFO is empty
1 = RXFIFO is not empty | +| 13 | RFS | R | 0x0 | Receive FIFO Service Request
0 = RXFIFO level is at or below RFT threshold (RFT) or SPI/I2S port is disabled
1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request | +| 12 | TUR | R/W1C | 0x0 | Transmit FIFO Underrun
0 = The TXFIFO has not experienced an underrun
1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causing an interrupt if it is enabled | +| 11:7 | TFL | R | 0x0 | Transmit FIFO Level This field is the number of entries in TXFIFO. When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the SSSR[TNF] field. | +| 6 | TNF | R | 0x1 | Transmit FIFO Not Full
0 = TXFIFO is full
1 = TXFIFO is not full | +| 5 | TFS | R | 0x0 | Transmit FIFO Service Request
0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SPI/I2S port disabled
1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request | +| 4 | EOC | R/W1C | 0x0 | End Of Chain
0 = DMA has not signaled an end of chain condition
1 = DMA has signaled an end of chain condition | +| 3 | TINT | R/W1C | 0x0 | Receiver Time-out Interrupt
0 = No receiver time-out is pending
1 = Receiver time-out pending, causes an interrupt request | +| 2 | PINT | R/W1C | 0x0 | Peripheral Trailing Byte Interrupt
0 = No peripheral trailing byte interrupt is pending
1 = Peripheral trailing byte interrupt is pending | +| 1 | CSS | R | 0x0 | Clock Synchronization Status
0 = The SPI/I2S port is ready for slave clock operations
1 = The SPI/I2S port is currently busy synchronizing slave mode signals | +| 0 | BSY | R | 0x0 | SPI/I2S Busy
0 = SPI/I2S port is idle or disabled
1 = SPI/I2S port is currently transmitting or receiving framed data | #### SSPSP REGISTER SPI/I2S programmable serial protocol control register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x18
BitsFieldTypeResetDescription
31:30RSVDR0Reserved for future use
29:27EDMYSTOPR/W0x0Extended Dummy Stop Most-significant bits of the dummy stop delay.Do not used in PSP Network mode.
26:25DMYSTOPR/W0x0Dummy Stop Least-significant bits of the dummy stop delay Programmed value of SSPSP[EDMYSTOP] + this field specifies the number (0-31) of active clocks (SS_SCLK) that follow the end of the transmitted data.Do not used in PSP Network mode.
24:23EDMYSTRTR/W0x0Extended Dummy Start Most-significant bits of the dummy start delay.Do not used in PSP Network mode.
22:21DMYSTRTR/W0x0Dummy Start Least-significant bits of the dummy start delay Programmed value of this field specifies the number (0-15) of active clocks (SS_SCLK) between the end of start delay and when the most-significant bit of transmit/receive data is driven. Do not used in PSP Network mode.
20:18STRTDLYR/W0x0Start Delay Programmed value specifies the number (0-7) of non-active clocks (SS_SCLK) that define the duration of idle time. Do not used in PSP Network mode.
17:12SFRMWDTHR/W0x0Serial Frame Width Least-significant bits of the serial frame width Programmed value of this field specifies the frame width from 0x00 (one SS_SCLK cycle) to 0x3F (63 SS_SCLK cycles).
11:5SFRMDLYR/W0x0Serial Frame Delay Programmed value specifies the number (0 -127) of active one-half clocks (SS_SCLK) asserted from the most-significant bit of TX (output) or RX (input) being driven to SS_FRM.Do not used in PSP Network mode.
4SFRMPR/W0x0Serial Frame Polarity
0 = SS_FRM is active low (0x0)
1 = SS_FRM is active high (0x1)
3FSRTR/W0x0Frame Sync Relative Timing Bit
0 = Next frame is asserted after the end of the DMTSTOP timing
1 = Next frame is asserted with the LSB of the previous frame
2ETDSR/W0x0End Of Transfer Data State
0 = Low
1 = Last Value <Bit 0>
1:0SCMODER/W0x0Serial Bit-rate Clock Mode
0x0 = Data Driven (Falling), Data Sampled (Rising), Idle State (Low)
0x1 = Data Driven (Rising), Data Sampled (Falling), Idle State (Low)
0x2 = Data Driven (Rising), Data Sampled (Falling), Idle State (High)
0x3 = Data Driven (Falling), Data Sampled (Rising), Idle State (High)
+**Offset: 0x18** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | RSVD | R | 0 | Reserved for future use | +| 29:27 | EDMYSTOP | R/W | 0x0 | Extended Dummy Stop Most-significant bits of the dummy stop delay. Do not use in PSP Network mode. | +| 26:25 | DMYSTOP | R/W | 0x0 | Dummy Stop Least-significant bits of the dummy stop delay Programmed value of SSPSP[EDMYSTOP] + this field specifies the number (0-31) of active clocks (SS_SCLK) that follow the end of the transmitted data. Do not use in PSP Network mode. | +| 24:23 | EDMYSTRT | R/W | 0x0 | Extended Dummy Start Most-significant bits of the dummy start delay. Do not use in PSP Network mode. | +| 22:21 | DMYSTRT | R/W | 0x0 | Dummy Start Least-significant bits of the dummy start delay Programmed value of this field specifies the number (0-15) of active clocks (SS_SCLK) between the end of start delay and when the most-significant bit of transmit/receive data is driven. Do not used in PSP Network mode. | +| 20:18 | STRTDLY | R/W | 0x0 | Start Delay Programmed value specifies the number (0-7) of non-active clocks (SS_SCLK) that define the duration of idle time. Do not used in PSP Network mode. | +| 17:12 | SFRMWDTH | R/W | 0x0 | Serial Frame Width Least-significant bits of the serial frame width Programmed value of this field specifies the frame width from 0x00 (one SS_SCLK cycle) to 0x3F (63 SS_SCLK cycles). | +| 11:5 | SFRMDLY | R/W | 0x0 | Serial Frame Delay Programmed value specifies the number (0 -127) of active one-half clocks (SS_SCLK) asserted from the most-significant bit of TX (output) or RX (input) being driven to SS_FRM.Do not used in PSP Network mode. | +| 4 | SFRMP | R/W | 0x0 | Serial Frame Polarity
0 = SS_FRM is active low (0x0)
1 = SS_FRM is active high (0x1) | +| 3 | FSRT | R/W | 0x0 | Frame Sync Relative Timing Bit
0 = Next frame is asserted after the end of the DMTSTOP timing
1 = Next frame is asserted with the LSB of the previous frame | +| 2 | ETDS | R/W | 0x0 | End Of Transfer Data State
0 = Low
1 = Last Value <Bit 0> | +| 1:0 | SCMODE | R/W | 0x0 | Serial Bit-rate Clock Mode
0x0 = Data Driven (Falling), Data Sampled (Rising), Idle State (Low)
0x1 = Data Driven (Rising), Data Sampled (Falling), Idle State (Low)
0x2 = Data Driven (Rising), Data Sampled (Falling), Idle State (High)
0x3 = Data Driven (Falling), Data Sampled (Rising), Idle State (High) | #### SSNWCR REGISTER SPI/I2S network control register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1C
BitsFieldTypeResetDescription
31:20RSVDR0Reserved for future use
19:12RTSAR/W0x0RX Time Slot Active, only used in network mode
0 = SPI/I2S port does not receive data in this time slot
1 = SPI/I2S port receives data in this time slot.
11:4TTSAR/W0x0TX Time Slot Active, only used in network mode
0 = SPI/I2S port does NOT transmit data in this time slot
1 = SPI/I2S port does transmit data in this time slot
3:1FRDCR/W0x0Frame Rate Divider Control Value of 0x0-0x7 specifies the number of time slots per frame when in network mode (the actual number of time slots is this field +1, so 1 to 8 time slots can be specified).
0MODR/W0x0Mode
0 = Normal mode
1 = Network mode. When set this bit to 1, must make sure at same time SSCR[FRF]=0x3
+**Offset: 0x1C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:20 | RSVD | R | 0 | Reserved for future use | +| 19:12 | RTSA | R/W | 0x0 | RX Time Slot Active, only used in network mode
0 = SPI/I2S port does not receive data in this time slot
1 = SPI/I2S port receives data in this time slot. | +| 11:4 | TTSA | R/W | 0x0 | TX Time Slot Active, only used in network mode
0 = SPI/I2S port does NOT transmit data in this time slot
1 = SPI/I2S port does transmit data in this time slot | +| 3:1 | FRDC | R/W | 0x0 | Frame Rate Divider Control Value of 0x0-0x7 specifies the number of time slots per frame when in network mode (the actual number of time slots is this field +1, so 1 to 8 time slots can be specified). | +| 0 | MOD | R/W | 0x0 | Mode
0 = Normal mode
1 = Network mode. When set this bit to 1, must make sure at same time SSCR[FRF]=0x3 | #### SSNWS REGISTER SPI/I2S network status register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x20
BitsFieldTypeResetDescription
31:4RSVDR0Reserved for future use
3NMBSYR0x0Network Mode Busy
0 = SPI/I2S port is in network mode and no frame is currently active
1 = SPI/I2S port is in network mode and a frame is currently active
2:0TSSR0x0Time Slot Status Value indicates which time slot is currently active. Because of synchronization between the SPI/I2S port's SS_SCLK domain and an internal bus clock domain, the value in this field becomes stable between the beginning and end of the currently active time slot.
+**Offset: 0x20** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | RSVD | R | 0 | Reserved for future use | +| 3 | NMBSY | R | 0x0 | Network Mode Busy
0 = SPI/I2S port is in network mode and no frame is currently active
1 = SPI/I2S port is in network mode and a frame is currently active | +| 2:0 | TSS | R | 0x0 | Time Slot Status Value indicates which time slot is currently active. Because of synchronization between the SPI/I2S port's SS_SCLK domain and an internal bus clock domain, the value in this field becomes stable between the beginning and end of the currently active time slot. | #### SSRWT REGISTER SPI/I2S root control register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x24
BitsFieldTypeResetDescription
31:5RSVDR0Reserved for future use
4MASK_RWOT_LAST_SAMPLER/W0x0Mask last_sample_flag in RWOT Mode
1 = Mask
0 = Unmask
3CLR_RWOT_CYCLER/W0x0Clear Internal rwot_counter
This field clears the rwot_counter to 0.
This field is self-cleared after SSCR[SSE] = 1.
1 = Clear rwot_counter
2SET_RWOT_CYCLER/W0x0Set RWOT Cycle This field is used to set the value of the RWTC register to the internal rwot_counter. This field is self-cleared by after SSCR[SSE] = 1.
1 = Set rwot_counter
1CYCLE_RWOT_ENR/W0x0Enable RWOT Cycle Counter Mode
1 = Enable
0 = Disable
0RWOTR/W0x0Receive Without Transmit
0 = Transmit/receive mode
1 = Receive without transmit mode
+**Offset: 0x24** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:5 | RSVD | R | 0 | Reserved for future use | +| 4 | MASK_RWOT_LAST_SAMPLE | R/W | 0x0 | Mask last_sample_flag in RWOT Mode
1 = Mask
0 = Unmask | +| 3 | CLR_RWOT_CYCLE | R/W | 0x0 | Clear Internal rwot_counter
This field clears the rwot_counter to 0.
This field is self-cleared after SSCR[SSE] = 1.
1 = Clear rwot_counter | +| 2 | SET_RWOT_CYCLE | R/W | 0x0 | Set RWOT Cycle This field is used to set the value of the RWTC register to the internal rwot_counter. This field is self-cleared by after SSCR[SSE] = 1.
1 = Set rwot_counter | +| 1 | CYCLE_RWOT_EN | R/W | 0x0 | Enable RWOT Cycle Counter Mode
1 = Enable
0 = Disable | +| 0 | RWOT | R/W | 0x0 | Receive Without Transmit
0 = Transmit/receive mode
1 = Receive without transmit mode | #### SSRWTCC REGISTER SPI/I2S root counter cycles match register. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x28
BitsFieldTypeResetDescription
31:0SSRWOTCCMR/W0x0It's just total SS_SCLK Cycles
The value of this register defines the total number of SS_SCLK cycles when SSP works in master and RWOT mode. When the rwot_counter matches this value, SSP returns to IDLE state and does not output SS_SCLK anymore.
+**Offset: 0x28** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | SSRWOTCCM | R/W | 0x0 | It's just total SS_SCLK Cycles
The value of this register defines the total number of SS_SCLK cycles when SSP works in master and RWOT mode. When the rwot_counter matches this value, SSP returns to IDLE state and does not output SS_SCLK anymore. | #### SSRWTCV REGISTER SPI/I2S root counter value write for read request register. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x2C
BitsFieldTypeResetDescription
31:0SSRWOTCVWRR/W0x0This register prevents the risk of instability on rwot_counter value reading, it's only valid after SPI/I2S has been enabled Write
0 = No effect Write
1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter
+**Offset: 0x2C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | SSRWOTCVWR | R/W | 0x0 | This register prevents the risk of instability on rwot_counter value reading, it's only valid after SPI/I2S has been enabled Write
0 = No effect Write
1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter | ## 17.3 UART @@ -3416,98 +1952,14 @@ All 10 UARTs support the 16550A and 167502 functions, but support slightly diffe The supported baud rates of each UART are tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
UARTSupport Baud Rates
960019.238.457.6115.223046092111.51.833.6
HzkHzMHz
1YesYesYesYesYesYesYesYesYesYesYesYesYes
2YesYesYesYesYesYesYesYesYesYesYesYesYes
3YesYesYesYesYesYesYesYesYesYesYesYesYes
4YesYesYesYesYesYesYesYesYesYesYesYesYes
+| UART | Support Baud Rates | +| --- | --- | +| 9600 | 19.2 | 38.4 | 57.6 | 115.2 | 230 | 460 | 921 | 1 | 1.5 | 1.8 | 3 | 3.6 | +| Hz | kHz | MHz | +| 1 | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | +| 2 | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | +| 3 | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | +| 4 | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | ### 17.3.2 Features @@ -3557,55 +2009,16 @@ The UARTs are functionally compatible with the 16550A and 16750 industry standar Each external signal that is connected to a UART module and how these pins function as modem control lines are tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameTypeDescription
RXDInputSerial Input
Serial data input to the Receive Shift register. In Infrared mode, it is connected to the infrared receiver input.
TXDOutputSerial Output
Serial data output to the communications-link peripheral, modem, or data set. The TXD signal is set to the logic 1 state upon a reset operation. It is connected to the output of the infrared transmitter in Infrared modeAuto-flow mode.
CTSnInputClear to Send
When asserted, indicates that the modem or data set is ready to exchange data. The CTSn signal is a modem status input, and its condition can be tested by reading the <CTS> field in the Modem Status Register. The <CTS> field is the complement of the CTSn signal. The <Delta Clear to Send> field in the Modem Status Register indicates whether the CTSn input has changed state since the last time the Modem Status Register was read. CTSn has no effect on the transmitter.
When the <CTS> field changes state and the modem-status interrupt is enabled, an interrupt is generated.

Non-Auto-flow mode:
When not in Auto-flow mode, the <CTS> field indicates the state of CTSn. The
<Delta Clear to Send> field indicates whether the CTSn input has changed state since the previous reading of MSR. CTSn has no effect on the transmitter. The user can program the UART to interrupt the K1 when DCTS changes state. Software can then stall the outgoing data stream by starving the Transmit FIFO or disabling the UART with the Interrupt Enable Register.
> Note. If UART transmission is stalled by disabling the UART, no Modem Status Register interrupt is received when CTSn re-asserts because disabling the UART also disables interrupts. To get around this issue, use either auto-CTS in Auto-flow mode or program the CTSn GPIO pin to interrupt.

Auto-flow mode:
In this mode, the UART Transmit circuit checks the state of CTSn before transmitting each byte. No data is transmitted when CTSn is high.
DSRnInputData Set Ready
When asserted, it indicates that the modem or data set is ready to establish a communications link with a UART. The DSRn signal is a modem-status input and its condition can be tested by reading the <Data Set Ready> field in the Modem Status Register, which is the complement of DSRn. The <Delta Data Set Ready> field in the Modem Status Register indicates whether the DSRn input has changed state since the Modem Status Register was last read. When the <Data Set Ready> changes state, an interrupt is generated if the modem-status interrupt is enabled.
DCDnInputData Carrier Detect
When asserted, indicates that the data carrier has been detected by the modem or data set. The DCDn signal is a modem-status input and its condition can be tested by reading the <Data Carrier Detect> field in the Modem Status Register, which is the complement of the DCDn signal. The <Delta Data Carrier Detect> field in the Modem Status Register indicates whether the DCDn input has changed state since the previous reading of the Modem Status Register. DCDn has no effect on the receiver.
An interrupt is generated when the <Data Carrier Detect> field changes state and the modem-status interrupt is enabled.
RinInputRing Indicator
When asserted, indicates that the modem or data set has received a telephone ringing signal. The RIn signal is a modem-status input and its condition can be tested by reading the <Ring Indicator> field in the Modem Status Register, which is the complement of the RIn signal. The <Trailing Edge Ring Indicator> field in the Modem Status Register indicates whether the RIn input has changed from low to high since the Modem Status Register was last read.
An interrupt is generated when the RI bit of the Modem Status Register changes from a high to low state and the modem-status interrupt is enabled.
DTRnOutputData Terminal Ready
When asserted, signals the modem or the data set that the UART is ready to establish a communications link. To assert the DTRn output (active low), set the <Data Terminal Ready> field in the Modem Control Register, which is the complement of the output signal. A reset operation de-asserts this signal (high). Loop-mode operation holds DTRn de-asserted.
RTSnOutputRequest To Send
When asserted, signals the modem or the data set that the UART is ready to exchange data. To assert the RTSn output (active low), set the <Request to Send> field in the Modem Control Register, which is the complement of the output signal. A reset operation de-asserts this signal (high). Loop-mode operation holds RTSn de-asserted.

Non-Auto-flow mode:
To assert the RTSn output (active low), set <Request to Send>.

Auto-flow mode:
RTSn is asserted automatically by the auto-flow circuitry when the Receive buffer exceeds its programmed trigger threshold. It is de-asserted when enough bytes are removed from the buffer to lower the data level back to the trigger threshold.
+| Name | Type | Description | +| --- | --- | --- | +| RXD | Input | Serial Input
Serial data input to the Receive Shift register. In Infrared mode, it is connected to the infrared receiver input. | +| TXD | Output | Serial Output
Serial data output to the communications-link peripheral, modem, or data set. The TXD signal is set to the logic 1 state upon a reset operation. It is connected to the output of the infrared transmitter in Infrared modeAuto-flow mode. | +| CTSn | Input | Clear to Send
When asserted, indicates that the modem or data set is ready to exchange data. The CTSn signal is a modem status input, and its condition can be tested by reading the <CTS> field in the Modem Status Register. The <CTS> field is the complement of the CTSn signal. The <Delta Clear to Send> field in the Modem Status Register indicates whether the CTSn input has changed state since the last time the Modem Status Register was read. CTSn has no effect on the transmitter.
When the <CTS> field changes state and the modem-status interrupt is enabled, an interrupt is generated.

Non-Auto-flow mode:
When not in Auto-flow mode, the <CTS> field indicates the state of CTSn. The
<Delta Clear to Send> field indicates whether the CTSn input has changed state since the previous reading of MSR. CTSn has no effect on the transmitter. The user can program the UART to interrupt the K1 when DCTS changes state. Software can then stall the outgoing data stream by starving the Transmit FIFO or disabling the UART with the Interrupt Enable Register.
> Note. If UART transmission is stalled by disabling the UART, no Modem Status Register interrupt is received when CTSn re-asserts because disabling the UART also disables interrupts. To get around this issue, use either auto-CTS in Auto-flow mode or program the CTSn GPIO pin to interrupt.

Auto-flow mode:
In this mode, the UART Transmit circuit checks the state of CTSn before transmitting each byte. No data is transmitted when CTSn is high. | +| DSRn | Input | Data Set Ready
When asserted, it indicates that the modem or data set is ready to establish a communications link with a UART. The DSRn signal is a modem-status input and its condition can be tested by reading the <Data Set Ready> field in the Modem Status Register, which is the complement of DSRn. The <Delta Data Set Ready> field in the Modem Status Register indicates whether the DSRn input has changed state since the Modem Status Register was last read. When the <Data Set Ready> changes state, an interrupt is generated if the modem-status interrupt is enabled. | +| DCDn | Input | Data Carrier Detect
When asserted, indicates that the data carrier has been detected by the modem or data set. The DCDn signal is a modem-status input and its condition can be tested by reading the <Data Carrier Detect> field in the Modem Status Register, which is the complement of the DCDn signal. The <Delta Data Carrier Detect> field in the Modem Status Register indicates whether the DCDn input has changed state since the previous reading of the Modem Status Register. DCDn has no effect on the receiver.
An interrupt is generated when the <Data Carrier Detect> field changes state and the modem-status interrupt is enabled. | +| Rin | Input | Ring Indicator
When asserted, indicates that the modem or data set has received a telephone ringing signal. The RIn signal is a modem-status input and its condition can be tested by reading the <Ring Indicator> field in the Modem Status Register, which is the complement of the RIn signal. The <Trailing Edge Ring Indicator> field in the Modem Status Register indicates whether the RIn input has changed from low to high since the Modem Status Register was last read.
An interrupt is generated when the RI bit of the Modem Status Register changes from a high to low state and the modem-status interrupt is enabled. | +| DTRn | Output | Data Terminal Ready
When asserted, signals the modem or the data set that the UART is ready to establish a communications link. To assert the DTRn output (active low), set the <Data Terminal Ready> field in the Modem Control Register, which is the complement of the output signal. A reset operation de-asserts this signal (high). Loop-mode operation holds DTRn de-asserted. | +| RTSn | Output | Request To Send
When asserted, signals the modem or the data set that the UART is ready to exchange data. To assert the RTSn output (active low), set the <Request to Send> field in the Modem Control Register, which is the complement of the output signal. A reset operation de-asserts this signal (high). Loop-mode operation holds RTSn de-asserted.

Non-Auto-flow mode:
To assert the RTSn output (active low), set <Request to Send>.

Auto-flow mode:
RTSn is asserted automatically by the auto-flow circuitry when the Receive buffer exceeds its programmed trigger threshold. It is de-asserted when enough bytes are removed from the buffer to lower the data level back to the trigger threshold. | The pins transmit digital CMOS-level signals are connected to K1 through GPIOs (refer to Section [Multi-Function Pin Registers](3.Pinout.md#36-multi-function-pin-registers)). @@ -3631,7 +2044,7 @@ When the UART unit is disabled, the transmitter or receiver finishes the current #### FIFO Operation -Each UART has a Transmit FIFO and a Receive FIFO, with each FIFO holding 64 characters of data.There are 2 methods for moving data into or out of the FIFOs: DMA, Program I/O. +Each UART has a Transmit FIFO and a Receive FIFO, with each FIFO holding 64 characters of data. There are 2 methods for moving data into or out of the FIFOs: DMA, Program I/O. In DMA mode, interrupts are used to control the data flow; whereas, in Program I/O mode, polling is used. @@ -3690,7 +2103,7 @@ The UART has 2 DMA requests: 1 for Transmit data service and 1 for Receive data ##### DMA Receive Programming Errors -If the DMA channel stops prematurely due to the end of a Descriptor chain or other error, the K1 must be notified since the DMAC can no longer service the UARTs FIFOs.If this occurs, the K1 must correct the situation by programming another Descriptor or by servicing the FIFOs via interrupt or polling mode, as described above. There are 2 methods for notifying the K1 of a stopped DMA channel: +If the DMA channel stops prematurely due to the end of a Descriptor chain or other error, the K1 must be notified since the DMAC can no longer service the UARTs FIFOs. If this occurs, the K1 must correct the situation by programming another Descriptor or by servicing the FIFOs via interrupt or polling mode, as described above. There are 2 methods for notifying the K1 of a stopped DMA channel: - Program the DMAC to interrupt on the event of a stopped channel by setting DCSR[StopIrqEn]. - For the Receive channel, the UART interrupts with an end-of-Descriptor chain (EOC) interrupt if \ is set, such that the UART makes a DMA request to remove trailing bytes (see Removing Trailing Bytes In DMA Mode). Using the UART interrupt for the Receive channel is preferable to the DMA DCSR interrupt because extra logic exists to ensure that the UART EOC interrupt asserts only when necessary. For example, a UART EOC interrupt does not assert if the UART has completed the reception of its message (indicated by the character timeout timer) and the Receive FIFO is empty. The \ field in the Interrupt Identification Register interrupt does not assert if \ is cleared. @@ -3774,114 +2187,27 @@ PIO—the K1 is restricted to reading or writing 1, 2, or 4 bytes per word. When #### Programmable Baud-Rate Generator -Each UART contains a programmable baud-rate generator that can take a fixed-input clock and divide it down to generate the preferred baud rate. The baud rate is calculated by taking the 14.7456 MHz fixed-input clock or the 57.60 MHz clock (in high speed mode and dividing it by the Divisor Latch Low Register. For high speed mode, a divisor of 1 or 2 is required. +Each UART contains a programmable baud-rate generator that can take a fixed-input clock and divide it down to generate the preferred baud rate. The baud rate is calculated by taking the 14.7456 MHz fixed-input clock or the 57.60 MHz clock in high speed mode and dividing it by the Divisor Latch Low Register. For high speed mode, a divisor of 1 or 2 is required. The baud-rate generator output frequency is 16 times the baud rate. Two 8-bit Divisor Latch Registers (Divisor Latch Low Register and Divisor Latch High Register as described in the _K1__ Registers_) store the divisor in a 16-bit binary format. Load these divisor latches during initialization to ensure that the baud-rate generator operates properly. The 16X clock stops if each Divisor Latch register is loaded with 0x0. The recommended baud rates based on divisor values (Divisor Latch High Byte Register / Divisor Latch Low Byte Register) is tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Required Baud RateDivisor 14.7456 MHz
Actual Baud Rate		48 MHz Actual Baud Rate57.60 MHz Actual Baud Rate
9600969600——
192004819200——
384002438400——
576001657600——
1152008115200——
2304004230400——
4608002460800——
9216001921600——
10000003—1000000—
15000002—1500000—
18420002——1954398
30000001—3000000—
36864001——3908796
+| Required Baud Rate | Divisor | 14.7456 MHz
Actual Baud Rate | 48 MHz Actual Baud Rate | 57.60 MHz Actual Baud Rate | +| --- | --- | --- | --- | --- | +| 9600 | 96 | 9600 | — | — | +| 19200 | 48 | 19200 | — | — | +| 38400 | 24 | 38400 | — | — | +| 57600 | 16 | 57600 | — | — | +| 115200 | 8 | 115200 | — | — | +| 230400 | 4 | 230400 | — | — | +| 460800 | 2 | 460800 | — | — | +| 921600 | 1 | 921600 | — | — | +| 1000000 | 3 | — | 1000000 | — | +| 1500000 | 2 | — | 1500000 | — | +| 1842000 | 2 | — | — | 1954398 | +| 3000000 | 1 | — | 3000000 | — | +| 3686400 | 1 | — | — | 3908796 | The divisor reset value is 0x0002. Changing the baud rate (writing to registers Divisor Latch Low Byte Register and Divisor Latch High Byte Register) is not permitted while actively transmitting or receiving data. @@ -3896,157 +2222,45 @@ The divisor reset value is 0x0002. Changing the baud rate (writing to registers In non-FIFO mode, this register holds the character(s) received by the UART Receive Shift Register. If this register is configured to use fewer than 8 bits, the bits are right-justified and the most significant bits (MSbs) are zeroed. Reading the register empties the register and clears the \ field in the Line Status Register. This register latches the value of the data byte at the front of the FIFO in FIFO mode. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31:24BYTE_3RO0x0Byte 3.
This field is only valid in 32-bit peripheral bus mode.
23:16BYTE_2RO0x0Byte 2.
This field is only valid in 32-bit peripheral bus mode.
15:8BYTE_1RO0x0Byte 1.
This field is only valid in 32-bit peripheral bus mode.
7:0BYTE_0RO0x0Byte 0.
This field is only valid in 32-bit peripheral bus mode.
+**Offset: 0x0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | BYTE_3 | RO | 0x0 | Byte 3.
This field is only valid in 32-bit peripheral bus mode. | +| 23:16 | BYTE_2 | RO | 0x0 | Byte 2.
This field is only valid in 32-bit peripheral bus mode. | +| 15:8 | BYTE_1 | RO | 0x0 | Byte 1.
This field is only valid in 32-bit peripheral bus mode. | +| 7:0 | BYTE_0 | RO | 0x0 | Byte 0.
This field is only valid in 32-bit peripheral bus mode. | #### Transmit Holding Register This register holds the data byte(s) to be transmitted next in non-FIFO mode. When the Transmit Shift Register is emptied, the contents of this register are loaded into the Transmit Shift Register and the \ field in the Line Status Register is set. A write to Transmit Holding Register puts data at the top of the FIFO in FIFO mode. The data at the front of the FIFO is loaded into the Transmit Shift Register when the Transmit Shift Register is empty. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31:24BYTE_3WO0x0Byte 3.
This field is only valid in 32-bit peripheral bus mode.
23:16BYTE_2WO0x0Byte 2.
This field is only valid in 32-bit peripheral bus mode.
15:8BYTE_1WO0x0Byte 1.
This field is only valid in 32-bit peripheral bus mode.
7:0BYTE_0WO0x0Byte 1.
This field is only valid in 32-bit peripheral bus mode.
+**Offset: 0x0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | BYTE_3 | WO | 0x0 | Byte 3.
This field is only valid in 32-bit peripheral bus mode. | +| 23:16 | BYTE_2 | WO | 0x0 | Byte 2.
This field is only valid in 32-bit peripheral bus mode. | +| 15:8 | BYTE_1 | WO | 0x0 | Byte 1.
This field is only valid in 32-bit peripheral bus mode. | +| 7:0 | BYTE_0 | WO | 0x0 | Byte 1.
This field is only valid in 32-bit peripheral bus mode. | #### Divisor Latch Low Byte Register - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31:8ReservedRO0x0Reserved for future use.
7:0DLLRW0x2Divisor Latch Low.
Low-byte compare value to generate baud rate.
+**Offset: 0x0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved for future use. | +| 7:0 | DLL | RW | 0x2 | Divisor Latch Low.
Low-byte compare value to generate baud rate. | #### Divisor Latch High Byte Register - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31:10ReservedRO0x0Reserved for future use.
7:0DLHRW0xxDivisor Latch High.
High-byte compare value to generate baud rate.
+**Offset: 0x4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:10 | Reserved | RO | 0x0 | Reserved for future use. | +| 7:0 | DLH | RW | 0xx | Divisor Latch High.
High-byte compare value to generate baud rate. | #### Interrupt Enable Register @@ -4062,83 +2276,19 @@ The \ field is used to enable DMA requests. This register al Software must not set the \ field while the \ or \ fields are set to ensure that the DMA controller and programmed I/O do not access the same FIFO. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31:8ReservedRO0x0Reserved for future use.
7DMAERW0x0DMA Requests Enable.
0 = DMA requests are disabled.
1 = DMA requests are enabled.
6UUERW0x0UART Unit Enable.
UART transmit and receive enable. Transmit data can be written to the Transmit Holding Register before the UART unit is enabled. When the UART unit is disabled, the transmitter or receiver finishes the current byte and stops transmitting or receiving more data. Data in the FIFO is not cleared and transmission resumes when the UART is enabled
0 = Unit is disabled.
1 = Unit is enabled.
5NRZERW0x0NRZ Coding Enable.
NRZ encoding/decoding is only used in UART mode, not in infrared mode. If the serial infrared receiver or transmitter is enabled, NRZ coding is disabled.
0 = NRZ coding disabled.
1 = NRZ coding enabled.
4RTOIERW0x0Receiver Time-out Interrupt Enable.
The source for this field is the <Time Out Detected> field in the Interrupt Identification Register.
0 = Receiver data time-out interrupt disabled.
1 = Receiver data time-out interrupt enabled.
3MIERW0x0Modem Interrupt Enable.
The source for this field is the <Interrupt Source Encoded> field in the Interrupt Identification Register.
0 = Modem status interrupt disabled.
1 = Modem status interrupt enabled.
2RLSERW0x0Receiver Line Status Interrupt Enable.
The source for this field is the <Interrupt Source Encoded> field in the Interrupt Identification Register.
0 = Receiver line status interrupt disabled.
1 = Receiver line status interrupt enabled.
1TIERW0x0Transmit Data Request Interrupt Enable.
The source for this field is the <Interrupt Source Encoded> field in the Interrupt Identification Register.
0 = Transmit FIFO data request interrupt disabled.
1 = Transmit FIFO data request interrupt enabled.
0RAVIERW0x0Receiver Data Available Interrupt Enable.
The source for this field is the <Interrupt Source Encoded> field in the Interrupt Identification Register.
0 = Receiver data available (trigger threshold reached) interrupt disabled.
1 = Receiver data available (trigger threshold reached) interrupt enabled.
+**Offset: 0x4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved for future use. | +| 7 | DMAE | RW | 0x0 | DMA Requests Enable.
0 = DMA requests are disabled.
1 = DMA requests are enabled. | +| 6 | UUE | RW | 0x0 | UART Unit Enable.
UART transmit and receive enable. Transmit data can be written to the Transmit Holding Register before the UART unit is enabled. When the UART unit is disabled, the transmitter or receiver finishes the current byte and stops transmitting or receiving more data. Data in the FIFO is not cleared and transmission resumes when the UART is enabled
0 = Unit is disabled.
1 = Unit is enabled. | +| 5 | NRZE | RW | 0x0 | NRZ Coding Enable.
NRZ encoding/decoding is only used in UART mode, not in infrared mode. If the serial infrared receiver or transmitter is enabled, NRZ coding is disabled.
0 = NRZ coding disabled.
1 = NRZ coding enabled. | +| 4 | RTOIE | RW | 0x0 | Receiver Time-out Interrupt Enable.
The source for this field is the <Time Out Detected> field in the Interrupt Identification Register.
0 = Receiver data time-out interrupt disabled.
1 = Receiver data time-out interrupt enabled. | +| 3 | MIE | RW | 0x0 | Modem Interrupt Enable.
The source for this field is the <Interrupt Source Encoded> field in the Interrupt Identification Register.
0 = Modem status interrupt disabled.
1 = Modem status interrupt enabled. | +| 2 | RLSE | RW | 0x0 | Receiver Line Status Interrupt Enable.
The source for this field is the <Interrupt Source Encoded> field in the Interrupt Identification Register.
0 = Receiver line status interrupt disabled.
1 = Receiver line status interrupt enabled. | +| 1 | TIE | RW | 0x0 | Transmit Data Request Interrupt Enable.
The source for this field is the <Interrupt Source Encoded> field in the Interrupt Identification Register.
0 = Transmit FIFO data request interrupt disabled.
1 = Transmit FIFO data request interrupt enabled. | +| 0 | RAVIE | RW | 0x0 | Receiver Data Available Interrupt Enable.
The source for this field is the <Interrupt Source Encoded> field in the Interrupt Identification Register.
0 = Receiver data available (trigger threshold reached) interrupt disabled.
1 = Receiver data available (trigger threshold reached) interrupt enabled. | #### Interrupt Identification Register @@ -4163,233 +2313,53 @@ The trigger level must be equal to the DMA burst length programmed in the DMA re When the number of bytes in the receive FIFO equals the interrupt trigger level programmed into this field and the received-data-available interrupt is enabled (via the Interrupt Enable Register), an interrupt is generated and the appropriate bits are set in the Interrupt Identification Register. The receive DMA request is generated as well when trigger level is reached. The trigger level must be greater than or equal to the DMA burst size programmed in the DMA registers. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8
BitsFieldTypeResetDescription
31:8ReservedRO0x0Reserved for future use.
7:6ITL
WO0x0Interrupt Trigger Level (threshold)
When the number of bytes in the receive FIFO equals the interrupt trigger threshold programmed into this field and the received-data-available interrupt is enabled via the Interrupt Enable Register, an interrupt is generated and appropriate bits are set in the Interrupt Identification Register. The receive DMA request is also generated when the trigger threshold is reached.
0x0 = 1 byte or more in FIFO causes interrupt (not valid in DMA mode).
0x1 = 8 bytes or more in FIFO causes interrupt and DMA request.
0x2 = 16 bytes or more in FIFO causes interrupt and DMA request.
0x3 = 32 bytes or more in FIFO causes interrupt and DMA request.
5BUSWO0x032-Bit Peripheral Bus.
0 = 8-bit peripheral bus.
1 = 32-bit peripheral bus.
4TRAILWO0x0Trailing Bytes.
0 = Trailing bytes are removed by the K1.
1 = Trailing bytes are removed by the DMAC.
3TILWO0x0Transmitter Interrupt Level
0 = Interrupt/DMA request when FIFO is half empty
1 = Interrupt/DMA request when FIFO is empty
2RESETTFWO0x0Reset Transmit FIFO.
When this field is set, all the bytes in the transmit FIFO are cleared. The <Transmit Data Request> field in the Line Status Register is set and the Interrupt Identification Register shows a transmitter requests data interrupt, if the <Transmit Data Request Interrupt Enable> field in the Interrupt Enable Register is set. The Transmit Shift Register is not cleared, and it completes the current transmission.
0 = Writing 0 has no effect.
1 = The transmit FIFO is cleared.
1RESETRFWO0x0Reset Receive FIFO.
When this field is set, all the bytes in the receive FIFO are cleared. The <Data Ready> field in the Line Status Register is reset to 0. All the error bits in the FIFO and the <FIFO Error Status> field in the Line Status Register are cleared. Any error bits, OE, PE, FE or BI, that had been set in the Line Status Register are still set. The Receive Shift Register is not cleared. If the Interrupt Identification Register had been set to receive data available, it is cleared.
0 = No effect.
1 = The receive FIFO is cleared.
0TRFIFOEWO0x0Transmit and Receive FIFO Enable.
This field enables/disables the transmit and receive FIFOs. When set, both FIFOs are enabled (FIFO mode). When clear, the FIFOs are both disabled (non-FIFO mode). Writing 0x0 to this field clears all bytes in both FIFOs. When changing from FIFO mode to non-FIFO mode and vice versa, data is cleared automatically from the FIFOs. This field must be set when other fields in this register are written or the other bits are not programmed.
0 = FIFOs are disabled.
1 = FIFOs are enabled.
+**Offset: 0x8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved for future use. | +| 7:6 | ITL | WO | 0x0 | Interrupt Trigger Level (threshold)
When the number of bytes in the receive FIFO equals the interrupt trigger threshold programmed into this field and the received-data-available interrupt is enabled via the Interrupt Enable Register, an interrupt is generated and appropriate bits are set in the Interrupt Identification Register. The receive DMA request is also generated when the trigger threshold is reached.
0x0 = 1 byte or more in FIFO causes interrupt (not valid in DMA mode).
0x1 = 8 bytes or more in FIFO causes interrupt and DMA request.
0x2 = 16 bytes or more in FIFO causes interrupt and DMA request.
0x3 = 32 bytes or more in FIFO causes interrupt and DMA request. | +| 5 | BUS | WO | 0x0 | 32-Bit Peripheral Bus.
0 = 8-bit peripheral bus.
1 = 32-bit peripheral bus. | +| 4 | TRAIL | WO | 0x0 | Trailing Bytes.
0 = Trailing bytes are removed by the K1.
1 = Trailing bytes are removed by the DMAC. | +| 3 | TIL | WO | 0x0 | Transmitter Interrupt Level
0 = Interrupt/DMA request when FIFO is half empty
1 = Interrupt/DMA request when FIFO is empty | +| 2 | RESETTF | WO | 0x0 | Reset Transmit FIFO.
When this field is set, all the bytes in the transmit FIFO are cleared. The <Transmit Data Request> field in the Line Status Register is set and the Interrupt Identification Register shows a transmitter requests data interrupt, if the <Transmit Data Request Interrupt Enable> field in the Interrupt Enable Register is set. The Transmit Shift Register is not cleared, and it completes the current transmission.
0 = Writing 0 has no effect.
1 = The transmit FIFO is cleared. | +| 1 | RESETRF | WO | 0x0 | Reset Receive FIFO.
When this field is set, all the bytes in the receive FIFO are cleared. The <Data Ready> field in the Line Status Register is reset to 0. All the error bits in the FIFO and the <FIFO Error Status> field in the Line Status Register are cleared. Any error bits, OE, PE, FE or BI, that had been set in the Line Status Register are still set. The Receive Shift Register is not cleared. If the Interrupt Identification Register had been set to receive data available, it is cleared.
0 = No effect.
1 = The receive FIFO is cleared. | +| 0 | TRFIFOE | WO | 0x0 | Transmit and Receive FIFO Enable.
This field enables/disables the transmit and receive FIFOs. When set, both FIFOs are enabled (FIFO mode). When clear, the FIFOs are both disabled (non-FIFO mode). Writing 0x0 to this field clears all bytes in both FIFOs. When changing from FIFO mode to non-FIFO mode and vice versa, data is cleared automatically from the FIFOs. This field must be set when other fields in this register are written or the other bits are not programmed.
0 = FIFOs are disabled.
1 = FIFOs are enabled. | #### Line Control Register This register specifies the format for the asynchronous data-communications exchange. The serial-data format consists of a start bit, 8 data bits, an optional parity bit, and 1 stop bit. This register has bits that allow access to the Divisor Latch registers and bits that can cause a break condition. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC
BitsFieldTypeResetDescription
31:8ReservedRO0x0Reserved for future use.
7DLABRW0x0Divisor Latch Access Bit.
Must be set to access the Divisor Latch registers of the baud-rate generator during a read or write operation. Must be clear to access the receive buffer, the Transmit Holding Register or the Interrupt Enable Register.
0 = access Transmit Holding Register, Receive Buffer Register, and Interrupt Enable Register.
1 = access Divisor Latch registers (DLL and DLH)
6SBRW0x0Set Break.
Causes a break condition to be transmitted to the receiving UART. Acts only on the TXD pin and has no effect on the transmit logic. In FIFO mode, wait until the transmitter is idle (<Transmitter Empty> field in the Line Status Register = 1] to set and clear SB.
0 = No effect on TXD output.
1 = Forces TXD output to 0 (space).
5STKYPRW0x0Sticky Parity.
Forces the bit value at the parity bit location to be the opposite of the <Even Parity Select> field rather than the parity value. This stops parity generation. If <Parity Enable> = 0, this field is ignored.
0 = No effect on parity bit.
1 = Forces parity bit to be opposite of <Even Parity Select> field value.
4EPSRW0x0Even Parity Select.
If <Parity Enable> = 0, this field is ignored.
0 = Sends or checks for odd parity.
1 = Sends or checks for even parity
3PENRW0x0Parity Enable.This field enables a parity bit to be generated on transmission or checked on reception.
0 = No parity.
1 = Parity
2STBRW0x0Stop Bits.
Specifies the number of stop bits transmitted and received in each character. When receiving, the receiver checks only the first stop bit. This field must be clear.
0 = 1 stop bit.
1:0WLS10RW0x0Word Length Select.
Specifies the number of data bits in each transmitted or received character.
0x0, 0x1, 0x2 = 7-bit character.
0x3 = 8-bit character.
+**Offset: 0xC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved for future use. | +| 7 | DLAB | RW | 0x0 | Divisor Latch Access Bit.
Must be set to access the Divisor Latch registers of the baud-rate generator during a read or write operation. Must be clear to access the receive buffer, the Transmit Holding Register or the Interrupt Enable Register.
0 = access Transmit Holding Register, Receive Buffer Register, and Interrupt Enable Register.
1 = access Divisor Latch registers (DLL and DLH) | +| 6 | SB | RW | 0x0 | Set Break.
Causes a break condition to be transmitted to the receiving UART. Acts only on the TXD pin and has no effect on the transmit logic. In FIFO mode, wait until the transmitter is idle (<Transmitter Empty> field in the Line Status Register = 1] to set and clear SB.
0 = No effect on TXD output.
1 = Forces TXD output to 0 (space). | +| 5 | STKYP | RW | 0x0 | Sticky Parity.
Forces the bit value at the parity bit location to be the opposite of the <Even Parity Select> field rather than the parity value. This stops parity generation. If <Parity Enable> = 0, this field is ignored.
0 = No effect on parity bit.
1 = Forces parity bit to be opposite of <Even Parity Select> field value. | +| 4 | EPS | RW | 0x0 | Even Parity Select.
If <Parity Enable> = 0, this field is ignored.
0 = Sends or checks for odd parity.
1 = Sends or checks for even parity | +| 3 | PEN | RW | 0x0 | Parity Enable. This field enables a parity bit to be generated on transmission or checked on reception.
0 = No parity.
1 = Parity | +| 2 | STB | RW | 0x0 | Stop Bits.
Specifies the number of stop bits transmitted and received in each character. When receiving, the receiver checks only the first stop bit. This field must be clear.
0 = 1 stop bit. | +| 1:0 | WLS10 | RW | 0x0 | Word Length Select.
Specifies the number of data bits in each transmitted or received character.
0x0, 0x1, 0x2 = 7-bit character.
0x3 = 8-bit character. | #### Modem Control Register This register uses the modem control pins RTSn and DTRn to control the interface with a modem or data set. This register also controls the loopback mode. Loopback mode must be enabled before the UART is enabled. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x10
BitsFieldTypeResetDescription
31:8ReservedRO0x0Reserved for future use.
7EPT_RXREQ_ENRW0x0this bit set to enable uart send dma_rx_req when time out not care the fifo empty state.
0=do not send dma_rxreq when fifo empty.
1= send dma_rxreq when time out no matter if there is data in the rx fifo.
6EOR_INT_MASKRW0x0mask bit for eor interrupt.
0 = eor interrupt detection logic will work.
1 = eor interrupt detection logic will not work.
5AFERW0x0Auto-flow Control Enable.
0 = Auto-RTS and auto-CTS are disabled.
1 = Auto-CTS is enabled. If <Request to Send> is also set, both auto-CTS and auto-RTS are enabled.
4LOOPRW0x0Loopback Mode.
This field provides a local loopback feature for diagnostic testing of the UART. When set, the following occurs: The transmitter serial output is set to a logic 1 state. The receiver serial input is disconnected from the pin. The output of the Transmit Shift Register is <q>looped back</q> into the Receive Shift Register input. The four modem control inputs (CTSn, DSRn, DCDn, and RIn) are disconnected from the pins and the modem control output pins (RTSn and DTRn) are forced to their inactive state. Coming out of the loopback mode may result in unpredictable activation of the delta bits (bits 30) in the Modem Status Register. CHIP recommends that the Modem Status Register be read once to clear its delta bits. Loopback mode must be configured before the UART is enabled. The lower four bits of this register are connected to the upper four Modem Status Register bits.<Data Terminal Ready> = 1 forces <Data Set Ready> in the Modem Status Register to a 1.<Request to Send> = 1 forces <Clear to Send> in the Modem Status Register to a 1.<Test Bit> = 1 forces <Ring Indicator> in the Modem Status Register to a 1.<OUT2 Signal Control> = 1 forces <Data Carrier Detect> in the Modem Status Register to a 1.In loopback mode, data that is transmitted is received immediately. This feature allows the <var Product Number> to verify the transmit and receive data paths of the UART. The transmit, receive, and modem-control interrupts are operational, except that the modem control interrupts are activated by Modem Control Register bits, not by the modem-control pins. A break signal can also be transferred from the transmitter section to the receiver section in loopback mode.
0 = normal UART operation.
1 = loopback-mode UART operation.
3OUT2RW0x0OUT2 Signal Control.
OUT2 connects the UART interrupt output to the interrupt controller unit. When <Loopback Mode> is clear.
0 = UART interrupt is disabled.1 = UART interrupt is enabled.When <Loopback Mode> is set, interrupts always go to the <var Product Number>.
0 = <Data Carrier Detect> field in the Modem Status Register forced to 0.
1 = <Data Carrier Detect> field forced to 1.
2ReservedRO0x0Reserved for future use.
1RTSRW0x0Request to Send.
0 = Non-auto-flow mode. RTSn pin is 1. Auto-RTS disabled. Auto-flow works only with auto-CTS.
1 = Auto-flow mode. RTSn pin is 0. Auto-RTS enabled. Auto-flow works with both auto-CTS and auto-RTS.
0DTRRW0x0Data Terminal Ready.
0 = DTRn pin is 1.
1 = DTRn pin is 0.
+**Offset: 0x10** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved for future use. | +| 7 | EPT_RXREQ_EN | RW | 0x0 | this bit set to enable uart send dma_rx_req when time out not care the fifo empty state.
0=do not send dma_rxreq when fifo empty.
1= send dma_rxreq when time out no matter if there is data in the rx fifo. | +| 6 | EOR_INT_MASK | RW | 0x0 | mask bit for eor interrupt.
0 = eor interrupt detection logic will work.
1 = eor interrupt detection logic will not work. | +| 5 | AFE | RW | 0x0 | Auto-flow Control Enable.
0 = Auto-RTS and auto-CTS are disabled.
1 = Auto-CTS is enabled. If <Request to Send> is also set, both auto-CTS and auto-RTS are enabled. | +| 4 | LOOP | RW | 0x0 | Loopback Mode.
This field provides a local loopback feature for diagnostic testing of the UART. When set, the following occurs: The transmitter serial output is set to a logic 1 state. The receiver serial input is disconnected from the pin. The output of the Transmit Shift Register is <q>looped back</q> into the Receive Shift Register input. The four modem control inputs (CTSn, DSRn, DCDn, and RIn) are disconnected from the pins and the modem control output pins (RTSn and DTRn) are forced to their inactive state. Coming out of the loopback mode may result in unpredictable activation of the delta bits (bits 30) in the Modem Status Register. CHIP recommends that the Modem Status Register be read once to clear its delta bits. Loopback mode must be configured before the UART is enabled. The lower four bits of this register are connected to the upper four Modem Status Register bits.<Data Terminal Ready> = 1 forces <Data Set Ready> in the Modem Status Register to a 1.<Request to Send> = 1 forces <Clear to Send> in the Modem Status Register to a 1.<Test Bit> = 1 forces <Ring Indicator> in the Modem Status Register to a 1.<OUT2 Signal Control> = 1 forces <Data Carrier Detect> in the Modem Status Register to a 1.In loopback mode, data that is transmitted is received immediately. This feature allows the <var Product Number> to verify the transmit and receive data paths of the UART. The transmit, receive, and modem-control interrupts are operational, except that the modem control interrupts are activated by Modem Control Register bits, not by the modem-control pins. A break signal can also be transferred from the transmitter section to the receiver section in loopback mode.
0 = normal UART operation.
1 = loopback-mode UART operation. | +| 3 | OUT2 | RW | 0x0 | OUT2 Signal Control.
OUT2 connects the UART interrupt output to the interrupt controller unit. When <Loopback Mode> is clear.
0 = UART interrupt is disabled.
1 = UART interrupt is enabled. When <Loopback Mode> is set, interrupts always go to the <var Product Number>.
0 = <Data Carrier Detect> field in the Modem Status Register forced to 0.
1 = <Data Carrier Detect> field forced to 1. | +| 2 | Reserved | RO | 0x0 | Reserved for future use. | +| 1 | RTS | RW | 0x0 | Request to Send.
0 = Non-auto-flow mode. RTSn pin is 1. Auto-RTS disabled. Auto-flow works only with auto-CTS.
1 = Auto-flow mode. RTSn pin is 0. Auto-RTS enabled. Auto-flow works with both auto-CTS and auto-RTS. | +| 0 | DTR | RW | 0x0 | Data Terminal Ready.
0 = DTRn pin is 1.
1 = DTRn pin is 0. | #### Line Status Register @@ -4401,83 +2371,19 @@ This register must be read before the erroneous character is read. Bits [4:1] re See FIFO DMA Mode Operation in **S****ection**** 18.3.3.4.6** for details on using the DMAC to receive data. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14
BitsFieldTypeResetDescription
31:8ReservedRO0x0Reserved for future use.
7FIFOERO0x0FIFO Error Status.
In non-FIFO mode, this bit is clear. In FIFO mode, this field is set when there is at least one parity error, framing error, or break indication for any of the characters in the FIFO. A <var Product Number> read of the this register does not reset this field. This field is reset when all erroneous characters have been read from the FIFO. If DMA requests are enabled (<DMA Requests Enable> field in the Interrupt Enable Register set) and this field is set, the error interrupt is generated, and no receive DMA request is generated even when the receive FIFO reaches the trigger threshold. Once the errors have been cleared by reading the FIFO, DMA requests are re-enabled automatically. If DMA requests are not enabled (<DMA Requests Enable> field clear), this field set does not generate an error interrupt.
0 = No FIFO or no errors in receive FIFO.
1 = At least one character in receive FIFO has errors.
6TEMTRO0x1Transmitter Empty.
Set when the Transmit Holding Register and the Transmit Shift Register are both empty. It is cleared when either the Transmit Holding Register or the Transmit Shift Register contains a data character. In FIFO mode, this field is set when the transmit FIFO and the Transmit Shift Register are both empty.
0 = There is data in the Transmit Shift Register, the Transmit Holding Register, or the FIFO.
1 = All the data in the transmitter has been shifted out.
5TDRQRO0x1Transmit Data Request.
This field indicates that the UART is ready to accept a new character for transmission. In addition, this field causes the UART to issue an interrupt to the <var Product Number> when the transmit data request interrupt enable is set and generates the DMA request to the DMA controller if DMA requests and FIFO mode are enabled. This field is set when a character is transferred from the Transmit Holding Register into the Transmit Shift Register. This field is cleared with the loading of the Transmit Holding Register. In FIFO mode, this field is set when half of the characters in the FIFO have been loaded into the Transmit Shift Register or the <Reset Transmit FIFO> field in the FIFO Control Register has been set. It is cleared when the FIFO has more than half data. If more than 64 characters are loaded into the FIFO, the excess characters are lost.
0 = There is data in the holding register or FIFO waiting to be shifted out.
1 = The transmit FIFO has half or less than half data.
4BIRO0x0Break Interrupt.
This field is set when the received data input is held low for longer than a full-word transmission time (the total time of start bit + data bits + parity bit + stop bit). It is cleared when the <var Product Number> reads the LSR. In FIFO mode, only one character equal to 0x00, is loaded into the FIFO regardless of the length of the break condition. BI shows the break condition for the character at the front of the FIFO, not the most recently received character.
0 = No break signal has been received.
1 = Break signal received.
3FERO0x0Framing Error.
This field indicates that the received character did not have a valid stop bit. It is set when the bit following the last data bit or parity bit is detected to be 0. It is cleared when the <var Product Number> reads this register. The UART will resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this start bit twice and then reads in the data. In FIFO mode, this field shows a framing error for the character at the front of the FIFO, not for the most recently received character.
0 = No Framing error.
1 = Invalid stop bit has been detected.
2PERO0x0Parity Error.
Indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. This field is set upon detection of a parity error and is cleared when the <var Product Number> reads this register. In FIFO mode, this field shows a parity error for the character at the front of the FIFO, not the most recently received character.
0 = No Parity error.
1 = Parity error has occurred.
1OERO0x0Overrun Error.
In non-FIFO mode, indicates that data in the Receive Buffer register was not read by the <var Product Number> before the next character was received. The new character is lost. In FIFO mode, this field indicates that all 64 bytes of the FIFO are full and the most recently received byte has been discarded. This field is set upon detection of an overrun condition and cleared when the <var Product Number> reads this register.
0 = No data has been lost.
1 = Receive data has been lost.
0DRRO0x0Data Ready.
Set when a complete incoming character has been received and transferred into the Receive Buffer Register or the FIFO. In non-FIFO mode, this field is cleared when the receive buffer is read. In FIFO mode, this field is cleared if the FIFO is empty (last character has been read from Receive Buffer Register) or the FIFO is reset with the <Reset Receive FIFO> field in the FIFO Control Register.
0 = No data has been received.
1 = Data is available in Receive Buffer Register or the FIFO.
+**Offset: 0x14** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved for future use. | +| 7 | FIFOE | RO | 0x0 | FIFO Error Status.
In non-FIFO mode, this bit is clear. In FIFO mode, this field is set when there is at least one parity error, framing error, or break indication for any of the characters in the FIFO. A <var Product Number> read of the this register does not reset this field. This field is reset when all erroneous characters have been read from the FIFO. If DMA requests are enabled (<DMA Requests Enable> field in the Interrupt Enable Register set) and this field is set, the error interrupt is generated, and no receive DMA request is generated even when the receive FIFO reaches the trigger threshold. Once the errors have been cleared by reading the FIFO, DMA requests are re-enabled automatically. If DMA requests are not enabled (<DMA Requests Enable> field clear), this field set does not generate an error interrupt.
0 = No FIFO or no errors in receive FIFO.
1 = At least one character in receive FIFO has errors. | +| 6 | TEMT | RO | 0x1 | Transmitter Empty.
Set when the Transmit Holding Register and the Transmit Shift Register are both empty. It is cleared when either the Transmit Holding Register or the Transmit Shift Register contains a data character. In FIFO mode, this field is set when the transmit FIFO and the Transmit Shift Register are both empty.
0 = There is data in the Transmit Shift Register, the Transmit Holding Register, or the FIFO.
1 = All the data in the transmitter has been shifted out. | +| 5 | TDRQ | RO | 0x1 | Transmit Data Request.
This field indicates that the UART is ready to accept a new character for transmission. In addition, this field causes the UART to issue an interrupt to the <var Product Number> when the transmit data request interrupt enable is set and generates the DMA request to the DMA controller if DMA requests and FIFO mode are enabled. This field is set when a character is transferred from the Transmit Holding Register into the Transmit Shift Register. This field is cleared with the loading of the Transmit Holding Register. In FIFO mode, this field is set when half of the characters in the FIFO have been loaded into the Transmit Shift Register or the <Reset Transmit FIFO> field in the FIFO Control Register has been set. It is cleared when the FIFO has more than half data. If more than 64 characters are loaded into the FIFO, the excess characters are lost.
0 = There is data in the holding register or FIFO waiting to be shifted out.
1 = The transmit FIFO has half or less than half data. | +| 4 | BI | RO | 0x0 | Break Interrupt.
This field is set when the received data input is held low for longer than a full-word transmission time (the total time of start bit + data bits + parity bit + stop bit). It is cleared when the <var Product Number> reads the LSR. In FIFO mode, only one character equal to 0x00, is loaded into the FIFO regardless of the length of the break condition. BI shows the break condition for the character at the front of the FIFO, not the most recently received character.
0 = No break signal has been received.
1 = Break signal received. | +| 3 | FE | RO | 0x0 | Framing Error.
This field indicates that the received character did not have a valid stop bit. It is set when the bit following the last data bit or parity bit is detected to be 0. It is cleared when the <var Product Number> reads this register. The UART will resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this start bit twice and then reads in the data. In FIFO mode, this field shows a framing error for the character at the front of the FIFO, not for the most recently received character.
0 = No Framing error.
1 = Invalid stop bit has been detected. | +| 2 | PE | RO | 0x0 | Parity Error.
Indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. This field is set upon detection of a parity error and is cleared when the <var Product Number> reads this register. In FIFO mode, this field shows a parity error for the character at the front of the FIFO, not the most recently received character.
0 = No Parity error.
1 = Parity error has occurred. | +| 1 | OE | RO | 0x0 | Overrun Error.
In non-FIFO mode, indicates that data in the Receive Buffer register was not read by the <var Product Number> before the next character was received. The new character is lost. In FIFO mode, this field indicates that all 64 bytes of the FIFO are full and the most recently received byte has been discarded. This field is set upon detection of an overrun condition and cleared when the <var Product Number> reads this register.
0 = No data has been lost.
1 = Receive data has been lost. | +| 0 | DR | RO | 0x0 | Data Ready.
Set when a complete incoming character has been received and transferred into the Receive Buffer Register or the FIFO. In non-FIFO mode, this field is cleared when the receive buffer is read. In FIFO mode, this field is cleared if the FIFO is empty (last character has been read from Receive Buffer Register) or the FIFO is reset with the <Reset Receive FIFO> field in the FIFO Control Register.
0 = No data has been received.
1 = Data is available in Receive Buffer Register or the FIFO. | #### Modem Status Register @@ -4487,177 +2393,45 @@ The status of the modem control lines does not affect the FIFOs. The \ field is set. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x18
BitsFieldTypeResetDescription
31:8ReservedRO0x0Reserved for future use.
7DCDRO0x0Data Carrier Detect.
Complement of the data-carrier-detect (DCDn) input. Equivalent to <OUT2 Signal Control> field in the Modem Control Register if <Loopback Mode> is set in the Modem Control Register.
0 = DCDn pin is 1.
1 = DCDn pin is 0.
6RIRO0x0Ring Indicator.
Complement of the ring-indicator (RIn) input. Equivalent to the <Test Bit> field in the Modem Control Register if <Loopback Mode> is set.
0 = RIn pin is 1.
1 = RIn pin is 0.
5DSRRO0x0Data Set Ready.
Complement of the data-set-ready (DSRn) input. Equivalent to <Data Terminal Ready> field in the Modem Control Register if <Loopback Mode> is set.
0 = DSRn pin is 1.
1 = DSRn pin is 0
4CTSRO0x0Clear to Send.
Complement of the clear-to-send (CTSn) input. Equivalent to <Request to Send> field in the Modem Control Register if <Loopback Mode> is set.
0 = CTSn pin is 1.
1 = CTSn pin is 0.
3DDCDRO0x0Delta Data Carrier Detect.
0 = No change in DCDn pin since the last read of this register.
1 = DCDn pin has changed state.
2TERIRO0x0Trailing Edge Ring Indicator.
0 = RIn pin has not changed from 0 to 1 since the last read of this register.
1 = RIn pin has changed state.
1DDSRRO0x0Delta Data Set Ready.
0 = No change in DSRn pin since the last read of this register.
1 = DSRn pin has changed state.
0DCTSRO0x0Delta Clear to Send.
0 = No change in CTSn pin since the last read of this register.
1 = CTSn pin has changed state.
+**Offset: 0x18** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved for future use. | +| 7 | DCD | RO | 0x0 | Data Carrier Detect.
Complement of the data-carrier-detect (DCDn) input. Equivalent to <OUT2 Signal Control> field in the Modem Control Register if <Loopback Mode> is set in the Modem Control Register.
0 = DCDn pin is 1.
1 = DCDn pin is 0. | +| 6 | RI | RO | 0x0 | Ring Indicator.
Complement of the ring-indicator (RIn) input. Equivalent to the <Test Bit> field in the Modem Control Register if <Loopback Mode> is set.
0 = RIn pin is 1.
1 = RIn pin is 0. | +| 5 | DSR | RO | 0x0 | Data Set Ready.
Complement of the data-set-ready (DSRn) input. Equivalent to <Data Terminal Ready> field in the Modem Control Register if <Loopback Mode> is set.
0 = DSRn pin is 1.
1 = DSRn pin is 0 | +| 4 | CTS | RO | 0x0 | Clear to Send.
Complement of the clear-to-send (CTSn) input. Equivalent to <Request to Send> field in the Modem Control Register if <Loopback Mode> is set.
0 = CTSn pin is 1.
1 = CTSn pin is 0. | +| 3 | DDCD | RO | 0x0 | Delta Data Carrier Detect.
0 = No change in DCDn pin since the last read of this register.
1 = DCDn pin has changed state. | +| 2 | TERI | RO | 0x0 | Trailing Edge Ring Indicator.
0 = RIn pin has not changed from 0 to 1 since the last read of this register.
1 = RIn pin has changed state. | +| 1 | DDSR | RO | 0x0 | Delta Data Set Ready.
0 = No change in DSRn pin since the last read of this register.
1 = DSRn pin has changed state. | +| 0 | DCTS | RO | 0x0 | Delta Clear to Send.
0 = No change in CTSn pin since the last read of this register.
1 = CTSn pin has changed state. | #### Scratchpad Register This register has no effect on the UART. It is intended as a scratchpad register for use by programmers and is included for 16550A compatibility. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1C
BitsFieldTypeResetDescription
31:8ReservedRO0x0Reserved for future use.
7:0SCRATCHPADRW0x0SCRATCHPAD.
This field has no effect on UART functions.
+**Offset: 0x1C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved for future use. | +| 7:0 | SCRATCHPAD | RW | 0x0 | SCRATCHPAD.
This field has no effect on UART functions. | #### Infrared Selection Register Each UART can manage an IrDA module associated with it. This register controls the IrDA functions (see Serial Infrared Asynchronous Interface in the Datasheet). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x20
BitsFieldTypeResetDescription
31:5ReservedRO0x0Reserved for future use.
4RXPLRW0x0Receive Data Polarity.
0 = SIR decoder takes positive pulses as zeros.
1 = SIR decoder takes negative pulses as zeros.
3TXPLRW0x0Transmit Data Polarity.
0 = SIR encoder generates a positive pulse for a data bit of 0.
1 = SIR encoder generates a negative pulse for a data bit of 0.
2XMODERW0x0Transmit Pulse Width Select.
When this field is clear, the UART 16x clock is used to clock the IrDA transmit and receive logic. When this field is set, the receive decoder operation does not change, and the transmit encoder generates 1.6 ms pulses (that are 3/16 of a bit time at 115.2 kbps) instead of pulses 3/16 of a bit time wide. CHIP recommends setting this field.
0 = Transmit pulse width is 3/16 of a bit time wide.
1 = Transmit pulse width is 1.6 ms.
1RCVEIRRW0x0Receiver SIR Enable.
When this field is set, the signal from the RXD pin is processed by the IrDA decoder before it is fed to the UART. If this field is clear, then all clocking to the IrDA decoder is blocked and the RXD pin is fed directly to the UART.
0 = Receiver is in UART mode.
1 = Receiver is in infrared mode.
0XMITIRRW0x0Transmitter SIR Enable.
When this field is set, the normal TXD output from the UART is processed by the IrDA encoder before it is fed to the device pin. If this field is clear, all clocking to the IrDA encoder is blocked and the UART's TXD signal is connected directly to the device pin. When transmitter SIR enable is set, the TXD output pin, which is in a normally high default state, switches to a normally low default state. This can cause a false start bit unless the infrared LED is disabled before this field is set.
0 = Transmitter is in UART mode.
1 = Transmitter is in infrared mode
+**Offset: 0x20** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:5 | Reserved | RO | 0x0 | Reserved for future use. | +| 4 | RXPL | RW | 0x0 | Receive Data Polarity.
0 = SIR decoder takes positive pulses as zeros.
1 = SIR decoder takes negative pulses as zeros. | +| 3 | TXPL | RW | 0x0 | Transmit Data Polarity.
0 = SIR encoder generates a positive pulse for a data bit of 0.
1 = SIR encoder generates a negative pulse for a data bit of 0. | +| 2 | XMODE | RW | 0x0 | Transmit Pulse Width Select.
When this field is clear, the UART 16x clock is used to clock the IrDA transmit and receive logic. When this field is set, the receive decoder operation does not change, and the transmit encoder generates 1.6 ms pulses (that are 3/16 of a bit time at 115.2 kbps) instead of pulses 3/16 of a bit time wide. CHIP recommends setting this field.
0 = Transmit pulse width is 3/16 of a bit time wide.
1 = Transmit pulse width is 1.6 ms. | +| 1 | RCVEIR | RW | 0x0 | Receiver SIR Enable.
When this field is set, the signal from the RXD pin is processed by the IrDA decoder before it is fed to the UART. If this field is clear, then all clocking to the IrDA decoder is blocked and the RXD pin is fed directly to the UART.
0 = Receiver is in UART mode.
1 = Receiver is in infrared mode. | +| 0 | XMITIR | RW | 0x0 | Transmitter SIR Enable.
When this field is set, the normal TXD output from the UART is processed by the IrDA encoder before it is fed to the device pin. If this field is clear, all clocking to the IrDA encoder is blocked and the UART's TXD signal is connected directly to the device pin. When transmitter SIR enable is set, the TXD output pin, which is in a normally high default state, switches to a normally low default state. This can cause a false start bit unless the infrared LED is disabled before this field is set.
0 = Transmitter is in UART mode.
1 = Transmitter is in infrared mode | #### Receive FIFO Occupancy Register @@ -4667,34 +2441,12 @@ This register can be used to determine the number of trailing bytes to remove in This register is incremented once for each byte of data written to the receive FIFO and decremented once for each byte read. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x24
BitsFieldTypeResetDescription
31:6ReservedRO0x0Reserved for future use.
5:0BYTE_COUNTRO0x0BYTE COUNT.
This field is used for the number of bytes (0-63) remaining in the receive FIFO.
+**Offset: 0x24** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:6 | Reserved | RO | 0x0 | Reserved for future use. | +| 5:0 | BYTE_COUNT | RO | 0x0 | BYTE COUNT.
This field is used for the number of bytes (0-63) remaining in the receive FIFO. | #### Auto-Baud Control Register @@ -4704,126 +2456,36 @@ The auto-baud circuitry counts the number of clocks in the start bit and writes Auto-baud-rate detection is not supported in IrDA serial-infrared mode. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x28
BitsFieldTypeResetDescription
31:4ReservedRO0x0Reserved for future use.
3ABTRW0x0ABT.
0 = Formula used to calculate baud rates, allowing all possible baud rates to be chosen by UART.
1 = Table used to calculate baud rates, which limits UART to choosing common baud rates
2ABUPRW0x0ABUP.
0 = <var Product Number> Programs Divisor Latch registers.
1 = UART Programs Divisor Latch registers.
1ABLIERW0x0ABLIE.
0 = Auto-baud-lock interrupt disabled (Source <Auto-baud Lock> field).
1 = Auto-baud-lock interrupt enabled (Source <Auto-baud Lock> field).
0ABERW0x0ABE.
0 = Auto-baud disabled.
1 = Auto-baud enabled.
+**Offset: 0x28** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | Reserved | RO | 0x0 | Reserved for future use. | +| 3 | ABT | RW | 0x0 | ABT.
0 = Formula used to calculate baud rates, allowing all possible baud rates to be chosen by UART.
1 = Table used to calculate baud rates, which limits UART to choosing common baud rates | +| 2 | ABUP | RW | 0x0 | ABUP.
0 = <var Product Number> Programs Divisor Latch registers.
1 = UART Programs Divisor Latch registers. | +| 1 | ABLIE | RW | 0x0 | ABLIE.
0 = Auto-baud-lock interrupt disabled (Source <Auto-baud Lock> field).
1 = Auto-baud-lock interrupt enabled (Source <Auto-baud Lock> field). | +| 0 | ABE | RW | 0x0 | ABE.
0 = Auto-baud disabled.
1 = Auto-baud enabled. | #### Auto-Baud Count Register This register stores the number of 14.7456-MHz clock cycles within a start-bit pulse. This value is then used by the \ or the UART to calculate the baud rate. If auto-baud mode (\ field in Auto-Baud Control Register) and auto-baud interrupts (\ field in Auto-Baud Control Register) are enabled, the UART interrupts the \ with the auto-baud-lock interrupt (IIR[ABL]) after it has written the count value into ACR. The value is written regardless of the state of the auto-baud UART program bit, (ABR[ABUP]). - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x2C
BitsFieldTypeResetDescription
31:16ReservedRO0x0Reserved for future use.
15:0COUNT_VALUERO0x0COUNT VALUE.
This field is used for the number of 14.7456-MHz clock cycles within a start-bit pulse.
+**Offset: 0x2C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0x0 | Reserved for future use. | +| 15:0 | COUNT_VALUE | RO | 0x0 | COUNT VALUE.
This field is used for the number of 14.7456-MHz clock cycles within a start-bit pulse. | #### Full Baud Divisor Register - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x30
BitsFieldTypeResetDescription
31:16ReservedRO0x0Reserved for future use.
15:8DLHRW0x0Divisor Latch High.
High-byte compare value to generate baud rate
7:0DLLRW0x2Divisor Latch Low.
Low-byte compare value to generate baud rate
+**Offset: 0x30** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0x0 | Reserved for future use. | +| 15:8 | DLH | RW | 0x0 | Divisor Latch High.
High-byte compare value to generate baud rate | +| 7:0 | DLL | RW | 0x2 | Divisor Latch Low.
Low-byte compare value to generate baud rate | #### FIFO Control Register @@ -4831,116 +2493,30 @@ Another address for FCR. Please refer to Offset = 0x8 for its detailed descripti It is a write and read register when baud_newreg_en is asserted. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x34
BitsFieldTypeResetDescription
31:8ReservedRO0x0Reserved for future use.
7:6ITLRW0x0Interrupt Trigger Level (threshold).
5BusRW0x032-Bit Peripheral Bus
4TRAILRW0x0Trailing Bytes
3TILRW0x0Transmitter Interrupt Level
2RESETTFRW0x0Reset Transmit FIFO
1RESETRFRW0x0Reset Receive FIFO
0TRFIFOERW0x0Transmit and Receive FIFO Enable
+**Offset: 0x34** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved for future use. | +| 7:6 | ITL | RW | 0x0 | Interrupt Trigger Level (threshold). | +| 5 | Bus | RW | 0x0 | 32-Bit Peripheral Bus | +| 4 | TRAIL | RW | 0x0 | Trailing Bytes | +| 3 | TIL | RW | 0x0 | Transmitter Interrupt Level | +| 2 | RESETTF | RW | 0x0 | Reset Transmit FIFO | +| 1 | RESETRF | RW | 0x0 | Reset Receive FIFO | +| 0 | TRFIFOE | RW | 0x0 | Transmit and Receive FIFO Enable | #### Baud Newreg Enable Register config the baud_newreg_en to use the new address for DLH, DLL, FCR - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x38
BitsFieldTypeResetDescription
31:2ReservedRO0x0Reserved for future use.
1BAUD_SYNC_DONERWC0x0baud_sync_done.
1 = the completion of {DLH, DLL } sync to clk_uart domain from clk_apb domain when <baud_newreg_en> is set previously, can be cleared by writing this resiger(0x38) or full baud divisor register(0x34).
0 = default status.
0BAUD_NEWREG_ENRW0x0baud_newreg_en.
0= no influence with the previous config, except the new read access for FCR in offset=0x34.
1= enable another new address access for {DLH, DLL} in offset= 0x30 and FCR in offset=0x34. The previous access for DLH, DLL, FCR are all blocked.
+**Offset: 0x38** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | RO | 0x0 | Reserved for future use. | +| 1 | BAUD_SYNC_DONE | RWC | 0x0 | baud_sync_done.
1 = the completion of {DLH, DLL } sync to clk_uart domain from clk_apb domain when <baud_newreg_en> is set previously, can be cleared by writing this resiger(0x38) or full baud divisor register(0x34).
0 = default status. | +| 0 | BAUD_NEWREG_EN | RW | 0x0 | baud_newreg_en.
0= no influence with the previous config, except the new read access for FCR in offset=0x34.
1= enable another new address access for {DLH, DLL} in offset= 0x30 and FCR in offset=0x34. The previous access for DLH, DLL, FCR are all blocked. | ## 17.4 GPIO @@ -4956,7 +2532,7 @@ GPIO is used to capture and generate application-specific input and output. All ### 17.4.3 Functional Description -####Block Diagram +#### Block Diagram The GPIO ports and GPIO unit connections are depicted below. @@ -4966,30 +2542,11 @@ AS can be seen, the GPIO unit output passes through MFPR to the GPIO pin, and th By virtue of the GPIO unit, software is able to set and check the status of a GPIO port. And there are 3 interrupts relevant to GPIO as tabled below - - - - - - - - - - - - - - - - - - - - - - - -
ICU InputsSignal Name Notes
Int Req [58]GPIO_APGenerated in the GPIO unit
Int Req [59]GPIO_AP_SECGenerated in the GPIO secure unit
Int Req [60]GPIO_edge_detectGenerated in MFPR, wake-up source
+| ICU Inputs | Signal Name | Notes | +| --- | --- | --- | +| Int Req [58] | GPIO_AP | Generated in the GPIO unit | +| Int Req [59] | GPIO_AP_SEC | Generated in the GPIO secure unit | +| Int Req [60] | GPIO_edge_detect | Generated in MFPR, wake-up source | All of the interrupts may be generated when GPIO input edge is detected. However, they are generated in different modules. GPIO_EDGE_DETECT is generated in MFPR which is in always on domain and can be used as wake-up source. The other 2 interrupts (GPIO_AP/CP) are generated in GPIO unit which is shut down when chip is in sleep mode. As a result, GPIO_AP/CP can not be used as wake-up sources. Furthermore, GPIO_AP/CP has its corresponding bit masks which allows software to mask a bit or not, while GPIO_EDGE_DETECT does not have its bit mask. @@ -5014,150 +2571,56 @@ The GPIO information described in this section applies only to the GPIO alternat > **Note.** The base address of GPIO registers are tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameAddress
GPIO0_BASE0xD4019000
GPIO1_BASE0xD4019004
GPIO2_BASE0xD4019008
GPIO3_BASE0xD4019100
SEC_GPIO0_BASE0xF0619000
SEC_GPIO1_BASE0xF0619004
SEC_GPIO2_BASE0xF0619008
SEC_GPIO3_BASE0xF0619100
+| Name | Address | +| --- | --- | +| GPIO0_BASE | 0xD4019000 | +| GPIO1_BASE | 0xD4019004 | +| GPIO2_BASE | 0xD4019008 | +| GPIO3_BASE | 0xD4019100 | +| SEC_GPIO0_BASE | 0xF0619000 | +| SEC_GPIO1_BASE | 0xF0619004 | +| SEC_GPIO2_BASE | 0xF0619008 | +| SEC_GPIO3_BASE | 0xF0619100 | #### GPIO_PLR REGISTER -The state of each of the GPIO ports is visible through this register. Each bit corresponds to the port number. These read-only registers determine the current value of a particular port (regardless of the programmed port direction). - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31:0PLnR0x0GPIO port level n (where n = 0 ~ 31)
0: Port state is low
1: Port state is high
+The state of each of the GPIO ports is visible through this register. Each bit corresponds to the port number. These read-only registers determine the current value of a particular port (regardless of the programmed port direction). + +**Offset: 0x0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | PLn | R | 0x0 | GPIO port level n (where n = 0 ~ 31)
0: Port state is low
1: Port state is high | #### GPIO_PDR REGISTER Users control port direction by programming the GPIO Pin Direction registers . They contain one direction control bit for each of the 32 ports. -If a direction bit is programmed to a 1, the GPIO function is an output. If it is programmed to a 0, it is an input. At reset, all bits in this register are cleared , which means all GPIO ports are configured to input. +If a direction bit is programmed to a 1, the GPIO function is an output. If it is programmed to a 0, it is an input. At reset, all bits in this register are cleared, which means all GPIO ports are configured to input. A pair of set/clear registers (GPIO_SDRx and GPIO_CDRx) is also provided to enable the setting and clearing of individual bits of this register. - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC
BitsFieldTypeResetDescription
31:0PDnR/W0x0GPIO port direction n (where n = 0 ~ 31)
0: Port configured as an input
1: Port configured as an output
+**Offset: 0xC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | PDn | R/W | 0x0 | GPIO port direction n (where n = 0 ~ 31)
0: Port configured as an input
1: Port configured as an output | #### GPIO_PSR REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x18
BitsFieldTypeResetDescription
31PSnW0x0GPIO output port set n (where n = 0 ~ 31)
0: Port level unaffected
1: If port configured as an output, set port level logic high
+**Offset: 0x18** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | PSn | W | 0x0 | GPIO output port set n (where n = 0 ~ 31)
0: Port level unaffected
1: If port configured as an output, set port level logic high | #### GPIO_PCR REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x24
BitsFieldTypeResetDescription
31:0PCnW0x0GPIO output port clear n (where n = 0 ~ 31)
0: Port level unaffected
1: If port configured as an output, clear port level logic low
+**Offset: 0x24** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | PCn | W | 0x0 | GPIO output port clear n (where n = 0 ~ 31)
0: Port level unaffected
1: If port configured as an output, clear port level logic low | #### GPIO_RER REGISTER @@ -5169,53 +2632,21 @@ The GPIO Rising-Edge Detect Enable and GPIO Falling-Edge Detect Enable Registers For a given GPIO port, its corresponding GPIO Rising-Edge Detect Enable Register bit is set to cause a GPIO Edge-Detect Status Register status bit to be set when the port transitions from logic level low to logic level high. Likewise, the GPIO Falling-Edge Detect Enable Register is used to set the corresponding GPIO Edge-Detect Status Register status bit when a transition from logic level high to logic level low occurs. When the corresponding bits are set in both registers, either a falling- or a rising-edge transition causes the corresponding GPIO Edge-Detect Status Register status bit to be set. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x30
BitsFieldTypeResetDescription
31:0PEnR/W0x0GPIO port n rising-edge detect enable (where n = 0 ~ 31)
0: Disable rising-edge detect enable
1: Set corresponding GPIO Edge Detect Status Register status bit when a rising edge is detected on the GPIO port
+**Offset: 0x30** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | PEn | R/W | 0x0 | GPIO port n rising-edge detect enable (where n = 0 ~ 31)
0: Disable rising-edge detect enable
1: Set corresponding GPIO Edge Detect Status Register status bit when a rising edge is detected on the GPIO port | #### GPIO_FER REGISTER Refer to description of **GPIO_RER**** REGISTER** - - - - - - - - - - - - - - - - - - - - -
Offset: 0x3C
BitsFieldTypeResetDescription
31:0FEnR/W0x0GPIO port falling-edge detect enable n (where n = 0 ~ 31)
0: Disable falling-edge detect enable
1: Set corresponding GPIO Edge Detect Status Register status bit when a falling edge is detected on the GPIO port
+**Offset: 0x3C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | FEn | R/W | 0x0 | GPIO port falling-edge detect enable n (where n = 0 ~ 31)
0: Disable falling-edge detect enable
1: Set corresponding GPIO Edge Detect Status Register status bit when a falling edge is detected on the GPIO port | #### GPIO_EDR REGISTER @@ -5223,27 +2654,11 @@ The GPIO Edge Detect Status Registers contain a total of 32 status bits that cor When an edge-detect occurs on a port that matches the type of edge programmed in the GPIO Rising-Edge Detect Enable and/or GPIO Falling-Edge Detect Enable Registers, the corresponding status bit is set in this register. Once a bit is set in this register, the CPU must clear it. Status bits in this register are cleared by writing a 1 to them. Writing a 0 has no effect. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x48
BitsFieldTypeResetDescription
31:0EDnR/W1C0x0GPIO edge detect status n (where n = 0 ~ 31)
0: No edge detect has occurred on the port as specified in GPIO Rising-Edge Detect Enable and/or GPIO Falling-Edge Detect Enable Registers
1: Edge detect has occurred on the port as specified in the GPIO Rising-Edge Detect Enable and/or GPIO Falling-Edge Detect Enable Registers
+**Offset: 0x48** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | EDn | R/W1C | 0x0 | GPIO edge detect status n (where n = 0 ~ 31)
0: No edge detect has occurred on the port as specified in GPIO Rising-Edge Detect Enable and/or GPIO Falling-Edge Detect Enable Registers
1: Edge detect has occurred on the port as specified in the GPIO Rising-Edge Detect Enable and/or GPIO Falling-Edge Detect Enable Registers | #### GPIO_SDR REGISTER @@ -5251,27 +2666,11 @@ Users control port direction by programming the GPIO pin Bit-wise Set of the GPI If a direction bit is programmed to 1, the corresponding bit in the GPIO Pin Direction Register is set and the GPIO function is configured as an output. If it is programmed to a 0, no change in the GPIO functionality or the GPIO Pin Direction Register occurs. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x54
BitsFieldTypeResetDescription
31:0SDnW0x0Set GPIO port direction n (where n = 0 ~31)
0: GPIO Pin Direction Register bit not affected
1: GPIO Pin Direction Register bit is set and GPIOx function is set to OUTPUT
+**Offset: 0x54** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | SDn | W | 0x0 | Set GPIO port direction n (where n = 0 ~31)
0: GPIO Pin Direction Register bit not affected
1: GPIO Pin Direction Register bit is set and GPIOx function is set to OUTPUT | #### GPIO_CDR REGISTER @@ -5279,131 +2678,51 @@ Users control pin direction by programming the GPIO pin Bit-wise Clear of the GP If a direction bit is programmed to a 1, the corresponding bit in the GPIO Pin Direction Register is cleared and the GPIO function is configured as an input. If it is programmed to a 0, no change in the GPIO functionality or the GPIO Pin Direction Register occurs. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x60
BitsFieldTypeResetDescription
31:0CDnW0x0Set GPIO port direction n (where n = 0 ~ 31)
0: GPIO Pin Direction Register bit not affected
1: GPIO Pin Direction Register bit is cleared and the GPIO n function is set to INPUT
+**Offset: 0x60** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CDn | W | 0x0 | Set GPIO port direction n (where n = 0 ~ 31)
0: GPIO Pin Direction Register bit not affected
1: GPIO Pin Direction Register bit is cleared and the GPIO n function is set to INPUT | #### GPIO_SRERX REGISTER Bit-wise set of GPIO rising edge detect enable register. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x6C
BitsFieldTypeResetDescription
31:0SRERnW0x0Set GPIO Rising Edge detect enable n (where n = 0~ 31)
0: GPIO Rising-Edge Detect Enable Register bit is not affected
1: GPIO Rising-Edge Detect Enable Register bit is set
+**Offset: 0x6C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | SRERn | W | 0x0 | Set GPIO Rising Edge detect enable n (where n = 0~ 31)
0: GPIO Rising-Edge Detect Enable Register bit is not affected
1: GPIO Rising-Edge Detect Enable Register bit is set | #### GPIO_CRERX REGISTER Bit-wise clear of GPIO rising edge detect enable register. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x78
BitsFieldTypeResetDescription
31:0CRERnW0x0Clear GPIO Rising Edge detect enable n (where n = 0 ~ 31)
0: GPIO Rising-Edge Detect Enable Register bit is not affected
1: GPIO Rising-Edge Detect Enable Register bit is cleared
+**Offset: 0x78** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CRERn | W | 0x0 | Clear GPIO Rising Edge detect enable n (where n = 0 ~ 31)
0: GPIO Rising-Edge Detect Enable Register bit is not affected
1: GPIO Rising-Edge Detect Enable Register bit is cleared | #### GPIO_SFERX REGISTER Bit-wise set of GPIO rising edge detect enable register. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x84
BitsFieldTypeResetDescription
31:0SFERnW0x0Set GPIO Falling Edge detect enable n (where n = 0 ~ 31)
0: GPIO Falling-Edge Detect Enable Register bit not affected
1: GPIO Falling-Edge Detect Enable Register bit is set
+**Offset: 0x84** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | SFERn | W | 0x0 | Set GPIO Falling Edge detect enable n (where n = 0 ~ 31)
0: GPIO Falling-Edge Detect Enable Register bit not affected
1: GPIO Falling-Edge Detect Enable Register bit is set | #### GPIO_CFERX REGISTER Bit-wise clear of GPIO rising edge detect enable register. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x90
BitsFieldTypeResetDescription
31:0CFERnW0x0Clear GPIO Falling Edge detect enable n (where n = 0 ~ 31)
0: GPIO Falling-Edge Detect Enable Register bit not affected
1: GPIO Falling-Edge Detect Enable Register bit is cleared
+**Offset: 0x90** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | CFERn | W | 0x0 | Clear GPIO Falling Edge detect enable n (where n = 0 ~ 31)
0: GPIO Falling-Edge Detect Enable Register bit not affected
1: GPIO Falling-Edge Detect Enable Register bit is cleared | ## 17.5 One-Wire Bus Master Interface @@ -5425,20 +2744,9 @@ The architecture of the One-Wire Bus Master Interface is depicted below. The functionality of the 1-Wire signal is tabled below. - - - - - - - - - - - - - -
NameDirectionDescription
ONE_WIRE
In/Out
1-Wire Data Line
This open-drain line is the 1-Wire bidirectional data bus signal. 1-Wire slave devices are connected to this pin. This pin must be pulled high by an external resistor, nominally 5 KΩ.
+| Name | Direction | Description | +| --- | --- | --- | +| ONE_WIRE | In/Out | 1-Wire Data Line
This open-drain line is the 1-Wire bidirectional data bus signal. 1-Wire slave devices are connected to this pin. This pin must be pulled high by an external resistor, nominally 5 KΩ. | #### Operations @@ -5504,7 +2812,7 @@ Since for a (“1” or “0”) pulse, the minimum period required is 0.25 µs - Write a value of 0x5 to the OneWire Clock Divisor Register, which provides a clock frequency of approximately 4 MHz and is within the timing requirements - The example in data 0xCF requires 18 pulses, so a total of 72 minimum periods need to be driven on the SDI bus. Program the 72 bits in the SDI Buffer Registers starting from offset 0x40. The “msb” is sent out on the interface first. In this example, the data programmed would be: -- SDI Buffer 0 = 0x1771_1111, SDI Buffer 1 = 0x1717_7171, SDI Buffer 2 = 0xXXXX_XX17,SDI Buffer 3 = 0xXXXX_XXXX, SDI Bit Count = 0x47 +- SDI Buffer 0 = 0x1771_1111, SDI Buffer 1 = 0x1717_7171, SDI Buffer 2 = 0xXXXX_XX17, SDI Buffer 3 = 0xXXXX_XXXX, SDI Bit Count = 0x47 - If required, set the SDI Control Register interrupt enable. Set the \ field in the SDI Control Register - Once all the bits are sent out, the \ field is cleared, and the interrupt is generated if it is enabled @@ -5524,7 +2832,7 @@ The typical programming flow for an RBF interrupt proceeds as follows: - Assert the INTR signal active high. Set W1IER[IAS] - Reset the bus. Set W1CMDR[1WR] - Unmask interrupts in the ICU -- When the PD interrupt occurs, mask interrupts in the ICU in the service routine, clear the W1IER[EPD] bit, and read the W1INTR[PDR] and W1INTR[PD] bits. Ensure that these values are correct (that is, PDR = 0 if there is a slave and PD = 1). Do not clear or write over the W1IER[IAS] bit. Exit the interrupt service routine. +- When the PD interrupt occurs, mask interrupts in the ICU in the service routine, clear the W1IER[EPD] bit, and read the W1INTR[PDR] and W1INTR[PD] bits. Ensure that these values are correct (that is, PDR = 0 if there is a slave and PD = 1). Do not clear or write over the W1IER[IAS] bit. Exit the interrupt service routine. - Send a command. Write to the xmit buffer: W1TRR[DATA]. Unmask interrupts. The Receive buffer is filled with the contents written to the xmit buffer. - Wait for the RBF interrupt. In a service routine, mask interrupts, and clear the W1IER[ERBF] bit. - Read the W1INTR[RBF] bit and ensure that it is set @@ -5568,88 +2876,26 @@ This control register contains four valid bit fields that control the One-Wire b This control register contains four valid bit fields that control the One-Wire bus master controller functionality. The One-Wire bus master interface controller can generate one special command on the bus, in addition to reading and writing, which is a One-Wire reset that must precede any command given on the bus. In addition, this register contains two bits to bypass the One-Wire bus master interface controller features and control the One-Wire bus directly. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31:4ReservedRO0x0Reserved for future use.
3DQIRO0x0ONE_WIRE input.
This bit reflects the present state of the One-Wire bus. Use it together with the <ONE_WIRE output> field when controlling the bus directly. The state of this bit does not affect any other functions of the One-Wire bus master interface controller. Operation of this bit is unaffected by the state of the <ONE_WIRE output enable> field in the One-Wire Interrupt Enable Register.
2DQOWO0x0ONE_WIRE output.
This bit is used to bypass One-Wire bus master interface controller operations and drive the bus directly if needed.
0 = This bit is cleared on power-up or reset. Clearing this bit drives the bus high. One-Wire bus master interface controller operations only function while the One-Wire bus is held high.
1 = Setting this bit drives the bus low until it is cleared or the One-Wire bus master interface controller reset. While the One-Wire bus is held low, no other One-Wire bus master interface controller operations function. By controlling the length of time this bit is set and the point when the line is sampled (see <ONE_WIRE input> field), any One-Wire communication can be generated by the host controller. To prevent accidental writes to the bus, <ONE_WIRE output enable> field in the One-Wire Interrupt Enable Register before the functions in this field.
1SRARW0x0Search ROM accelerator.
0 = SRA turned off.
1 = One-Wire bus master interface controller switches to SRA mode
Refer to the Book of iButton Standards for more information on this feature.
01WRRW0x0One-Wire reset.
This field generates a reset on the One-Wire bus.
0 = Bus is not in reset mode.
1 = Setting this bit automatically clears the <Search ROM accelerator> field. This field is cleared automatically as soon as the One-Wire reset completes. The One-Wire bus master interface controller sets the <Presence detect> interrupt flag in the One-Wire Interrupt Register when the reset is complete and sufficient time for a presence detect to occur has passed. The result of the presence detect is placed in the <Presence detect result> field in the One-Wire Interrupt Register. If a presence detect pulse was received, the <Presence detect result> field is cleared, otherwise it is set.
+**Offset: 0x0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | Reserved | RO | 0x0 | Reserved for future use. | +| 3 | DQI | RO | 0x0 | ONE_WIRE input.
This bit reflects the present state of the One-Wire bus. Use it together with the <ONE_WIRE output> field when controlling the bus directly. The state of this bit does not affect any other functions of the One-Wire bus master interface controller. Operation of this bit is unaffected by the state of the <ONE_WIRE output enable> field in the One-Wire Interrupt Enable Register. | +| 2 | DQO | WO | 0x0 | ONE_WIRE output.
This bit is used to bypass One-Wire bus master interface controller operations and drive the bus directly if needed.
0 = This bit is cleared on power-up or reset. Clearing this bit drives the bus high. One-Wire bus master interface controller operations only function while the One-Wire bus is held high.
1 = Setting this bit drives the bus low until it is cleared or the One-Wire bus master interface controller reset. While the One-Wire bus is held low, no other One-Wire bus master interface controller operations function. By controlling the length of time this bit is set and the point when the line is sampled (see <ONE_WIRE input> field), any One-Wire communication can be generated by the host controller. To prevent accidental writes to the bus, <ONE_WIRE output enable> field in the One-Wire Interrupt Enable Register before the functions in this field. | +| 1 | SRA | RW | 0x0 | Search ROM accelerator.
0 = SRA turned off.
1 = One-Wire bus master interface controller switches to SRA mode
Refer to the Book of iButton Standards for more information on this feature. | +| 0 | 1WR | RW | 0x0 | One-Wire reset.
This field generates a reset on the One-Wire bus.
0 = Bus is not in reset mode.
1 = Setting this bit automatically clears the <Search ROM accelerator> field. This field is cleared automatically as soon as the One-Wire reset completes. The One-Wire bus master interface controller sets the <Presence detect> interrupt flag in the One-Wire Interrupt Register when the reset is complete and sufficient time for a presence detect to occur has passed. The result of the presence detect is placed in the <Presence detect result> field in the One-Wire Interrupt Register. If a presence detect pulse was received, the <Presence detect result> field is cleared, otherwise it is set. | #### Transmit/Receive Buffer Register Data sent and received from the One-Wire bus master interface controller passes through the transmit/receive buffer location. The One-Wire bus master interface controller is double-buffered with separate transmit and receive buffers. Writing to this location connects the transmit buffer to the data bus, while reading connects the receive buffer to the data bus. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31:8ReservedRO0x0Reserved for future use.
7:0DataRW0x0Transmitted/received data.
+**Offset: 0x4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved for future use. | +| 7:0 | Data | RW | 0x0 | Transmitted/received data. | #### Interrupt Register @@ -5657,69 +2903,17 @@ This read-only register contains flags from transmit, receive, and One-Wire rese This read-only register contains flags from transmit, receive, and One-Wire reset operations. Only the presence-detect flag (\) is cleared when this register is read. The other flags are cleared automatically when the transmit and receive buffers are written to or read, respectively. These flags can generate an interrupt on the INTR signal if the corresponding enable bit is set in the One-Wire Interrupt Enable Register. Reading the One-Wire Interrupt register always sets the INTR signal inactive, even if all flags are not cleared. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8
BitsFieldTypeResetDescription
31:6ReservedRO0x0Reserved for future use.
5RSRFRO0x0Receive Shift Register Full.
0=This flag is cleared when the byte is read from the Receive shift register.
1=This flag is set when there's a byte written to shift register.
4RBFRO0x0Receive buffer full.
0 = This flag is cleared when the byte is read from the Receive Buffer register.
1 = This flag is set when there is a byte waiting to be read in the receive buffer.
3TEMTRO0x0Tx Shift register empty
0 = This flag is cleared when data is shifted into the Trx Shift register from the transmit buffer.
1 = This flag is set after the last bit has been transmitted on the One-Wire bus.
TEMT status bit is valid upon completion of the first data transfer.
2TBERO0x1Transmit buffer empty.
0 = This flag is cleared when data is written to the transmit buffer.
1 = This flag is set when the last bit is transferred to the Tx Shift register.
TBE status bit is valid after the first data transfer.
1PDRRO0x1Presence detect result.When a Presence Detect interrupt occurs, this field reflects the result of the presence detect read.
0 = A slave device was found.
1 = No slave device was found.
0PDRO0x0Presence detect.
0 = The required time after a One-Wire reset has not elapsed or this register has been read since the last One-Wire reset.
1 = After a One-Wire reset has been issued, this flag is set after the appropriate amount of time for a presence detect pulse to have occurred.
This bit is cleared when the Interrupt register is read.
+**Offset: 0x8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:6 | Reserved | RO | 0x0 | Reserved for future use. | +| 5 | RSRF | RO | 0x0 | Receive Shift Register Full.
0=This flag is cleared when the byte is read from the Receive shift register.
1=This flag is set when there's a byte written to shift register. | +| 4 | RBF | RO | 0x0 | Receive buffer full.
0 = This flag is cleared when the byte is read from the Receive Buffer register.
1 = This flag is set when there is a byte waiting to be read in the receive buffer. | +| 3 | TEMT | RO | 0x0 | Tx Shift register empty
0 = This flag is cleared when data is shifted into the Trx Shift register from the transmit buffer.
1 = This flag is set after the last bit has been transmitted on the One-Wire bus.
TEMT status bit is valid upon completion of the first data transfer. | +| 2 | TBE | RO | 0x1 | Transmit buffer empty.
0 = This flag is cleared when data is written to the transmit buffer.
1 = This flag is set when the last bit is transferred to the Tx Shift register.
TBE status bit is valid after the first data transfer. | +| 1 | PDR | RO | 0x1 | Presence detect result. When a Presence Detect interrupt occurs, this field reflects the result of the presence detect read.
0 = A slave device was found.
1 = No slave device was found. | +| 0 | PD | RO | 0x0 | Presence detect.
0 = The required time after a One-Wire reset has not elapsed or this register has been read since the last One-Wire reset.
1 = After a One-Wire reset has been issued, this flag is set after the appropriate amount of time for a presence detect pulse to have occurred.
This bit is cleared when the Interrupt register is read. | #### Interrupt Enable Register @@ -5727,123 +2921,31 @@ This register allows system programmers to specify which of the interrupt source This register allows system programmers to specify which of the interrupt sources causes an interrupt the INTR signal to be active and to define the active state for the INTR signal. When a master reset is received, all non-reserved bits in this register except for the \ field are cleared to 0, disabling all interrupt sources. The \ field is reset to 1 by the One-Wire controller, setting the active state of the INTR signal to high. This means the INTR signal is pulled low since all interrupts are disabled. The INTR signal is also reset to an inactive state by reading the Interrupt register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC
BitsFieldTypeResetDescription
31:8ReservedRO0x0Reserved for future use.
7DQOERW0x0ONE_WIRE output enable.
This bit acts as a control select for the ONE_WIRE bus. When set to 0, the bus is controlled by the One-Wire bus master interface controller as normal.
0 = This bit defaults to 0 on power-up or reset and should be left 0 unless users want to control the bus manually through the <ONE_WIRE output> field in the One-Wire Command Register.
1 = The <ONE_WIRE output> field controls the state of the bus directly.
6ReservedRO0x0Reserved for future use.
5ERSFRW0x0Enable Receive Shift Register Full Interrupt.
0 = Enable receive shift register full interrupt disabled.
1 = If the receive shift register full flag is set, then an interrupt is generated.
4ERBFRO0x0Enable Receive Buffer Full Interrupt.
0 = Enable receive buffer full interrupt disabled.
1 = If the receive buffer full flag is set, then an interrupt is generated.
3ETMTRO0x0Enable Tx Shift register empty interrupt.
0 = Enable Tx Shift register empty interrupt disabled.
1 = If the Tx Shift register empty flag is set, then an interrupt is generated.
2ETBERO0x0Enable transmit buffer empty interrupt.
0 = Enable transmit buffer empty interrupt disabled.
1 = If the transmit buffer empty flag is set, then an interrupt is generated.
1ReservedRO0x0Reserved for future use
0EPDRW0x0Enable presence detect interrupt.
0 = Enable presence detect interrupt disabled.
1 = If the enable presence detect flag is set, an interrupt is generated whenever a One-Wire reset is sent and the required amount of time has passed for a presence detect pulse to have occurred.
+**Offset: 0xC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved for future use. | +| 7 | DQOE | RW | 0x0 | ONE_WIRE output enable.
This bit acts as a control select for the ONE_WIRE bus. When set to 0, the bus is controlled by the One-Wire bus master interface controller as normal.
0 = This bit defaults to 0 on power-up or reset and should be left 0 unless users want to control the bus manually through the <ONE_WIRE output> field in the One-Wire Command Register.
1 = The <ONE_WIRE output> field controls the state of the bus directly. | +| 6 | Reserved | RO | 0x0 | Reserved for future use. | +| 5 | ERSF | RW | 0x0 | Enable Receive Shift Register Full Interrupt.
0 = Enable receive shift register full interrupt disabled.
1 = If the receive shift register full flag is set, then an interrupt is generated. | +| 4 | ERBF | RO | 0x0 | Enable Receive Buffer Full Interrupt.
0 = Enable receive buffer full interrupt disabled.
1 = If the receive buffer full flag is set, then an interrupt is generated. | +| 3 | ETMT | RO | 0x0 | Enable Tx Shift register empty interrupt.
0 = Enable Tx Shift register empty interrupt disabled.
1 = If the Tx Shift register empty flag is set, then an interrupt is generated. | +| 2 | ETBE | RO | 0x0 | Enable transmit buffer empty interrupt.
0 = Enable transmit buffer empty interrupt disabled.
1 = If the transmit buffer empty flag is set, then an interrupt is generated. | +| 1 | Reserved | RO | 0x0 | Reserved for future use | +| 0 | EPD | RW | 0x0 | Enable presence detect interrupt.
0 = Enable presence detect interrupt disabled.
1 = If the enable presence detect flag is set, an interrupt is generated whenever a One-Wire reset is sent and the required amount of time has passed for a presence detect pulse to have occurred. | #### Clock Divisor Register This register divides the internal reference clock to generate the One-Wire clock timing patterns using a base clock of 24 MHz. This register must be programmed before using the One-Wire bus master interface. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x10
BitsFieldTypeResetDescription
31:5ReservedRO0x0Reserved for future use.
4:2DIVRW0x0Divider.
The One-Wire bus master interface controller uses the output of the prescaler and divides by the DIV value to produce the One-Wire clocks. This clock must be approximately 1 MHz for correct operation. This value must be set to 0x2.
1:0PRERW0x0Prescaler value.
The One-Wire bus master interface controller uses the input 24-MHz clock and initially divides by this value before outputting to the divider section. This value must be set to 0x3, selecting a prescale of 7.
+**Offset: 0x10** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:5 | Reserved | RO | 0x0 | Reserved for future use. | +| 4:2 | DIV | RW | 0x0 | Divider.
The One-Wire bus master interface controller uses the output of the prescaler and divides by the DIV value to produce the One-Wire clocks. This clock must be approximately 1 MHz for correct operation. This value must be set to 0x2. | +| 1:0 | PRE | RW | 0x0 | Prescaler value.
The One-Wire bus master interface controller uses the input 24-MHz clock and initially divides by this value before outputting to the divider section. This value must be set to 0x3, selecting a prescale of 7. | ## 17.6 IR-RX @@ -5891,338 +2993,92 @@ For example, the following data in RLC format implies that: #### IRC_EN REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31:1ReservedRO0x0Reserved
0IRC_ENRW0x0This is the global enable bit for the IR-RX.
0x0: Disabled
0x1: Enabled
+**Offset: 0x0** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:1 | Reserved | RO | 0x0 | Reserved | +| 0 | IRC_EN | RW | 0x0 | This is the global enable bit for the IR-RX.
0x0: Disabled
0x1: Enabled | #### CLKDIV REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31:24ReservedRO0x0Reserved
23:0CLKDIVRW0x0Frequency dividing parameter for generating the internal working clock (WCLK). The generated WCLK frequency is:
Freq_of_WCLK = Freq_of_CLK / (CLKDIV +1)
+**Offset: 0x4** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Reserved | RO | 0x0 | Reserved | +| 23:0 | CLKDIV | RW | 0x0 | Frequency dividing parameter for generating the internal working clock (WCLK). The generated WCLK frequency is:
Freq_of_WCLK = Freq_of_CLK / (CLKDIV +1) | #### NOISEHTR REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8
BitsFieldTypeResetDescription
31:8
ReservedRO0x0Reserved
7:0NOISETHR
RW0x0Noise detection threshold.
+**Offset: 0x8** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved | +| 7:0 | NOISETHR | RW | 0x0 | Noise detection threshold. | #### IDLE_STATE REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC
BitsFieldTypeResetDescription
31:1ReservedRO0x0Reserved
0IDLE_STATERW0x1This is the IDLE status bit.
0x0: Not IDLE
0x1: IDLE
It is cleared by hardware at the change of input infrared signal. Software could set this bit to 0x1.
+**Offset: 0xC** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:1 | Reserved | RO | 0x0 | Reserved | +| 0 | IDLE_STATE | RW | 0x1 | This is the IDLE status bit.
0x0: Not IDLE
0x1: IDLE
It is cleared by hardware at the change of input infrared signal. Software could set this bit to 0x1. | #### FIFO_OUT REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x10
BitsFieldTypeResetDescription
31:8ReservedRO
0x0Reserved
7:0FIFO_OUTRO
0x0This is the data output of FIFO.
+**Offset: 0x10** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved | +| 7:0 | FIFO_OUT | RO | 0x0 | This is the data output of FIFO. | #### FIFO_STS REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14
BitsFieldTypeResetDescription
31FIFO_fullRO0x0Flag bit of FIFO full.
30FIFO_emptyRO0x1Flag bit of FIFO empty.
29:6ReservedRO0x0Reserved
5:0FIFO_CNTRO0x0This is the number of unread data in FIFO.
+**Offset: 0x14** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | FIFO_full | RO | 0x0 | Flag bit of FIFO full. | +| 30 | FIFO_empty | RO | 0x1 | Flag bit of FIFO empty. | +| 29:6 | Reserved | RO | 0x0 | Reserved | +| 5:0 | FIFO_CNT | RO | 0x0 | This is the number of unread data in FIFO. | #### FIFO_CMP REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x18
BitsFieldTypeResetDescription
31:6ReservedRO0x0Reserved
5:0FIFO_CMPRW0x0Comparison value for the number of unread data in FIFO. It is used to generate interruption.
+**Offset: 0x18** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:6 | Reserved | RO | 0x0 | Reserved | +| 5:0 | FIFO_CMP | RW | 0x0 | Comparison value for the number of unread data in FIFO. It is used to generate interruption. | #### INT_EN REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x1C
BitsFieldTypeResetDescription
31:4ReservedRO0x0Reserved
3CMP_INT_ENRW0x0Interrupt enable bit for comparison between FIFO_CMP and the number of unread data in FIFO.
2CNT_INT_ENRW0x0Interrup enable bit for RLC_COUNT counts to 127.
1PEDGE_INT_ENRW0x0Interrupt enable bit for the positive edge of the input infrared signal.
0NEDGE_INT_ENRW0x0Interrupt enable bit for the negtive edge of the input infrared signal.
+**Offset: 0x1C** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | Reserved | RO | 0x0 | Reserved | +| 3 | CMP_INT_EN | RW | 0x0 | Interrupt enable bit for comparison between FIFO_CMP and the number of unread data in FIFO. | +| 2 | CNT_INT_EN | RW | 0x0 | Interrup enable bit for RLC_COUNT counts to 127. | +| 1 | PEDGE_INT_EN | RW | 0x0 | Interrupt enable bit for the positive edge of the input infrared signal. | +| 0 | NEDGE_INT_EN | RW | 0x0 | Interrupt enable bit for the negtive edge of the input infrared signal. | #### INT_FLAG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x20
BitsFieldTypeResetDescription
31:4ReservedRO0x0Reserved
3CMP_INT_FLAGRW1C0x0This bit is set to 1 if the number of unread data in FIFO equals to FIFO_CMP. Interrupt is generated if CMP_INT_EN=1. It can be cleared by writing 0x1 to this bit.
2CNT_INT_FLAGRW1C0x0
This bit is set to 1 if RLC_COUNT=127. Interrupt is generated if CNT_INT_EN=1. It can be cleared by writing 0x1 to this bit.
1PEDGE_INT_FLAGRW1C0x0This bit is set to 1 if positive edge of the input infrared signal is detected. Interrupt is generated if PEDGE_INT_EN=1. It can be cleared by writing 0x1 to this bit.
0NEDGE_INT_FLAGRW1C0x0This bit is set to 1 if negtive edge of the input infrared signal is detected. Interrupt is generated if NEDGE_INT_EN=1. It can be cleared by writing 0x1 to this bit.
+**Offset: 0x20** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | Reserved | RO | 0x0 | Reserved | +| 3 | CMP_INT_FLAG | RW1C | 0x0 | This bit is set to 1 if the number of unread data in FIFO equals to FIFO_CMP. Interrupt is generated if CMP_INT_EN=1. It can be cleared by writing 0x1 to this bit. | +| 2 | CNT_INT_FLAG | RW1C | 0x0 | This bit is set to 1 if RLC_COUNT=127. Interrupt is generated if CNT_INT_EN=1. It can be cleared by writing 0x1 to this bit. | +| 1 | PEDGE_INT_FLAG | RW1C | 0x0 | This bit is set to 1 if positive edge of the input infrared signal is detected. Interrupt is generated if PEDGE_INT_EN=1. It can be cleared by writing 0x1 to this bit. | +| 0 | NEDGE_INT_FLAG | RW1C | 0x0 | This bit is set to 1 if negtive edge of the input infrared signal is detected. Interrupt is generated if NEDGE_INT_EN=1. It can be cleared by writing 0x1 to this bit. | ## 17.7 PWM @@ -6254,55 +3110,15 @@ PWM Control registers. These registers configure the behavior characteristics of the PWM shutdown response and the divisor for the input clocks to the PWM control unit that configures the frequency of the scaled counter clock. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0+(n-1)*0x400
BitsFieldTypeResetDescription
31:9ReservedRO0x0Reserved for future use.
8PWM_OUTCNTenRW0x0PWM Out Counter Register enable.
0=disable, 1=enable.
7ReservedRO0Reserved for future use.
6Pulse Width Modulator Shutdown ModeRW0x00=Graceful shutdown of PWM when the SoC stops the clock to the PWM.
1=Abrupt shutdown of PWM when the SoC stops the clocks to the PWM.
5:0PrescaleRW0x0The scaled counter clock frequency is: PSCLK_PWM/(PRESCALE+1)
+**Offset: 0x0+(n-1) x 0x400** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:9 | Reserved | RO | 0x0 | Reserved for future use. | +| 8 | PWM_OUTCNTen | RW | 0x0 | PWM Out Counter Register enable.
0=disable, 1=enable. | +| 7 | Reserved | RO | 0 | Reserved for future use. | +| 6 | Pulse Width Modulator Shutdown Mode | RW | 0x0 | 0=Graceful shutdown of PWM when the SoC stops the clock to the PWM.
1=Abrupt shutdown of PWM when the SoC stops the clocks to the PWM. | +| 5:0 | Prescale | RW | 0x0 | The scaled counter clock frequency is: PSCLK_PWM/(PRESCALE+1) | #### PWM_DCR REGISTER @@ -6310,41 +3126,13 @@ PWM Duty Cycle registers. These registers configure the duty cycle of the corresponding PWM_OUT signals. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4+(n-1)*0x400
BitsFieldTypeResetDescription
31:11ReservedRO0x0Reserved for future use.
10Full Duty CycleRW0x00=PWM_OUT is determined by the <Duty Cycle of PWM_OUT> value.
1=PWM_OUT is continuously asserted
9:0Duty Cycle of PWM_OUTRW0x00=PWM_OUT is continuously de-asserted.
1=PWM_OUT is high for the number of 12 MHz clock periods equal to this field (<PRESCALE> in PWM Control Registers + 1).
If <Full Duty Cycle> is set, this filed has no effect on the ouptut of PWM.
+**Offset: 0x4+(n-1) x 0x400** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:11 | Reserved | RO | 0x0 | Reserved for future use. | +| 10 | Full Duty Cycle | RW | 0x0 | 0=PWM_OUT is determined by the <Duty Cycle of PWM_OUT> value.
1=PWM_OUT is continuously asserted | +| 9:0 | Duty Cycle of PWM_OUT | RW | 0x0 | 0=PWM_OUT is continuously de-asserted.
1=PWM_OUT is high for the number of 12 MHz clock periods equal to this field (<PRESCALE> in PWM Control Registers + 1).
If <Full Duty Cycle> is set, this filed has no effect on the ouptut of PWM. | #### PWM_PCR REGISTER @@ -6354,64 +3142,20 @@ These registers configure the cycle time of the corresponding PWM_OUT signals. If this register is cleared, the PWM_OUT signal maintains in a high state. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8+(n-1)*0x400
BitsFieldTypeResetDescription
31:10ReservedRO0x0Reserved for future use.
9:0Perios ValueRW0x4The value of scaled clock cycles per cycle of PWM_OUT plus one. If all zeros are written to this register, the signal remains high.
+**Offset: 0x8+(n-1) x 0x400** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:10 | Reserved | RO | 0x0 | Reserved for future use. | +| 9:0 | Perios Value | RW | 0x4 | The value of scaled clock cycles per cycle of PWM_OUT plus one. If all zeros are written to this register, the signal remains high. | #### PWM_OUTCNT REGISTER PWM Output Counter registers. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x10+(n-1)*0x400
BitsFieldTypeResetDescription
31:16ReservedRO0x0Reserved for future use.
15:0Counter ValueRW0x0The value of pwm out pulse number.
+**Offset: 0x10+(n-1) x 0x400** + +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0x0 | Reserved for future use. | +| 15:0 | Counter Value | RW | 0x0 | The value of pwm out pulse number. | diff --git a/en/key_stone/k1/k1_docs/k1_usermanual/6.Address_Mapping.md b/en/key_stone/k1/k1_docs/k1_usermanual/6.Address_Mapping.md index 8880df0..a51ad91 100644 --- a/en/key_stone/k1/k1_docs/k1_usermanual/6.Address_Mapping.md +++ b/en/key_stone/k1/k1_docs/k1_usermanual/6.Address_Mapping.md @@ -13,224 +13,192 @@ The different SoC address mappings from each CPU perspective are provided in the ## 6.2 Main CPU Domain Address Mapping - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ModuleAddressSizeNote
DRAM_00x0000_00000x8000_0000
PCIe PortA Data0x8000_00000x1000_0000
PCIe PortB Data0x9000_00000x1000_0000
PCIe PortC Data0xA000_00000x1800_0000
QSPI0xB800_00000x0800_0000
DDRPHY Config0xC000_00000x0010_0000
V2D0xC010_00000x0010_0000
ASR ISP0xC020_00000x000f_0000
ASR CPP0xC02f_00000x0001_0000
ASR LCD DSI0xC030_00000x0010_0000
FBC-DEC00xC040_00000x0000_0100
FBC-DEC10xC040_01000x0000_0100
ASTC-DEC0xC040_02000x0000_0100
LCD_TOP0xC040_03000x0000_0100
LCD_MMU0xC040_04000x0000_0100
Reserved0xC040_05000x0003_FB00
Saturn0xC044_00000x0004_0000
VPU0xC050_00000x0008_0000
Reserved0xC058_00000x0028_0000
AUDIO SRAM0xC080_00000x0004_0000
Reserved0xC084_00000x0004_0000
AUDIO Peripherals0xC088_00000x0008_0000
USB20 Controller0xC090_00000x0004_0000
USB20 PHY0xC094_00000x0004_0000
USB20 Host Controller0xC098_00000x0004_0000
USB20 Host PHY0xC09C_00000x0004_0000
USB300xC0A0_00000x0010_0000
PCIe PortA PHY0xC0B0_00000x0010_0000
PCIe PortB PHY0xC0C0_00000x0010_0000
PCIe PortC PHY0xC0D0_00000x0010_0000
Reserved0xC0E0_00000x0920_0000
PCIe PortA Config0xCA00_00000x0040_0000
PCIe PortB Config0xCA40_00000x0040_0000
PCIe PortC Config0xCA80_00000x0040_0000
GPU0xCAC0_00000x0008_0000
GMAC00xCAC8_00000x0000_1000
GMAC10xCAC8_10000x0000_1000
Reserved0xCAC8_20000x0937_E000
PDMA Controller0xD400_00000x0001_0000
RTC0xD401_00000x0000_0800
IIC00xD401_08000x0000_0800
IIC10xD401_10000x0000_0800
OneWire0xD401_18000x0000_0800
IIC20xD401_20000x0000_0800
IIC40xD401_28000x0000_0800
DRO0xD401_30000x0000_0400
IPC (mailbox)0xD401_34000x0000_0400Real CPU to Main X60™ CPU
IIC50xD401_38000x0000_0800
Timer10xD401_40000x0000_1000
APB Bus Clock Unit0xD401_50000x0000_1000
Timer20xD401_60000x0000_1000
UART00xD401_70000x0000_0100
UART20xD401_71000x0000_0100
UART30xD401_72000x0000_0100
UART40xD401_73000x0000_0100
UART50xD401_74000x0000_0100
UART60xD401_75000x0000_0100
UART70xD401_76000x0000_0100
UART80xD401_77000x0000_0100
UART90xD401_78000x0000_0100
Reserved0xD401_79000x0000_0600
IR0xD401_7F000x0000_0100
Tsensor0xD401_80000x0000_0800
IIC60xD401_88000x0000_0800
GPIO0xD401_90000x0000_0800
GPIO Edge0xD401_98000x0000_0800
PWM00xD401_A0000x0000_0400
PWM10xD401_A4000x0000_0400
PWM20xD401_A8000x0000_0400
PWM30xD401_AC000x0000_0400
PWM40xD401_B0000x0000_0400
PWM50xD401_B4000x0000_0400
PWM60xD401_B8000x0000_0400
PWM70xD401_BC000x0000_0400
SSP3(SPI)0xD401_C0000x0000_2000
IIC70xD401_D0000x0000_0800
IIC80xD401_D8000x0000_0800
Pad Configuration(Pinmux)0xD401_E0000x0000_0C00
PWM80xD402_00000x0000_0400
PWM90xD402_04000x0000_0400
PWM100xD402_08000x0000_0400
PWM110xD402_0C000x0000_0400
PWM120xD402_10000x0000_0400
PWM130xD402_14000x0000_0400
PWM140xD402_18000x0000_0400
PWM150xD402_1C000x0000_0400
PWM160xD402_20000x0000_0400
PWM170xD402_24000x0000_0400
PWM180xD402_28000x0000_0400
PWM190xD402_2C000x0000_0400
Reserved0xD402_30000x0000_2000
SSPA0 (I2S0)0xD402_60000x0000_0800
SSPA1 (I2S1)0xD402_68000x0000_0800
Reserved0xD402_70000x0000_1000
CAN00xD402_80000x0000_0400
Reserved0xD402_84000x0002_7C00
Main PMU (NDR)0xD405_00000x0001_0000
Reserved0xD406_00000x0002_0000
PMU Timer & WDT (NDR)0xD408_00000x0001_0000
Extra Logic (NDR)0xD409_00000x0001_0000
Reserved0xD40A_00000x0001_0000
Resource IPC (NDR)0xD40B_00000x0001_0000
Reserved0xD40C_00000x0014_6000
IPE3(mipi-csi)0xD420_60000x0000_0800
Reserved0xD420_68000x0000_2800
SPI_LCD0xD420_90000x0000_1000
IPE1 (mipi-csi)0xD420_A0000x0000_0800
IPE2 (mipi-csi)0xD420_A8000x0000_0800
Reserved0xD420_B0000x0000_1000
QSPI reg0xD420_C0000x0000_3000
ISP MMU0xD420_F0000x0000_1000
Reserved0xD421_00000x0000_A800
LCD_DSI0xD421_A8000x0000_5800
Reserved0xD427_F0000x0000_1000
SDH10xD428_00000x0000_0800
SDH20xD428_08000x0000_0800
SDH30xD428_10000x0000_1000
AP PMU0xD428_28000x0000_0100
Reserved0xD428_29000x0000_0300
CPU Config Unit0xD428_2C000x0000_0400
Reserved0xD428_30000x00D7_E000
Reserved0xD500_30000x02FF_D000
RSICV TCM(512KB)0xD800_00000x0008_0000
Reserved0xD808_00000x003C_0000
CIU Dragon0xD844_00000x000C_0000CIUDRAGON regsheet
CCI5000xD850_00000x0010_0000
REE(AES Engine)0xD860_00000x0010_0000
Reserved0xD870_00000x0790_0000
RISCV_APB0xE000_00000x1000_0000
Secure DDRC Config0xF000_00000x0030_0000
Secure LCD_DSI0xF030_00000x0010_0000
Secure LCD_HDMI0xF040_00000x0010_0000
Secure VPU0xF050_00000x0008_0000
Secure Configuration Unit0xF058_00000x0008_0000
Secure DMA Controller Config0xF060_00000x0001_0000
SEC APB2 Bus Clock Unit0xF061_00000x0000_2000
SEC UART10xF061_20000x0000_1000
SEC SSP2 (SPI)0xF061_30000x0000_1000
SEC_IIC30xF061_40000x0000_1000
SEC_RTC0xF061_50000x0000_1000
SEC_Timer 00xF061_60000x0000_1000
SEC_Keypad Controller0xF061_70000x0000_1000
SEC_JTAG Software0xF061_80000x0000_1000
SEC_GPIO0xF061_90000x000E_7000
Secure BCM config (Crypto)0xF070_00000x0000_3800
Reserved0xF800_00000x07E0_0000
ROM0xFFE0_00000x0020_0000
DRAM_10x1_0000_00000x3_8000_0000
+| Module | Address | Size | Note | +| --- | --- | --- | --- | +| DRAM_0 | 0x0000_0000 | 0x8000_0000 | | +| PCIe PortA Data | 0x8000_0000 | 0x1000_0000 | | +| PCIe PortB Data | 0x9000_0000 | 0x1000_0000 | | +| PCIe PortC Data | 0xA000_0000 | 0x1800_0000 | | +| QSPI | 0xB800_0000 | 0x0800_0000 | | +| DDRPHY Config | 0xC000_0000 | 0x0010_0000 | | +| V2D | 0xC010_0000 | 0x0010_0000 | | +| ASR ISP | 0xC020_0000 | 0x000f_0000 | | +| ASR CPP | 0xC02f_0000 | 0x0001_0000 | | +| ASR LCD DSI | 0xC030_0000 | 0x0010_0000 | | +| FBC-DEC0 | 0xC040_0000 | 0x0000_0100 | | +| FBC-DEC1 | 0xC040_0100 | 0x0000_0100 | | +| ASTC-DEC | 0xC040_0200 | 0x0000_0100 | | +| LCD_TOP | 0xC040_0300 | 0x0000_0100 | | +| LCD_MMU | 0xC040_0400 | 0x0000_0100 | | +| Reserved | 0xC040_0500 | 0x0003_FB00 | | +| Saturn | 0xC044_0000 | 0x0004_0000 | | +| VPU | 0xC050_0000 | 0x0008_0000 | | +| Reserved | 0xC058_0000 | 0x0028_0000 | | +| AUDIO SRAM | 0xC080_0000 | 0x0004_0000 | | +| Reserved | 0xC084_0000 | 0x0004_0000 | | +| AUDIO Peripherals | 0xC088_0000 | 0x0008_0000 | | +| USB20 Controller | 0xC090_0000 | 0x0004_0000 | | +| USB20 PHY | 0xC094_0000 | 0x0004_0000 | | +| USB20 Host Controller | 0xC098_0000 | 0x0004_0000 | | +| USB20 Host PHY | 0xC09C_0000 | 0x0004_0000 | | +| USB30 | 0xC0A0_0000 | 0x0010_0000 | | +| PCIe PortA PHY | 0xC0B0_0000 | 0x0010_0000 | | +| PCIe PortB PHY | 0xC0C0_0000 | 0x0010_0000 | | +| PCIe PortC PHY | 0xC0D0_0000 | 0x0010_0000 | | +| Reserved | 0xC0E0_0000 | 0x0920_0000 | | +| PCIe PortA Config | 0xCA00_0000 | 0x0040_0000 | | +| PCIe PortB Config | 0xCA40_0000 | 0x0040_0000 | | +| PCIe PortC Config | 0xCA80_0000 | 0x0040_0000 | | +| GPU | 0xCAC0_0000 | 0x0008_0000 | | +| GMAC0 | 0xCAC8_0000 | 0x0000_1000 | | +| GMAC1 | 0xCAC8_1000 | 0x0000_1000 | | +| Reserved | 0xCAC8_2000 | 0x0937_E000 | | +| PDMA Controller | 0xD400_0000 | 0x0001_0000 | | +| RTC | 0xD401_0000 | 0x0000_0800 | | +| IIC0 | 0xD401_0800 | 0x0000_0800 | | +| IIC1 | 0xD401_1000 | 0x0000_0800 | | +| OneWire | 0xD401_1800 | 0x0000_0800 | | +| IIC2 | 0xD401_2000 | 0x0000_0800 | | +| IIC4 | 0xD401_2800 | 0x0000_0800 | | +| DRO | 0xD401_3000 | 0x0000_0400 | | +| IPC (mailbox) | 0xD401_3400 | 0x0000_0400 | Real CPU to Main X60™ CPU | +| IIC5 | 0xD401_3800 | 0x0000_0800 | | +| Timer1 | 0xD401_4000 | 0x0000_1000 | | +| APB Bus Clock Unit | 0xD401_5000 | 0x0000_1000 | | +| Timer2 | 0xD401_6000 | 0x0000_1000 | | +| UART0 | 0xD401_7000 | 0x0000_0100 | | +| UART2 | 0xD401_7100 | 0x0000_0100 | | +| UART3 | 0xD401_7200 | 0x0000_0100 | | +| UART4 | 0xD401_7300 | 0x0000_0100 | | +| UART5 | 0xD401_7400 | 0x0000_0100 | | +| UART6 | 0xD401_7500 | 0x0000_0100 | | +| UART7 | 0xD401_7600 | 0x0000_0100 | | +| UART8 | 0xD401_7700 | 0x0000_0100 | | +| UART9 | 0xD401_7800 | 0x0000_0100 | | +| Reserved | 0xD401_7900 | 0x0000_0600 | | +| IR | 0xD401_7F00 | 0x0000_0100 | | +| Tsensor | 0xD401_8000 | 0x0000_0800 | | +| IIC6 | 0xD401_8800 | 0x0000_0800 | | +| GPIO | 0xD401_9000 | 0x0000_0800 | | +| GPIO Edge | 0xD401_9800 | 0x0000_0800 | | +| PWM0 | 0xD401_A000 | 0x0000_0400 | | +| PWM1 | 0xD401_A400 | 0x0000_0400 | | +| PWM2 | 0xD401_A800 | 0x0000_0400 | | +| PWM3 | 0xD401_AC00 | 0x0000_0400 | | +| PWM4 | 0xD401_B000 | 0x0000_0400 | | +| PWM5 | 0xD401_B400 | 0x0000_0400 | | +| PWM6 | 0xD401_B800 | 0x0000_0400 | | +| PWM7 | 0xD401_BC00 | 0x0000_0400 | | +| SSP3(SPI) | 0xD401_C000 | 0x0000_2000 | | +| IIC7 | 0xD401_D000 | 0x0000_0800 | | +| IIC8 | 0xD401_D800 | 0x0000_0800 | | +| Pad Configuration(Pinmux) | 0xD401_E000 | 0x0000_0C00 | | +| PWM8 | 0xD402_0000 | 0x0000_0400 | | +| PWM9 | 0xD402_0400 | 0x0000_0400 | | +| PWM10 | 0xD402_0800 | 0x0000_0400 | | +| PWM11 | 0xD402_0C00 | 0x0000_0400 | | +| PWM12 | 0xD402_1000 | 0x0000_0400 | | +| PWM13 | 0xD402_1400 | 0x0000_0400 | | +| PWM14 | 0xD402_1800 | 0x0000_0400 | | +| PWM15 | 0xD402_1C00 | 0x0000_0400 | | +| PWM16 | 0xD402_2000 | 0x0000_0400 | | +| PWM17 | 0xD402_2400 | 0x0000_0400 | | +| PWM18 | 0xD402_2800 | 0x0000_0400 | | +| PWM19 | 0xD402_2C00 | 0x0000_0400 | | +| Reserved | 0xD402_3000 | 0x0000_2000 | | +| SSPA0 (I2S0) | 0xD402_6000 | 0x0000_0800 | | +| SSPA1 (I2S1) | 0xD402_6800 | 0x0000_0800 | | +| Reserved | 0xD402_7000 | 0x0000_1000 | | +| CAN0 | 0xD402_8000 | 0x0000_0400 | | +| Reserved | 0xD402_8400 | 0x0002_7C00 | | +| Main PMU (NDR) | 0xD405_0000 | 0x0001_0000 | | +| Reserved | 0xD406_0000 | 0x0002_0000 | | +| PMU Timer & WDT (NDR) | 0xD408_0000 | 0x0001_0000 | | +| Extra Logic (NDR) | 0xD409_0000 | 0x0001_0000 | | +| Reserved | 0xD40A_0000 | 0x0001_0000 | | +| Resource IPC (NDR) | 0xD40B_0000 | 0x0001_0000 | | +| Reserved | 0xD40C_0000 | 0x0014_6000 | | +| IPE3(mipi-csi) | 0xD420_6000 | 0x0000_0800 | | +| Reserved | 0xD420_6800 | 0x0000_2800 | | +| SPI_LCD | 0xD420_9000 | 0x0000_1000 | | +| IPE1 (mipi-csi) | 0xD420_A000 | 0x0000_0800 | | +| IPE2 (mipi-csi) | 0xD420_A800 | 0x0000_0800 | | +| Reserved | 0xD420_B000 | 0x0000_1000 | | +| QSPI reg | 0xD420_C000 | 0x0000_3000 | | +| ISP MMU | 0xD420_F000 | 0x0000_1000 | | +| Reserved | 0xD421_0000 | 0x0000_A800 | | +| LCD_DSI | 0xD421_A800 | 0x0000_5800 | | +| Reserved | 0xD427_F000 | 0x0000_1000 | | +| SDH1 | 0xD428_0000 | 0x0000_0800 | | +| SDH2 | 0xD428_0800 | 0x0000_0800 | | +| SDH3 | 0xD428_1000 | 0x0000_1000 | | +| AP PMU | 0xD428_2800 | 0x0000_0100 | | +| Reserved | 0xD428_2900 | 0x0000_0300 | | +| CPU Config Unit | 0xD428_2C00 | 0x0000_0400 | | +| Reserved | 0xD428_3000 | 0x00D7_E000 | | +| Reserved | 0xD500_3000 | 0x02FF_D000 | | +| RSICV TCM(512KB) | 0xD800_0000 | 0x0008_0000 | | +| Reserved | 0xD808_0000 | 0x003C_0000 | | +| CIU Dragon | 0xD844_0000 | 0x000C_0000 | CIUDRAGON regsheet | +| CCI500 | 0xD850_0000 | 0x0010_0000 | | +| REE(AES Engine) | 0xD860_0000 | 0x0010_0000 | | +| Reserved | 0xD870_0000 | 0x0790_0000 | | +| RISCV_APB | 0xE000_0000 | 0x1000_0000 | | +| Secure DDRC Config | 0xF000_0000 | 0x0030_0000 | | +| Secure LCD_DSI | 0xF030_0000 | 0x0010_0000 | | +| Secure LCD_HDMI | 0xF040_0000 | 0x0010_0000 | | +| Secure VPU | 0xF050_0000 | 0x0008_0000 | | +| Secure Configuration Unit | 0xF058_0000 | 0x0008_0000 | | +| Secure DMA Controller Config | 0xF060_0000 | 0x0001_0000 | | +| SEC APB2 Bus Clock Unit | 0xF061_0000 | 0x0000_2000 | | +| SEC UART1 | 0xF061_2000 | 0x0000_1000 | | +| SEC SSP2 (SPI) | 0xF061_3000 | 0x0000_1000 | | +| SEC_IIC3 | 0xF061_4000 | 0x0000_1000 | | +| SEC_RTC | 0xF061_5000 | 0x0000_1000 | | +| SEC_Timer 0 | 0xF061_6000 | 0x0000_1000 | | +| SEC_Keypad Controller | 0xF061_7000 | 0x0000_1000 | | +| SEC_JTAG Software | 0xF061_8000 | 0x0000_1000 | | +| SEC_GPIO | 0xF061_9000 | 0x000E_7000 | | +| Secure BCM config (Crypto) | 0xF070_0000 | 0x0000_3800 | | +| Reserved | 0xF800_0000 | 0x07E0_0000 | | +| ROM | 0xFFE0_0000 | 0x0020_0000 | | +| DRAM_1 | 0x1_0000_0000 | 0x3_8000_0000 | | ## 6.3 Real-Time CPU Domain Address Mapping - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ModuleAddressSizeNote
SRAM0x0000_00000x0004_0000
Reserved0x0004_00000x2FFC_0000
DDR0x3000_00000x1000_0000
Reserved0x4000_00000x8087_0000
R CAN0xC087_00000x0000_4000
Reserved0xC087_40000x0000_4000
sys_ctrl_regs0xC088_00000x0000_1000
SHUB_UART00xC088_10000x0000_1000
Audio_ctrl_reg0xC088_20000x0000_1000
CODEC ADMA0xC088_30000x0000_0100
CODEC SSPA0xC088_31000x0000_0300
I2S1 ADMA0xC088_34000x0000_0100
I2S1 SSPA0xC088_35000x0000_0300
HDMI ADMA0xC088_38000x0000_0100
HDMI SSPA0xC088_39000x0000_0300
I2S0 ADMA0xC088_3C000x0000_0100
I2S0 SSPA0xC088_3D000x0000_0300
AHBDMA0xC088_40000x0000_1000
SHUB_SSP0 (SPI)0xC088_50000x0000_1000
SHUB_SSP1 (SPI)0xC088_60000x0000_1000
SHUB_I2C00xC088_70000x0000_1000
SHUB_PWM0-90xC088_80000x0000_1000
AON _TIMER0xC088_90000x0000_1000
AON_IPC2AP0xC088_A0000x0000_1000
Reserved0xC088_B0000x0000_0800
Reserved0xC088_B8000x0000_0800
AON _PMU_REG0xC088_C0000x0000_0800
Reserved0xC088_C8000x0000_0800
SHUB_UART10xC088_D0000x0000_1000
R_IR_RX0xC088_E0000x0000_1000
Reserved0xC089_00000x0004_0000
Audio Buffer0xC08D_00000x0000_4000
Reserved0xC08D_40000x1372_C000
To AP APB0xD400_00000x0040_0000
\ No newline at end of file +| Module | Address | Size | Note | +| --- | --- | --- | --- | +| SRAM | 0x0000_0000 | 0x0004_0000 | | +| Reserved | 0x0004_0000 | 0x2FFC_0000 | | +| DDR | 0x3000_0000 | 0x1000_0000 | | +| Reserved | 0x4000_0000 | 0x8087_0000 | | +| R CAN | 0xC087_0000 | 0x0000_4000 | | +| Reserved | 0xC087_4000 | 0x0000_4000 | | +| sys_ctrl_regs | 0xC088_0000 | 0x0000_1000 | | +| SHUB_UART0 | 0xC088_1000 | 0x0000_1000 | | +| Audio_ctrl_reg | 0xC088_2000 | 0x0000_1000 | | +| CODEC ADMA | 0xC088_3000 | 0x0000_0100 | | +| CODEC SSPA | 0xC088_3100 | 0x0000_0300 | | +| I2S1 ADMA | 0xC088_3400 | 0x0000_0100 | | +| I2S1 SSPA | 0xC088_3500 | 0x0000_0300 | | +| HDMI ADMA | 0xC088_3800 | 0x0000_0100 | | +| HDMI SSPA | 0xC088_3900 | 0x0000_0300 | | +| I2S0 ADMA | 0xC088_3C00 | 0x0000_0100 | | +| I2S0 SSPA | 0xC088_3D00 | 0x0000_0300 | | +| AHBDMA | 0xC088_4000 | 0x0000_1000 | | +| SHUB_SSP0 (SPI) | 0xC088_5000 | 0x0000_1000 | | +| SHUB_SSP1 (SPI) | 0xC088_6000 | 0x0000_1000 | | +| SHUB_I2C0 | 0xC088_7000 | 0x0000_1000 | | +| SHUB_PWM0-9 | 0xC088_8000 | 0x0000_1000 | | +| AON _TIMER | 0xC088_9000 | 0x0000_1000 | | +| AON_IPC2AP | 0xC088_A000 | 0x0000_1000 | | +| Reserved | 0xC088_B000 | 0x0000_0800 | | +| Reserved | 0xC088_B800 | 0x0000_0800 | | +| AON _PMU_REG | 0xC088_C000 | 0x0000_0800 | | +| Reserved | 0xC088_C800 | 0x0000_0800 | | +| SHUB_UART1 | 0xC088_D000 | 0x0000_1000 | | +| R_IR_RX | 0xC088_E000 | 0x0000_1000 | | +| Reserved | 0xC089_0000 | 0x0004_0000 | | +| Audio Buffer | 0xC08D_0000 | 0x0000_4000 | | +| Reserved | 0xC08D_4000 | 0x1372_C000 | | +| To AP APB | 0xD400_0000 | 0x0040_0000 | | \ No newline at end of file diff --git a/en/key_stone/k1/k1_docs/k1_usermanual/9.Top_System.md b/en/key_stone/k1/k1_docs/k1_usermanual/9.Top_System.md index c53fc3e..397b579 100644 --- a/en/key_stone/k1/k1_docs/k1_usermanual/9.Top_System.md +++ b/en/key_stone/k1/k1_docs/k1_usermanual/9.Top_System.md @@ -336,1587 +336,290 @@ K1 allows applying different schemes of resource reset as tabled below. ##### ISP CLOCK/RESET CONTROL REGISTER (PMU_ISP_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x38
BitsFieldTypeResetDescription
31RSVDRO0x0Reserved
30ISP_REPAIR_MEM_CTRL_TRIGW1C0x0ISP Repairable Memory Control Trigger
- 1'b1: Triggers ISP repairable memory control
- The field is cleared by hardware once the repair is done.
29ISP_REPAIR_MEM_CTRL_DONE_BYPASSRW0x0ISP Repairable Memory Control Done Bypass in ISP Hardware Mode.
- This field is valid when the ISP is in hardware mode (ISP_HW_MODE = 1).
28ISP_CPP_CLK_ENRW0x0ISP CPP Function Clock Enable
- 1'b1: Clock enabled
- 1'b0：Clock disabled
27ISP_CPP_CLK_RSTNRW0x0ISP CPP Clock Reset
- 1'b0: Reset
26ISP_CPP_CLK_SELRW0x0ISP CPP Clock Select
- 1'b0: 312Mhz
- 1'b1: 416Mhz
25:24ISP_CPP_CLK_DIVRW0x1ISP CPP Clock Divider.
- isp_mcu_clk = CLK/ (this field +1)
23ISP_CI_BUS_CLK_FC_REQW1C0x0ISP_CI Bus Clock FC Request
- 1'b1: Triggers a frequency change
- The field is cleared by hardware once the frequency change is done.
22:21ISP_CI_BUS_CLK_SELRW0x0ISP_CI Bus Clock Select
- 2'b00: PLL1_409 MHz
- 2'b01: PLL1_491 MHz
- 2'b10: PLL1_307MHz
- 2'b11: PLL1_245Mhz
20:18ISP_CI_BUS_CLK_DIVRW0x1ISP_CI BUS Clock Divide Ratio.
Isp_ci_divided_bus_clk = isp_ci_bus_clk / (this field +1)
17ISP_CI_BUS_CLK_ENRW0x0ISP_CI Bus Clock Enable.
- This field enables the DMA clock for CCIC and ISP.
- It controls the first level AXI clock gating for CCIC and ISP.
- The second level AXI clock gating for CCIC and ISP is managed by separate gating control registers.
- 1'b1: Clock enabled
16ISP_CI_BUS_CLK_RSTRW0x0isp_ci bus clk Reset
- 1'b0: Reset.
- This reset will reset all the AXI logic in SC2 except ISP AXI logic.
15:10RSVDRO0x0Reserved
9:8ISP_CLK_SELRW0x0ISP Function Clock Source Select:
- 2'b00: 416 MHz
- 2'b01: 499 MHz
- 2'b10: 624 MHz
- 2'b11: PLL1_307MHz
7ISP_CLK_FC_REQW1C0x0ISP Function Clock Frequency Change Request.
- 1'b1: Triggers a frequency change.
- The field is cleared by hardware once the frequency change is done.
6:4ISP_CLK_DIVRW0x1ISP Function Clock Divide Ratio.
isp_clk = ISP_CLK_DIV/(this field +1)
3ISP_AHB_RESETNRW0x0ISP AHB Resetn
- 1'b0: Reset
2RSVDRO0x0Reserved
1ISP_CLK_ENRW0x0ISP Function Clock Enable
- 1'b1: Clock enabled
- 1'b0: Clock disabled
0ISP_CLK_RSTNRW0x0ISP Function Clock Reset
- 1'b0: Reset
+Offset: 0xD4282800+0x38 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | RSVD | RO | 0x0 | Reserved | +| 30 | ISP_REPAIR_MEM_CTRL_TRIG | W1C | 0x0 | ISP Repairable Memory Control Trigger- 1'b1: Triggers ISP repairable memory control- The field is cleared by hardware once the repair is done. | +| 29 | ISP_REPAIR_MEM_CTRL_DONE_BYPASS | RW | 0x0 | ISP Repairable Memory Control Done Bypass in ISP Hardware Mode. - This field is valid when the ISP is in hardware mode (ISP_HW_MODE = 1). | +| 28 | ISP_CPP_CLK_EN | RW | 0x0 | ISP CPP Function Clock Enable- 1'b1: Clock enabled- 1'b0：Clock disabled | +| 27 | ISP_CPP_CLK_RSTN | RW | 0x0 | ISP CPP Clock Reset - 1'b0: Reset | +| 26 | ISP_CPP_CLK_SEL | RW | 0x0 | ISP CPP Clock Select- 1'b0: 312Mhz - 1'b1: 416Mhz | +| 25:24 | ISP_CPP_CLK_DIV | RW | 0x1 | ISP CPP Clock Divider.- isp_mcu_clk = CLK/ (this field +1) | +| 23 | ISP_CI_BUS_CLK_FC_REQ | W1C | 0x0 | ISP_CI Bus Clock FC Request - 1'b1: Triggers a frequency change - The field is cleared by hardware once the frequency change is done. | +| 22:21 | ISP_CI_BUS_CLK_SEL | RW | 0x0 | ISP_CI Bus Clock Select - 2'b00: PLL1_409 MHz - 2'b01: PLL1_491 MHz - 2'b10: PLL1_307MHz- 2'b11: PLL1_245Mhz | +| 20:18 | ISP_CI_BUS_CLK_DIV | RW | 0x1 | ISP_CI BUS Clock Divide Ratio.Isp_ci_divided_bus_clk = isp_ci_bus_clk / (this field +1) | +| 17 | ISP_CI_BUS_CLK_EN | RW | 0x0 | ISP_CI Bus Clock Enable. - This field enables the DMA clock for CCIC and ISP. - It controls the first level AXI clock gating for CCIC and ISP. - The second level AXI clock gating for CCIC and ISP is managed by separate gating control registers.- 1'b1: Clock enabled | +| 16 | ISP_CI_BUS_CLK_RST | RW | 0x0 | isp_ci bus clk Reset- 1'b0: Reset. - This reset will reset all the AXI logic in SC2 except ISP AXI logic. | +| 15:10 | RSVD | RO | 0x0 | Reserved | +| 9:8 | ISP_CLK_SEL | RW | 0x0 | ISP Function Clock Source Select:- 2'b00: 416 MHz - 2'b01: 499 MHz - 2'b10: 624 MHz- 2'b11: PLL1_307MHz | +| 7 | ISP_CLK_FC_REQ | W1C | 0x0 | ISP Function Clock Frequency Change Request.- 1'b1: Triggers a frequency change.- The field is cleared by hardware once the frequency change is done. | +| 6:4 | ISP_CLK_DIV | RW | 0x1 | ISP Function Clock Divide Ratio.isp_clk = ISP_CLK_DIV/(this field +1) | +| 3 | ISP_AHB_RESETN | RW | 0x0 | ISP AHB Resetn- 1'b0: Reset | +| 2 | RSVD | RO | 0x0 | Reserved | +| 1 | ISP_CLK_EN | RW | 0x0 | ISP Function Clock Enable - 1'b1: Clock enabled- 1'b0: Clock disabled | +| 0 | ISP_CLK_RSTN | RW | 0x0 | ISP Function Clock Reset- 1'b0: Reset | ##### LCD CLOCK/RESET CONTROL REGISTER1 (PMU_LCD_CLK_RES_CTRL1) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x44
BitsFieldTypeResetDescription
31MIPI_BIT_CLK_FC_REQW1C0x0MIPI BIT CLK FC Request.
- Write 1 to trigger a frequency change.
- The field is cleared by hardware once the frequency change is done.
30LCD_PXCLK_FC_REQW1C0x0LCD PXCLK FC Request.
- Write 1 to trigger a frequency change.
- The field is cleared by hardware once the frequency change is done.
29LCD_MCLK_FC_REQW1C0x0LCD MCLK FC Request.
- Write 1 to trigger a frequency change.
- The field is cleared by hardware once the frequency change is done.
28V2D_FCLK_FC_REQW1C0x0V2D FCLK FC Request.
- Write 1 to trigger a frequency change.
- The field is cleared by hardware once the frequency change is done.
27V2D_SW_RSTRW0x0v2d clk domain reset
- 1'b0: Reset assert
- 1'b1: Reset release
26:24RSVDRO0x0Reserved
23MIPI_BIT_BLANK_MSKRW0x1MIPI BIT CLK FC wait BLANK signal mask:
- 0: Wait for the LCD BLANK signal
- 1: Do not wait for the LCD BLANK signal
22:20MIPI_BIT_CLK_SELRW0x0MIPI BIT Clock Select
- 3'b000: 832Mhz
- 3'b001: 1.5GHz(PLL2_DIV2)
- 3'b010: 1GHz(PLL2_DIV3)
- 3'b011: 1248MHz
- 3'b100: 750MHz
- 3'b101: 600MHz
- 3'b110: 429MHz
- 3'b111: 375MHz
19:17MIPI_BIT_CLK_DIVRW0x0MIPI BIT Clock Divide Ratio.
MIPI_BIT_CLK = clock source/ (this field +1)
16MIPI_BIT_CLK_ENRW0x0MIPI BIT CLK Enable.
- 1'b0: Disabled
- 1'b1: Enabled
15MIPI_BIT_CLK_RSTRW
0x0MIPI BIT CLK Reset
- 1'b0: Reset
- 1'b1: No Reset
14RSVDRO0x0Reserved
13:12V2D_FCLK_SELRW0x0V2D FCLK Clock Select
- 2'b00: 499 MHz
- 2'b01: 416 MHz
- 2'b10: 312 MHz
- 2'b11: 624 MHz
11:9V2D_FCLK_DIVRW0x2V2D FCLK Clock Divide Ratio.
V2D_FCLK = clock source / (this field +1)
8V2D_FCLK_ENRW0x0V2D FCLK Enable
- 1'b0: Disabled
- 1'b1: Enabled
7RSVDRO0x0Reserved
6LCD_HCLK_SWAP_CTRLRW0x0LCD HCLK Swap
This field is used to control the HCLK source for the LCD in D1P mode.
- 1'b0: Use System fabric clock as the LCD HCLK source in D1P mode
- 1'b1: Use Bypass VCTXO clock as LCD HCLK source in D1P mode
5LCD_HCLK_ENRW0x0LCD HCLK Enable
- 1'b0: Disabled
- 1'b1: Enabled
4LCD_SW_RSTRW0x0LCD Software Reset
- 1'b0: Reset
- 1'b1: No reset
3DSI_ESCCLK_RESETRW0x0DSI ESC Clock Reset
- 1'b0: Reset
2DSI_ESC_ENRW0x0DSI ESC Clock Enable
- 1'b1: REF clock enabled
- 1'b0: REF clock disabled
1:0DSI_ESC_SELRW0x0DSI ESC Clock Select
- 2'b00: 52 MHz
- 2'b01: 48 MHz
- 2'b10: 26 MHz
- 2'b11: 78 MHz
+Offset: 0xD4282800+0x44 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | MIPI_BIT_CLK_FC_REQ | W1C | 0x0 | MIPI BIT CLK FC Request. - Write 1 to trigger a frequency change. - The field is cleared by hardware once the frequency change is done. | +| 30 | LCD_PXCLK_FC_REQ | W1C | 0x0 | LCD PXCLK FC Request. - Write 1 to trigger a frequency change. - The field is cleared by hardware once the frequency change is done. | +| 29 | LCD_MCLK_FC_REQ | W1C | 0x0 | LCD MCLK FC Request. - Write 1 to trigger a frequency change. - The field is cleared by hardware once the frequency change is done. | +| 28 | V2D_FCLK_FC_REQ | W1C | 0x0 | V2D FCLK FC Request. - Write 1 to trigger a frequency change. - The field is cleared by hardware once the frequency change is done. | +| 27 | V2D_SW_RST | RW | 0x0 | v2d clk domain reset- 1'b0: Reset assert- 1'b1: Reset release | +| 26:24 | RSVD | RO | 0x0 | Reserved | +| 23 | MIPI_BIT_BLANK_MSK | RW | 0x1 | MIPI BIT CLK FC wait BLANK signal mask:- 0: Wait for the LCD BLANK signal - 1: Do not wait for the LCD BLANK signal | +| 22:20 | MIPI_BIT_CLK_SEL | RW | 0x0 | MIPI BIT Clock Select - 3'b000: 832Mhz- 3'b001: 1.5GHz(PLL2_DIV2)- 3'b010: 1GHz(PLL2_DIV3)- 3'b011: 1248MHz- 3'b100: 750MHz- 3'b101: 600MHz- 3'b110: 429MHz- 3'b111: 375MHz | +| 19:17 | MIPI_BIT_CLK_DIV | RW | 0x0 | MIPI BIT Clock Divide Ratio.MIPI_BIT_CLK = clock source/ (this field +1) | +| 16 | MIPI_BIT_CLK_EN | RW | 0x0 | MIPI BIT CLK Enable.- 1'b0: Disabled- 1'b1: Enabled | +| 15 | MIPI_BIT_CLK_RST | RW | 0x0 | MIPI BIT CLK Reset- 1'b0: Reset- 1'b1: No Reset | +| 14 | RSVD | RO | 0x0 | Reserved | +| 13:12 | V2D_FCLK_SEL | RW | 0x0 | V2D FCLK Clock Select- 2'b00: 499 MHz- 2'b01: 416 MHz- 2'b10: 312 MHz- 2'b11: 624 MHz | +| 11:9 | V2D_FCLK_DIV | RW | 0x2 | V2D FCLK Clock Divide Ratio.V2D_FCLK = clock source / (this field +1) | +| 8 | V2D_FCLK_EN | RW | 0x0 | V2D FCLK Enable - 1'b0: Disabled- 1'b1: Enabled | +| 7 | RSVD | RO | 0x0 | Reserved | +| 6 | LCD_HCLK_SWAP_CTRL | RW | 0x0 | LCD HCLK Swap This field is used to control the HCLK source for the LCD in D1P mode. - 1'b0: Use System fabric clock as the LCD HCLK source in D1P mode - 1'b1: Use Bypass VCTXO clock as LCD HCLK source in D1P mode | +| 5 | LCD_HCLK_EN | RW | 0x0 | LCD HCLK Enable - 1'b0: Disabled- 1'b1: Enabled | +| 4 | LCD_SW_RST | RW | 0x0 | LCD Software Reset - 1'b0: Reset- 1'b1: No reset | +| 3 | DSI_ESCCLK_RESET | RW | 0x0 | DSI ESC Clock Reset - 1'b0: Reset | +| 2 | DSI_ESC_EN | RW | 0x0 | DSI ESC Clock Enable - 1'b1: REF clock enabled- 1'b0: REF clock disabled | +| 1:0 | DSI_ESC_SEL | RW | 0x0 | DSI ESC Clock Select - 2'b00: 52 MHz - 2'b01: 48 MHz- 2'b10: 26 MHz- 2'b11: 78 MHz | ##### LCD_SPI CLOCK/RESET CONTROL REGISTER (PMU_LCD_SPI_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x48
BitsFieldTypeResetDescription
31:15RSVDRO0x0Reserved
14:12LCD_SPI_CLK_SELRW0x0- 3'b000: clk_312m, //div8
- 3'b001: clk_in_416m_pll1, //div6
- 3'b010: clk_in_249m_pll1, //div10
- 3'b011: clk_pll_div11
- 3'b100: clk_pll_div13
- 3'b101: clk_pll_div23
- 3'b110: clk_in_pll2_div3
- 3'b111: clk_in_pll2_div5
11RSVDRO0x0Reserved
10:8LCD_SPI_CLK_DIVRW0x0
LCD_SPI CLK = clock source/ (this field +1)
7LCD_SPI_PXCLK_REQW1C0x0- Write 1 to trigger a frequency change.
- The field is cleared by hardware once the frequency change is done.
6LCD_SPI_ACLK_ENRW0x0- 1'b0: Disabled
- 1'b1: Enabled
5LCD_SPI_BUS_CLK_ENRW0x0- 1'b0: Disabled
- 1'b1: Enabled
4LCD_SPI_BUS_RESETRW0x0- 1'b0: Reset
3LCD_SPI_HBUS_CLK_ENRW0x0- 1'b0: Disabled
- 1'b1: Enabled
2LCD_SPI_HBUS_RESETRW0x0- 1'b0: Reset
1LCD_SPI_CLK_ENRW0x0- 1'b0: Disabled
- 1'b1: Enabled
0LCD_SPI_RESETRW0x0- 1'b0: Reset
+Offset: 0xD4282800+0x48 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:15 | RSVD | RO | 0x0 | Reserved | +| 14:12 | LCD_SPI_CLK_SEL | RW | 0x0 | - 3'b000: clk_312m, //div8 - 3'b001: clk_in_416m_pll1, //div6- 3'b010: clk_in_249m_pll1, //div10 - 3'b011: clk_pll_div11- 3'b100: clk_pll_div13- 3'b101: clk_pll_div23 - 3'b110: clk_in_pll2_div3- 3'b111: clk_in_pll2_div5 | +| 11 | RSVD | RO | 0x0 | Reserved | +| 10:8 | LCD_SPI_CLK_DIV | RW | 0x0 | LCD_SPI CLK = clock source/ (this field +1) | +| 7 | LCD_SPI_PXCLK_REQ | W1C | 0x0 | - Write 1 to trigger a frequency change. - The field is cleared by hardware once the frequency change is done. | +| 6 | LCD_SPI_ACLK_EN | RW | 0x0 | - 1'b0: Disabled- 1'b1: Enabled | +| 5 | LCD_SPI_BUS_CLK_EN | RW | 0x0 | - 1'b0: Disabled- 1'b1: Enabled | +| 4 | LCD_SPI_BUS_RESET | RW | 0x0 | - 1'b0: Reset | +| 3 | LCD_SPI_HBUS_CLK_EN | RW | 0x0 | - 1'b0: Disabled- 1'b1: Enabled | +| 2 | LCD_SPI_HBUS_RESET | RW | 0x0 | - 1'b0: Reset | +| 1 | LCD_SPI_CLK_EN | RW | 0x0 | - 1'b0: Disabled- 1'b1: Enabled | +| 0 | LCD_SPI_RESET | RW | 0x0 | - 1'b0: Reset | ##### LCD CLOCK/RESET CONTROL REGISTER2 (PMU_LCD_CLK_RES_CTRL2) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x4C
BitsFieldTypeResetDescription
31:25RSVDRO0x0Reserved
24LCD_PXCLK_BLANK_MSKRW0x1LCD PXCLK Frequency Change wait BLANK signal mask:
- 1'b0: Wait for the LCD BLANK signal
- 1'b1: Do not wait for the LCD BLANK signal
23:21LCD_PXCLK_SELRW0x0LCD PXCLK Select
- 3'b000: PLL1_409MHz
- 3'b001: PLL1_491MHz
- 3'b010: PLL1_614MHz
- 3'b011: PLL1_312MHz
- 3'b100: 428MHz(PLL2_DIV7)
- 3'b101: 375MHz(PLL2_DIV8)
20:17LCD_PXCLK_DIVRW0x2 LCD PXCLK Divide Ratio
LCD_PXCLK = clock source/ (this field +1)
16LCD_PXCLK_ENRW0x0LCD PXCLK Enable
- 1'b0: Disable
- 1'b1: Enabled
15:10RSVDRO0x0Reserved
9LCD_MCLK_RESETRW0x1- 1'b0: Reset
8RSVDRO0x0Reserved
7:5LCD_MCLK_SELRW0x0LCD MCLK Select
- 3'b000: PLL1_409 MHz
- 3'b001: PLL1_491 MHz
- 3'b010: PLL1_614 MHz
- 3'b011: PLL1_307 MHz
- 3'b100~3'b111: N/A
4:1LCD_MCLK_DIVRW0x2LCD MCLK Clock Divide Ratio.
LCD_MCLK = clock source/ (this field +1)
0LCD_MCLK_ENRW0x0LCD MCLK Enable.
- 1'b0: Disabled
- 1'b1: Enabled
> Note. This clock is also used for camera AHB Clock. The camera can only enable this clock but cannot change its frequency.
+Offset: 0xD4282800+0x4C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:25 | RSVD | RO | 0x0 | Reserved | +| 24 | LCD_PXCLK_BLANK_MSK | RW | 0x1 | LCD PXCLK Frequency Change wait BLANK signal mask:- 1'b0: Wait for the LCD BLANK signal - 1'b1: Do not wait for the LCD BLANK signal | +| 23:21 | LCD_PXCLK_SEL | RW | 0x0 | LCD PXCLK Select- 3'b000: PLL1_409MHz - 3'b001: PLL1_491MHz- 3'b010: PLL1_614MHz- 3'b011: PLL1_312MHz- 3'b100: 428MHz(PLL2_DIV7)- 3'b101: 375MHz(PLL2_DIV8) | +| 20:17 | LCD_PXCLK_DIV | RW | 0x2 | LCD PXCLK Divide Ratio LCD_PXCLK = clock source/ (this field +1) | +| 16 | LCD_PXCLK_EN | RW | 0x0 | LCD PXCLK Enable- 1'b0: Disable- 1'b1: Enabled | +| 15:10 | RSVD | RO | 0x0 | Reserved | +| 9 | LCD_MCLK_RESET | RW | 0x1 | - 1'b0: Reset | +| 8 | RSVD | RO | 0x0 | Reserved | +| 7:5 | LCD_MCLK_SEL | RW | 0x0 | LCD MCLK Select - 3'b000: PLL1_409 MHz- 3'b001: PLL1_491 MHz - 3'b010: PLL1_614 MHz - 3'b011: PLL1_307 MHz- 3'b100~3'b111: N/A | +| 4:1 | LCD_MCLK_DIV | RW | 0x2 | LCD MCLK Clock Divide Ratio.LCD_MCLK = clock source/ (this field +1) | +| 0 | LCD_MCLK_EN | RW | 0x0 | LCD MCLK Enable.- 1'b0: Disabled- 1'b1: Enabled> Note. This clock is also used for camera AHB Clock. The camera can only enable this clock but cannot change its frequency. | ##### CCIC CLOCK/RESET CONTROL REGISTER (PMU_CCIC_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x50
BitsFieldTypeResetDescription
31CCIC_ISP_HCLK_SWAP_CTRLRW0x0CCIC ISP HCLK Swap Control.
This field is used to control the HCLK source for CCIC and ISP in D1P mode.
- 1'b0: Use System fabric clock as the HCLK source
- 1'b1: Use Bypass VCTXO clock as the HCLK source
30MASK_ISP_BLANK_CHECKRW0x0ISP FCLK Frequency Change Mask ISP blank Check.
This field is used to mask the ISP blank indication check during ISP FCLK frequency change.
- 1'b1: The ISP FCLK FC will wait for the blank signal
- 1'b0: Mask the ISP blank check (i.e., does not wait for the blank signal)
29ISP_BLANK_CHECK_MODERW0x0ISP FCLK Frequency Change ISP blank Check Mode.
This field is used to select the ISP blank mode for ISP FCLK frequency change.
- 1'b1: Use V blank flag
- 1'b0: Use H blank flag
28:26RSVDRO0x0Reserved
25:23CCICI_CLK4X_SELRW0x00CCIC4x Controller Function Clock Source Select.
- 3'b000: PLL1_491 MHz
- 3'b001: PLL1_409 MHz
- 3'b010: PLL1_614 MHz
- 3'b011: PLL1_819 MHz
- 3'b100: PLL2_div2
- 3'b101: PLL2_div3
- 3'b110: PLL2_div4
- 3'b111: PLL1_1248 MHz
22:21RSVDRO0x0Reserved
20:18CICIC_CLK4X_DIVRW0x1CI Function Clock Divide Ratio.
ci_fnc_clk = CI_FNC_CLK_DIV / (this field +1)
17:16RSVDRO0x0Reserved
15CCIC_CLK4X_FC_REQW1C0x0CCIC Function clk4x Frequency Change Request.
- Write 1 to trigger a frequency change.
- The field is cleared by hardware once the frequency change is done.
14:8RSVDRO0x0Reserved
7CCIC1_PHYCLK_SELRW0x0CCIC1 PHY Clock Select.
- 1'b0: 104 MHz
- 1'b1: 52 MHz
6RSVDRO0x0Reserved
5CCIC1_PHYCLK_ENRW0x0CCIC1 PHY Clock Enable
- 1'b1: PHY clock enabled
- 1'b0: PHY clock disabled
4CCIC_CLK4X_ENRW0x0CMOS Camera Interface Controller Peripheral Clock Enable
- 1'b1: Peripheral clock enabled
- 1'b0: Peripheral clock disabled
3RSVDRO0x0Reserved
2CCIC1_PHYCLK_RSTRW0x0CCIC1 PHY Clock Reset
- 1'b0: Reset
Note: This clock is also used for DPHY reset.
1CCIC_CLK4X_RSTRW0x0CMOS Camera Interface Controller Peripheral Reset
- 1'b0: Reset
0RSVDRO0x0Reserved
+Offset: 0xD4282800+0x50 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | CCIC_ISP_HCLK_SWAP_CTRL | RW | 0x0 | CCIC ISP HCLK Swap Control. This field is used to control the HCLK source for CCIC and ISP in D1P mode. - 1'b0: Use System fabric clock as the HCLK source- 1'b1: Use Bypass VCTXO clock as the HCLK source | +| 30 | MASK_ISP_BLANK_CHECK | RW | 0x0 | ISP FCLK Frequency Change Mask ISP blank Check. This field is used to mask the ISP blank indication check during ISP FCLK frequency change. - 1'b1: The ISP FCLK FC will wait for the blank signal- 1'b0: Mask the ISP blank check (i.e., does not wait for the blank signal) | +| 29 | ISP_BLANK_CHECK_MODE | RW | 0x0 | ISP FCLK Frequency Change ISP blank Check Mode. This field is used to select the ISP blank mode for ISP FCLK frequency change. - 1'b1: Use V blank flag- 1'b0: Use H blank flag | +| 28:26 | RSVD | RO | 0x0 | Reserved | +| 25:23 | CCICI_CLK4X_SEL | RW | 0x00 | CCIC4x Controller Function Clock Source Select.- 3'b000: PLL1_491 MHz- 3'b001: PLL1_409 MHz- 3'b010: PLL1_614 MHz- 3'b011: PLL1_819 MHz- 3'b100: PLL2_div2- 3'b101: PLL2_div3- 3'b110: PLL2_div4- 3'b111: PLL1_1248 MHz | +| 22:21 | RSVD | RO | 0x0 | Reserved | +| 20:18 | CICIC_CLK4X_DIV | RW | 0x1 | CI Function Clock Divide Ratio.ci_fnc_clk = CI_FNC_CLK_DIV / (this field +1) | +| 17:16 | RSVD | RO | 0x0 | Reserved | +| 15 | CCIC_CLK4X_FC_REQ | W1C | 0x0 | CCIC Function clk4x Frequency Change Request. - Write 1 to trigger a frequency change. - The field is cleared by hardware once the frequency change is done. | +| 14:8 | RSVD | RO | 0x0 | Reserved | +| 7 | CCIC1_PHYCLK_SEL | RW | 0x0 | CCIC1 PHY Clock Select.- 1'b0: 104 MHz- 1'b1: 52 MHz | +| 6 | RSVD | RO | 0x0 | Reserved | +| 5 | CCIC1_PHYCLK_EN | RW | 0x0 | CCIC1 PHY Clock Enable - 1'b1: PHY clock enabled- 1'b0: PHY clock disabled | +| 4 | CCIC_CLK4X_EN | RW | 0x0 | CMOS Camera Interface Controller Peripheral Clock Enable- 1'b1: Peripheral clock enabled- 1'b0: Peripheral clock disabled | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | CCIC1_PHYCLK_RST | RW | 0x0 | CCIC1 PHY Clock Reset - 1'b0: ResetNote: This clock is also used for DPHY reset. | +| 1 | CCIC_CLK4X_RST | RW | 0x0 | CMOS Camera Interface Controller Peripheral Reset- 1'b0: Reset | +| 0 | RSVD | RO | 0x0 | Reserved | ##### SDH0 CLOCK/RESET CONTROL REGISTER (PMU_SDH0_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x54
BitsFieldTypeResetDescription
31:12RSVDRO0x0Reserved
11SDH0_CLK_FC_REQW1C0x0SDH0 Clock Frequency Change Request.
- Write 1 to force SDH0_CLK_DIV to work.
- The field is cleared by hardware once the clock switch is done.
10:8SDH0_CLK_DIVRW0x1SDH0 Clock Frequency Divisor.
SDH0_CLK = SDH0 source clock/(SDH0_CLK_DIV + 1)
7:5SDH0_CLK_SELRW0x0SDH0 Clock source Select.
- 3'b000: 409MHz(clk_in_416m_pll1)
- 3'b001: 614MHz(clk_in_pll1_2x)
- 3'b010: PLL2_div8
- 3'b011: PLL2_div5
- 3'b100: PLL1_div11
- 3'b101: PLL1_div13
- 3'b110: PLL1_div23
- 3'b111: Reserved
4SDH0_CLK_ENRW0x0SDH0 Peripheral Clock Enable.
- 1'b1: Peripheral clock enabled
- 1'b0: Peripheral clock disabled
3SDH_AXICLK_ENRW0x0All SDH AXI Clock Enable
This field is used to enable the AXI click for all 3 SDH modules.
- 1: AXI clock enabled
- 0: AXI clock disabled
2RSVDRO0x0Reserved
1SDH0_RSTRW0x0SDH0 Peripheral Reset.
- 1'b0: Reset
0SDH_AXI_RSTRW0x0All SDH AXI Reset
This field is used to perform an AXI reset for all 3 SDH modules.
+Offset: 0xD4282800+0x54 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:12 | RSVD | RO | 0x0 | Reserved | +| 11 | SDH0_CLK_FC_REQ | W1C | 0x0 | SDH0 Clock Frequency Change Request. - Write 1 to force SDH0_CLK_DIV to work. - The field is cleared by hardware once the clock switch is done. | +| 10:8 | SDH0_CLK_DIV | RW | 0x1 | SDH0 Clock Frequency Divisor. SDH0_CLK = SDH0 source clock/(SDH0_CLK_DIV + 1) | +| 7:5 | SDH0_CLK_SEL | RW | 0x0 | SDH0 Clock source Select.- 3'b000: 409MHz(clk_in_416m_pll1) - 3'b001: 614MHz(clk_in_pll1_2x)- 3'b010: PLL2_div8- 3'b011: PLL2_div5 - 3'b100: PLL1_div11 - 3'b101: PLL1_div13- 3'b110: PLL1_div23- 3'b111: Reserved | +| 4 | SDH0_CLK_EN | RW | 0x0 | SDH0 Peripheral Clock Enable.- 1'b1: Peripheral clock enabled- 1'b0: Peripheral clock disabled | +| 3 | SDH_AXICLK_EN | RW | 0x0 | All SDH AXI Clock Enable This field is used to enable the AXI click for all 3 SDH modules. - 1: AXI clock enabled- 0: AXI clock disabled | +| 2 | RSVD | RO | 0x0 | Reserved | +| 1 | SDH0_RST | RW | 0x0 | SDH0 Peripheral Reset.- 1'b0: Reset | +| 0 | SDH_AXI_RST | RW | 0x0 | All SDH AXI Reset This field is used to perform an AXI reset for all 3 SDH modules. | ##### SDH1 CLOCK/RESET CONTROL REGISTER (PMU_SDH1_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x58
BitsFieldTypeResetDescription
31:12RSVDRO0x0Reserved
11SDH1_CLK_FC_REQW1C0x0SDH1 Clock Frequency Change Request.
- Write 1 to force SDH1_CLK_DIV to work.
- The field is cleared by hardware once the clock switch is done.
10:8SDH1_CLK_DIVRW0x1SDH1 Clock Frequency Divisor.
SDH1_CLK = SDH1 source clock/(SDH0_CLK_DIV + 1)
7:5SDH1_CLK_SELRW0x0SDH1 Clock source Select.
- 3'b000: 409MHz(clk_in_416m_pll1)
- 3'b001: 614MHz(clk_in_pll1_2x)
- 3'b010: PLL2_div8
- 3'b011: PLL2_div5
- 3'b100: PLL1_div11
- 3'b101: PLL1_div13
- 3'b110: PLL1_div23
- 3'b111: Reserved
4SDH1_CLK_ENRW0x0SDH1 Peripheral Clock Enable.
- 1'b1: Peripheral clock enabled
- 1'b0: Peripheral clock disabled
3:2RSVDRO0x0Reserved
1SDH1_RSTRW0x0SDH1 Peripheral Reset.
- 1'b0: Reset
0RSVDRO0x0Reserved
+Offset: 0xD4282800+0x58 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:12 | RSVD | RO | 0x0 | Reserved | +| 11 | SDH1_CLK_FC_REQ | W1C | 0x0 | SDH1 Clock Frequency Change Request. - Write 1 to force SDH1_CLK_DIV to work. - The field is cleared by hardware once the clock switch is done. | +| 10:8 | SDH1_CLK_DIV | RW | 0x1 | SDH1 Clock Frequency Divisor. SDH1_CLK = SDH1 source clock/(SDH0_CLK_DIV + 1) | +| 7:5 | SDH1_CLK_SEL | RW | 0x0 | SDH1 Clock source Select.- 3'b000: 409MHz(clk_in_416m_pll1) - 3'b001: 614MHz(clk_in_pll1_2x)- 3'b010: PLL2_div8- 3'b011: PLL2_div5 - 3'b100: PLL1_div11 - 3'b101: PLL1_div13- 3'b110: PLL1_div23- 3'b111: Reserved | +| 4 | SDH1_CLK_EN | RW | 0x0 | SDH1 Peripheral Clock Enable.- 1'b1: Peripheral clock enabled- 1'b0: Peripheral clock disabled | +| 3:2 | RSVD | RO | 0x0 | Reserved | +| 1 | SDH1_RST | RW | 0x0 | SDH1 Peripheral Reset.- 1'b0: Reset | +| 0 | RSVD | RO | 0x0 | Reserved | ##### USB CLOCK/RESET CONTROL REGISTER (PMU_USB_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x5C
BitsFieldTypeResetDescription
31VBUS_DLY_CNT_ENRW0x0Enable for VBUS fall edge debounce
30:23DLY_CNT_REGRW0x0Debounce Counter Register:
- Configures the debounce duration to detect the VBUS fall edge signal.
- Valid only when vbus_dly_cnt_en is set to 1.
22:18RSVDRO0x0Reserved
17USBP1_AHB_PROT_IN_SUSPRW0x0- 1'b1: Gated access to the USB port controller and PHY registers
- Software sets this bit to 1 before suspending USB, and clear it before reactivating USB
16USB_AHB_PROT_IN_SUSPRW0x0- 1'b1: Gated access to the USB port controller and PHY registers
- Software sets this bit to 1 before suspending USB, and clear it before reactivating USB
15:12RSVDRO0x0Reserved
11USB3_0_PHY_RESETNRW0x0dedicated now.
10USB3_0_VCC_RESETNRW0x0usb3_0_vcc_resetn
9USB3_0_AHB_RSTNRW0x0usb3_0_ahb_rstn
8USB3_0_BUS_CLK_ENRW0x0usb3_0_bus_clk_en
7:6RSVDRO0x0Reserved
5USBP1_AXICLK_ENRW0x0USBP1 AXI Clock Enable
- 1'b1: AXI clock enabled
- 1'b0: AXI clock disabled
4USBP1_AXI_RSTRW0x0USBP1 AXI Reset
- 1'b0: Reset
- 1'b1: De-reset
3:2RSVDRO0x0Reserved
1USB_AXICLK_ENRW0x0USB AXI Clock Enable
- 1'b1: AXI clock enabled
- 1'b0: AXI clock disabled
0USB_AXI_RSTRW0x0 USB AXI Reset.
- 1'b0: Reset
- 1'b1: De-reset
+Offset: 0xD4282800+0x5C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | VBUS_DLY_CNT_EN | RW | 0x0 | Enable for VBUS fall edge debounce | +| 30:23 | DLY_CNT_REG | RW | 0x0 | Debounce Counter Register:- Configures the debounce duration to detect the VBUS fall edge signal.- Valid only when vbus_dly_cnt_en is set to 1. | +| 22:18 | RSVD | RO | 0x0 | Reserved | +| 17 | USBP1_AHB_PROT_IN_SUSP | RW | 0x0 | - 1'b1: Gated access to the USB port controller and PHY registers- Software sets this bit to 1 before suspending USB, and clear it before reactivating USB | +| 16 | USB_AHB_PROT_IN_SUSP | RW | 0x0 | - 1'b1: Gated access to the USB port controller and PHY registers- Software sets this bit to 1 before suspending USB, and clear it before reactivating USB | +| 15:12 | RSVD | RO | 0x0 | Reserved | +| 11 | USB3_0_PHY_RESETN | RW | 0x0 | dedicated now. | +| 10 | USB3_0_VCC_RESETN | RW | 0x0 | usb3_0_vcc_resetn | +| 9 | USB3_0_AHB_RSTN | RW | 0x0 | usb3_0_ahb_rstn | +| 8 | USB3_0_BUS_CLK_EN | RW | 0x0 | usb3_0_bus_clk_en | +| 7:6 | RSVD | RO | 0x0 | Reserved | +| 5 | USBP1_AXICLK_EN | RW | 0x0 | USBP1 AXI Clock Enable- 1'b1: AXI clock enabled- 1'b0: AXI clock disabled | +| 4 | USBP1_AXI_RST | RW | 0x0 | USBP1 AXI Reset - 1'b0: Reset- 1'b1: De-reset | +| 3:2 | RSVD | RO | 0x0 | Reserved | +| 1 | USB_AXICLK_EN | RW | 0x0 | USB AXI Clock Enable- 1'b1: AXI clock enabled- 1'b0: AXI clock disabled | +| 0 | USB_AXI_RST | RW | 0x0 | USB AXI Reset.- 1'b0: Reset - 1'b1: De-reset | ##### QSPI CLOCK/RESET CONTROL REGISTER (PMU_QSPI_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x60
BitsFieldTypeResetDescription
31:13RSVDRO0Reserved
12QSPI_CLK_FC_REQRWAC0x0- Write 1 to force QSPI_CLK_SEL to work.
- The field is cleared by hardware once the clock switch is done.
11:9QSPI_CLK_DIVRW0x7QSPI Clock division ratio.
QSPI_Clock_Freq = QSPI_CLK_SEL Freq/(QSPI_CLK_DIV+1)
8:6QSPI_CLK_SELRW0x5- 3'b000: 409 MHz(PLL1_div6)
- 3'b001: 375 MHz(PLL2_div8)
- 3'b010: 307 MHz(PLL1_div8)
- 3'b011: 245 MHz(PLL1_div10)
- 3'b100: 223 MHz (PLL1_div11)
- 3'b101: 106 MHz(PLL1_div23)
- 3'b110: 495 MHz(PLL1_div5)
- 3'b111: 189 MHz(PLL1_div13)
5RSVDRO0Reserved
4QSPI_CLK_ENRW0x1QSPI Function Clock Enable
- 1'b1: Peripheral clock enabled
- 1'b0: Peripheral clock disabled
3QSPI_BUS_CLK_ENRW0x1QSPI Bus Clock Enable
- 1'b1: Bus clock enabled
- 1'b0: Bus clock disabled
2RSVDRO0Reserved
1QSPI_CLK_RSTRW0x1QSPI clk Reset
- 1'b0: Reset
0QSPI_BUS_RSTRW0x1QSPI_BUS_CLK Reset.
- 1'b0: Reset
+Offset: 0xD4282800+0x60 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:13 | RSVD | RO | 0 | Reserved | +| 12 | QSPI_CLK_FC_REQ | RWAC | 0x0 | - Write 1 to force QSPI_CLK_SEL to work. - The field is cleared by hardware once the clock switch is done. | +| 11:9 | QSPI_CLK_DIV | RW | 0x7 | QSPI Clock division ratio.QSPI_Clock_Freq = QSPI_CLK_SEL Freq/(QSPI_CLK_DIV+1) | +| 8:6 | QSPI_CLK_SEL | RW | 0x5 | - 3'b000: 409 MHz(PLL1_div6) - 3'b001: 375 MHz(PLL2_div8)- 3'b010: 307 MHz(PLL1_div8)- 3'b011: 245 MHz(PLL1_div10)- 3'b100: 223 MHz (PLL1_div11)- 3'b101: 106 MHz(PLL1_div23)- 3'b110: 495 MHz(PLL1_div5) - 3'b111: 189 MHz(PLL1_div13) | +| 5 | RSVD | RO | 0 | Reserved | +| 4 | QSPI_CLK_EN | RW | 0x1 | QSPI Function Clock Enable- 1'b1: Peripheral clock enabled- 1'b0: Peripheral clock disabled | +| 3 | QSPI_BUS_CLK_EN | RW | 0x1 | QSPI Bus Clock Enable- 1'b1: Bus clock enabled- 1'b0: Bus clock disabled | +| 2 | RSVD | RO | 0 | Reserved | +| 1 | QSPI_CLK_RST | RW | 0x1 | QSPI clk Reset- 1'b0: Reset | +| 0 | QSPI_BUS_RST | RW | 0x1 | QSPI_BUS_CLK Reset.- 1'b0: Reset | ##### DMA CLOCK/RESET CONTROL REGISTER (PMU_DMA_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x64
BitsFieldTypeResetDescription
31:4RSVDRO0x0Reserved
3DMA_AXICLK_ENRW0x0DMA AXI Clock Enable
- 1'b1: AXI clock enabled
- 1'b0: AXI clock disabled
2:1RSVDRO0x0Reserved
0DMA_AXI_RSTRW0x0DMA AXI Reset
+Offset: 0xD4282800+0x64 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | RSVD | RO | 0x0 | Reserved | +| 3 | DMA_AXICLK_EN | RW | 0x0 | DMA AXI Clock Enable- 1'b1: AXI clock enabled- 1'b0: AXI clock disabled | +| 2:1 | RSVD | RO | 0x0 | Reserved | +| 0 | DMA_AXI_RST | RW | 0x0 | DMA AXI Reset | ##### AES CLOCK/RESET CONTROL REGISTER (PMU_AES_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x68
BitsFieldTypeResetDescription
31:7RSVDRO0x0Reserved
6WTM_CLK_SELRW0x0 WTM Clock Select
- 1'b0: 208 MHz
- 1'b1: 104 MHz
5WTM_CLK_ENRW0x0WTM Clock Enable
- 1'b0: WTM clock disabled
- 1'b1: WTM clock enabled
4WTM_RSTRW0x0WTM Clock Reset
3:0RSVDRO0x0Reserved
+Offset: 0xD4282800+0x68 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0x0 | Reserved | +| 6 | WTM_CLK_SEL | RW | 0x0 | WTM Clock Select - 1'b0: 208 MHz - 1'b1: 104 MHz | +| 5 | WTM_CLK_EN | RW | 0x0 | WTM Clock Enable- 1'b0: WTM clock disabled- 1'b1: WTM clock enabled | +| 4 | WTM_RST | RW | 0x0 | WTM Clock Reset | +| 3:0 | RSVD | RO | 0x0 | Reserved | ##### VPU CLOCK/RESET CONTROL REGISTER (PMU_VPU_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0xA4
BitsFieldTypeResetDescription
31:22RSVDRO0x0Reserved
21VPU_CLK_FC_REQW1C0x0VPU Clock Frequency Change Request
- Write 1 to trigger a frequency change.
- The field is cleared by hardware once the trigger a frequency change is done.
20:16RSVDRO0x0Reserved
15:13VPU_CLK_DIVRW0x1VPU Function Clock Divide Ratio.
VPU_CLK = VPU_CLK_SEL / (this field +1).
> Note. Divider only used for clock source 0, 1, 2 and 3.
12:10VPU_CLK_SELRW0x0VPU Function Clock Select.
- 3'b000: PLL1_614MHz
- 3'b001: PLL1_491MHz
- 3'b010: PLL1_819MHz
- 3'b011: PLL1_409Mhz
- 3'b100: PLL3_DIV6
- 3'b101: PLL2_DIV3
- 3'b110: PLL2_DIV4
- 3'b111: PLL2_DIV5
9:4RSVDRO0x0Reserved
3VPU_CLK_ENRW0x0VPU Function Clock Enable
- 1'b1: clock enabled
- 1'b0: clock disabled
2:1RSVDRO0x0Reserved
0VPU_RSTRW0x0VPU Reset.
- 1'b1: Release reset
- 1'b0: Reset
+Offset: 0xD4282800+0xA4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:22 | RSVD | RO | 0x0 | Reserved | +| 21 | VPU_CLK_FC_REQ | W1C | 0x0 | VPU Clock Frequency Change Request - Write 1 to trigger a frequency change. - The field is cleared by hardware once the trigger a frequency change is done. | +| 20:16 | RSVD | RO | 0x0 | Reserved | +| 15:13 | VPU_CLK_DIV | RW | 0x1 | VPU Function Clock Divide Ratio.VPU_CLK = VPU_CLK_SEL / (this field +1). > Note. Divider only used for clock source 0, 1, 2 and 3. | +| 12:10 | VPU_CLK_SEL | RW | 0x0 | VPU Function Clock Select.- 3'b000: PLL1_614MHz- 3'b001: PLL1_491MHz- 3'b010: PLL1_819MHz- 3'b011: PLL1_409Mhz- 3'b100: PLL3_DIV6 - 3'b101: PLL2_DIV3- 3'b110: PLL2_DIV4- 3'b111: PLL2_DIV5 | +| 9:4 | RSVD | RO | 0x0 | Reserved | +| 3 | VPU_CLK_EN | RW | 0x0 | VPU Function Clock Enable- 1'b1: clock enabled- 1'b0: clock disabled | +| 2:1 | RSVD | RO | 0x0 | Reserved | +| 0 | VPU_RST | RW | 0x0 | VPU Reset.- 1'b1: Release reset- 1'b0: Reset | ##### DDR MEMORY CONTROLLER HARDWARE SLEEP TYPE REGISTER (PMU_MC_HW_SLP_TYPE) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0xB0
BitsFieldTypeResetDescription
31:24RSVDRO0x0Reserved
23DCLK_BYPASS_FC_REQW1C0x0DCLK Bypass Clock Frequency Change Request.
- Write 1 to trigger a frequency change.
- The field is cleared by hardware once the trigger a frequency change is done.
22DCLK_BYPASS_CLK_ENRW0x1DCLK Bypass Clock Enable.
- 1'b1: Peripheral clock enabled
- 1'b0: Peripheral clock disabled
21DCLK_BYPASS_RSTRW0x1DCLK Bypass Clock Reset.
- 1'b0: Reset
20:19DCLK_BYPASS_SELRW0x0DCLK Bypass Clock Select.
- 2'b00: PLL1 312 MHz
- 2'b01: PLL1 416 MHz
- 2'b10: 24MHz
- 2'b11: Reserved
18:16DCLK_BYPASS_DIVRW0x1DCLK Bypass Clock Divider.
DCLK Bypass Clock = DCLK_BYPASS_SEL / (this field +1).
> Note. Divider only used for Clock source 0 and 1.
15:11RSVDRO0x0Reserved
10MC_REG_TABLE_ENRW0x1Frequency Change table mask.
- 1'b0: Enabled
- 1'b1: Disabled
9FREQ_PLL_CHG_MODERW0x0Determines the behavior of the DDRPHY PLL during a frequency change.
- 1'b0: Perform a full PLL switch, including VCO reconfiguration, to transition to a new frequency.
- 1'b1: Keep the VCO frequency unchanged and only update the clock divider or input clock source.
8:7RSVDRO0x0Reserved
6:3MC_REG_TABLE_NUMRW0x0Memory Controller Register Table Number:
- bit[3]: 1'b1: Frequency change occurs within the same timing table
- bit [2]: 1'b1: The target frequency is a high frequency
- bit[1:0]: Specifies the target timing table number for the memory controller.
2:0RSVDRO0x0Reserved
+Offset: 0xD4282800+0xB0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | RSVD | RO | 0x0 | Reserved | +| 23 | DCLK_BYPASS_FC_REQ | W1C | 0x0 | DCLK Bypass Clock Frequency Change Request. - Write 1 to trigger a frequency change. - The field is cleared by hardware once the trigger a frequency change is done. | +| 22 | DCLK_BYPASS_CLK_EN | RW | 0x1 | DCLK Bypass Clock Enable.- 1'b1: Peripheral clock enabled- 1'b0: Peripheral clock disabled | +| 21 | DCLK_BYPASS_RST | RW | 0x1 | DCLK Bypass Clock Reset.- 1'b0: Reset | +| 20:19 | DCLK_BYPASS_SEL | RW | 0x0 | DCLK Bypass Clock Select.- 2'b00: PLL1 312 MHz- 2'b01: PLL1 416 MHz- 2'b10: 24MHz- 2'b11: Reserved | +| 18:16 | DCLK_BYPASS_DIV | RW | 0x1 | DCLK Bypass Clock Divider.DCLK Bypass Clock = DCLK_BYPASS_SEL / (this field +1). > Note. Divider only used for Clock source 0 and 1. | +| 15:11 | RSVD | RO | 0x0 | Reserved | +| 10 | MC_REG_TABLE_EN | RW | 0x1 | Frequency Change table mask. - 1'b0: Enabled- 1'b1: Disabled | +| 9 | FREQ_PLL_CHG_MODE | RW | 0x0 | Determines the behavior of the DDRPHY PLL during a frequency change.- 1'b0: Perform a full PLL switch, including VCO reconfiguration, to transition to a new frequency.- 1'b1: Keep the VCO frequency unchanged and only update the clock divider or input clock source. | +| 8:7 | RSVD | RO | 0x0 | Reserved | +| 6:3 | MC_REG_TABLE_NUM | RW | 0x0 | Memory Controller Register Table Number: - bit[3]: 1'b1: Frequency change occurs within the same timing table - bit [2]: 1'b1: The target frequency is a high frequency- bit[1:0]: Specifies the target timing table number for the memory controller. | +| 2:0 | RSVD | RO | 0x0 | Reserved | ##### PLL CLOCK SELECT STATUS REGISTER (PMU_PLL_SEL_STATUS) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0xC4
BitsFieldTypeResetDescription
31:14RSVDRO0x0Reserved
13:11AP_C1_PLL_SELRO0x0Core Clock selection
- 3'b000: 614M.
- 3'b001: 819M.
- 3'b010: 409M.
- 3'b011: 491M.
- 3'b100: 1228M.
- 3'b101: PLL3_DIV3(1066M)
- 3'b110: PLL2_DIV3(1000M)
- 3'b111: PLL3_DIV2(1600M)
10:8AP_C0_PLL_SELRO0x0Core Clock selection
- 3'b000: 614MHz.
- 3'b001: 819MHz.
- 3'b010: 409MHz.
- 3'b011: 491MHz.
- 3'b100: 1228MHz.
- 3'b101: PLL3_DIV3(1066MHz)
- 3'b110: PLL2_DIV3(1000MHz)
- 3'b111: PLL3_DIV2(1600MHz)
7:6ACLK_PLL_SELRO0x0 ACLK source selection
- 1'b0: 249MHz
- 1'b1: 312MHz
5:0RSVDRO0x0Reserved
+Offset: 0xD4282800+0xC4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:14 | RSVD | RO | 0x0 | Reserved | +| 13:11 | AP_C1_PLL_SEL | RO | 0x0 | Core Clock selection- 3'b000: 614M. - 3'b001: 819M. - 3'b010: 409M. - 3'b011: 491M. - 3'b100: 1228M. - 3'b101: PLL3_DIV3(1066M)- 3'b110: PLL2_DIV3(1000M)- 3'b111: PLL3_DIV2(1600M) | +| 10:8 | AP_C0_PLL_SEL | RO | 0x0 | Core Clock selection- 3'b000: 614MHz. - 3'b001: 819MHz.- 3'b010: 409MHz. - 3'b011: 491MHz.- 3'b100: 1228MHz. - 3'b101: PLL3_DIV3(1066MHz)- 3'b110: PLL2_DIV3(1000MHz)- 3'b111: PLL3_DIV2(1600MHz) | +| 7:6 | ACLK_PLL_SEL | RO | 0x0 | ACLK source selection- 1'b0: 249MHz- 1'b1: 312MHz | +| 5:0 | RSVD | RO | 0x0 | Reserved | ##### GPU CLOCK/RESET CONTROL REGISTER (PMU_GPU_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0xCC
BitsFieldTypeResetDescription
31:21RSVDRO0x0Reserved
20:18GPU_CLK_SELRW0x0GPU Clock Select
- 3'b000: PLL1_614MHz
- 3'b001: PLL1_491MHz
- 3'b010: PLL1_819MHz
- 3'b011: PLL1_409MHz
- 3'b100: PLL3_DIV6
- 3'b101: PLL2_DIV3
- 3'b110: PLL2_DIV4
- 3'b111: PLL2_DIV5
17:16RSVDRO0x0Reserved
15GPU_FNC_FC_REQW1C0x0GPU Clock Frequency Change Request
- Write 1 to trigger a frequency change.
- The field is cleared by hardware once the trigger a frequency change is done.
14:12GPU_CLK_DIVRW0x1GPU Clock Divider.
GPU_fnc_clk = GPU_CLK_SEL / (this field +1).
> Note. Divider only used for clock source 0, 1 and 2.
11:5RSVDRO0x0Reserved
4GPU_CLK_ENRW0x0GPU Clock Enable.
- 1'b1: Peripheral clock enabled
- 1'b0: Peripheral clock disabled
3:2RSVDRO0x0Reserved
1GPU_RSTRW0x0GPU Reset.
- 1'b1: Release Reset
- 1'b0: Reset
0RSVDRO0x0Reserved
+Offset: 0xD4282800+0xCC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:21 | RSVD | RO | 0x0 | Reserved | +| 20:18 | GPU_CLK_SEL | RW | 0x0 | GPU Clock Select- 3'b000: PLL1_614MHz- 3'b001: PLL1_491MHz - 3'b010: PLL1_819MHz - 3'b011: PLL1_409MHz- 3'b100: PLL3_DIV6- 3'b101: PLL2_DIV3- 3'b110: PLL2_DIV4- 3'b111: PLL2_DIV5 | +| 17:16 | RSVD | RO | 0x0 | Reserved | +| 15 | GPU_FNC_FC_REQ | W1C | 0x0 | GPU Clock Frequency Change Request - Write 1 to trigger a frequency change. - The field is cleared by hardware once the trigger a frequency change is done. | +| 14:12 | GPU_CLK_DIV | RW | 0x1 | GPU Clock Divider.GPU_fnc_clk = GPU_CLK_SEL / (this field +1). > Note. Divider only used for clock source 0, 1 and 2. | +| 11:5 | RSVD | RO | 0x0 | Reserved | +| 4 | GPU_CLK_EN | RW | 0x0 | GPU Clock Enable.- 1'b1: Peripheral clock enabled- 1'b0: Peripheral clock disabled | +| 3:2 | RSVD | RO | 0x0 | Reserved | +| 1 | GPU_RST | RW | 0x0 | GPU Reset.- 1'b1: Release Reset- 1'b0: Reset | +| 0 | RSVD | RO | 0x0 | Reserved | ##### SDH2 CLOCK/RESET CONTROL REGISTER (PMUA_SDH2_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0xE0
BitsFieldTypeResetDescription
31:12RSVDRO0x0Reserved
11SDH2_CLK_FC_REQW1C0x0SDH2 Clock Frequency Change Request.
When this field is set to 1, it will force SDH2_CLK_DIV to work. This field will be automatically cleared by hardware when the clock switch is done.
- Write 1 to force SDH2_CLK_DIV to work.
- The field is cleared by hardware once forcing SDH2_CLK_DIV to work is done.
10:8SDH2_CLK_DIVRW0x1SDH2 Clock Frequency Divisor 0-7.
SDH2_CLK = SDH2 source clock/(SDH2_CLK_DIV + 1)
7:5SDH2_CLK_SELRW0x0SDH2 Clock source Select
- 3'b000: 409MHz
- 3'b001: 614MHz
- 3'b010: PLL2_div8
- 3'b011: 819MHz
- 3'b100: PLL1_div11
- 3'b101: PLL1_div13
- 3'b110: PLL1_div23
- 3'b111: Reserved
4SDH2_CLK_ENRW0x0SDH2 Peripheral Clock Enable
- 1'b1: Peripheral clock enabled
- 1'b0: Peripheral clock disabled
3:2RSVDRO0x0Reserved
1SDH2_RSTRW0x0SDH2 Peripheral Reset
- 1'b0: Reset
0RSVDRO0x0Reserved
+Offset: 0xD4282800+0xE0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:12 | RSVD | RO | 0x0 | Reserved | +| 11 | SDH2_CLK_FC_REQ | W1C | 0x0 | SDH2 Clock Frequency Change Request. When this field is set to 1, it will force SDH2_CLK_DIV to work. This field will be automatically cleared by hardware when the clock switch is done. - Write 1 to force SDH2_CLK_DIV to work. - The field is cleared by hardware once forcing SDH2_CLK_DIV to work is done. | +| 10:8 | SDH2_CLK_DIV | RW | 0x1 | SDH2 Clock Frequency Divisor 0-7.SDH2_CLK = SDH2 source clock/(SDH2_CLK_DIV + 1) | +| 7:5 | SDH2_CLK_SEL | RW | 0x0 | SDH2 Clock source Select- 3'b000: 409MHz- 3'b001: 614MHz- 3'b010: PLL2_div8- 3'b011: 819MHz- 3'b100: PLL1_div11- 3'b101: PLL1_div13- 3'b110: PLL1_div23- 3'b111: Reserved | +| 4 | SDH2_CLK_EN | RW | 0x0 | SDH2 Peripheral Clock Enable- 1'b1: Peripheral clock enabled- 1'b0: Peripheral clock disabled | +| 3:2 | RSVD | RO | 0x0 | Reserved | +| 1 | SDH2_RST | RW | 0x0 | SDH2 Peripheral Reset- 1'b0: Reset | +| 0 | RSVD | RO | 0x0 | Reserved | ##### MEMORY CONTROLLER AHB REGISTER (PMUA_MC_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0xE8
BitsFieldTypeResetDescription
31DFC_D1P_BLOCKRW0x0- 1'b1: Disable Dynmanic Frequency Change during D1P
- 1'b0: Enable Dynmanic Frequency Change during D1P
30DDR_DPHY_PURW0x1DDR DPHY PU control.
> Note. Do not modify this value; it must always remain high.
29MC_CLK_GATE_BYPSRW0x0Memory Controller Clock Gating Bypass:
- 1'b1: Bypass MCK_root clock gating during low power state.
- 1'b0: No Bypass, MCK_root is gated during low power state (for power saving)
28:02RSVDRO0Reserved
1MC_AHBCLK_ENRW0x0Memory Controller AHB Clock Enable.
- 1'b1: AHB clock enabled
- 1'b0: AHB clock disabled
0MC_HCLK_RSTRW0x0Memory Controller HCLK Reset.
- 1'b0: Reset
+Offset: 0xD4282800+0xE8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | DFC_D1P_BLOCK | RW | 0x0 | - 1'b1: Disable Dynmanic Frequency Change during D1P - 1'b0: Enable Dynmanic Frequency Change during D1P | +| 30 | DDR_DPHY_PU | RW | 0x1 | DDR DPHY PU control. > Note. Do not modify this value; it must always remain high. | +| 29 | MC_CLK_GATE_BYPS | RW | 0x0 | Memory Controller Clock Gating Bypass:- 1'b1: Bypass MCK_root clock gating during low power state.- 1'b0: No Bypass, MCK_root is gated during low power state (for power saving) | +| 28:02 | RSVD | RO | 0 | Reserved | +| 1 | MC_AHBCLK_EN | RW | 0x0 | Memory Controller AHB Clock Enable.- 1'b1: AHB clock enabled- 1'b0: AHB clock disabled | +| 0 | MC_HCLK_RST | RW | 0x0 | Memory Controller HCLK Reset.- 1'b0: Reset | ##### AP CLOCK CONTROL REGISTER2 (PMU_CC2_AP) @@ -1942,2441 +645,437 @@ This register is used to trigger CPU CORE reset as follows: - MP (Multiprocessor) Level: - Additionally resets the debug logic for each processor in the debug power domain. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x100
BitsFieldTypeResetDescription
31:30RSVDRO0x0Reserved
29MPSUB_DBG_RSTRW0x0MP Debug Reset.
This field is used to reset the MP debug/Coresight logic, including core debug logic.
- 1'b1: Reset is asserted
- 1'b0: Reset is de-asserted
28C1_MPSUB_SW_RSTRW0x0Cluster1 Reset.
This field is used to reset Cluster1 logic except debug/Coresight logic.
- 1'b1: Reset is asserted
- 1'b0: Reset is de-asserted
27RSVDRO0x0Reserved
26CPU7_SW_RSTRW0x0CPU7 Core Software Reset
- 1'b1: Reset is asserted
- 1'b0: Reset is de-asserted
25CPU7_POR_RSTRW0x0CPU7 Core Power on Reset.
This field is used to reset CPU7 all logic, including debug logic.
- 1'b1:Reset is asserted
- 1'b0:Reset is de-asserted
24RSVDRO0x0Reserved
23CPU6_SW_RSTRW0x0CPU6 Core Software Reset
- 1'b1: Reset is asserted
- 1'b0: Reset is de-asserted
22CPU6_POR_RSTRW0x0CPU6 Core Power on Reset.
This field is used to reset CPU6 all logic, including debug logic.
- 1'b1:Reset is asserted
- 1'b0:Reset is de-asserted
21RSVDRO0x0Reserved
20CPU5_SW_RSTRW0x0CPU5 Core Software Reset
- 1'b1: Reset is asserted
- 1'b0: Reset is de-asserted
19CPU5_POR_RSTRW0x0CPU5 Core Power on Reset.
This field is used to reset CPU5 all logic, including debug logic.
- 1'b1:Reset is asserted
- 1'b0:Reset is de-asserted
18RSVDRO0x0Reserved
17CPU4_SW_RSTRW0x0CPU4 Core Software Reset
- 1'b1: Reset is asserted
- 1'b0: Reset is de-asserted
16CPU4_POR_RSTRW0x0CPU4 Core Power on Reset.
This field is used to reset CPU4 all logic, including debug logic.
- 1'b1:Reset is asserted
- 1'b0:Reset is de-asserted
15:13RSVDRO0x0Reserved
12C0_MPSUB_SW_RSTRW0x0Cluster0 Reset.
This field is used to reset Cluster0 logic except debug/Coresight logic.
- 1'b1: Reset is asserted
- 1'b0: Reset is de-asserted
11RSVDRO0x0Reserved
10CPU3_SW_RSTRW0x0CPU3 Core Software Reset
- 1'b1: Reset is asserted
- 1'b0: Reset is de-asserted
9CPU3_POR_RSTRW0x0CPU3 Core Power on Reset.
This field is used to reset CPU3 all logic, including debug logic.
- 1'b1:Reset is asserted
- 1'b0:Reset is de-asserted
8RSVDRO0x0Reserved
7CPU2_SW_RSTRW0x0CPU2 Core Software Reset
- 1'b1: Reset is asserted
- 1'b0: Reset is de-asserted
6CPU2_POR_RSTRW0x0CPU2 Core Power on Reset.
This field is used to reset CPU2 all logic, including debug logic.
- 1'b1:Reset is asserted
- 1'b0:Reset is de-asserted
5RSVDRO0x0Reserved
4CPU1_SW_RSTRW0x0CPU1 Core Software Reset
- 1'b1: Reset is asserted
- 1'b0: Reset is de-asserted
3CPU1_POR_RSTRW0x0CPU1 Core Power on Reset.
This field is used to reset CPU1 all logic, including debug logic.
- 1'b1:Reset is asserted
- 1'b0:Reset is de-asserted
2RSVDRO0x0Reserved
1CPU0_SW_RSTRW0x0CPU0 Core Software Reset
- 1'b1: Reset is asserted
- 1'b0: Reset is de-asserted
0CPU0_POR_RSTRW0x0CPU0 Core Power on Reset.
This field is used to reset CPU0 all logic, including debug logic.
- 1'b1:Reset is asserted
- 1'b0:Reset is de-asserted
+Offset: 0xD4282800+0x100 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | RSVD | RO | 0x0 | Reserved | +| 29 | MPSUB_DBG_RST | RW | 0x0 | MP Debug Reset.This field is used to reset the MP debug/Coresight logic, including core debug logic. - 1'b1: Reset is asserted- 1'b0: Reset is de-asserted | +| 28 | C1_MPSUB_SW_RST | RW | 0x0 | Cluster1 Reset. This field is used to reset Cluster1 logic except debug/Coresight logic. - 1'b1: Reset is asserted- 1'b0: Reset is de-asserted | +| 27 | RSVD | RO | 0x0 | Reserved | +| 26 | CPU7_SW_RST | RW | 0x0 | CPU7 Core Software Reset- 1'b1: Reset is asserted - 1'b0: Reset is de-asserted | +| 25 | CPU7_POR_RST | RW | 0x0 | CPU7 Core Power on Reset.This field is used to reset CPU7 all logic, including debug logic. - 1'b1:Reset is asserted- 1'b0:Reset is de-asserted | +| 24 | RSVD | RO | 0x0 | Reserved | +| 23 | CPU6_SW_RST | RW | 0x0 | CPU6 Core Software Reset- 1'b1: Reset is asserted - 1'b0: Reset is de-asserted | +| 22 | CPU6_POR_RST | RW | 0x0 | CPU6 Core Power on Reset.This field is used to reset CPU6 all logic, including debug logic. - 1'b1:Reset is asserted- 1'b0:Reset is de-asserted | +| 21 | RSVD | RO | 0x0 | Reserved | +| 20 | CPU5_SW_RST | RW | 0x0 | CPU5 Core Software Reset- 1'b1: Reset is asserted - 1'b0: Reset is de-asserted | +| 19 | CPU5_POR_RST | RW | 0x0 | CPU5 Core Power on Reset.This field is used to reset CPU5 all logic, including debug logic. - 1'b1:Reset is asserted- 1'b0:Reset is de-asserted | +| 18 | RSVD | RO | 0x0 | Reserved | +| 17 | CPU4_SW_RST | RW | 0x0 | CPU4 Core Software Reset- 1'b1: Reset is asserted - 1'b0: Reset is de-asserted | +| 16 | CPU4_POR_RST | RW | 0x0 | CPU4 Core Power on Reset.This field is used to reset CPU4 all logic, including debug logic. - 1'b1:Reset is asserted- 1'b0:Reset is de-asserted | +| 15:13 | RSVD | RO | 0x0 | Reserved | +| 12 | C0_MPSUB_SW_RST | RW | 0x0 | Cluster0 Reset. This field is used to reset Cluster0 logic except debug/Coresight logic. - 1'b1: Reset is asserted- 1'b0: Reset is de-asserted | +| 11 | RSVD | RO | 0x0 | Reserved | +| 10 | CPU3_SW_RST | RW | 0x0 | CPU3 Core Software Reset- 1'b1: Reset is asserted - 1'b0: Reset is de-asserted | +| 9 | CPU3_POR_RST | RW | 0x0 | CPU3 Core Power on Reset.This field is used to reset CPU3 all logic, including debug logic. - 1'b1:Reset is asserted- 1'b0:Reset is de-asserted | +| 8 | RSVD | RO | 0x0 | Reserved | +| 7 | CPU2_SW_RST | RW | 0x0 | CPU2 Core Software Reset- 1'b1: Reset is asserted - 1'b0: Reset is de-asserted | +| 6 | CPU2_POR_RST | RW | 0x0 | CPU2 Core Power on Reset.This field is used to reset CPU2 all logic, including debug logic. - 1'b1:Reset is asserted- 1'b0:Reset is de-asserted | +| 5 | RSVD | RO | 0x0 | Reserved | +| 4 | CPU1_SW_RST | RW | 0x0 | CPU1 Core Software Reset- 1'b1: Reset is asserted - 1'b0: Reset is de-asserted | +| 3 | CPU1_POR_RST | RW | 0x0 | CPU1 Core Power on Reset.This field is used to reset CPU1 all logic, including debug logic. - 1'b1:Reset is asserted- 1'b0:Reset is de-asserted | +| 2 | RSVD | RO | 0x0 | Reserved | +| 1 | CPU0_SW_RST | RW | 0x0 | CPU0 Core Software Reset- 1'b1: Reset is asserted - 1'b0: Reset is de-asserted | +| 0 | CPU0_POR_RST | RW | 0x0 | CPU0 Core Power on Reset.This field is used to reset CPU0 all logic, including debug logic. - 1'b1:Reset is asserted- 1'b0:Reset is de-asserted | ##### EMMC5.0 CLOCK/RESET CONTROL REGISTER (PMUA_EM_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x104
BitsFieldTypeResetDescription
31EM_PHY_TMS_SWRW0x0Control the bypass/test mode for EM5.0 EPHY pad:
- 1'b1: bypass/test mode enabled
- 1'b0: bypass/test disabled
30EM_PHY_TOE_SWRW0x0Control the selection of Test Data Output (TDO) ports:
- 1'b1: TDO ports are sampled with FCLK (low speed only).
- 1'b0: TDO ports are directly from receiver
29EM_PHY_VREFRW0x0SW controls the EPHY VREF port value
28EM_PHY_V18ENRW0x0EPHY IO 1.8 enable SW control.
This bit controls the 1.8V power supply for EPHY IO:
- 1'b1: 1.8V enabled
- 1'b0: 1.8V disabled
27EM_PHY_LP_SELRW0x0EPHY Low Power (LP) mode SW control.
This bit controls the Low Power Mode for EPHY:
- 1'b1: LP mode enabled
- 1'b0: LP mode disabled
26:16RSVDRO0Reserved
15EM_1248M_CLK_ENRW0x0EM5.0 1248 MHz Input Clock Enable
This bit Controls the 1248 MHz clock source for the EM clock divider:
- 1'b0: Disable EM 1248M clock divider clock source
- 1'b1: Enable EM 1248M clock divider clock source
14:12EM_1248M_CLK_DIVRW0x0EMMC5.0 1248 MHz Input Clock Frequency Divisor 0x0 to 0x7.
EM_1248M_DIV5 = 1248Mhz source clock/(EM_1248_CLK_DIV + 1)
11EM_CLK_FC_REQRW0x0- Write 1 to force EM_CLK_DIV to work.
- The field is cleared by hardware once forcing EM_CLK_DIV to work is done.
10:8EM_CLK_DIVRW0x0EM_CLK_DIV 0-7.
EM_CLK = EM source clock/(EM_CLK_DIV + 1)
7:6EM_CLK_SELRW0x0EM Clock source Selection
- 1'b0: 416MHz(clk_in_416m_PLL1)
- 1'b1: 624MHz(clk_in_PLL1_2x)
- 2'b10: 48MHz
- 2'b11: 800MHz(clk_in_PLL2)
5RSVDRO0Reserved
4EM_CLK_ENRW0x0EM Peripheral Clock Enable.
This bit controls the peripheral clock for EM:
- 1'b1: Peripheral clock enabled
- 1'b0: Peripheral clock disabled
3EM_AXICLK_ENRW0x0EM AXI Clock Enable.
This bit controls the AXI Clock for EM
- 1'b1: AXI clock enabled
- 1'b0: AXI clock disabled
2RSVDRO0Reserved
1EM_RSTRW0x0EM Peripheral Reset
- 1'b0: Reset
> Note. The eMMC5.0 controller primarily uses EM_AXI_RST instead of this reset.
0EM_AXI_RSTRW0x0EM AXI Reset.
+Offset: 0xD4282800+0x104 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | EM_PHY_TMS_SW | RW | 0x0 | Control the bypass/test mode for EM5.0 EPHY pad:- 1'b1: bypass/test mode enabled- 1'b0: bypass/test disabled | +| 30 | EM_PHY_TOE_SW | RW | 0x0 | Control the selection of Test Data Output (TDO) ports: - 1'b1: TDO ports are sampled with FCLK (low speed only).- 1'b0: TDO ports are directly from receiver | +| 29 | EM_PHY_VREF | RW | 0x0 | SW controls the EPHY VREF port value | +| 28 | EM_PHY_V18EN | RW | 0x0 | EPHY IO 1.8 enable SW control.This bit controls the 1.8V power supply for EPHY IO:- 1'b1: 1.8V enabled- 1'b0: 1.8V disabled | +| 27 | EM_PHY_LP_SEL | RW | 0x0 | EPHY Low Power (LP) mode SW control.This bit controls the Low Power Mode for EPHY:- 1'b1: LP mode enabled - 1'b0: LP mode disabled | +| 26:16 | RSVD | RO | 0 | Reserved | +| 15 | EM_1248M_CLK_EN | RW | 0x0 | EM5.0 1248 MHz Input Clock Enable This bit Controls the 1248 MHz clock source for the EM clock divider:- 1'b0: Disable EM 1248M clock divider clock source- 1'b1: Enable EM 1248M clock divider clock source | +| 14:12 | EM_1248M_CLK_DIV | RW | 0x0 | EMMC5.0 1248 MHz Input Clock Frequency Divisor 0x0 to 0x7.EM_1248M_DIV5 = 1248Mhz source clock/(EM_1248_CLK_DIV + 1) | +| 11 | EM_CLK_FC_REQ | RW | 0x0 | - Write 1 to force EM_CLK_DIV to work. - The field is cleared by hardware once forcing EM_CLK_DIV to work is done. | +| 10:8 | EM_CLK_DIV | RW | 0x0 | EM_CLK_DIV 0-7.EM_CLK = EM source clock/(EM_CLK_DIV + 1) | +| 7:6 | EM_CLK_SEL | RW | 0x0 | EM Clock source Selection- 1'b0: 416MHz(clk_in_416m_PLL1) - 1'b1: 624MHz(clk_in_PLL1_2x)- 2'b10: 48MHz - 2'b11: 800MHz(clk_in_PLL2) | +| 5 | RSVD | RO | 0 | Reserved | +| 4 | EM_CLK_EN | RW | 0x0 | EM Peripheral Clock Enable.This bit controls the peripheral clock for EM:- 1'b1: Peripheral clock enabled - 1'b0: Peripheral clock disabled | +| 3 | EM_AXICLK_EN | RW | 0x0 | EM AXI Clock Enable.This bit controls the AXI Clock for EM- 1'b1: AXI clock enabled- 1'b0: AXI clock disabled | +| 2 | RSVD | RO | 0 | Reserved | +| 1 | EM_RST | RW | 0x0 | EM Peripheral Reset - 1'b0: Reset> Note. The eMMC5.0 controller primarily uses EM_AXI_RST instead of this reset. | +| 0 | EM_AXI_RST | RW | 0x0 | EM AXI Reset. | ##### USB PHY CONTROL REGISTER0 (PMUA_USB_PHY_CTRL0) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x110
BitsFieldTypeResetDescription
31:4RSVDRO0x0Reserved
3COMBO_PHY_SELRW0x0It specifies the function of the shared PUPHY
- 1'b0: Indicate the shared PUPHY is used for PCIe.
- 1'b1 : Indicate the shared PUPHY is used for USB3.
2:0RSVDRO0x0Reserved
+Offset: 0xD4282800+0x110 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | RSVD | RO | 0x0 | Reserved | +| 3 | COMBO_PHY_SEL | RW | 0x0 | It specifies the function of the shared PUPHY- 1'b0: Indicate the shared PUPHY is used for PCIe.- 1'b1: Indicate the shared PUPHY is used for USB3. | +| 2:0 | RSVD | RO | 0x0 | Reserved | ##### AUDIO CLOCK RESET ENABLE REGISTER (PMU_AUDIO_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x14C
BitsFieldTypeResetDescription
31AUDIO_PWR_STATUS
RO0x1Audio Power domain status
It indicates the power status of the Audio PMU:
- 1'b1: Audio PMU is in Power-On status
- 1'b0: Audio PMU is in Power-Off status
30USE_SOFT_RSTRW0x0This bit set to force audio use soft reset
29AUDIO_AUTO_POWER_ON_OFF_TRIGGER_IN_HARDWARE_MODERW0x1Audio Auto Power On/Off Trigger
It controls the automatic power-on or power-off request for Audio Power Island:
- 1'b1: Triggers request to power-up the Audio Power Island
- 1'b0: Triggers request to power-down Audio Power Island
28AP_POWER_CTL_AUDIO_AUTHORW0x1AP Power Control Audio Authority.
It specifies whether the AP (Application Processor) can control Audio power
- 1'b1: AP has control over Audio power
- 1'b0: AP can not control Audio power, and Audio PMU manages the audio power switch.
27:24RSVDRO0x0Reserved
23AUDIO_PWR_STATUSRO0x1Status for Audio PMU.
It indicates the power status of the Audio PMU
- 1'b0: Audio PMU is in Power-Off status.
- 1'b1: Audio PMU is in Power-On status
22:20RSVDRO0x0Reserved
19LOG_ENRW0x0Debug Information Recording Enable:
It controls whether debug information (e.g., PC value, bus status) is recorded.
- 1'b0: Disabled
- 1'b1: Enabled
18ADSP_ENRW0x0It controls whether the DSP is active or not
1'b0: Hold DSP (DSP is in wait status)
1'b1: Active DSP (DSP is running)
17:16RSVDRO0x0Reserved
15AUDIO_FC_REQW1C0x0Audio island main clock Frequency Change Request.
- 1'b1: Triggers a frequency change.
- The field is cleared by hardware once the frequency change is done
14FORCE_AUD_PWR_OFFRW0x0It controls whether to force the audio power to turn off
- 1'b1: Force audio power off
- 1'b0: Do not force audio power off
13FORCE_AUD_PWR_ONRW0x0It controls whether to force the audio power to turn on
- 1'b1: Force audio power on
- 1'b0: Do not force audio power on
12AUDIO_CLK_ENRW0x0Audio clock enable
- 1'b1: Enabled
11CUR_PWR_MSTRO0x0Audio Power Control Authority Indicator
It indicates which component controls the audio power switch
- 1'b1: AP controls audio power switch
- 1'b0: Audio PMU controls audio power switch
10AUDIO_HW_CKG_BYPASSRW0x0Audio Always On Domain reset
This bit should be always set to 1 after the silicon power up
9:7AUDIO_CLK_SELRW0x0Audio Main Clock Selection
It controls the clock source for the audio main clock
- 3'b000: PLL1 245.76MHz
- 3'b001: PLL1 312MHz
- 3'b010: Reserved
- 3'b011: PLL1 416MHz
- 3'b100-3'b111: Reserved
6:4AUDIO_CLK_DIVRW0x0Clock divider control for audio main clock.
Audio Main Clock = selected Clock/(AUDIO_CLK_DIV+1)
when AUDIO_CLK_SEL=1 or 3, AUDIO_CLK_DIV must be greater than 0
3AUDIO_APMU_RESETRW0x0Audio APMU reset
This bit should be always set to 1 after the silicon power up
2AUD_MCU_CORE_RESETRW0x0Soft AUD_MCU core_rst.
It controls the reset state of the AUD_MCU core
- 1'b0: Reset
- 1'b1: Release reset
1RSVDRO0x0Reserved
0AUDIO_SYS_RESETRW0x0Soft audio island system reset
It controls the reset state of the audio island system
- 1'b0: Reset
- 1'b1: Release reset
+Offset: 0xD4282800+0x14C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | AUDIO_PWR_STATUS | RO | 0x1 | Audio Power domain statusIt indicates the power status of the Audio PMU:- 1'b1: Audio PMU is in Power-On status - 1'b0: Audio PMU is in Power-Off status | +| 30 | USE_SOFT_RST | RW | 0x0 | This bit set to force audio use soft reset | +| 29 | AUDIO_AUTO_POWER_ON_OFF_TRIGGER_IN_HARDWARE_MODE | RW | 0x1 | Audio Auto Power On/Off TriggerIt controls the automatic power-on or power-off request for Audio Power Island:- 1'b1: Triggers request to power-up the Audio Power Island- 1'b0: Triggers request to power-down Audio Power Island | +| 28 | AP_POWER_CTL_AUDIO_AUTHO | RW | 0x1 | AP Power Control Audio Authority.It specifies whether the AP (Application Processor) can control Audio power- 1'b1: AP has control over Audio power- 1'b0: AP can not control Audio power, and Audio PMU manages the audio power switch. | +| 27:24 | RSVD | RO | 0x0 | Reserved | +| 23 | AUDIO_PWR_STATUS | RO | 0x1 | Status for Audio PMU.It indicates the power status of the Audio PMU- 1'b0: Audio PMU is in Power-Off status.- 1'b1: Audio PMU is in Power-On status | +| 22:20 | RSVD | RO | 0x0 | Reserved | +| 19 | LOG_EN | RW | 0x0 | Debug Information Recording Enable:It controls whether debug information (e.g., PC value, bus status) is recorded.- 1'b0: Disabled- 1'b1: Enabled | +| 18 | ADSP_EN | RW | 0x0 | It controls whether the DSP is active or not1'b0: Hold DSP (DSP is in wait status)1'b1: Active DSP (DSP is running) | +| 17:16 | RSVD | RO | 0x0 | Reserved | +| 15 | AUDIO_FC_REQ | W1C | 0x0 | Audio island main clock Frequency Change Request.- 1'b1: Triggers a frequency change. - The field is cleared by hardware once the frequency change is done | +| 14 | FORCE_AUD_PWR_OFF | RW | 0x0 | It controls whether to force the audio power to turn off- 1'b1: Force audio power off- 1'b0: Do not force audio power off | +| 13 | FORCE_AUD_PWR_ON | RW | 0x0 | It controls whether to force the audio power to turn on- 1'b1: Force audio power on- 1'b0: Do not force audio power on | +| 12 | AUDIO_CLK_EN | RW | 0x0 | Audio clock enable- 1'b1: Enabled | +| 11 | CUR_PWR_MST | RO | 0x0 | Audio Power Control Authority IndicatorIt indicates which component controls the audio power switch- 1'b1: AP controls audio power switch - 1'b0: Audio PMU controls audio power switch | +| 10 | AUDIO_HW_CKG_BYPASS | RW | 0x0 | Audio Always On Domain resetThis bit should be always set to 1 after the silicon power up | +| 9:7 | AUDIO_CLK_SEL | RW | 0x0 | Audio Main Clock SelectionIt controls the clock source for the audio main clock- 3'b000: PLL1 245.76MHz- 3'b001: PLL1 312MHz- 3'b010: Reserved- 3'b011: PLL1 416MHz- 3'b100-3'b111: Reserved | +| 6:4 | AUDIO_CLK_DIV | RW | 0x0 | Clock divider control for audio main clock.Audio Main Clock = selected Clock/(AUDIO_CLK_DIV+1) when AUDIO_CLK_SEL=1 or 3, AUDIO_CLK_DIV must be greater than 0 | +| 3 | AUDIO_APMU_RESET | RW | 0x0 | Audio APMU resetThis bit should be always set to 1 after the silicon power up | +| 2 | AUD_MCU_CORE_RESET | RW | 0x0 | Soft AUD_MCU core_rst.It controls the reset state of the AUD_MCU core- 1'b0: Reset- 1'b1: Release reset | +| 1 | RSVD | RO | 0x0 | Reserved | +| 0 | AUDIO_SYS_RESET | RW | 0x0 | Soft audio island system resetIt controls the reset state of the audio island system- 1'b0: Reset- 1'b1: Release reset | ##### MP DCLK DYNAMIC FREQ CHANGE CONTROL REGISTER (DFC_AP) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x180
BitsFieldTypeResetDescription
31:4RSVDRO0x0Reserved
3:1FLRW0x0DCLK Frequency Level in Active Mode
It specifies the required frequency level for DCLK in active mode, as determined by MP.
0DFC_REQRW0x0DCLK HFC Request in Active Mode.
It is used by software to signal that a DCLK HFC is required for the MP in active mode.
- Writing 1 to this bit to trigger this request, and the hardware automatically clears it once the request action is done.
- Writing 0 to this bit has no effect.
+Offset: 0xD4282800+0x180 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | RSVD | RO | 0x0 | Reserved | +| 3:1 | FL | RW | 0x0 | DCLK Frequency Level in Active Mode It specifies the required frequency level for DCLK in active mode, as determined by MP. | +| 0 | DFC_REQ | RW | 0x0 | DCLK HFC Request in Active Mode. It is used by software to signal that a DCLK HFC is required for the MP in active mode.- Writing 1 to this bit to trigger this request, and the hardware automatically clears it once the request action is done.- Writing 0 to this bit has no effect. | ##### MP DCLK HARDWARE FREQ CHANGE STATUS REGISTER (DFC_STATUS) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x188
BitsFieldTypeResetDescription
31:11RSVDRO0x0Reserved
10:7DFC_CAUSERO0x0DCLK DFC Cause.
This field indicates the reason for the current DFC of the DCLK.
This field is valid only when the <DCLK_DFC_STATUS> field is set to 1.
- 4'b0001: MP Triggered DFC
- Other values: Low power mode entry/exit triggered DFC
6:4TFLRO0x0Target Frequency Level of DCLK
3:1CFLRO0x0Current Frequency Level of DCLK
0DFC_STATUSRW0x0DCLK DFC Status
It indicates the status of DFC for the DCLK, specifying whether a DFC is active:
- 1'b0: No ongoing DFC, or the DFC has just completed
- 1'b1: A DFC is currently active
+Offset: 0xD4282800+0x188 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:11 | RSVD | RO | 0x0 | Reserved | +| 10:7 | DFC_CAUSE | RO | 0x0 | DCLK DFC Cause. This field indicates the reason for the current DFC of the DCLK.This field is valid only when the field is set to 1.- 4'b0001: MP Triggered DFC - Other values: Low power mode entry/exit triggered DFC | +| 6:4 | TFL | RO | 0x0 | Target Frequency Level of DCLK | +| 3:1 | CFL | RO | 0x0 | Current Frequency Level of DCLK | +| 0 | DFC_STATUS | RW | 0x0 | DCLK DFC Status It indicates the status of DFC for the DCLK, specifying whether a DFC is active:- 1'b0: No ongoing DFC, or the DFC has just completed- 1'b1: A DFC is currently active | ##### DCLK FREQ LEVEL 0 CONTROL REGISTER (DFC_LEVEL_X) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x190/0x194/0x198/0x19C/0x1A0/0x1A4/0x1A8/0x1AC
BitsFieldTypeResetDescription
31:16RSVDRO0x0Reserved
15:14PLL_CLK_DIVRW0x0PLL Clock Divider Configuration
- 2'b11: DIV4
- 2'b10: DIV3
- 2'b01: DIV2
- 2'b00: DIV1
13DCLK_POSTDIVRW0x0PLL bypass Clock Divider Configuration.
1'b1: Divide the clock by 2
1'b0: No division (bypass)
12PLL_BYPASS_SELRW0x0
PLL Bypass Selection
- 1'b1: Bypass PLL
- 1'b0: Enable PLL
11:9RSVDRO0x0Reserved
8PLL_SELRW0x0PLL Selection
It indicates which PLL (PLL1 or PLL2) is selected for operation.
It is effective only when FREQ_PLL_CHG_MODE is set to 1.
- 1'b0: PLL2 is selected
- 1'b1：PLL1 is selected
7PLL_SEL_OFF
RW0x0PLL Selection (for disabling Unused PLL)
It controls the disabling of one of the PLLs.
It is effective only when FREQ_PLL_CHG_MODE is set to 1.
- 1’b0: Do not disable the PLL
- 1'b1: Disable unused PLL.
1. If PLL_SEL is 1, it will disable PLL2.
2. If PLL_SEL is 0, it will disable PLL1.
6:4MC_TABLE_NUMRW0x0This field is used to control frequency changes by selecting from pre-defined configuration
- bit[6]: 1'b1: The target frequency is high frequency
- bit[5:4]: Specifies the target timing table number
3:0VLRW0x0Required Voltage Level
+Offset: 0xD4282800+0x190/0x194/0x198/0x19C/0x1A0/0x1A4/0x1A8/0x1AC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RSVD | RO | 0x0 | Reserved | +| 15:14 | PLL_CLK_DIV | RW | 0x0 | PLL Clock Divider Configuration- 2'b11: DIV4- 2'b10: DIV3- 2'b01: DIV2- 2'b00: DIV1 | +| 13 | DCLK_POSTDIV | RW | 0x0 | PLL bypass Clock Divider Configuration.1'b1: Divide the clock by 21'b0: No division (bypass) | +| 12 | PLL_BYPASS_SEL | RW | 0x0 | PLL Bypass Selection- 1'b1: Bypass PLL - 1'b0: Enable PLL | +| 11:9 | RSVD | RO | 0x0 | Reserved | +| 8 | PLL_SEL | RW | 0x0 | PLL SelectionIt indicates which PLL (PLL1 or PLL2) is selected for operation.It is effective only when FREQ_PLL_CHG_MODE is set to 1.- 1'b0: PLL2 is selected- 1'b1：PLL1 is selected | +| 7 | PLL_SEL_OFF | RW | 0x0 | PLL Selection (for disabling Unused PLL)It controls the disabling of one of the PLLs.It is effective only when FREQ_PLL_CHG_MODE is set to 1.- 1’b0: Do not disable the PLL- 1'b1: Disable unused PLL. 1. If PLL_SEL is 1, it will disable PLL2. 2. If PLL_SEL is 0, it will disable PLL1. | +| 6:4 | MC_TABLE_NUM | RW | 0x0 | This field is used to control frequency changes by selecting from pre-defined configuration- bit[6]: 1'b1: The target frequency is high frequency - bit[5:4]: Specifies the target timing table number | +| 3:0 | VL | RW | 0x0 | Required Voltage Level | ##### HDMI CLOCK/RESET CONTROL REGISTER (PMU_HDMI_CLK_RES_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x1B8
BitsFieldTypeResetDescription
31:30RSVDRO0x0Reserved
29HDMI_MCLK_FC_REQW1C0x0HDMI MCLK FC Request
- Write 1 to trigger the frequency change.
- The field is cleared by hardware once the frequency change is done.
28:10RSVDRO0x0Reserved
9HDMI_MCLK_RESETRW0x1- 1'b0: Reset
8RSVDRO0x0Reserved
7:5HDMI_MCLK_SELRW0x0HDMI MCLK Clock Selection
- 3'b000: PLL1_409MHz
- 3'b001: PLL1_491MHz
- 3'b010: PLL1_614MHz
- 3‘b011: PLL1_307MHz
- 3'b100-3'b111: NA
4:1HDMI_MCLK_DIVRW0x2HDMI MCLK Clock Divide Ratio.
HDMI_MCLK = clock source/ (this field +1)
0HDMI_MCLK_ENRW0x0HDMI MCLK Enable.
- 1'b0: Disabled
- 1'b1: Enabled
+Offset: 0xD4282800+0x1B8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | RSVD | RO | 0x0 | Reserved | +| 29 | HDMI_MCLK_FC_REQ | W1C | 0x0 | HDMI MCLK FC Request - Write 1 to trigger the frequency change. - The field is cleared by hardware once the frequency change is done. | +| 28:10 | RSVD | RO | 0x0 | Reserved | +| 9 | HDMI_MCLK_RESET | RW | 0x1 | - 1'b0: Reset | +| 8 | RSVD | RO | 0x0 | Reserved | +| 7:5 | HDMI_MCLK_SEL | RW | 0x0 | HDMI MCLK Clock Selection- 3'b000: PLL1_409MHz- 3'b001: PLL1_491MHz- 3'b010: PLL1_614MHz- 3‘b011: PLL1_307MHz- 3'b100-3'b111: NA | +| 4:1 | HDMI_MCLK_DIV | RW | 0x2 | HDMI MCLK Clock Divide Ratio.HDMI_MCLK = clock source/ (this field +1) | +| 0 | HDMI_MCLK_EN | RW | 0x0 | HDMI MCLK Enable.- 1'b0: Disabled- 1'b1: Enabled | ##### CMOS CAMERA INTERFACE CONTROLLER 2 DYNAMIC CLOCK GATE CONTROL REGISTER (PMU_CCIC2_CLK_GATE_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x1BC
BitsFieldTypeResetDescription
31:30CCIC2_GATE_CSI_CLK_STATICRW0x3CCIC2 CSI Static Clock Gate Control
- 2'b00: Stop clock
- 2'b01: Stop clock
- 2'b10: Stop clock
- 2'b11: Free running
29:28CCIC2_GATE_CLK4X_STATICRW0x3CCIC2 clk4x Static Clock Gate Control
- 2'b00: Stop clock
- 2'b01: Stop clock
- 2'b10: Stop clock
- 2'b11: Free running
27:26CCIC2_GATE_CLK1X_STATICRW0x3CCIC2 clk1x Static Clock Gate Control
- 2'b00: Stop clock
- 2'b01: Stop clock
- 2'b10: Stop clock
- 2'b11: Free running
25:24CCIC2_GATE_HCLK_STATICRW0x3CCIC2 hclk Static Clock Gate Control
- 2'b00: Stop clock
- 2'b01: Stop clock
- 2'b10: Stop clock
- 2'b11: Free running
23:22CCIC2_GATE_ACLK_STATICRW0x3CCIC2 aclk Static Clock Gate Control
- 2'b00: Stop clock
- 2'b01: Stop clock
- 2'b10: Stop clock
- 2'b11: Free running
21:16RSVDRO0x0Reserved
15:14CCIC2_GATE_LANE3_CLK_DYNAMICRW0x3
CCIC2 CSI Lane 3 Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
13:12CCIC2_GATE_LANE2_CLK_DYNAMICRW0x3CCIC2 CSI Lane 2 Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
11:10CCIC2_GATE_LANE1_CLK_DYNAMICRW0x3 CIC2 CSI Lane 1 Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
9:8CCIC2_GATE_LANE0_CLK_DYNAMICRW0x3CCIC2 CSI Lane 0 Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
7:6CCIC2_GATE_CSI_CLK_DYNAMICRW0x3CCIC2 CSI Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
5:4CCIC2_GATE_AHB_CLK_DYNAMICRW0x3CCIC2 ahb Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
3:2CCIC2_GATE_PIP_CLK_DYNAMICRW0x3CCIC2 axi Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
1:0CCIC2_GATE__AXI_CLK_DYNAMICRW0x3CCIC2 axi Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
+Offset: 0xD4282800+0x1BC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | CCIC2_GATE_CSI_CLK_STATIC | RW | 0x3 | CCIC2 CSI Static Clock Gate Control - 2'b00: Stop clock- 2'b01: Stop clock- 2'b10: Stop clock- 2'b11: Free running | +| 29:28 | CCIC2_GATE_CLK4X_STATIC | RW | 0x3 | CCIC2 clk4x Static Clock Gate Control - 2'b00: Stop clock- 2'b01: Stop clock- 2'b10: Stop clock- 2'b11: Free running | +| 27:26 | CCIC2_GATE_CLK1X_STATIC | RW | 0x3 | CCIC2 clk1x Static Clock Gate Control - 2'b00: Stop clock- 2'b01: Stop clock- 2'b10: Stop clock- 2'b11: Free running | +| 25:24 | CCIC2_GATE_HCLK_STATIC | RW | 0x3 | CCIC2 hclk Static Clock Gate Control - 2'b00: Stop clock- 2'b01: Stop clock- 2'b10: Stop clock- 2'b11: Free running | +| 23:22 | CCIC2_GATE_ACLK_STATIC | RW | 0x3 | CCIC2 aclk Static Clock Gate Control - 2'b00: Stop clock- 2'b01: Stop clock- 2'b10: Stop clock- 2'b11: Free running | +| 21:16 | RSVD | RO | 0x0 | Reserved | +| 15:14 | CCIC2_GATE_LANE3_CLK_DYNAMIC | RW | 0x3 | CCIC2 CSI Lane 3 Clock Dynamic Clock Gate Control- 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 13:12 | CCIC2_GATE_LANE2_CLK_DYNAMIC | RW | 0x3 | CCIC2 CSI Lane 2 Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 11:10 | CCIC2_GATE_LANE1_CLK_DYNAMIC | RW | 0x3 | CIC2 CSI Lane 1 Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 9:8 | CCIC2_GATE_LANE0_CLK_DYNAMIC | RW | 0x3 | CCIC2 CSI Lane 0 Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 7:6 | CCIC2_GATE_CSI_CLK_DYNAMIC | RW | 0x3 | CCIC2 CSI Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 5:4 | CCIC2_GATE_AHB_CLK_DYNAMIC | RW | 0x3 | CCIC2 ahb Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 3:2 | CCIC2_GATE_PIP_CLK_DYNAMIC | RW | 0x3 | CCIC2 axi Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 1:0 | CCIC2_GATE__AXI_CLK_DYNAMIC | RW | 0x3 | CCIC2 axi Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | ##### CMOS CAMERA INTERFACE CONTROLLER 3 DYNAMIC CLOCK GATE CONTROL REGISTER (PMU_CCIC3_CLK_GATE_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x1C0
BitsFieldTypeResetDescription
31:30CCIC3_GATE_CSI_CLK_STATICRW0x3CCIC3 CSI Static Clock Gate Control
- 2'b00: Stop clock
- 2'b01: Stop clock
- 2'b10: Stop clock
- 2'b11: Free running
29:28CCIC3_GATE_CLK4X_STATICRW0x3CCIC3 clk4x Static Clock Gate Control
- 2'b00: Stop clock
- 2'b01: Stop clock
- 2'b10: Stop clock
- 2'b11: Free running
27:26CCIC3_GATE_CLK1X_STATICRW0x3CCIC3 clk1x Static Clock Gate Control
- 2'b00: Stop clock
- 2'b01: Stop clock
- 2'b10: Stop clock
- 2'b11: Free running
25:24CCIC3_GATE_HCLK_STATICRW0x3CCIC3 hclk Static Clock Gate Control
- 2'b00: Stop clock
- 2'b01: Stop clock
- 2'b10: Stop clock
- 2'b11: Free running
23:22CCIC3_GATE_ACLK_STATICRW0x3CCIC3 aclk Static Clock Gate Control
- 2'b00: Stop clock
- 2'b01: Stop clock
- 2'b10: Stop clock
- 2'b11: Free running
21:16RSVDRO0x0Reserved
15:14CCIC3_GATE_LANE3_CLK_DYNAMICRW0x3
CCIC3 CSI Lane 3 Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
13:12CCIC3_GATE_LANE2_CLK_DYNAMICRW0x3CCIC3 CSI Lane 2 Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
11:10CCIC3_GATE_LANE1_CLK_DYNAMICRW0x3CIC2 CSI Lane 1 Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
9:8CCIC3_GATE_LANE0_CLK_DYNAMICRW0x3CCIC3 CSI Lane 0 Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
7:6CCIC3_GATE_CSI_CLK_DYNAMICRW0x3CCIC3 CSI Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
5:4CCIC3_GATE_AHB_CLK_DYNAMICRW0x3CCIC3 ahb Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
3:2CCIC3_GATE_PIP_CLK_DYNAMICRW0x3CCIC3 axi Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
1:0CCIC3_GATE__AXI_CLK_DYNAMICRW0x3CCIC3 axi Clock Dynamic Clock Gate Control
- 2'b00: Hardware dynamic control
- 2'b01: Hardware dynamic control
- 2'b10: Stop clock
- 2'b11: Free running
+Offset: 0xD4282800+0x1C0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:30 | CCIC3_GATE_CSI_CLK_STATIC | RW | 0x3 | CCIC3 CSI Static Clock Gate Control - 2'b00: Stop clock- 2'b01: Stop clock- 2'b10: Stop clock- 2'b11: Free running | +| 29:28 | CCIC3_GATE_CLK4X_STATIC | RW | 0x3 | CCIC3 clk4x Static Clock Gate Control - 2'b00: Stop clock- 2'b01: Stop clock- 2'b10: Stop clock- 2'b11: Free running | +| 27:26 | CCIC3_GATE_CLK1X_STATIC | RW | 0x3 | CCIC3 clk1x Static Clock Gate Control - 2'b00: Stop clock- 2'b01: Stop clock- 2'b10: Stop clock- 2'b11: Free running | +| 25:24 | CCIC3_GATE_HCLK_STATIC | RW | 0x3 | CCIC3 hclk Static Clock Gate Control - 2'b00: Stop clock- 2'b01: Stop clock- 2'b10: Stop clock- 2'b11: Free running | +| 23:22 | CCIC3_GATE_ACLK_STATIC | RW | 0x3 | CCIC3 aclk Static Clock Gate Control - 2'b00: Stop clock- 2'b01: Stop clock- 2'b10: Stop clock- 2'b11: Free running | +| 21:16 | RSVD | RO | 0x0 | Reserved | +| 15:14 | CCIC3_GATE_LANE3_CLK_DYNAMIC | RW | 0x3 | CCIC3 CSI Lane 3 Clock Dynamic Clock Gate Control- 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 13:12 | CCIC3_GATE_LANE2_CLK_DYNAMIC | RW | 0x3 | CCIC3 CSI Lane 2 Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 11:10 | CCIC3_GATE_LANE1_CLK_DYNAMIC | RW | 0x3 | CIC2 CSI Lane 1 Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 9:8 | CCIC3_GATE_LANE0_CLK_DYNAMIC | RW | 0x3 | CCIC3 CSI Lane 0 Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 7:6 | CCIC3_GATE_CSI_CLK_DYNAMIC | RW | 0x3 | CCIC3 CSI Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 5:4 | CCIC3_GATE_AHB_CLK_DYNAMIC | RW | 0x3 | CCIC3 ahb Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 3:2 | CCIC3_GATE_PIP_CLK_DYNAMIC | RW | 0x3 | CCIC3 axi Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | +| 1:0 | CCIC3_GATE__AXI_CLK_DYNAMIC | RW | 0x3 | CCIC3 axi Clock Dynamic Clock Gate Control - 2'b00: Hardware dynamic control- 2'b01: Hardware dynamic control- 2'b10: Stop clock- 2'b11: Free running | ##### CCI550 CLOCK CONTROL REGISTER (PMU_CCI_CLK_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x300
BitsFieldTypeResetDescription
31:17RSVDRO0x0Reserved
16MASK_DRAGON_ADB400_CCI_SIDE_IDLERW0x0Mask Dragon ADB400 CCI Side Idle Flag:
It controls whether to mask the CCI side idle flag for cci_idle_clk_off_req
- 1'b1: Mask the idle flag
- 1'b0: Unmask the idle flag
15CCI_CLK_SMOOTH_MUX_DISRW0x0
CCI Clock Smooth Multiplexer Disable
It controls whether a smooth transition for the CCI clock is enabled or disabled.
- 1'b0: Enable CCI clock smooth MUX
1. Hardware automatically switches to the VCXO clock when the CPU enters M2 mode and the GPU shuts down.
- 1'b1: Disable CCI clock smooth MUX
1. The clock for the CCI will only come from cci_clock_gen
2. The clock for the CCI is gated when the CPU enters M2 mode and the GPU shuts down
14CCI_CLKEN_BY_INT_APRW0x0CCI Clock Enable by SYS_INT_AP
It controls whether the CCI clock can be enabled by sys_int_ap[127:0]
- 1'b0: The CCI clock is only controlled by the status of CPU Clusters and GPU
- 1'b1: Enable this function
13CCI550_CLKGEN_AUTO_CG_ENRW0x0CCI Clock Generator Automatic Gating Control
It manages automatic gating for the CCI clock generator working clock
- 1'b0: The automatic clock gating for the CCI550 clock generator is disabled, and the clock is free-running
- 1'b1: The automatic clock gating for the CCI550 clock generator is enabled
12CCI550_FC_REQRW0x0CCI frequency change request.
- The field is cleared by hardware once the frequency change is done.
11RSVDRO0x0Reserved
10:8CCI550_BIU_CLK_DIVRW0x1Clock Divider Selection for CCI AXI_M0 port to fabric.
ACLK_M0 = ACLKM1/ (this field +1)
7:2RSVDRO0x0Reserved
1:0CCI550_PLLSELRW0x0CCI Clock Selection.
- 2'b00: PLL1_491MHz.
- 2'b01: PLL1 614MHz.
- 2'b10: 819MHz.
- 3'b11: PLL2_div3(1000MHz), as a backup for increasing voltage scenario
+Offset: 0xD4282800+0x300 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:17 | RSVD | RO | 0x0 | Reserved | +| 16 | MASK_DRAGON_ADB400_CCI_SIDE_IDLE | RW | 0x0 | Mask Dragon ADB400 CCI Side Idle Flag:It controls whether to mask the CCI side idle flag for cci_idle_clk_off_req- 1'b1: Mask the idle flag- 1'b0: Unmask the idle flag | +| 15 | CCI_CLK_SMOOTH_MUX_DIS | RW | 0x0 | CCI Clock Smooth Multiplexer DisableIt controls whether a smooth transition for the CCI clock is enabled or disabled.- 1'b0: Enable CCI clock smooth MUX 1. Hardware automatically switches to the VCXO clock when the CPU enters M2 mode and the GPU shuts down.- 1'b1: Disable CCI clock smooth MUX 1. The clock for the CCI will only come from cci_clock_gen 2. The clock for the CCI is gated when the CPU enters M2 mode and the GPU shuts down | +| 14 | CCI_CLKEN_BY_INT_AP | RW | 0x0 | CCI Clock Enable by SYS_INT_APIt controls whether the CCI clock can be enabled by sys_int_ap[127:0]- 1'b0: The CCI clock is only controlled by the status of CPU Clusters and GPU- 1'b1: Enable this function | +| 13 | CCI550_CLKGEN_AUTO_CG_EN | RW | 0x0 | CCI Clock Generator Automatic Gating ControlIt manages automatic gating for the CCI clock generator working clock- 1'b0: The automatic clock gating for the CCI550 clock generator is disabled, and the clock is free-running - 1'b1: The automatic clock gating for the CCI550 clock generator is enabled | +| 12 | CCI550_FC_REQ | RW | 0x0 | CCI frequency change request. - The field is cleared by hardware once the frequency change is done. | +| 11 | RSVD | RO | 0x0 | Reserved | +| 10:8 | CCI550_BIU_CLK_DIV | RW | 0x1 | Clock Divider Selection for CCI AXI_M0 port to fabric. ACLK_M0 = ACLKM1/ (this field +1) | +| 7:2 | RSVD | RO | 0x0 | Reserved | +| 1:0 | CCI550_PLLSEL | RW | 0x0 | CCI Clock Selection.- 2'b00: PLL1_491MHz. - 2'b01: PLL1 614MHz. - 2'b10: 819MHz. - 3'b11: PLL2_div3(1000MHz), as a backup for increasing voltage scenario | ##### AP ACLK CONTROL REGISTER (PMUA_ACLK_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x388
BitsFieldTypeResetDescription
31:5RSVDRO0x0Reserved
4ACLK_FC_REQRW0x0ACLK frequency change request.
- 1'b1: Enable ACLK Frequency Change.
- The field is cleared by hardware once the frequency change is done.
3RSVDRO0x0Reserved
2:1ACLK_DIVRW0x0ACLK_DIV
ACLK=<ACLK_SEL>/(<ACLK_DIV>+1)
0ACLK_SELRW0x0ACLK source selection
- 1'b0: 249MHz
- 1'b1: 312MHz
+Offset: 0xD4282800+0x388 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:5 | RSVD | RO | 0x0 | Reserved | +| 4 | ACLK_FC_REQ | RW | 0x0 | ACLK frequency change request.- 1'b1: Enable ACLK Frequency Change. - The field is cleared by hardware once the frequency change is done. | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2:1 | ACLK_DIV | RW | 0x0 | ACLK_DIVACLK=/(+1) | +| 0 | ACLK_SEL | RW | 0x0 | ACLK source selection - 1'b0: 249MHz- 1'b1: 312MHz | ##### AP CPU CLUSTER0 CLK CONTROL REGISTER (PMUA_CPU_C0_CLK_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x38C
BitsFieldTypeResetDescription
31:14RSVDRO0x0Reserved
13C0_HI_CLK_SELRW0x0CPU cluster0 highest Clock Frequecny Selection.
It controls the selection of the highest clock frequency from CPU Cluster 0 based on the configuration of PLL3
- 1'b0: PLL3_div2(1600MHz) if PLL3 VCO is 3200M
- 1'b1: PLL3_div1(1600MHz) if PLL3 VCO is 1600M
12C0_CLK_FC_REQRW0x0CPU cluster0 clk frequency change request.
- 1'b1: Enable clock frequency change.
- The field is cleared by hardware once the frequency change is done.
11:9C0_TCM_AXI_DIVRW0x1Clock Divider Selection for Cluster0 TCM AXI slave Clock.
Formula:
C0_TCM_AXI = C0_CORE_CLK / (this field +1)
8:6C0_ACE_CLK_DIVRW0x1Clock Divider Selection for Cluster0 ACE Interface Clock
Formula:
C0_ACE_CLK = C0_CORE_CLK / (this field +1)
5:3C0_CORE_CLK_DIVRW0x0Clock Divider Selection for C0_CORE_CLK
Formula:
C0_CORE_CLK = Clock Selection / (this field +1)
2:0C0_CLK_SELRW0x0CPU Cluster0 Clock Selection
- 3'b000: 614MHz
- 3'b001: 819MHz
- 3'b010: 409MHz
- 3'b011: 491MHz
- 3'b100: 1228MHz
- 3'b101: PLL3_div3(1066MHz)
- 3'b110: PLL2_div3_gated(1000MHz)
- 3'b111: depends on bit[13]
1. 1'b0: PLL3_div2(1600MHz)
2. 1'b1: PLL3_div1(1600MHz)
+Offset: 0xD4282800+0x38C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:14 | RSVD | RO | 0x0 | Reserved | +| 13 | C0_HI_CLK_SEL | RW | 0x0 | CPU cluster0 highest Clock Frequency Selection.It controls the selection of the highest clock frequency from CPU Cluster 0 based on the configuration of PLL3- 1'b0: PLL3_div2(1600MHz) if PLL3 VCO is 3200M - 1'b1: PLL3_div1(1600MHz) if PLL3 VCO is 1600M | +| 12 | C0_CLK_FC_REQ | RW | 0x0 | CPU cluster0 clk frequency change request.- 1'b1: Enable clock frequency change. - The field is cleared by hardware once the frequency change is done. | +| 11:9 | C0_TCM_AXI_DIV | RW | 0x1 | Clock Divider Selection for Cluster0 TCM AXI slave Clock. Formula:C0_TCM_AXI = C0_CORE_CLK / (this field +1) | +| 8:6 | C0_ACE_CLK_DIV | RW | 0x1 | Clock Divider Selection for Cluster0 ACE Interface Clock Formula:C0_ACE_CLK = C0_CORE_CLK / (this field +1) | +| 5:3 | C0_CORE_CLK_DIV | RW | 0x0 | Clock Divider Selection for C0_CORE_CLKFormula: C0_CORE_CLK = Clock Selection / (this field +1) | +| 2:0 | C0_CLK_SEL | RW | 0x0 | CPU Cluster0 Clock Selection- 3'b000: 614MHz- 3'b001: 819MHz- 3'b010: 409MHz- 3'b011: 491MHz- 3'b100: 1228MHz- 3'b101: PLL3_div3(1066MHz)- 3'b110: PLL2_div3_gated(1000MHz)- 3'b111: depends on bit[13] 1. 1'b0: PLL3_div2(1600MHz) 2. 1'b1: PLL3_div1(1600MHz) | ##### AP CPU CLUSTER1 CLK CONTROL REGISTER (PMUA_CPU_C1_CLK_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x390
BitsFieldTypeResetDescription
31:14RSVDRO0x0Reserved
13C1_HI_CLK_SELRW0x0CPU cluster1 highest Clock frequecny selection.
It controls the selection of the highest clock frequency from CPU Cluster 1 based on the configuration of PLL3
- 1'b0: PLL3_div2(1600MHz) if PLL3 VCO is 3200M
- 1'b1: PLL3_div1(1600MHz) if PLL3 VCO is 1600M
12C1_CLK_FC_REQRW0x0CPU cluster1 Clock frequency change request.
- 1'b1: Enable clock frequency change.
- The field is cleared by hardware once the frequency change is done.
11:9C1_TCM_AXI_DIVRW0x1Clock Divider Selection for Cluster0 TCM AXI slave Clock.
Formula:
C1_TCM_AXI = C1_CORE_CLK / (this field +1)
8:6C1_ACE_CLK_DIVRW0x1Clock Divider Selection for Cluster1 ACE Interface Clock
Formula:
C1_ACE_CLK = C1_CORE_CLK / (this field +1)
5:3C1_CORE_CLK_DIVRW0x0Clock Divider Selection for C1_CORE_CLK
Formula:
C1_CORE_CLK = Clock Selection / (this field +1)
2:0C1_CLK_SELRW0x0CPU cluster1 clock selection
- 3'b000: 614MHz
- 3'b001: 819MHz
- 3'b010: 409MHz
- 3'b011: 491MHz
- 3'b100: 1228MHz
- 3'b101: PLL3_div3(1066MHz)
- 3'b110: PLL2_div3_gated(1000MHz)
- 3'b111: depends on bit[13]
1. 1'b0: PLL3_div2(1600MHz)
2. 1'b1: PLL3_div1(1600MHz)
+Offset: 0xD4282800+0x390 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:14 | RSVD | RO | 0x0 | Reserved | +| 13 | C1_HI_CLK_SEL | RW | 0x0 | CPU cluster1 highest Clock frequency selection.It controls the selection of the highest clock frequency from CPU Cluster 1 based on the configuration of PLL3- 1'b0: PLL3_div2(1600MHz) if PLL3 VCO is 3200M - 1'b1: PLL3_div1(1600MHz) if PLL3 VCO is 1600M | +| 12 | C1_CLK_FC_REQ | RW | 0x0 | CPU cluster1 Clock frequency change request.- 1'b1: Enable clock frequency change. - The field is cleared by hardware once the frequency change is done. | +| 11:9 | C1_TCM_AXI_DIV | RW | 0x1 | Clock Divider Selection for Cluster0 TCM AXI slave Clock. Formula:C1_TCM_AXI = C1_CORE_CLK / (this field +1) | +| 8:6 | C1_ACE_CLK_DIV | RW | 0x1 | Clock Divider Selection for Cluster1 ACE Interface Clock Formula:C1_ACE_CLK = C1_CORE_CLK / (this field +1) | +| 5:3 | C1_CORE_CLK_DIV | RW | 0x0 | Clock Divider Selection for C1_CORE_CLKFormula: C1_CORE_CLK = Clock Selection / (this field +1) | +| 2:0 | C1_CLK_SEL | RW | 0x0 | CPU cluster1 clock selection- 3'b000: 614MHz- 3'b001: 819MHz- 3'b010: 409MHz- 3'b011: 491MHz- 3'b100: 1228MHz- 3'b101: PLL3_div3(1066MHz)- 3'b110: PLL2_div3_gated(1000MHz)- 3'b111: depends on bit[13] 1. 1'b0: PLL3_div2(1600MHz) 2. 1'b1: PLL3_div1(1600MHz) | ##### PCIE PORTA CLK RESET CONTROL REGISTER (PCIE_CLK_RES_CTRL_PORTA) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3CC
BitsFieldTypeResetDescription
31PCIE_DEVICE_TYPE_SELRW0x0PCIe mode selection:
- 1'b0: EP
- 1'b1: RC
30PCIE_APP_HOLD_PHY_RSTRW0x1Set this signal to 1 before the de-assertion of power-on reset sequence to hold the PHY in reset. This can be used for PHY configuration.
29PCIE_APP_SRIS_MODERW0x0Used to enable or disable SRIS mode for PCIe controller
28:24PCIE_APP_DEV_NUMRW0x0Device number for RC mode
23:16PCIE_APP_BUS_NUMRW0x0Bus number for RC mode
15PCIE_APPS_PM_XMT_PMERW0x0Wake Up.
Used to wake the PCIe controller from low-power states (L1/L2) and restore active operation.
- When the PME is enabled and configured in the PMCSR, asserting this signal wakes the controller from L1 or L2 states; once the controller transitions back to the L0 state, it sends a PME message and sets the PME_Status. The root complex then clears PME_Status and changes the D-state back to D0.
14PCIE_APP_DBI_RO_WR_DISABLERW0x0DBI Read-only Write Disabled
Controls the write access behavior of the DBI_RO_WR_EN register field.
- 1'b0: MISC_CONTROL_1_OFF
1. DBI_RO_WR_EN register field is read-write.
- 1'b1: MISC_CONTROL_1_OFF
1. DBI_RO_WR_EN register field is forced to 0 and is read-only.
13PCIE_EP_WAKE_SWRW0x0In EP mode, SE can program this bit to 1 to drive WAKE# to low.
This is a wakeup event for RC side
12PCIE_RC_PERSTRW0x0In RC mode, SW can program this bit to 1 to drive PERST# to low.
This is a WARM reset for EP side
11PCIE_PORTA_CLKREQ_OERW0x0If this bit is set to 1, the chip drives the CLKREQ# signal for PortA to 0
10PCIE_PORTA_CLKREQ_INRO0x1Show the value of portA CLKREQ# IO input value
9PCIE_SYS_AUX_PWR_DETRW0x1Auxiliary Power Detected
Used to report to the host software that auxiliary power (Vaux) is present
8PCIE_GLB_RSTRW0x1Global reset.
Software (SW) must clear this bit to 0 while simultaneously asserting the following reset signals:
- pcie_axi_dbi_resetn
- pcie_axi_slv_resetn
- pcie_axi_mstr_resetn
> Note. This reset signal is high-level-valid
7PCIE_PERSTN_INRO0x1PERST value form PAD for EP mode
6PCIE_LTSSM_ENRW0x0Enable the PCIe controller to start training
- 1'b1: Enable
- 1'b0: Hold the LTSSM in detect state.
5PCIE_AXI_MSTR_RESETNRW0x0PCIe AXI data master port reset-n.
- 1'b1: Non-Reset
- 1'b0: Reset
4PCIE_AXI_SLV_RESETNRW0x0PCIe AXI data slave port reset-n
- 1'b1: Non-Reset
- 1'b0: Reset
3PCIE_AXI_DBI_RESETNRW0x0PCIe AXI DBI slave port reset-n
- 1'b1: Non-Reset
- 1'b0: Reset
2PCIE_AXI_MSTR_CLK_ENRW0x0PCIe AXI data master port clock enable
- 1'b1: Enable
- 1’b0: Disable
1PCIE_AXI_SLV_CLK_ENRW0x0PCIe AXI data slave port clock enable
- 1'b1: Enable
- 1’b0: Disable
0PCIE_AXI_DBI_CLK_ENRW0x0PCIe AXI DBI slave port clock enable
- 1'b1: Enable
- 1’b0: Disable
+Offset: 0xD4282800+0x3CC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | PCIE_DEVICE_TYPE_SEL | RW | 0x0 | PCIe mode selection: - 1'b0: EP - 1'b1: RC | +| 30 | PCIE_APP_HOLD_PHY_RST | RW | 0x1 | Set this signal to 1 before the de-assertion of power-on reset sequence to hold the PHY in reset. This can be used for PHY configuration. | +| 29 | PCIE_APP_SRIS_MODE | RW | 0x0 | Used to enable or disable SRIS mode for PCIe controller | +| 28:24 | PCIE_APP_DEV_NUM | RW | 0x0 | Device number for RC mode | +| 23:16 | PCIE_APP_BUS_NUM | RW | 0x0 | Bus number for RC mode | +| 15 | PCIE_APPS_PM_XMT_PME | RW | 0x0 | Wake Up. Used to wake the PCIe controller from low-power states (L1/L2) and restore active operation. - When the PME is enabled and configured in the PMCSR, asserting this signal wakes the controller from L1 or L2 states; once the controller transitions back to the L0 state, it sends a PME message and sets the PME_Status. The root complex then clears PME_Status and changes the D-state back to D0. | +| 14 | PCIE_APP_DBI_RO_WR_DISABLE | RW | 0x0 | DBI Read-only Write DisabledControls the write access behavior of the DBI_RO_WR_EN register field.- 1'b0: MISC_CONTROL_1_OFF 1. DBI_RO_WR_EN register field is read-write. - 1'b1: MISC_CONTROL_1_OFF 1. DBI_RO_WR_EN register field is forced to 0 and is read-only. | +| 13 | PCIE_EP_WAKE_SW | RW | 0x0 | In EP mode, SE can program this bit to 1 to drive WAKE# to low. This is a wakeup event for RC side | +| 12 | PCIE_RC_PERST | RW | 0x0 | In RC mode, SW can program this bit to 1 to drive PERST# to low. This is a WARM reset for EP side | +| 11 | PCIE_PORTA_CLKREQ_OE | RW | 0x0 | If this bit is set to 1, the chip drives the CLKREQ# signal for PortA to 0 | +| 10 | PCIE_PORTA_CLKREQ_IN | RO | 0x1 | Show the value of portA CLKREQ# IO input value | +| 9 | PCIE_SYS_AUX_PWR_DET | RW | 0x1 | Auxiliary Power DetectedUsed to report to the host software that auxiliary power (Vaux) is present | +| 8 | PCIE_GLB_RST | RW | 0x1 | Global reset.Software (SW) must clear this bit to 0 while simultaneously asserting the following reset signals:- pcie_axi_dbi_resetn- pcie_axi_slv_resetn- pcie_axi_mstr_resetn> Note. This reset signal is high-level-valid | +| 7 | PCIE_PERSTN_IN | RO | 0x1 | PERST value form PAD for EP mode | +| 6 | PCIE_LTSSM_EN | RW | 0x0 | Enable the PCIe controller to start training - 1'b1: Enable- 1'b0: Hold the LTSSM in detect state. | +| 5 | PCIE_AXI_MSTR_RESETN | RW | 0x0 | PCIe AXI data master port reset-n.- 1'b1: Non-Reset- 1'b0: Reset | +| 4 | PCIE_AXI_SLV_RESETN | RW | 0x0 | PCIe AXI data slave port reset-n- 1'b1: Non-Reset- 1'b0: Reset | +| 3 | PCIE_AXI_DBI_RESETN | RW | 0x0 | PCIe AXI DBI slave port reset-n- 1'b1: Non-Reset- 1'b0: Reset | +| 2 | PCIE_AXI_MSTR_CLK_EN | RW | 0x0 | PCIe AXI data master port clock enable- 1'b1: Enable- 1’b0: Disable | +| 1 | PCIE_AXI_SLV_CLK_EN | RW | 0x0 | PCIe AXI data slave port clock enable - 1'b1: Enable- 1’b0: Disable | +| 0 | PCIE_AXI_DBI_CLK_EN | RW | 0x0 | PCIe AXI DBI slave port clock enable- 1'b1: Enable- 1’b0: Disable | ##### PCIE PORTA CONTROL LOGIC REGISTER (PCIE_CTRL_LOGIC_PORTA) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3D0
BitsFieldTypeResetDescription
31:22RSVDRO0x0Reserved
21:20
PCIE_RC_WAKEN_DEB_CFGRW0x3Used to configure the debounce settings for the PCIe Root Complex (RC) WAKE_N signal
19:18PCIE_PERSTN_IN_DEB_CFGRW0x3Used to configure the debounce settings for the PCIe PERST# input signal
17:16PCIE_RXELECIDLE_DEB_CFGRW0x3Used to configure the debounce settings for the PCIe RX Electrical Idle signal
15PCIE_WAKEUP_INT_ENRW0x0Used to enable the PCIe wake-up interrupt
14PCIE_WAKEUP_ENRW0x0Used to enable the wake-up functionality of the PCIe device itself
13:11PCIE_WAKEUP_INT_REGRO0x0Used to indicate the PCIe wakeup interrupt status:
- bit 13: PCIe RC wakeup event
- bit 12: PCIe EP perstn wakeup event
- bit 11: PCIe RX Electrical Idle wakeup event
10:8PCIE_WAKEUP_INT_CLRRW0x0Used to clear the wake-up interrupt status bits for various PCIe wake-up events
- bit 10: PCIe RC wakeup event
- bit 9: PCIe EP perstn wakeup event
- bit 8: PCIe RX Electrical Idle wakeup event
7RSVDRO0x0Reserved
6:4PCIE_WAKEUP_MASKRW0x0PCIe wakeup interrupt mask
1'b1: Enable
- bit 6: PCIe RC wakeup event
- bit 5: PCIe EP perstn wakeup event
- bit 4: PCIe RX Electrical Idle wakeup event
3PCIE_WAKE_SOURCE_SELRW0x0Wake# Source Selection in EP mode
- 1'b1: the WAKE# pad is driven by pcie_ep_wake_sw bit of PCIe CLK Reset Control Register
- 1'b0: the WAKE# pad is driven by PCIe controller
2PCIE_IGNORE_PERSTNRW0x0Used to control whether the PCIe controller and PHY in EP mode respond to the PERSTN signal from the RC.
- When this bit is set to 1, The PCIe controller and PHY ignore the PERSTN signal from the RC
1PCIE_FORCE_PERSTNRW0x0In EP mode, SW can set this bit to 1 to force the PERST# signal to be asserted
0PCIE_SOFT_RESETRW0x0PCIe soft reset
- 1'b1: Reset
- 1'b0: Non-Reset
+Offset: 0xD4282800+0x3D0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:22 | RSVD | RO | 0x0 | Reserved | +| 21:20 | PCIE_RC_WAKEN_DEB_CFG | RW | 0x3 | Used to configure the debounce settings for the PCIe Root Complex (RC) WAKE_N signal | +| 19:18 | PCIE_PERSTN_IN_DEB_CFG | RW | 0x3 | Used to configure the debounce settings for the PCIe PERST# input signal | +| 17:16 | PCIE_RXELECIDLE_DEB_CFG | RW | 0x3 | Used to configure the debounce settings for the PCIe RX Electrical Idle signal | +| 15 | PCIE_WAKEUP_INT_EN | RW | 0x0 | Used to enable the PCIe wake-up interrupt | +| 14 | PCIE_WAKEUP_EN | RW | 0x0 | Used to enable the wake-up functionality of the PCIe device itself | +| 13:11 | PCIE_WAKEUP_INT_REG | RO | 0x0 | Used to indicate the PCIe wakeup interrupt status:- bit 13: PCIe RC wakeup event - bit 12: PCIe EP perstn wakeup event - bit 11: PCIe RX Electrical Idle wakeup event | +| 10:8 | PCIE_WAKEUP_INT_CLR | RW | 0x0 | Used to clear the wake-up interrupt status bits for various PCIe wake-up events- bit 10: PCIe RC wakeup event- bit 9: PCIe EP perstn wakeup event - bit 8: PCIe RX Electrical Idle wakeup event | +| 7 | RSVD | RO | 0x0 | Reserved | +| 6:4 | PCIE_WAKEUP_MASK | RW | 0x0 | PCIe wakeup interrupt mask 1'b1: Enable- bit 6: PCIe RC wakeup event - bit 5: PCIe EP perstn wakeup event - bit 4: PCIe RX Electrical Idle wakeup event | +| 3 | PCIE_WAKE_SOURCE_SEL | RW | 0x0 | Wake# Source Selection in EP mode- 1'b1: the WAKE# pad is driven by pcie_ep_wake_sw bit of PCIe CLK Reset Control Register - 1'b0: the WAKE# pad is driven by PCIe controller | +| 2 | PCIE_IGNORE_PERSTN | RW | 0x0 | Used to control whether the PCIe controller and PHY in EP mode respond to the PERSTN signal from the RC.- When this bit is set to 1, The PCIe controller and PHY ignore the PERSTN signal from the RC | +| 1 | PCIE_FORCE_PERSTN | RW | 0x0 | In EP mode, SW can set this bit to 1 to force the PERST# signal to be asserted | +| 0 | PCIE_SOFT_RESET | RW | 0x0 | PCIe soft reset- 1'b1: Reset- 1'b0: Non-Reset | ##### PCIE PORTB CLK RESET CONTROL REGISTER (PCIE_CLK_RES_CTRL_PORTB) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3D4
BitsFieldTypeResetDescription
31PCIE_DEVICE_TYPE_SELRW0x0PCIe mode selection:
- 1'b0: EP
- 1'b1: RC
30PCIE_APP_HOLD_PHY_RSTRW0x1Set this signal to 1 before the de-assertion of power-on reset sequence to hold the PHY in reset. This can be used for PHY configuration.
29PCIE_APP_SRIS_MODERW0x0Used to enable or disable SRIS mode for PCIe controller
28:24PCIE_APP_DEV_NUMRW0x0Device number for RC mode
23:16PCIE_APP_BUS_NUMRW0x0Bus number for RC mode
15PCIE_APPS_PM_XMT_PMERW0x0Wake Up.
Used to wake the PCIe controller from low-power states (L1/L2) and restore active operation.
- When the PME is enabled and configured in the PMCSR, asserting this signal wakes the controller from L1 or L2 states; once the controller transitions back to the L0 state, it sends a PME message and sets the PME_Status. The root complex then clears PME_Status and changes the D-state back to D0.
14PCIE_APP_DBI_RO_WR_DISABLERW0x0DBI Read-only Write Disabled
Controls the write access behavior of the DBI_RO_WR_EN register field.
- 1'b0: MISC_CONTROL_1_OFF
1. DBI_RO_WR_EN register field is read-write.
- 1'b1: MISC_CONTROL_1_OFF
1. DBI_RO_WR_EN register field is forced to 0 and is read-only.
13PCIE_EP_WAKE_SWRW0x0In EP mode, SE can program this bit to 1 to drive WAKE# to low. This is a wakeup event for RC side
12PCIE_RC_PERSTRW0x0In RC mode, SW can program this bit to 1 to drive PERST# to low. This is a WARM reset for EP side
11PCIE_PORTB_CLKREQ_OERW0x0If this bit is set to 1, the chip drives the CLKREQ# signal for PortB to 0
10PCIE_PORTB_CLKREQ_INRO0x1Show the value of PortB CLKREQ# IO input value
9PCIE_SYS_AUX_PWR_DETRW0x1Auxiliary Power Detected
Used to report to the host software that auxiliary power (Vaux) is present
8PCIE_GLB_RSTRW0x1Global reset
Software (SW) must clear this bit to 0 while simultaneously asserting the following reset signals:
- pcie_axi_dbi_resetn
- pcie_axi_slv_resetn
- pcie_axi_mstr_resetn
> Note. This reset signal is high-level-valid
7PCIE_PERSTN_INRO0x1PERST value form PAD for EP mode
6PCIE_LTSSM_ENRW0x0Enable the PCIe controller to start training
- 1'b1: enable
- 1'b0: hold the ltssm in detect.
5PCIE_AXI_MSTR_RESETNRW0x0PCIe AXI data master port reset-n.
- 1'b1: Non-Reset
- 1'b0: Reset
4PCIE_AXI_SLV_RESETNRW0x0PCIe AXI data slave port reset-n
- 1'b1: Non-Reset
- 1'b0: Reset
3PCIE_AXI_DBI_RESETNRW0x0PCIe AXI DBI slave port resetn
- 1'b1: Non-Reset
- 1'b0: Reset
2PCIE_AXI_MSTR_CLK_ENRW0x0PCIe AXI data master port clock enable
- 1'b1: Enable
- 1’b0: Disable
1PCIE_AXI_SLV_CLK_ENRW0x0PCIe AXI data slave port clock enable
- 1'b1: Enable
- 1’b0: Disable
0PCIE_AXI_DBI_CLK_ENRW0x0PCIe AXI dbi slave port clock enable
- 1'b1: Enable
- 1’b0: Disable
+Offset: 0xD4282800+0x3D4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | PCIE_DEVICE_TYPE_SEL | RW | 0x0 | PCIe mode selection: - 1'b0: EP - 1'b1: RC | +| 30 | PCIE_APP_HOLD_PHY_RST | RW | 0x1 | Set this signal to 1 before the de-assertion of power-on reset sequence to hold the PHY in reset. This can be used for PHY configuration. | +| 29 | PCIE_APP_SRIS_MODE | RW | 0x0 | Used to enable or disable SRIS mode for PCIe controller | +| 28:24 | PCIE_APP_DEV_NUM | RW | 0x0 | Device number for RC mode | +| 23:16 | PCIE_APP_BUS_NUM | RW | 0x0 | Bus number for RC mode | +| 15 | PCIE_APPS_PM_XMT_PME | RW | 0x0 | Wake Up. Used to wake the PCIe controller from low-power states (L1/L2) and restore active operation. - When the PME is enabled and configured in the PMCSR, asserting this signal wakes the controller from L1 or L2 states; once the controller transitions back to the L0 state, it sends a PME message and sets the PME_Status. The root complex then clears PME_Status and changes the D-state back to D0. | +| 14 | PCIE_APP_DBI_RO_WR_DISABLE | RW | 0x0 | DBI Read-only Write DisabledControls the write access behavior of the DBI_RO_WR_EN register field.- 1'b0: MISC_CONTROL_1_OFF 1. DBI_RO_WR_EN register field is read-write. - 1'b1: MISC_CONTROL_1_OFF 1. DBI_RO_WR_EN register field is forced to 0 and is read-only. | +| 13 | PCIE_EP_WAKE_SW | RW | 0x0 | In EP mode, SE can program this bit to 1 to drive WAKE# to low. This is a wakeup event for RC side | +| 12 | PCIE_RC_PERST | RW | 0x0 | In RC mode, SW can program this bit to 1 to drive PERST# to low. This is a WARM reset for EP side | +| 11 | PCIE_PORTB_CLKREQ_OE | RW | 0x0 | If this bit is set to 1, the chip drives the CLKREQ# signal for PortB to 0 | +| 10 | PCIE_PORTB_CLKREQ_IN | RO | 0x1 | Show the value of PortB CLKREQ# IO input value | +| 9 | PCIE_SYS_AUX_PWR_DET | RW | 0x1 | Auxiliary Power DetectedUsed to report to the host software that auxiliary power (Vaux) is present | +| 8 | PCIE_GLB_RST | RW | 0x1 | Global resetSoftware (SW) must clear this bit to 0 while simultaneously asserting the following reset signals:- pcie_axi_dbi_resetn- pcie_axi_slv_resetn- pcie_axi_mstr_resetn> Note. This reset signal is high-level-valid | +| 7 | PCIE_PERSTN_IN | RO | 0x1 | PERST value form PAD for EP mode | +| 6 | PCIE_LTSSM_EN | RW | 0x0 | Enable the PCIe controller to start training - 1'b1: enable- 1'b0: hold the ltssm in detect. | +| 5 | PCIE_AXI_MSTR_RESETN | RW | 0x0 | PCIe AXI data master port reset-n.- 1'b1: Non-Reset- 1'b0: Reset | +| 4 | PCIE_AXI_SLV_RESETN | RW | 0x0 | PCIe AXI data slave port reset-n- 1'b1: Non-Reset- 1'b0: Reset | +| 3 | PCIE_AXI_DBI_RESETN | RW | 0x0 | PCIe AXI DBI slave port resetn- 1'b1: Non-Reset- 1'b0: Reset | +| 2 | PCIE_AXI_MSTR_CLK_EN | RW | 0x0 | PCIe AXI data master port clock enable- 1'b1: Enable- 1’b0: Disable | +| 1 | PCIE_AXI_SLV_CLK_EN | RW | 0x0 | PCIe AXI data slave port clock enable - 1'b1: Enable- 1’b0: Disable | +| 0 | PCIE_AXI_DBI_CLK_EN | RW | 0x0 | PCIe AXI dbi slave port clock enable- 1'b1: Enable- 1’b0: Disable | ##### PCIE PORTB CONTROL LOGIC REGISTER (PCIE_CTRL_LOGIC_PORTB) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3D8
BitsFieldTypeResetDescription
31:22RSVDRO0x0Reserved
21:20PCIE_RC_WAKEN_DEB_CFGRW0x3Used to configure the debounce settings for the PCIe Root Complex (RC) WAKE_N signal
19:18PCIE_PERSTN_IN_DEB_CFGRW0x3Used to configure the debounce settings for the PCIe PERST# input signal
17:16PCIE_RXELECIDLE_DEB_CFGRW0x3Used to configure the debounce settings for the PCIe RX Electrical Idle signal
15PCIE_WAKEUP_INT_ENRW0x0Used to enable the PCIe wake-up interrupt
14PCIE_WAKEUP_ENRW0x0Used to enable the wake-up functionality of the PCIe device itself
13:11PCIE_WAKEUP_INT_REGRO0x0Used to indicate the PCIe wakeup interrupt status:
- bit 13: PCIe RC wakeup event
- bit 12: PCIe EP perstn wakeup event
- bit 11: PCIe RX Electrical Idle wakeup event
10:8PCIE_WAKEUP_INT_CLRRW0x0Used to clear the wake-up interrupt status bits for various PCIe wake-up events
- bit 10: PCIe RC wakeup event
- bit 9: PCIe EP perstn wakeup event
- bit 8: PCIe RX Electrical Idle wakeup event
7RSVDRO0x0Reserved
6:4PCIE_WAKEUP_MASKRW0x0PCIe wakeup interrupt mask
1'b1: Enable
- bit 6: PCIe RC wakeup event
- bit 5: PCIe EP perstn wakeup event
- bit 4: PCIe RX Electrical Idle wakeup event
3PCIE_WAKE_SOURCE_SELRW0x0Wake# Source Selection in EP mode
- 1'b1: the WAKE# pad is driven by pcie_ep_wake_sw bit of PCIe CLK Reset Control Register
- 1'b0: the WAKE# pad is driven by PCIe controller
2PCIE_IGNORE_PERSTNRW0x0Used to control whether the PCIe controller and PHY in EP mode respond to the PERSTN signal from the RC.
- When this bit is set to 1, The PCIe controller and PHY ignore the PERSTN signal from the RC
1PCIE_FORCE_PERSTNRW0x0In EP mode, SW can set this bit to 1 to force the PERST# signal to be asserted
0PCIE_SOFT_RESETRW0x0PCIe soft reset
- 1' b1: Reset
- 1'b0: Non-Reset
+Offset: 0xD4282800+0x3D8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:22 | RSVD | RO | 0x0 | Reserved | +| 21:20 | PCIE_RC_WAKEN_DEB_CFG | RW | 0x3 | Used to configure the debounce settings for the PCIe Root Complex (RC) WAKE_N signal | +| 19:18 | PCIE_PERSTN_IN_DEB_CFG | RW | 0x3 | Used to configure the debounce settings for the PCIe PERST# input signal | +| 17:16 | PCIE_RXELECIDLE_DEB_CFG | RW | 0x3 | Used to configure the debounce settings for the PCIe RX Electrical Idle signal | +| 15 | PCIE_WAKEUP_INT_EN | RW | 0x0 | Used to enable the PCIe wake-up interrupt | +| 14 | PCIE_WAKEUP_EN | RW | 0x0 | Used to enable the wake-up functionality of the PCIe device itself | +| 13:11 | PCIE_WAKEUP_INT_REG | RO | 0x0 | Used to indicate the PCIe wakeup interrupt status:- bit 13: PCIe RC wakeup event - bit 12: PCIe EP perstn wakeup event - bit 11: PCIe RX Electrical Idle wakeup event | +| 10:8 | PCIE_WAKEUP_INT_CLR | RW | 0x0 | Used to clear the wake-up interrupt status bits for various PCIe wake-up events- bit 10: PCIe RC wakeup event- bit 9: PCIe EP perstn wakeup event - bit 8: PCIe RX Electrical Idle wakeup event | +| 7 | RSVD | RO | 0x0 | Reserved | +| 6:4 | PCIE_WAKEUP_MASK | RW | 0x0 | PCIe wakeup interrupt mask 1'b1: Enable- bit 6: PCIe RC wakeup event - bit 5: PCIe EP perstn wakeup event - bit 4: PCIe RX Electrical Idle wakeup event | +| 3 | PCIE_WAKE_SOURCE_SEL | RW | 0x0 | Wake# Source Selection in EP mode- 1'b1: the WAKE# pad is driven by pcie_ep_wake_sw bit of PCIe CLK Reset Control Register - 1'b0: the WAKE# pad is driven by PCIe controller | +| 2 | PCIE_IGNORE_PERSTN | RW | 0x0 | Used to control whether the PCIe controller and PHY in EP mode respond to the PERSTN signal from the RC.- When this bit is set to 1, The PCIe controller and PHY ignore the PERSTN signal from the RC | +| 1 | PCIE_FORCE_PERSTN | RW | 0x0 | In EP mode, SW can set this bit to 1 to force the PERST# signal to be asserted | +| 0 | PCIE_SOFT_RESET | RW | 0x0 | PCIe soft reset- 1' b1: Reset- 1'b0: Non-Reset | ##### PCIE PORTC CLK RESET CONTROL REGISTER (PCIE_CLK_RES_CTRL_PORTC) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3DC
BitsFieldTypeResetDescription
31PCIE_DEVICE_TYPE_SELRW0x0PCIe mode selection:
- 1'b0: EP
- 1'b1: RC
30PCIE_APP_HOLD_PHY_RSTRW0x1Set this signal to 1 before the de-assertion of power-on reset sequence to hold the PHY in reset. This can be used for PHY configuration.
29PCIE_APP_SRIS_MODERW0x0Used to enable or disable SRIS mode for PCIe controller
28:24PCIE_APP_DEV_NUMRW0x0Device number for RC mode
23:16PCIE_APP_BUS_NUMRW0x0Bus number for RC mode
15PCIE_APPS_PM_XMT_PMERW0x0Wake Up.
Used to wake the PCIe controller from low-power states (L1/L2) and restore active operation.
- When the PME is enabled and configured in the PMCSR, asserting this signal wakes the controller from L1 or L2 states; once the controller transitions back to the L0 state, it sends a PME message and sets the PME_Status. The root complex then clears PME_Status and changes the D-state back to D0.
14PCIE_APP_DBI_RO_WR_DISABLERW0x0DBI Read-only Write Disabled
Controls the write access behavior of the DBI_RO_WR_EN register field.
- 1'b0: MISC_CONTROL_1_OFF
1. DBI_RO_WR_EN register field is read-write.
- 1'b1: MISC_CONTROL_1_OFF
1. DBI_RO_WR_EN register field is forced to 0 and is read-only.
13PCIE_EP_WAKE_SWRW0x0In EP mode, SE can program this bit to 1 to drive WAKE# to low.
This is a wakeup event for RC side
12PCIE_RC_PERSTRW0x0In RC mode, SW can program this bit to 1 to drive PERST# to low.
This is a WARM reset for EP side
11PCIE_PORTC_CLKREQ_OERW0x0If this bit is set to 1, the chip drives the CLKREQ# signal for PortC to 0
10PCIE_PORTC_CLKREQ_INRO0x1Show the value of PortC CLKREQ# IO input value
9PCIE_SYS_AUX_PWR_DETRW0x1Auxiliary Power Detected
Used to report to the host software that auxiliary power (Vaux) is present
8PCIE_GLB_RSTRW0x1Global reset
Software (SW) must clear this bit to 0 while simultaneously asserting the following reset signals:
- pcie_axi_dbi_resetn
- pcie_axi_slv_resetn
- pcie_axi_mstr_resetn
> Note. This reset signal is high-level-valid
7PCIE_PERSTN_INRO0x1PERST value form PAD for EP mode
6PCIE_LTSSM_ENRW0x0Enable the PCIe controller to start training
- 1'b1: Enable
- 1'b0: Hold the LTSSM in detect state.
5PCIE_AXI_MSTR_RESETNRW0x0PCIe AXI data master port reset-n.
- 1'b1: Non-Reset
- 1'b0: Reset
4PCIE_AXI_SLV_RESETNRW0x0PCIe AXI data slave port reset-n
- 1'b1: Non-Reset
- 1'b0: Reset
3PCIE_AXI_DBI_RESETNRW0x0PCIe AXI DBI slave port reset-n
- 1'b1: Non-Reset
- 1'b0: Reset
2PCIE_AXI_MSTR_CLK_ENRW0x0PCIe AXI data master port clock enable
- 1'b1: Enable
- 1’b0: Disable
1PCIE_AXI_SLV_CLK_ENRW0x0PCIe AXI data slave port clock enable
- 1'b1: Enable
- 1’b0: Disable
0PCIE_AXI_DBI_CLK_ENRW0x0PCIe AXI DBI slave port clock enable
- 1'b1: Enable
- 1’b0: Disable
+Offset: 0xD4282800+0x3DC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | PCIE_DEVICE_TYPE_SEL | RW | 0x0 | PCIe mode selection: - 1'b0: EP - 1'b1: RC | +| 30 | PCIE_APP_HOLD_PHY_RST | RW | 0x1 | Set this signal to 1 before the de-assertion of power-on reset sequence to hold the PHY in reset. This can be used for PHY configuration. | +| 29 | PCIE_APP_SRIS_MODE | RW | 0x0 | Used to enable or disable SRIS mode for PCIe controller | +| 28:24 | PCIE_APP_DEV_NUM | RW | 0x0 | Device number for RC mode | +| 23:16 | PCIE_APP_BUS_NUM | RW | 0x0 | Bus number for RC mode | +| 15 | PCIE_APPS_PM_XMT_PME | RW | 0x0 | Wake Up. Used to wake the PCIe controller from low-power states (L1/L2) and restore active operation. - When the PME is enabled and configured in the PMCSR, asserting this signal wakes the controller from L1 or L2 states; once the controller transitions back to the L0 state, it sends a PME message and sets the PME_Status. The root complex then clears PME_Status and changes the D-state back to D0. | +| 14 | PCIE_APP_DBI_RO_WR_DISABLE | RW | 0x0 | DBI Read-only Write DisabledControls the write access behavior of the DBI_RO_WR_EN register field.- 1'b0: MISC_CONTROL_1_OFF 1. DBI_RO_WR_EN register field is read-write. - 1'b1: MISC_CONTROL_1_OFF 1. DBI_RO_WR_EN register field is forced to 0 and is read-only. | +| 13 | PCIE_EP_WAKE_SW | RW | 0x0 | In EP mode, SE can program this bit to 1 to drive WAKE# to low. This is a wakeup event for RC side | +| 12 | PCIE_RC_PERST | RW | 0x0 | In RC mode, SW can program this bit to 1 to drive PERST# to low. This is a WARM reset for EP side | +| 11 | PCIE_PORTC_CLKREQ_OE | RW | 0x0 | If this bit is set to 1, the chip drives the CLKREQ# signal for PortC to 0 | +| 10 | PCIE_PORTC_CLKREQ_IN | RO | 0x1 | Show the value of PortC CLKREQ# IO input value | +| 9 | PCIE_SYS_AUX_PWR_DET | RW | 0x1 | Auxiliary Power DetectedUsed to report to the host software that auxiliary power (Vaux) is present | +| 8 | PCIE_GLB_RST | RW | 0x1 | Global resetSoftware (SW) must clear this bit to 0 while simultaneously asserting the following reset signals:- pcie_axi_dbi_resetn- pcie_axi_slv_resetn- pcie_axi_mstr_resetn> Note. This reset signal is high-level-valid | +| 7 | PCIE_PERSTN_IN | RO | 0x1 | PERST value form PAD for EP mode | +| 6 | PCIE_LTSSM_EN | RW | 0x0 | Enable the PCIe controller to start training - 1'b1: Enable- 1'b0: Hold the LTSSM in detect state. | +| 5 | PCIE_AXI_MSTR_RESETN | RW | 0x0 | PCIe AXI data master port reset-n.- 1'b1: Non-Reset- 1'b0: Reset | +| 4 | PCIE_AXI_SLV_RESETN | RW | 0x0 | PCIe AXI data slave port reset-n- 1'b1: Non-Reset- 1'b0: Reset | +| 3 | PCIE_AXI_DBI_RESETN | RW | 0x0 | PCIe AXI DBI slave port reset-n- 1'b1: Non-Reset- 1'b0: Reset | +| 2 | PCIE_AXI_MSTR_CLK_EN | RW | 0x0 | PCIe AXI data master port clock enable- 1'b1: Enable- 1’b0: Disable | +| 1 | PCIE_AXI_SLV_CLK_EN | RW | 0x0 | PCIe AXI data slave port clock enable - 1'b1: Enable- 1’b0: Disable | +| 0 | PCIE_AXI_DBI_CLK_EN | RW | 0x0 | PCIe AXI DBI slave port clock enable- 1'b1: Enable- 1’b0: Disable | ##### PCIE PORTC CONTROL LOGIC REGISTER (PCIE_CTRL_LOGIC_PORTC) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3D8
BitsFieldTypeResetDescription
31:22RSVDRO0x0Reserved
21:20PCIE_RC_WAKEN_DEB_CFGRW0x3pcie_rc_waken debounce configuration
Used to configure the debounce settings for the PCIe Root Complex (RC) WAKE_N signal
19:18PCIE_PERSTN_IN_DEB_CFGRW0x3pcie_perstn_in debounce configuration
Used to configure the debounce settings for the PCIe PERST# input signal
17:16PCIE_RXELECIDLE_DEB_CFGRW0x3pcie_rxelecidle debounce configuration
Used to configure the debounce settings for the PCIe RX Electrical Idle signal
15PCIE_WAKEUP_INT_ENRW0x0PCIE wake up enable
Used to enable the PCIe wake-up interrupt
14PCIE_WAKEUP_ENRW0x0PCIE wake up event interrupt enable
Used to enable the wake-up functionality of the PCIe device itself
13:11PCIE_WAKEUP_INT_REGRO0x0Used to indicate the PCIe wakeup interrupt status:
- bit 13: PCIe RC wakeup event
- bit 12: PCIe EP perstn wakeup event
- bit 11: PCIe RX Electrical Idle wakeup event
10:8PCIE_WAKEUP_INT_CLRRW0x0Used to clear the wake-up interrupt status bits for various PCIe wake-up events
- bit 10: PCIe RC wakeup event
- bit 9: PCIe EP perstn wakeup event
- bit 8: PCIe RX Electrical Idle wakeup event
7RSVDRO0x0Reserved
6:4PCIE_WAKEUP_MASKRW0x0PCIe wakeup interrupt mask
1'b1: Enable
- bit 6: PCIe RC wakeup event
- bit 5: PCIe EP perstn wakeup event
- bit 4: PCIe RX Electrical Idle wakeup event
3PCIE_WAKE_SOURCE_SELRW0x0Wake# Source Selection in EP mode
- 1'b1: the WAKE# pad is driven by pcie_ep_wake_sw bit of PCIe CLK Reset Control Register
- 1'b0: the WAKE# pad is driven by PCIe controller
2PCIE_IGNORE_PERSTNRW0x0Used to control whether the PCIe controller and PHY in EP mode respond to the PERSTN signal from the RC.
- When this bit is set to 1, The PCIe controller and PHY ignore the PERSTN signal from the RC
1PCIE_FORCE_PERSTNRW0x0In EP mode, SW can set this bit to 1 to force the PERST# signal to be asserted
0PCIE_SOFT_RESETRW0x0PCIe soft reset
- 1'b1: Reset
- 1'b0: Non-Reset
+Offset: 0xD4282800+0x3D8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:22 | RSVD | RO | 0x0 | Reserved | +| 21:20 | PCIE_RC_WAKEN_DEB_CFG | RW | 0x3 | pcie_rc_waken debounce configuration Used to configure the debounce settings for the PCIe Root Complex (RC) WAKE_N signal | +| 19:18 | PCIE_PERSTN_IN_DEB_CFG | RW | 0x3 | pcie_perstn_in debounce configuration Used to configure the debounce settings for the PCIe PERST# input signal | +| 17:16 | PCIE_RXELECIDLE_DEB_CFG | RW | 0x3 | pcie_rxelecidle debounce configuration Used to configure the debounce settings for the PCIe RX Electrical Idle signal | +| 15 | PCIE_WAKEUP_INT_EN | RW | 0x0 | PCIE wake up enable Used to enable the PCIe wake-up interrupt | +| 14 | PCIE_WAKEUP_EN | RW | 0x0 | PCIE wake up event interrupt enable Used to enable the wake-up functionality of the PCIe device itself | +| 13:11 | PCIE_WAKEUP_INT_REG | RO | 0x0 | Used to indicate the PCIe wakeup interrupt status:- bit 13: PCIe RC wakeup event - bit 12: PCIe EP perstn wakeup event - bit 11: PCIe RX Electrical Idle wakeup event | +| 10:8 | PCIE_WAKEUP_INT_CLR | RW | 0x0 | Used to clear the wake-up interrupt status bits for various PCIe wake-up events- bit 10: PCIe RC wakeup event- bit 9: PCIe EP perstn wakeup event - bit 8: PCIe RX Electrical Idle wakeup event | +| 7 | RSVD | RO | 0x0 | Reserved | +| 6:4 | PCIE_WAKEUP_MASK | RW | 0x0 | PCIe wakeup interrupt mask 1'b1: Enable- bit 6: PCIe RC wakeup event - bit 5: PCIe EP perstn wakeup event - bit 4: PCIe RX Electrical Idle wakeup event | +| 3 | PCIE_WAKE_SOURCE_SEL | RW | 0x0 | Wake# Source Selection in EP mode- 1'b1: the WAKE# pad is driven by pcie_ep_wake_sw bit of PCIe CLK Reset Control Register - 1'b0: the WAKE# pad is driven by PCIe controller | +| 2 | PCIE_IGNORE_PERSTN | RW | 0x0 | Used to control whether the PCIe controller and PHY in EP mode respond to the PERSTN signal from the RC.- When this bit is set to 1, The PCIe controller and PHY ignore the PERSTN signal from the RC | +| 1 | PCIE_FORCE_PERSTN | RW | 0x0 | In EP mode, SW can set this bit to 1 to force the PERST# signal to be asserted | +| 0 | PCIE_SOFT_RESET | RW | 0x0 | PCIe soft reset- 1'b1: Reset- 1'b0: Non-Reset | ##### EMAC0_CLK_RST_CTRL REGISTER (EMAC0_CLK_RST_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3E4
BitsFieldTypeResetDescription
31:16RSVDRO0x0Reserved
15EMAC0_1588_CLK_ENRW0x0- 1'b1: EMAC0 1588 clock enable
- 1'b0: EMAC0 1588 clock disable
14EMAC0_CLK_REF_SELECTRW0x0- 1'b1: TX refclk Select 125MHz Clock
- 1'b0: TX refclk Select 25MHz Clock
13EMAC0_AXI_MST_IDRW0x0- 1'b1: EMAC0 AXI MST interface uses single ID to issue transfer
- 1'b0: EMAC0 AXI MST interface uses multiple IDs to issue transfer
12EMAC0_PHY_INTR_ENRW0x0- 1'b1: EMAC0 PHY interrupt enable
- 1'b0: EMAC0 PHY interrupt disable
11:9RSVDRO0x0Reserved
8EMAC0_RGMII_TXC_SRC_SELRW0x0This bit is only valid in RGMII mode. EMAC RGMII tx clock source selection.
- 1'b1: TX clock source from SoC
- 1'b0: TX clock source from RX clock
7:2RSVDRO0x0Reserved
1EMAC0_BUS_RSTRW0x0EMAC0 AXI Bus Reset
- 1'b1: Reset Release (deasserted)
- 1'b0: Reset
0EMAC0_BUS_ENRW0x0EMAC0 AXI Bus Clock Enable
- 1'b1: AXI clock enabled
- 1'b0: AXI clock disabled
+Offset: 0xD4282800+0x3E4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RSVD | RO | 0x0 | Reserved | +| 15 | EMAC0_1588_CLK_EN | RW | 0x0 | - 1'b1: EMAC0 1588 clock enable- 1'b0: EMAC0 1588 clock disable | +| 14 | EMAC0_CLK_REF_SELECT | RW | 0x0 | - 1'b1: TX refclk Select 125MHz Clock- 1'b0: TX refclk Select 25MHz Clock | +| 13 | EMAC0_AXI_MST_ID | RW | 0x0 | - 1'b1: EMAC0 AXI MST interface uses single ID to issue transfer- 1'b0: EMAC0 AXI MST interface uses multiple IDs to issue transfer | +| 12 | EMAC0_PHY_INTR_EN | RW | 0x0 | - 1'b1: EMAC0 PHY interrupt enable- 1'b0: EMAC0 PHY interrupt disable | +| 11:9 | RSVD | RO | 0x0 | Reserved | +| 8 | EMAC0_RGMII_TXC_SRC_SEL | RW | 0x0 | This bit is only valid in RGMII mode. EMAC RGMII tx clock source selection.- 1'b1: TX clock source from SoC- 1'b0: TX clock source from RX clock | +| 7:2 | RSVD | RO | 0x0 | Reserved | +| 1 | EMAC0_BUS_RST | RW | 0x0 | EMAC0 AXI Bus Reset- 1'b1: Reset Release (deasserted) - 1'b0: Reset | +| 0 | EMAC0_BUS_EN | RW | 0x0 | EMAC0 AXI Bus Clock Enable- 1'b1: AXI clock enabled- 1'b0: AXI clock disabled | ##### EMAC0_RGMII_DLINE REGISTER (EMAC0_RGMII_DLINE) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3E8
BitsFieldTypeResetDescription
31:24EMAC0_RGMII_TXC_DLINE_ADJRW0x0Delay code
23:17RSVDRO0x0Reserved
16EMAC0_RGMII_TXC_DLINE_PURW0x0Delay line enable
15:8EMAC0_RGMII_RXC_DLINE_ADJRW0x0Delay code
7:1RSVDRO0x0Reserved
0EMAC0_RGMII_RXC_DLINE_PURW0x0Delay line enable
+Offset: 0xD4282800+0x3E8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | EMAC0_RGMII_TXC_DLINE_ADJ | RW | 0x0 | Delay code | +| 23:17 | RSVD | RO | 0x0 | Reserved | +| 16 | EMAC0_RGMII_TXC_DLINE_PU | RW | 0x0 | Delay line enable | +| 15:8 | EMAC0_RGMII_RXC_DLINE_ADJ | RW | 0x0 | Delay code | +| 7:1 | RSVD | RO | 0x0 | Reserved | +| 0 | EMAC0_RGMII_RXC_DLINE_PU | RW | 0x0 | Delay line enable | ##### EMAC1_CLK_RST_CTRL REGISTER (EMAC1_CLK_RST_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3EC
BitsFieldTypeResetDescription
31:16RSVDRO0x0Reserved
15EMAC1_1588_CLK_ENRW0x0- 1'b1: EMAC1 1588 clock enable
- 1'b0: EMAC1 1588 clock disable
14EMAC1_CLK_REF_SELECTRW0x0- 1'b1: TX refclk Select 125MHz Clock
- 1'b0: TX refclk Select 25MHz Clock
13EMAC1_AXI_MST_IDRW0x0- 1'b1: EMAC1 AXI MST interface uses single ID to issue transfer
- 1'b0: EMAC1 AXI MST interface uses multiple IDs to issue transfer
12EMAC1_PHY_INTR_ENRW0x0- 1'b1: EMAC1 PHY interrupt enable
- 1'b0: EMAC1 PHY interrupt disable
11:9RSVDRO0x0Reserved
8EMAC1_RGMII_TXC_SRC_SELRW0x0This bit is only valid in RGMII mode. EMAC RGMII tx clock source selection.
- 1'b1: TX clock source from SoC
- 1'b0: TX clock source from RX clock
7:2RSVDRO0x0Reserved
1EMAC1_BUS_RSTRW0x0EMAC1 AXI Bus Reset
- 1'b1: Reset Release (deasserted)
- 1'b0: Reset
0EMAC1_BUS_ENRW0x0EMAC1 AXI Bus Clock Enable
- 1'b1: AXI clock enabled
- 1'b0: AXI clock disabled
+Offset: 0xD4282800+0x3EC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RSVD | RO | 0x0 | Reserved | +| 15 | EMAC1_1588_CLK_EN | RW | 0x0 | - 1'b1: EMAC1 1588 clock enable- 1'b0: EMAC1 1588 clock disable | +| 14 | EMAC1_CLK_REF_SELECT | RW | 0x0 | - 1'b1: TX refclk Select 125MHz Clock- 1'b0: TX refclk Select 25MHz Clock | +| 13 | EMAC1_AXI_MST_ID | RW | 0x0 | - 1'b1: EMAC1 AXI MST interface uses single ID to issue transfer- 1'b0: EMAC1 AXI MST interface uses multiple IDs to issue transfer | +| 12 | EMAC1_PHY_INTR_EN | RW | 0x0 | - 1'b1: EMAC1 PHY interrupt enable- 1'b0: EMAC1 PHY interrupt disable | +| 11:9 | RSVD | RO | 0x0 | Reserved | +| 8 | EMAC1_RGMII_TXC_SRC_SEL | RW | 0x0 | This bit is only valid in RGMII mode. EMAC RGMII tx clock source selection.- 1'b1: TX clock source from SoC- 1'b0: TX clock source from RX clock | +| 7:2 | RSVD | RO | 0x0 | Reserved | +| 1 | EMAC1_BUS_RST | RW | 0x0 | EMAC1 AXI Bus Reset- 1'b1: Reset Release (deasserted) - 1'b0: Reset | +| 0 | EMAC1_BUS_EN | RW | 0x0 | EMAC1 AXI Bus Clock Enable- 1'b1: AXI clock enabled- 1'b0: AXI clock disabled | ##### EMAC1_RGMII_DLINE REGISTER (EMAC1_RGMII_DLINE) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3E8
BitsFieldTypeResetDescription
31:24EMAC1_RGMII_TXC_DLINE_ADJRW0x0Delay code
23:17RSVDRO0x0Reserved
16EMAC1_RGMII_TXC_DLINE_PURW0x0Delay line enable
15:8EMAC1_RGMII_RXC_DLINE_ADJRW0x0Delay code
7:1RSVDRO0x0Reserved
0EMAC1_RGMII_RXC_DLINE_PURW0x0Delay line enable
+Offset: 0xD4282800+0x3E8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | EMAC1_RGMII_TXC_DLINE_ADJ | RW | 0x0 | Delay code | +| 23:17 | RSVD | RO | 0x0 | Reserved | +| 16 | EMAC1_RGMII_TXC_DLINE_PU | RW | 0x0 | Delay line enable | +| 15:8 | EMAC1_RGMII_RXC_DLINE_ADJ | RW | 0x0 | Delay code | +| 7:1 | RSVD | RO | 0x0 | Reserved | +| 0 | EMAC1_RGMII_RXC_DLINE_PU | RW | 0x0 | Delay line enable | #### Basing on \ @@ -4384,1291 +1083,276 @@ This register is used to trigger CPU CORE reset as follows: X=0/1/2/3/4/5/6/7/8/9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x0/0x4/0x24/0x70/0x74/0x78/0x94/0x98/0x9C
BitsFieldTypeResetDescription
31:7RSVDRO0x0Reserved
6:4FNCLKSELRW0x0Functional Clock Select
- 3'b000: 57.6 MHz
- 3'b001: 14.7456 MHz
- 3'b010: 48 MHz
- 3'b011: UART_LP
- All other values: Reserved, do not use
3RSVDRO0x0Reserved
2RSTRW0x1UART Reset Generation.
This field resets both APB and Functional domains.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0UART Functional Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0UART APB Bus Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xD4015000+0x0/0x4/0x24/0x70/0x74/0x78/0x94/0x98/0x9C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0x0 | Reserved | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 3'b000: 57.6 MHz- 3'b001: 14.7456 MHz- 3'b010: 48 MHz- 3'b011: UART_LP- All other values: Reserved, do not use | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | UART Reset Generation.This field resets both APB and Functional domains. - 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | UART Functional Clock Enable/Disable.- 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | UART APB Bus Clock Enable/Disable.- 1'b0: Clock gating- 1'b1: Clock on | ##### GPIO CLOCK RESET CONTROL REGISTER (APBC_GPIO_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x8
BitsFieldTypeResetDescription
31:3RSVDRO0x0Reserved
2RSTRW0x1UART Reset Generation.
This field resets both APB and Functional domains.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0GPIO Functional Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0GPIO APB Bus Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xD4015000+0x8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | UART Reset Generation.This field resets both APB and Functional domains. - 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | GPIO Functional Clock Enable/Disable.- 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | GPIO APB Bus Clock Enable/Disable.- 1'b0: Clock gating- 1'b1: Clock on | ##### PWMX CLOCK RESET CONTROL REGISTER (APBC_PWMX_CLK_RST) X=0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16/17/18/19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0xC/0x10/0x14/0x18/0xA8/0xAC/0xB0/0xB4/0xB8/0xBC/0xC0/0xC4/0xC8/0xCC/0xD0/0xD4/0xD8/0xDC/0xE0/0xE4
BitsFieldTypeResetDescription
31:7RSVDRO0x0Reserved
6:4FNCLKSELRW0x0Functional Clock Select
- 3'b000: 12.8 MHz
- 3'b001: 32 KHz
- All other values: Reserved, do not use
3RSVDRO0x0Reserved
2RSTRW0x1PWMX Reset Generation.
This field resets both APB and Functional domains.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0PWMX Functional Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0PWMX APB Bus Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xD4015000+0xC/0x10/0x14/0x18/0xA8/0xAC/0xB0/0xB4/0xB8/0xBC/0xC0/0xC4/0xC8/0xCC/0xD0/0xD4/0xD8/0xDC/0xE0/0xE4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0x0 | Reserved | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select- 3'b000: 12.8 MHz- 3'b001: 32 KHz- All other values: Reserved, do not use | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | PWMX Reset Generation.This field resets both APB and Functional domains. - 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | PWMX Functional Clock Enable/Disable.- 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | PWMX APB Bus Clock Enable/Disable.- 1'b0: Clock gating- 1'b1: Clock on | ##### SSPX CLOCK RESET CONTROL REGISTER (APBC_SSPX_CLK_RST) X=3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x7C
BitsFieldTypeResetDescription
31:8RSVDRO0x0Reserved
7SEL_SSP_FUNC_CLKRW0x0AC97 Clock Switch
This bit enables the SSP module to switch clocks internally.
6:4FNCLKSELRW0x0Functional Clock Select
- 3'b000: 6.4 MHz
- 3'b001: 12.8 MHz
- 3'b010: 25.6 MHz
- 3'b011: 51.2 MHz
- 3'b100: 3.2 MHz
- 3'b101: 1.6 MHz
- 3'b110: 800 kHz
- All other values: Reserved, do not use
3RSVDRO0x0Reserved
2RSTRW0x1SSP 3 Reset Generation
This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0SSP 3 Functional Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0SSP 3 APB Bus Clock Enable/Disable
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xD4015000+0x7C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | RSVD | RO | 0x0 | Reserved | +| 7 | SEL_SSP_FUNC_CLK | RW | 0x0 | AC97 Clock Switch This bit enables the SSP module to switch clocks internally. | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 3'b000: 6.4 MHz- 3'b001: 12.8 MHz- 3'b010: 25.6 MHz- 3'b011: 51.2 MHz- 3'b100: 3.2 MHz- 3'b101: 1.6 MHz- 3'b110: 800 kHz- All other values: Reserved, do not use | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | SSP 3 Reset GenerationThis field resets both the APB and functional domain.- 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | SSP 3 Functional Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | SSP 3 APB Bus Clock Enable/Disable - 1'b0: Clock gating- 1'b1: Clock on | ##### RTC CLOCK RESET CONTROL REGISTER (APBC_RTC_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x28
BitsFieldTypeResetDescription
31:8RSVDRO0x0Reserved
7PM_POWER_SENSORRW0x0Power Enabled.
This field enables the register read/write for the RTC module by indicating power is enabled.
Set this field to 0x1 before enabling RTC operations.
6:4FNCLKSELRW0x0Functional Clock Select.
- 3'b000: 32 KHz
- All other values: Reserved, do not use
3RSVDRO0x0Reserved
2RSTRW0x1RTC Reset Generation
This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0RTC Functional Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0RTC APB Bus Clock Enable/Disable
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xD4015000+0x28 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | RSVD | RO | 0x0 | Reserved | +| 7 | PM_POWER_SENSOR | RW | 0x0 | Power Enabled. This field enables the register read/write for the RTC module by indicating power is enabled. Set this field to 0x1 before enabling RTC operations. | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select.- 3'b000: 32 KHz - All other values: Reserved, do not use | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | RTC Reset GenerationThis field resets both the APB and functional domain.- 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | RTC Functional Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | RTC APB Bus Clock Enable/Disable - 1'b0: Clock gating- 1'b1: Clock on | ##### TWSI0 CLOCK RESET CONTROL REGISTER (APBC_TWSI0_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x2C
BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select
- 0x0: 31.5 MHz
- 0x1: 51.2 MHz
- 0x2: 61.44 MHz
- All other values: Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1TWSI0 Reset Generation
This field resets both the APB and functional domain.
- 0: No Reset
- 1: Reset
1FNCLKRW0x0TWSI0 Functional Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
0APBCLKRW0x0TWSI0 APB Bus Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
+Offset: 0xD4015000+0x2C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0 | Reserved for future use | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 0x0: 31.5 MHz - 0x1: 51.2 MHz - 0x2: 61.44 MHz - All other values: Reserved, do not use | +| 3 | RSVD | RO | 0 | Reserved for future use | +| 2 | RST | RW | 0x1 | TWSI0 Reset Generation This field resets both the APB and functional domain. - 0: No Reset - 1: Reset | +| 1 | FNCLK | RW | 0x0 | TWSI0 Functional Clock Enable/Disable. - 0: Clock off - 1: Clock on | +| 0 | APBCLK | RW | 0x0 | TWSI0 APB Bus Clock Enable/Disable. - 0: Clock off - 1: Clock on | ##### TWSI1 CLOCK RESET CONTROL REGISTER (APBC_TWSI1_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x30
BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select
- 0x0: 31.5 MHz
- 0x1: 51.2 MHz
- 0x2: 61.44 MHz
- All other values: Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1TWSI1 Reset Generation
This field resets both the APB and functional domain.
- 0: No Reset
- 1: Reset
1FNCLKRW0x0TWSI1 Functional Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
0APBCLKRW0x0TWSI1 APB Bus Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
+Offset: 0xD4015000+0x30 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0 | Reserved for future use | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 0x0: 31.5 MHz - 0x1: 51.2 MHz - 0x2: 61.44 MHz - All other values: Reserved, do not use | +| 3 | RSVD | RO | 0 | Reserved for future use | +| 2 | RST | RW | 0x1 | TWSI1 Reset Generation This field resets both the APB and functional domain. - 0: No Reset - 1: Reset | +| 1 | FNCLK | RW | 0x0 | TWSI1 Functional Clock Enable/Disable. - 0: Clock off - 1: Clock on | +| 0 | APBCLK | RW | 0x0 | TWSI1 APB Bus Clock Enable/Disable. - 0: Clock off - 1: Clock on | ##### TWSI2 CLOCK RESET CONTROL REGISTER (APBC_TWSI2_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x38
BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select
- 0x0: 31.5 MHz
- 0x1: 51.2 MHz
- 0x2: 61.44 MHz
- All other values: Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1TWSI2 Reset Generation
This field resets both the APB and functional domain.
- 0: No Reset
- 1: Reset
1FNCLKRW0x0TWSI2 Functional Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
0APBCLKRW0x0TWSI2 APB Bus Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
+Offset: 0xD4015000+0x38 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0 | Reserved for future use | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 0x0: 31.5 MHz - 0x1: 51.2 MHz - 0x2: 61.44 MHz - All other values: Reserved, do not use | +| 3 | RSVD | RO | 0 | Reserved for future use | +| 2 | RST | RW | 0x1 | TWSI2 Reset Generation This field resets both the APB and functional domain. - 0: No Reset - 1: Reset | +| 1 | FNCLK | RW | 0x0 | TWSI2 Functional Clock Enable/Disable. - 0: Clock off - 1: Clock on | +| 0 | APBCLK | RW | 0x0 | TWSI2 APB Bus Clock Enable/Disable. - 0: Clock off - 1: Clock on | ##### TWSI4 CLOCK RESET CONTROL REGISTER (APBC_TWSI4_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x40
BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select
- 0x0: 31.5 MHz
- 0x1: 51.2 MHz
- 0x2: 61.44 MHz
- All other values: Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1TWSI4 Reset Generation
This field resets both the APB and functional domain.
- 0: No Reset
- 1: Reset
1FNCLKRW0x0TWSI4 Functional Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
0APBCLKRW0x0TWSI4 APB Bus Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
+Offset: 0xD4015000+0x40 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0 | Reserved for future use | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 0x0: 31.5 MHz - 0x1: 51.2 MHz - 0x2: 61.44 MHz - All other values: Reserved, do not use | +| 3 | RSVD | RO | 0 | Reserved for future use | +| 2 | RST | RW | 0x1 | TWSI4 Reset Generation This field resets both the APB and functional domain. - 0: No Reset - 1: Reset | +| 1 | FNCLK | RW | 0x0 | TWSI4 Functional Clock Enable/Disable. - 0: Clock off - 1: Clock on | +| 0 | APBCLK | RW | 0x0 | TWSI4 APB Bus Clock Enable/Disable. - 0: Clock off - 1: Clock on | ##### TWSI5 CLOCK RESET CONTROL REGISTER (APBC_TWSI5_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x4C
BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select
- 0x0: 31.5 MHz
- 0x1: 51.2 MHz
- 0x2: 61.44 MHz
- All other values: Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1TWSI5 Reset Generation
This field resets both the APB and functional domain.
- 0: No Reset
- 1: Reset
1FNCLKRW0x0TWSI5 Functional Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
0APBCLKRW0x0TWSI5 APB Bus Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
+Offset: 0xD4015000+0x4C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0 | Reserved for future use | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 0x0: 31.5 MHz - 0x1: 51.2 MHz - 0x2: 61.44 MHz - All other values: Reserved, do not use | +| 3 | RSVD | RO | 0 | Reserved for future use | +| 2 | RST | RW | 0x1 | TWSI5 Reset Generation This field resets both the APB and functional domain. - 0: No Reset - 1: Reset | +| 1 | FNCLK | RW | 0x0 | TWSI5 Functional Clock Enable/Disable. - 0: Clock off - 1: Clock on | +| 0 | APBCLK | RW | 0x0 | TWSI5 APB Bus Clock Enable/Disable. - 0: Clock off - 1: Clock on | ##### TWSI6 CLOCK RESET CONTROL REGISTER (APBC_TWSI6_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x60
BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSEL
RW0x0Functional Clock Select
- 0x0: 31.5 MHz
- 0x1: 51.2 MHz
- 0x2: 61.44 MHz
- All other values: Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1TWSI6 Reset Generation
This field resets both the APB and functional domain.
- 0: No Reset
- 1: Reset
1FNCLKRW0x0TWSI6 Functional Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
0APBCLKRW0x0TWSI6 APB Bus Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
+Offset: 0xD4015000+0x60 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0 | Reserved for future use | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 0x0: 31.5 MHz - 0x1: 51.2 MHz - 0x2: 61.44 MHz - All other values: Reserved, do not use | +| 3 | RSVD | RO | 0 | Reserved for future use | +| 2 | RST | RW | 0x1 | TWSI6 Reset Generation This field resets both the APB and functional domain. - 0: No Reset - 1: Reset | +| 1 | FNCLK | RW | 0x0 | TWSI6 Functional Clock Enable/Disable. - 0: Clock off - 1: Clock on | +| 0 | APBCLK | RW | 0x0 | TWSI6 APB Bus Clock Enable/Disable. - 0: Clock off - 1: Clock on | ##### TWSI7 CLOCK RESET CONTROL REGISTER (APBC_TWSI7_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x68
BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select
- 0x0: 31.5 MHz
- 0x1: 51.2 MHz
- 0x2: 61.44 MHz
- All other values: Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1TWSI7 Reset Generation
This field resets both the APB and functional domain.
- 0: No Reset
- 1: Reset
1FNCLKRW0x0TWSI7 Functional Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
0APBCLKRW0x0TWSI7 APB Bus Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
+Offset: 0xD4015000+0x68 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0 | Reserved for future use | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 0x0: 31.5 MHz - 0x1: 51.2 MHz - 0x2: 61.44 MHz - All other values: Reserved, do not use | +| 3 | RSVD | RO | 0 | Reserved for future use | +| 2 | RST | RW | 0x1 | TWSI7 Reset Generation This field resets both the APB and functional domain. - 0: No Reset - 1: Reset | +| 1 | FNCLK | RW | 0x0 | TWSI7 Functional Clock Enable/Disable. - 0: Clock off - 1: Clock on | +| 0 | APBCLK | RW | 0x0 | TWSI7 APB Bus Clock Enable/Disable. - 0: Clock off - 1: Clock on | ##### TWSI8 CLOCK RESET CONTROL REGISTER (APBC_TWSI8_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x20
BitsFieldTypeResetDescription
31:7RSVDWO0Reserved for future use
6:4FNCLKSELWO0x0Functional Clock Select
- 0x0: 31.5 MHz
- 0x1: 51.2 MHz
- 0x2: 61.44 MHz
- All other values: Reserved, do not use
3RSVDWO0Reserved for future use
2RSTWO0x1TWSI8 Reset Generation
This field resets both the APB and functional domain.
- 0: No Reset
- 1: Reset
1FNCLKWO0x0TWSI8 Functional Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
0APBCLKWO0x0TWSI8 APB Bus Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
+Offset: 0xD4015000+0x20 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | WO | 0 | Reserved for future use | +| 6:4 | FNCLKSEL | WO | 0x0 | Functional Clock Select - 0x0: 31.5 MHz - 0x1: 51.2 MHz - 0x2: 61.44 MHz - All other values: Reserved, do not use | +| 3 | RSVD | WO | 0 | Reserved for future use | +| 2 | RST | WO | 0x1 | TWSI8 Reset Generation This field resets both the APB and functional domain. - 0: No Reset - 1: Reset | +| 1 | FNCLK | WO | 0x0 | TWSI8 Functional Clock Enable/Disable. - 0: Clock off - 1: Clock on | +| 0 | APBCLK | WO | 0x0 | TWSI8 APB Bus Clock Enable/Disable. - 0: Clock off - 1: Clock on | ##### TIMERX CLOCK RESET CONTROL REGISTER (APBC_TIMERX_CLK_RST) X=1/2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x34/0x44
BitsFieldTypeResetDescription
31:7RSVDRO0x0Reserved
6:4FNCLKSELRW0x0Functional Clock Select
- 3'b000: 12.8 MHz
- 3'b001: 32 KHz
- 3'b010: 6.4 MHz
- 3'b011: 3.00 MHz
- 3'b100: 1 MHz
- All other values: Reserved, do not use
3RSVDRO0x0Reserved
2RSTRW0x1TIMER Reset Generation
This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0TIMER Functional Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0TIMER APB Bus Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xD4015000+0x34/0x44 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0x0 | Reserved | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 3'b000: 12.8 MHz- 3'b001: 32 KHz - 3'b010: 6.4 MHz- 3'b011: 3.00 MHz- 3'b100: 1 MHz- All other values: Reserved, do not use | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | TIMER Reset GenerationThis field resets both the APB and functional domain.- 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | TIMER Functional Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | TIMER APB Bus Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | ##### AIB CLOCK RESET CONTROL REGISTER (APBC_AIB_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x3C
BitsFieldTypeResetDescription
31:7RSVDRO0x0Reserved
6:4FNCLKSELRW0x0Reserved for future use
3RSVDRO0x0Reserved
2RSTRW0x1AIB Reset Generation This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0AIB Functional Clock Enable/ disable
- 1'b0: Clock off
- 1'b1: Clock on
0APBCLKRW0x0AIB APB Bus Clock Enable/Disable
- 1'b0: Clock off
- 1'b1: Clock on
+Offset: 0xD4015000+0x3C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0x0 | Reserved | +| 6:4 | FNCLKSEL | RW | 0x0 | Reserved for future use | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | AIB Reset Generation This field resets both the APB and functional domain. - 1'b0: No Reset - 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | AIB Functional Clock Enable/ disable - 1'b0: Clock off - 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | AIB APB Bus Clock Enable/Disable - 1'b0: Clock off - 1'b1: Clock on | ##### SSPAX CLOCK RESET CONTROL REGISTER (APBC_SSPAX_CLK_RST) X=1/2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x80/0x84
BitsFieldTypeResetDescription
31:7RSVDRO0x0Reserved
6:4FNCLKSELRW0x0Functional Clock Select
- 0x0 = 6.5 MHz
- 0x1 = 13MHz
- 0x2 = 26 MHz
- 0x3 = 52 MHz
- 0x4 = 3.25 MHz
- 0x5=1.625 MHz
- 0x6=812.5 kHz
- 0x7=1 MHz clock or i2s bit clock (MN divided from PLL DIV8)
- All other values: Reserved, do not use
3SEL_1MHzRW0- 0x0 = 1 MHz
- 0x1 = i2s bit clock MN divided from PLL_div8
2RSTRW0x1SSPA Reset Generation
This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0SSPA Functional Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0SSPA APB Bus Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xD4015000+0x80/0x84 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0x0 | Reserved | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 0x0 = 6.5 MHz - 0x1 = 13MHz - 0x2 = 26 MHz - 0x3 = 52 MHz - 0x4 = 3.25 MHz- 0x5=1.625 MHz - 0x6=812.5 kHz - 0x7=1 MHz clock or i2s bit clock (MN divided from PLL DIV8)- All other values: Reserved, do not use | +| 3 | SEL_1MHz | RW | 0 | - 0x0 = 1 MHz- 0x1 = i2s bit clock MN divided from PLL_div8 | +| 2 | RST | RW | 0x1 | SSPA Reset GenerationThis field resets both the APB and functional domain.- 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | SSPA Functional Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | SSPA APB Bus Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | ##### ONEWIRE CLOCK RESET CONTROL REGISTER (APBC_ONEWIRE_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x49
BitsFieldTypeResetDescription
31:7RSVDRO0Reserved
6:4FNCLKSELRW0x0IR Reset Generation
This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
3RSVDRO0Reserved
2RSTRW0x1IR Reset Generation
This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0One-Wire Functional Clock Enable/Disable
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0One-Wire APB Bus Clock Enable/Disable
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xD4015000+0x49 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0 | Reserved | +| 6:4 | FNCLKSEL | RW | 0x0 | IR Reset GenerationThis field resets both the APB and functional domain.- 1'b0: No Reset- 1'b1: Reset | +| 3 | RSVD | RO | 0 | Reserved | +| 2 | RST | RW | 0x1 | IR Reset GenerationThis field resets both the APB and functional domain.- 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | One-Wire Functional Clock Enable/Disable - 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | One-Wire APB Bus Clock Enable/Disable - 1'b0: Clock gating- 1'b1: Clock on | ##### DRO CLOCK RESET CONTROL REGISTER (APBC_DRO_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x58
BitsFieldTypeResetDescription
31:3RSVDRO0x0Reserved
2RSTRW0x1DRO Reset Generation
This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
1RSVDRO0x0Reserved
0APBCLKRW0x0DRO APB Bus Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xD4015000+0x58 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | DRO Reset GenerationThis field resets both the APB and functional domain.- 1'b0: No Reset- 1'b1: Reset | +| 1 | RSVD | RO | 0x0 | Reserved | +| 0 | APBCLK | RW | 0x0 | DRO APB Bus Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | ##### IR CLOCK RESET CONTROL REGISTER (APBC_IR_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x5C
BitsFieldTypeResetDescription
31:3RSVDRO0x0Reserved
2RSTRW0x1IR Reset Generation
This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
1RSVDRO0x0Reserved
0APBCLKRW0x0IR APB Bus Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xD4015000+0x5C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | IR Reset GenerationThis field resets both the APB and functional domain.- 1'b0: No Reset- 1'b1: Reset | +| 1 | RSVD | RO | 0x0 | Reserved | +| 0 | APBCLK | RW | 0x0 | IR APB Bus Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | ##### COUNTER CLOCK RESET CONTROL REGISTER (APBC_COUNTER_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x64
BitsFieldTypeResetDescription
31:16LOW_FREQ_STEPRW0x2DCGeneric Counter Step of Low Frequency
This value represents the Generic Counter step when operating at low frequency.
Default: 24 MHz / 32768 = 0x2DC
15:2RSVDRO0x0Reserved
1FREQ_SW_SELRW0x0Generic Counter Frequency Software Select.
- 1'b0: 24 MHz
- 1'b1: 32 KHz
0FREQ_HW_CTRLRW0x0Generic Counter Frequency Controlled by Hardware.
- 1'b0: Software FREQ_SW_SEL
- 1'b1: Hardware VCTCXO_EN signal.
1. If VCTCXO_EN=1, Generic Counter clock frequency is 24 MHz.
2. If VCTCXO_EN=0, Generic Counter clock frequency is 32 kHz
+Offset: 0xD4015000+0x64 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | LOW_FREQ_STEP | RW | 0x2DC | Generic Counter Step of Low Frequency This value represents the Generic Counter step when operating at low frequency.Default: 24 MHz / 32768 = 0x2DC | +| 15:2 | RSVD | RO | 0x0 | Reserved | +| 1 | FREQ_SW_SEL | RW | 0x0 | Generic Counter Frequency Software Select.- 1'b0: 24 MHz- 1'b1: 32 KHz | +| 0 | FREQ_HW_CTRL | RW | 0x0 | Generic Counter Frequency Controlled by Hardware.- 1'b0: Software FREQ_SW_SEL- 1'b1: Hardware VCTCXO_EN signal. 1. If VCTCXO_EN=1, Generic Counter clock frequency is 24 MHz. 2. If VCTCXO_EN=0, Generic Counter clock frequency is 32 kHz | ##### TEMPERATURE SENSOR CLOCK RESET CONTROL REGISTER (APBC_TSEN_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x6C
BitsFieldTypeResetDescription
31:3RSVDRO0x0Reserved
2TSEN_RST_ENRW0x1Temperature Sensor Reset Enable
- 1'b0: Release reset
- 1'b1: Reset Temperature Sensor
1TSEN_FCLK_ENRW0x0Temperature Sensor Function Clock Enable
- 1'b0: Disable temperature sensor function clock
- 1'b1: Enable temperature sensor function clock
0TSEN_PCLK_ENRW0x0Temperature Sensor APB Clock Enable
- 1'b0: Disable temperature sensor APB clock
- 1'b1: Enable temperature sensor APB clock
+Offset: 0xD4015000+0x6C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | RSVD | RO | 0x0 | Reserved | +| 2 | TSEN_RST_EN | RW | 0x1 | Temperature Sensor Reset Enable- 1'b0: Release reset- 1'b1: Reset Temperature Sensor | +| 1 | TSEN_FCLK_EN | RW | 0x0 | Temperature Sensor Function Clock Enable- 1'b0: Disable temperature sensor function clock- 1'b1: Enable temperature sensor function clock | +| 0 | TSEN_PCLK_EN | RW | 0x0 | Temperature Sensor APB Clock Enable- 1'b0: Disable temperature sensor APB clock- 1'b1: Enable temperature sensor APB clock | ##### INTER-PROCESSOR COMMUNICATION AP TO AUDIO CLOCK RESET CONTROL REGISTER (APBC_IPC_AP2AUD_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0x90
BitsFieldTypeResetDescription
31:3RSVDRO0x0Reserved
2RSTRW0x1IPC Reset Generation
This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0IPC Functional Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0IPC APB Bus Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xD4015000+0x90 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | IPC Reset GenerationThis field resets both the APB and functional domain.- 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | IPC Functional Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | IPC APB Bus Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | ##### CAN CLOCK RESET CONTROL REGISTER (APBC_CAN_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4015000+0xA0
BitsFieldTypeResetDescription
31:7RSVDRO0x0Reserved
6:4FNCLKSELRW0x0Functional Clock Select
- 3'b000: 20 MHz
- 3'b001: 40 MHz
- 3'b010: 80 MHz
- All other values: Reserved, do not use
2RSTRW0x1CAN Reset Generation
This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0CAN Functional Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0CAN APB Bus Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xD4015000+0xA0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0x0 | Reserved | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select- 3'b000: 20 MHz- 3'b001: 40 MHz- 3'b010: 80 MHz - All other values: Reserved, do not use | +| 2 | RST | RW | 0x1 | CAN Reset GenerationThis field resets both the APB and functional domain.- 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | CAN Functional Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | CAN APB Bus Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | #### Basing on **\** @@ -5676,972 +1360,200 @@ X=1/2 X=1/2/3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4090000+0x100/0x118/0x124
BitsFieldTypeResetDescription
31:24PLL_REG8RW0x00PLL test control.
- [31]: Not in use
- [30]: Input frequency selection between 24 and 19.2/38.4 MHz.
1. 1'b0: Input frequency = 24 MHz
2. 1'b1: Input frequency = 19.2 or 38.4 MHz
- [29]: FVCO configuration sources.
1. 1'b0: External value from digital value
2. 1'b1: Internal value from default value in force
- [28]: Selection on input frequency between 19.2 and 38.4 MHz.
1. 1'b0: Input frequency = 38.4 MHz
2. 1'b1: Input frequency = 19.2 MHz
- [27:24]: CK_test driving capability and clock configuration
1. <27:26> CK_test driving capability
- 2'b00: 2 driver cell
- 2'b01: 3 driver cell
- 2'b10: 4 driver cell
- 2'b11: 5 driver cell
2. <25:24> CK input select.
- 2'b00: ckin_1 (div200_aud)
- 2'b01: ckin_2(div3_soc)
- 2'b10: ckin_3(div5_soc)
- 2'b11: ckin_4(clk_dac)
23:16PLL_REG7RW0x50- [23]: Bypass PLL power down
1. 1'b1: PD is bypassed and always on
2. 1'b0: Controlled by PD
- [22]: SSC enable select
1. 1'b1: Pre_lock
2. 1'b0: LDO_rdy
- [21]: choose vreg caliration period
1. 1'b1: 256*Tref
2. 1'b0: 128*Tref
- [20]: Enable PLL fast lock
- [19]: Force PLL lock
- [18:16]: ATEST/DTEST select
15:8PLL_REG6RW0xDD- [15:14]: select LPF proportionality factor
1. 2'b00: fref = 38.4 MHz
2. 2'b01/2'b10: fref = 30/27/26/25/24 MHz
3. 2'b11: fref = 19.2 MHz
- [13:12]: PLL pre-divider select
1. 2'b00: pre_div = div1 (vco range: 1G~2G)
2. 2'b01: pre_div = div2 (vco range: 2G~4G)
3. 2'b10: pre_div = div3 (default) (vco range: 4G~6G)
4. 2'b11: pre_div = div4
- [11]: High kvco enable
1. 1'b1: Enable
2. 1'b0: Disable
- [10]: Enable regulator calibration
1. 1'b1: Enable
2. 1'b0: Disable
- [9:8]: regulator calibration vref select
1. 2'b00: vrefh = 727mV, vrefl = 626mV
2. 2'b01: vrefh = 750mV, vrefl = 650mV
3. 2'b10: vrefh = 776mV, vrefl = 679mV
4. 2'b11: vrefh = 802mV, vrefl = 707mV
7:0PLL_REG5RW0x64- [7:5]: Charge-bump current select
1. 3'b000: 0.5 µA
2. 3'b100: 0.75 µA (24/25/26/27/30 MHz)
3. 3'b010/3'b001: 1.0 µA
4. 3'b101: 1.25 µA (19.2 MHz)
5. 3'b011/3'b010: 1.5 µA
6. 3'b110: 1.75 µA (38.4 MHz)
7. 3'b001/3'b011: 2.0 µA
8. 3'b111: 2.25 µA
- [4]: config DAC clock
1. 1'b0: DAC's T_dac = 10xTvco
2. 1'b1: DAC's T_dac = 12xTvco
- [3]: config ADC clock
1. 1'b0: ADC's T_adc = 10xTvco
2. 1'b1: ADC's T_adc = 12xTvco
- [2:0]: vco frequency-band (GHz) select when reg6<3>(bit[11]) = 0:
1. 3'b000: 0.61~0.76~0.92
2. 3'b001: 0.85~1.07~1.24
3. 3'b010: 1.24~1.37~1.67
4. 3'b011: 1.34~1.67~2.01
5. 3'b100: 1.68~1.97~2.27
6. 3'b101: 1.94~2.28~2.62
7. 3'b110: 2.19~2.58~2.96
8. 3'b111: 2.45~2.88~3.32
- [2:0]: vco frequency-band (GHz) select when reg6<3>(bit[11]) = 1:
1. 3'b000: 0.61~0.76~0.92
2. 3'b001: 0.85~1.07~1.24
3. 3'b010: 1.24~1.37~1.67
4. 3'b011: 1.34~1.67~2.01
5. 3'b100: 1.68~1.97~2.27
6. 3'b101: 1.94~2.28~2.62
7. 3'b110: 2.19~2.58~2.96
8. 3'b111: 2.45~2.88~3.32
+Offset: 0xD4090000+0x100/0x118/0x124 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | PLL_REG8 | RW | 0x00 | PLL test control. - [31]: Not in use - [30]: Input frequency selection between 24 and 19.2/38.4 MHz. 1. 1'b0: Input frequency = 24 MHz 2. 1'b1: Input frequency = 19.2 or 38.4 MHz- [29]: FVCO configuration sources. 1. 1'b0: External value from digital value 2. 1'b1: Internal value from default value in force- [28]: Selection on input frequency between 19.2 and 38.4 MHz. 1. 1'b0: Input frequency = 38.4 MHz 2. 1'b1: Input frequency = 19.2 MHz- [27:24]: CK_test driving capability and clock configuration 1. <27:26> CK_test driving capability - 2'b00: 2 driver cell - 2'b01: 3 driver cell - 2'b10: 4 driver cell - 2'b11: 5 driver cell 2. <25:24> CK input select. - 2'b00: ckin_1 (div200_aud) - 2'b01: ckin_2(div3_soc) - 2'b10: ckin_3(div5_soc) - 2'b11: ckin_4(clk_dac) | +| 23:16 | PLL_REG7 | RW | 0x50 | - [23]: Bypass PLL power down 1. 1'b1: PD is bypassed and always on 2. 1'b0: Controlled by PD- [22]: SSC enable select 1. 1'b1: Pre_lock 2. 1'b0: LDO_rdy - [21]: choose vreg caliration period 1. 1'b1: 256*Tref 2. 1'b0: 128*Tref - [20]: Enable PLL fast lock- [19]: Force PLL lock- [18:16]: ATEST/DTEST select | +| 15:8 | PLL_REG6 | RW | 0xDD | - [15:14]: select LPF proportionality factor 1. 2'b00: fref = 38.4 MHz 2. 2'b01/2'b10: fref = 30/27/26/25/24 MHz 3. 2'b11: fref = 19.2 MHz- [13:12]: PLL pre-divider select 1. 2'b00: pre_div = div1 (vco range: 1G~2G) 2. 2'b01: pre_div = div2 (vco range: 2G~4G) 3. 2'b10: pre_div = div3 (default) (vco range: 4G~6G) 4. 2'b11: pre_div = div4- [11]: High kvco enable 1. 1'b1: Enable 2. 1'b0: Disable- [10]: Enable regulator calibration 1. 1'b1: Enable 2. 1'b0: Disable- [9:8]: regulator calibration vref select 1. 2'b00: vrefh = 727mV, vrefl = 626mV 2. 2'b01: vrefh = 750mV, vrefl = 650mV 3. 2'b10: vrefh = 776mV, vrefl = 679mV 4. 2'b11: vrefh = 802mV, vrefl = 707mV | +| 7:0 | PLL_REG5 | RW | 0x64 | - [7:5]: Charge-bump current select 1. 3'b000: 0.5 µA 2. 3'b100: 0.75 µA (24/25/26/27/30 MHz) 3. 3'b010/3'b001: 1.0 µA 4. 3'b101: 1.25 µA (19.2 MHz) 5. 3'b011/3'b010: 1.5 µA 6. 3'b110: 1.75 µA (38.4 MHz) 7. 3'b001/3'b011: 2.0 µA 8. 3'b111: 2.25 µA- [4]: config DAC clock 1. 1'b0: DAC's T_dac = 10xTvco 2. 1'b1: DAC's T_dac = 12xTvco- [3]: config ADC clock 1. 1'b0: ADC's T_adc = 10xTvco 2. 1'b1: ADC's T_adc = 12xTvco - [2:0]: vco frequency-band (GHz) select when reg6<3>(bit[11]) = 0: 1. 3'b000: 0.61~0.76~0.92 2. 3'b001: 0.85~1.07~1.24 3. 3'b010: 1.24~1.37~1.67 4. 3'b011: 1.34~1.67~2.01 5. 3'b100: 1.68~1.97~2.27 6. 3'b101: 1.94~2.28~2.62 7. 3'b110: 2.19~2.58~2.96 8. 3'b111: 2.45~2.88~3.32 - [2:0]: vco frequency-band (GHz) select when reg6<3>(bit[11]) = 1: 1. 3'b000: 0.61~0.76~0.92 2. 3'b001: 0.85~1.07~1.24 3. 3'b010: 1.24~1.37~1.67 4. 3'b011: 1.34~1.67~2.01 5. 3'b100: 1.68~1.97~2.27 6. 3'b101: 1.94~2.28~2.62 7. 3'b110: 2.19~2.58~2.96 8. 3'b111: 2.45~2.88~3.32 | ##### PLLX SW2 CONTROL REGISTER (PLLX_SW2_CTRL) X=1/2/3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4090000+0x104/0x11C/0x128
BitsFieldTypeResetDescription
31:24BG_REGRW0x58- internal pin name: {nc,nc,nc, bgsel<2:0>, rtemp<1:0>} bg_reg1<7:5>: Reserved
- bg_reg1<4:2>: bandgap output control bits
- bg_reg1<1:0>: bandgap output temperature coefficient control bits
23BG_ENRW0x1Bandgap enable
- 1'b1: Enable
22REFBUF2_ENRW0x0REFBUF SW enable
- 1'b1: Enable.
- 1'b0: HW control
21PLL_UPDATE_ENRW0x1PLLX divider update enable
- 1'b1: Enable
- 1'b0: Disable
20PLL_DIV23_ENRW0x0PLLX_DIV23_EN
- 1'b1: Enable
19:17PLL1_MON_CFGRW0x4PLLX_MON_CFG.
- [19]: Monitor enable
- [18:17]: Monitor divider
16PLL_DIV13_ENRW0x0PLLX_DIV13_EN
- 1'b1: Enable
15PLL_DIV11_ENRW0x0PLLX_DIV11_EN
- 1'b1: Enable
14EN_DTESTRW0x0DTEST enable
13EN_CKTESTRW0x0CKTEST enable
12EN_ATESTRW0x0ATEST enable
11PLL_24P576_AUD_ENRW0x1PLL1_24p576_AUD_EN
- 1'b1: Enable
10PLL_245P76_AUD_ENRW0x1PLL1_245p76_AUD_EN
- 1'b1: Enable
9PLL_245P6_DAC_ENRW0x1If APBaux/PLL_ADDA_OVRD_EN=1, this bit controls PLLX_245p6_DAC_EN
- 1'b1: Enable
8PLL_245P6_ADC_ENRW0x1If APBaux/PLL_ADDA_OVRD_EN=1, this bit controls PLLX_245p6_ADC_EN
- 1'b1: Enable
7PLL_DIV8_ENRW0x1PLLX_DIV8_EN
- 1'b1: Enable
6PLL_DIV7_ENRW0x1PLLX_DIV7_EN
- 1'b1: Enable
5PLL_DIV6_ENRW0x1PLLX_DIV6_EN
- 1'b1: Enable
4PLL_DIV5_ENRW0x1PLLX_DIV5_EN
- 1'b1: Enable
3PLL_DIV4_ENRW0x1PLLX_DIV4_EN
- 1'b1: Enable
2PLL_DIV3_ENRW0x1PLLX_DIV3_EN
- 1'b1: Enable
1PLL_DIV2_ENRW0x1PLLX_DIV2_EN
- 1'b1: Enable
0PLL_DIV1_ENRW0x1PLLX_DIV1_EN
- 1'b1: Enable
+Offset: 0xD4090000+0x104/0x11C/0x128 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | BG_REG | RW | 0x58 | - internal pin name: {nc,nc,nc, bgsel<2:0>, rtemp<1:0>} bg_reg1<7:5>: Reserved- bg_reg1<4:2>: bandgap output control bits- bg_reg1<1:0>: bandgap output temperature coefficient control bits | +| 23 | BG_EN | RW | 0x1 | Bandgap enable - 1'b1: Enable | +| 22 | REFBUF2_EN | RW | 0x0 | REFBUF SW enable- 1'b1: Enable.- 1'b0: HW control | +| 21 | PLL_UPDATE_EN | RW | 0x1 | PLLX divider update enable- 1'b1: Enable- 1'b0: Disable | +| 20 | PLL_DIV23_EN | RW | 0x0 | PLLX_DIV23_EN- 1'b1: Enable | +| 19:17 | PLL1_MON_CFG | RW | 0x4 | PLLX_MON_CFG. - [19]: Monitor enable - [18:17]: Monitor divider | +| 16 | PLL_DIV13_EN | RW | 0x0 | PLLX_DIV13_EN- 1'b1: Enable | +| 15 | PLL_DIV11_EN | RW | 0x0 | PLLX_DIV11_EN- 1'b1: Enable | +| 14 | EN_DTEST | RW | 0x0 | DTEST enable | +| 13 | EN_CKTEST | RW | 0x0 | CKTEST enable | +| 12 | EN_ATEST | RW | 0x0 | ATEST enable | +| 11 | PLL_24P576_AUD_EN | RW | 0x1 | PLL1_24p576_AUD_EN - 1'b1: Enable | +| 10 | PLL_245P76_AUD_EN | RW | 0x1 | PLL1_245p76_AUD_EN- 1'b1: Enable | +| 9 | PLL_245P6_DAC_EN | RW | 0x1 | If APBaux/PLL_ADDA_OVRD_EN=1, this bit controls PLLX_245p6_DAC_EN- 1'b1: Enable | +| 8 | PLL_245P6_ADC_EN | RW | 0x1 | If APBaux/PLL_ADDA_OVRD_EN=1, this bit controls PLLX_245p6_ADC_EN- 1'b1: Enable | +| 7 | PLL_DIV8_EN | RW | 0x1 | PLLX_DIV8_EN- 1'b1: Enable | +| 6 | PLL_DIV7_EN | RW | 0x1 | PLLX_DIV7_EN - 1'b1: Enable | +| 5 | PLL_DIV6_EN | RW | 0x1 | PLLX_DIV6_EN - 1'b1: Enable | +| 4 | PLL_DIV5_EN | RW | 0x1 | PLLX_DIV5_EN- 1'b1: Enable | +| 3 | PLL_DIV4_EN | RW | 0x1 | PLLX_DIV4_EN- 1'b1: Enable | +| 2 | PLL_DIV3_EN | RW | 0x1 | PLLX_DIV3_EN- 1'b1: Enable | +| 1 | PLL_DIV2_EN | RW | 0x1 | PLLX_DIV2_EN- 1'b1: Enable | +| 0 | PLL_DIV1_EN | RW | 0x1 | PLLX_DIV1_EN- 1'b1: Enable | ##### PLLX SW3 CONTROL REGISTER (PLLX_SW3_CTRL) X=1/2/3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4090000+0x108/0x120/0x12C
BitsFieldTypeResetDescription
31PLL_SW_ENRW0x0- 1'b0: PLL enable controlled by PMU HW
- 1'b1: SW force enabled
30:0RSVDRO0x0Reserved
+Offset: 0xD4090000+0x108/0x120/0x12C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | PLL_SW_EN | RW | 0x0 | - 1'b0: PLL enable controlled by PMU HW- 1'b1: SW force enabled | +| 30:0 | RSVD | RO | 0x0 | Reserved | #### Basing on \ ##### APB2 UART1 CLOCK RESET CONTROL REGISTER (APB2_UART1_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xF0610000+0x0
BitsFieldTypeResetDescription
31:7RSVDRO0x0Reserved
6:4FNCLKSELRW0x0Functional Clock Select
- 3'b000: 57.6 MHz
- 3'b001: 14.7456 MHz
- 3'b010: 48MHz
- 3'b011: UART_LP
- All other values: Reserved, do not use
3RSVDRO0x0Reserved
2RSTRW0x1UART Reset Generation.
This field resets both APB and Functional domains.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0UART Functional Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0UART APB Bus Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xF0610000+0x0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0x0 | Reserved | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 3'b000: 57.6 MHz- 3'b001: 14.7456 MHz- 3'b010: 48MHz- 3'b011: UART_LP- All other values: Reserved, do not use | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | UART Reset Generation.This field resets both APB and Functional domains. - 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | UART Functional Clock Enable/Disable.- 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | UART APB Bus Clock Enable/Disable.- 1'b0: Clock gating- 1'b1: Clock on | ##### APB2 SSP2 CLOCK RESET CONTROL REGISTER (APB2_SSP2_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xF0610000+0x4
BitsFieldTypeResetDescription
31:8RSVDRO0x0Reserved
7SEL_SSP_FUNC_CLKRW0x0AC97 Clock Switch
This bit enables the SSP module to switch clocks internally.
6:4FNCLKSELRW0x0Functional Clock Select
- 3'b000: 6.4 MHz
- 3'b001: 12.8 MHz
- 3'b010: 25.6 MHz
- 3'b011: 51.2 MHz
- 3'b100: 3.2 MHz
- 3'b101: 1.6 MHz
- 3'b110: 800 kHz
- All other values: Reserved, do not use
3RSVDRO0x0Reserved
2RSTRW0x1SSP 3 Reset Generation
This field resets both the APB and functional domain
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0SSP 3 Functional Clock Enable/Disable
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0SSP 3 APB Bus Clock Enable/Disable
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xF0610000+0x4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | RSVD | RO | 0x0 | Reserved | +| 7 | SEL_SSP_FUNC_CLK | RW | 0x0 | AC97 Clock Switch This bit enables the SSP module to switch clocks internally. | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 3'b000: 6.4 MHz- 3'b001: 12.8 MHz- 3'b010: 25.6 MHz- 3'b011: 51.2 MHz- 3'b100: 3.2 MHz- 3'b101: 1.6 MHz- 3'b110: 800 kHz- All other values: Reserved, do not use | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | SSP 3 Reset GenerationThis field resets both the APB and functional domain- 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | SSP 3 Functional Clock Enable/Disable- 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | SSP 3 APB Bus Clock Enable/Disable - 1'b0: Clock gating- 1'b1: Clock on | ##### TWSI3 CLOCK RESET CONTROL REGISTER (APBC_TWSI3_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xF0610000+0x8
BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select
- 0x0: 31.5 MHz
- 0x1: 51.2 MHz
- 0x2: 61.44 MHz
- All other values: Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1TWSI3 Reset Generation
This field resets both the APB and functional domain.
- 0: No Reset
- 1: Reset
1FNCLKRW0x0TWSI3 Functional Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
0APBCLKRW0x0TWSI3 APB Bus Clock Enable/Disable.
- 0: Clock off
- 1: Clock on
+Offset: 0xF0610000+0x8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0 | Reserved for future use | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 0x0: 31.5 MHz - 0x1: 51.2 MHz - 0x2: 61.44 MHz - All other values: Reserved, do not use | +| 3 | RSVD | RO | 0 | Reserved for future use | +| 2 | RST | RW | 0x1 | TWSI3 Reset Generation This field resets both the APB and functional domain. - 0: No Reset - 1: Reset | +| 1 | FNCLK | RW | 0x0 | TWSI3 Functional Clock Enable/Disable. - 0: Clock off - 1: Clock on | +| 0 | APBCLK | RW | 0x0 | TWSI3 APB Bus Clock Enable/Disable. - 0: Clock off - 1: Clock on | ##### APB2 SECURE RTC CLOCK RESET CONTROL REGISTER (APB2_SEC_RTC_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xF0610000+0xC
BitsFieldTypeResetDescription
31:8RSVDRO0x0Reserved
7PM_POWER_SENSORRW0x0Power Enabled.
This field enables the register read/write for the RTC module by indicating power is enabled.
Set this field to 0x1 before enabling RTC operations.
6:4FNCLKSELRW0x0Functional Clock Select.
- 3'b000: 32 KHz
- All other values: Reserved, do not use
3RSVDRO0x0Reserved
2RSTRW0x1RTC Reset Generation
This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0RTC Functional Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0RTC APB Bus Clock Enable/Disable
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xF0610000+0xC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | RSVD | RO | 0x0 | Reserved | +| 7 | PM_POWER_SENSOR | RW | 0x0 | Power Enabled. This field enables the register read/write for the RTC module by indicating power is enabled. Set this field to 0x1 before enabling RTC operations. | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select.- 3'b000: 32 KHz - All other values: Reserved, do not use | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | RTC Reset GenerationThis field resets both the APB and functional domain.- 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | RTC Functional Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | RTC APB Bus Clock Enable/Disable - 1'b0: Clock gating- 1'b1: Clock on | ##### APB2 TIMER0 CLOCK RESET CONTROL REGISTER (APB2_TIMER0_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xF0610000+0x10
BitsFieldTypeResetDescription
31:7RSVDRO0x0Reserved
6:4FNCLKSELRW0x0Functional Clock Select
- 3'b000: 12.8 MHz
- 3'b001: 32 KHz
- 3'b010: 6.4 MHz
- 3'b011: 3.00 MHz
- 3'b100: 1 MHz
- All other values: Reserved, do not use
3RSVDRO0x0Reserved
2RSTRW0x1TIMER Reset Generation
This field resets both the APB and functional domain.
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0TIMER Functional Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0TIMER APB Bus Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xF0610000+0x10 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0x0 | Reserved | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select - 3'b000: 12.8 MHz- 3'b001: 32 KHz - 3'b010: 6.4 MHz- 3'b011: 3.00 MHz- 3'b100: 1 MHz- All other values: Reserved, do not use | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | TIMER Reset GenerationThis field resets both the APB and functional domain.- 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | TIMER Functional Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | TIMER APB Bus Clock Enable/Disable. - 1'b0: Clock gating- 1'b1: Clock on | ##### APB2 KPC CLOCK RESET CONTROL REGISTER (APB2_KPC_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xF0610000+0x14
BitsFieldTypeResetDescription
31:7RSVDRO0x0Reserved
6:4FNCLKSELRW0x0Functional Clock Select
3RSVDRO0x0Reserved
2RSTRW0x1KPC Reset Generation
This field resets both APB and Functional domains
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0KPC Functional Clock Enable/Disable
- 1'b0: Clock gating
- 1'b1: Clock on
0APBCLKRW0x0KPC APB Bus Clock Enable/Disable.
- 1'b0: Clock gating
- 1'b1: Clock on
+Offset: 0xF0610000+0x14 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:7 | RSVD | RO | 0x0 | Reserved | +| 6:4 | FNCLKSEL | RW | 0x0 | Functional Clock Select | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | KPC Reset GenerationThis field resets both APB and Functional domains- 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | KPC Functional Clock Enable/Disable- 1'b0: Clock gating- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | KPC APB Bus Clock Enable/Disable.- 1'b0: Clock gating- 1'b1: Clock on | #### Basing on \ ##### RCPU SSP0 CLOCK RESET CONTROL REGISTER (RCPU_SSP0_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0880000+0x28
BitsFieldTypeResetDescription
31:19RSVDRO0x0Reserved
18:8SHUBSSP0_FCLK_DIVRW0x0RCPU SSP0 clk div
fclk= source_clk/(rcpussp0_fclk_div + 1)
7:6RSVDRO0x0Reserved
5:4SHUBSSP0_FCLK_SELRW0x0RCPU SSP0 fclk selection:
- 2'b00: clk_61.44MHz
- 2'b01: clk_25.6MHz
- 2'b10: clk_12.8MHz
- 2'b11: clk_3MHz
3RSVDRO0x0Reserved
2SHUBSSP0_PCLK_ENRW0x0
Enable bit for RCPU SSP0 pclk.
- 1'b0: Disable
- 1'b1: Enable
1SHUBSSP0_FCLK_ENRW0x0Enable bit for RCPU SSP0 fclk
- 1'b0: Disable
- 1'b1: Enable
0SHUBSSP0_SW_RSTNRW0x0Enable bit for RCPU SSP0 reset
- 1'b0: Disable
- 1'b1: Enable
+Offset: 0xC0880000+0x28 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | RSVD | RO | 0x0 | Reserved | +| 18:8 | SHUBSSP0_FCLK_DIV | RW | 0x0 | RCPU SSP0 clk div fclk= source_clk/(rcpussp0_fclk_div + 1) | +| 7:6 | RSVD | RO | 0x0 | Reserved | +| 5:4 | SHUBSSP0_FCLK_SEL | RW | 0x0 | RCPU SSP0 fclk selection: - 2'b00: clk_61.44MHz- 2'b01: clk_25.6MHz- 2'b10: clk_12.8MHz- 2'b11: clk_3MHz | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | SHUBSSP0_PCLK_EN | RW | 0x0 | Enable bit for RCPU SSP0 pclk.- 1'b0: Disable- 1'b1: Enable | +| 1 | SHUBSSP0_FCLK_EN | RW | 0x0 | Enable bit for RCPU SSP0 fclk - 1'b0: Disable- 1'b1: Enable | +| 0 | SHUBSSP0_SW_RSTN | RW | 0x0 | Enable bit for RCPU SSP0 reset - 1'b0: Disable- 1'b1: Enable | ##### RCPU I2C0 CLOCK RESET CONTROL REGISTER (RCPU_I2C0_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0880000+0x30
BitsFieldTypeResetDescription
31:19RSVDRO0x0Reserved
18:8SHUBI2C0_FCLK_DIVRW0x0RCPU I2C0 clk div
fclk= source_clk/(rcpui2c0_fclk_div + 1)
7:6RSVDRO0x0Reserved
5:4SHUBI2C0_FCLK_SELRW0x0RCPU I2C0 fclk selection
- 2'b00: clk_61.44MHz
- 2'b01: clk_25.6MHz
- 2'b10: clk_12.8MHz
- 2'b11: clk_3MHz
3RSVDRO0x0Reserved
2SHUBI2C0_PCLK_ENRW0x0
Enable bit for RCPU I2C0 pclk.
- 1'b0: Disable
- 1'b1: Enable
1SHUBI2C0_FCLK_ENRW0x0Enable bit for RCPU I2C0 fclk
- 1'b0: Disable
- 1'b1: Enable
0SHUBI2C0_SW_RSTNRW0x0Enable bit for RCPU I2C0 reset
- 1'b0: Disable
- 1'b1: Enable
+Offset: 0xC0880000+0x30 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | RSVD | RO | 0x0 | Reserved | +| 18:8 | SHUBI2C0_FCLK_DIV | RW | 0x0 | RCPU I2C0 clk div fclk= source_clk/(rcpui2c0_fclk_div + 1) | +| 7:6 | RSVD | RO | 0x0 | Reserved | +| 5:4 | SHUBI2C0_FCLK_SEL | RW | 0x0 | RCPU I2C0 fclk selection - 2'b00: clk_61.44MHz- 2'b01: clk_25.6MHz- 2'b10: clk_12.8MHz- 2'b11: clk_3MHz | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | SHUBI2C0_PCLK_EN | RW | 0x0 | Enable bit for RCPU I2C0 pclk.- 1'b0: Disable- 1'b1: Enable | +| 1 | SHUBI2C0_FCLK_EN | RW | 0x0 | Enable bit for RCPU I2C0 fclk - 1'b0: Disable- 1'b1: Enable | +| 0 | SHUBI2C0_SW_RSTN | RW | 0x0 | Enable bit for RCPU I2C0 reset - 1'b0: Disable- 1'b1: Enable | ##### RCPU UARTX CLOCK RESET CONTROL REGISTER (RCPU_UARTX_CLK_RST) X=1/0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0880000+0x3C/0xD8
BitsFieldTypeResetDescription
31:19RSVDRO0x0Reserved
18:8UART_FCLK_DIVRW0x0uart clk div
fclk= source_clk/(uart_fclk_div + 1)
7:6RSVDRO0x0Reserved
5:4UART_FCLK_SELRW0x0UART fclk selection
- 2'b00: clk_61.44MHz
- 2'b01: clk_25.6MHz
- 2'b10: clk_12.8MHz
- 2'b11: clk_3MHz
3RSVDRO0x0Reserved
2UART_PCLK_ENRW
0x0Enable bit for UART pclk
- 1'b0: Disable
- 1'b1: Enable
1UART_FCLK_ENRW0x0Enable bit for UART fclk
- 1'b0: Disable
- 1'b1: Enable
0UART_SW_RSTNRW0x0Enable bit for UART reset
- 1'b0: Disable
- 1'b1: Enable
+Offset: 0xC0880000+0x3C/0xD8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | RSVD | RO | 0x0 | Reserved | +| 18:8 | UART_FCLK_DIV | RW | 0x0 | uart clk divfclk= source_clk/(uart_fclk_div + 1) | +| 7:6 | RSVD | RO | 0x0 | Reserved | +| 5:4 | UART_FCLK_SEL | RW | 0x0 | UART fclk selection- 2'b00: clk_61.44MHz- 2'b01: clk_25.6MHz- 2'b10: clk_12.8MHz- 2'b11: clk_3MHz | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | UART_PCLK_EN | RW | 0x0 | Enable bit for UART pclk- 1'b0: Disable- 1'b1: Enable | +| 1 | UART_FCLK_EN | RW | 0x0 | Enable bit for UART fclk - 1'b0: Disable- 1'b1: Enable | +| 0 | UART_SW_RSTN | RW | 0x0 | Enable bit for UART reset- 1'b0: Disable- 1'b1: Enable | ##### RCPU CAN CLOCK RESET CONTROL REGISTER (RCPU_CAN_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0880000+0x48
BitsFieldTypeResetDescription
31:19RSVDRO0x0Reserved
18:8CAN_FCLK_DIVRW0x0CAN clk div
fclk= source_clk/(can_fclk_div + 1)
7:6RSVDRO0x0Reserved
5:4CAN_FCLK_SELRW0x0CAN fclk selection:
- 2'b00: 20 MHz
- 2'b01: 40 MHz
- 2'b10: 80 MHz
- 2'b11: Reserved
3RSVDRO0x0Reserved
2CAN_PCLK_ENRW0x0Enable bit for CAN pclk
- 1'b0: Disable
- 1'b1: Enable
1CAN_FCLK_ENRW0x0Enable bit for CAN clk
- 1'b0: Disable
- 1'b1: Enable
0CAN_SW_RSTNRW0x0Enable bit for CAN reset
- 1'b0: Disable
- 1'b1: Enable
+Offset: 0xC0880000+0x48 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | RSVD | RO | 0x0 | Reserved | +| 18:8 | CAN_FCLK_DIV | RW | 0x0 | CAN clk divfclk= source_clk/(can_fclk_div + 1) | +| 7:6 | RSVD | RO | 0x0 | Reserved | +| 5:4 | CAN_FCLK_SEL | RW | 0x0 | CAN fclk selection:- 2'b00: 20 MHz- 2'b01: 40 MHz- 2'b10: 80 MHz- 2'b11: Reserved | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | CAN_PCLK_EN | RW | 0x0 | Enable bit for CAN pclk- 1'b0: Disable- 1'b1: Enable | +| 1 | CAN_FCLK_EN | RW | 0x0 | Enable bit for CAN clk - 1'b0: Disable- 1'b1: Enable | +| 0 | CAN_SW_RSTN | RW | 0x0 | Enable bit for CAN reset- 1'b0: Disable- 1'b1: Enable | ##### RCPU IR CLOCK RESET CONTROL REGISTER (RCPU_IR_CLK_RST) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0880000+0x4C
BitsFieldTypeResetDescription
31:3RSVDRO0x0Reserved
2R_IR_PCLK_ENRW0x0Enable bit for R_IR pclk
- 1'b0: Disable
- 1'b1: Enable
1RSVDRO0Reserved
0R_IR_SW_RSTNRW0x0Enable bit for R_IR reset
- 1'b1: Enable
+Offset: 0xC0880000+0x4C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | RSVD | RO | 0x0 | Reserved | +| 2 | R_IR_PCLK_EN | RW | 0x0 | Enable bit for R_IR pclk- 1'b0: Disable- 1'b1: Enable | +| 1 | RSVD | RO | 0 | Reserved | +| 0 | R_IR_SW_RSTN | RW | 0x0 | Enable bit for R_IR reset - 1'b1: Enable | #### Basing on \ @@ -6649,444 +1561,96 @@ X=1/0 This register controls the audio SSPA and ADMA clock. Both share the same bus clock, while SSPA has a separate functional clock. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0882000+0x14
BitsFieldTypeResetDescription
31:18RSVDRO0x0Reserved
17:16SSPA_FCLK_SRC_SELRW0x0SSPA function clock source
- 2'b0: SSPA_FCLK_SRC = 24.576M
- 2'b1: SSPA_FCLK_SRC = 245.76M
15RSVDRO0x0Reserved
14:4SSPA_FCLK_DIVRW0x9fSSPA function clock divider
sspa_fclk = SSPA_FCLK_SRC/( SSPA_FCLK_DIV+1)
3RSVDRO0x0Reserved
2SSPA_FCLK_ENRW0x0- 1'b0: SSPA function clock gated
- 1'b1: SSPA function clock enable
1TXRX_BUS_CLK_ENRW0x0- 1'b0: bus clock gated
- 1'b1: bus clock enable
0TXRX_SW_RSTNRW0x0Reset control for audio SSPA and ADMA
- 1'b0: Software reset
- 1'b1: Release reset
- -##### AUDIO DEF CLOCK CONTROL REGISTER ( AUDIO_DFE_CLK_CTRL) +Offset: 0xC0882000+0x14 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:18 | RSVD | RO | 0x0 | Reserved | +| 17:16 | SSPA_FCLK_SRC_SEL | RW | 0x0 | SSPA function clock source - 2'b0: SSPA_FCLK_SRC = 24.576M - 2'b1: SSPA_FCLK_SRC = 245.76M | +| 15 | RSVD | RO | 0x0 | Reserved | +| 14:4 | SSPA_FCLK_DIV | RW | 0x9f | SSPA function clock dividersspa_fclk = SSPA_FCLK_SRC/( SSPA_FCLK_DIV+1) | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | SSPA_FCLK_EN | RW | 0x0 | - 1'b0: SSPA function clock gated - 1'b1: SSPA function clock enable | +| 1 | TXRX_BUS_CLK_EN | RW | 0x0 | - 1'b0: bus clock gated - 1'b1: bus clock enable | +| 0 | TXRX_SW_RSTN | RW | 0x0 | Reset control for audio SSPA and ADMA- 1'b0: Software reset - 1'b1: Release reset | + +##### AUDIO DEF CLOCK CONTROL REGISTER ( AUDIO_DFE_CLK_CTRL) This register is for the Audio Codec DFE clock control. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0882000+0x1C
BitsFieldTypeResetDescription
31:6RSVDRO0x0
Reserved
5DFE_SW_RSTRW
0x0
- 1'b0: Software reset
- 1'b1: Release reset
4DFE_FUNC_CLK_ENRW0x0- 1'b0: Disable
- 1'b1: Enable
3DAC_SW_RSTRW0x0- 1'b0: Software reset
- 1'b1: Release reset
2DAC_CLK_INV_ENRW0x0DAC clock can use the original clock from analog or the invert clock
- 1’b0: DAC uses the original clock
- 1'b1: DAC uses the invert clock
1ADC_SW_RSTRW0x0- 1'b0: Software reset
- 1'b1: Release reset
0ADC_CLK_INV_ENRW0x0ADC clock can use the original clock from analog or the invert clock
- 1’b0: ADC uses the original clock
- 1'b1: ADC uses the invert clock
+Offset: 0xC0882000+0x1C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:6 | RSVD | RO | 0x0 | Reserved | +| 5 | DFE_SW_RST | RW | 0x0 | - 1'b0: Software reset - 1'b1: Release reset | +| 4 | DFE_FUNC_CLK_EN | RW | 0x0 | - 1'b0: Disable- 1'b1: Enable | +| 3 | DAC_SW_RST | RW | 0x0 | - 1'b0: Software reset - 1'b1: Release reset | +| 2 | DAC_CLK_INV_EN | RW | 0x0 | DAC clock can use the original clock from analog or the invert clock - 1’b0: DAC uses the original clock - 1'b1: DAC uses the invert clock | +| 1 | ADC_SW_RST | RW | 0x0 | - 1'b0: Software reset - 1'b1: Release reset | +| 0 | ADC_CLK_INV_EN | RW | 0x0 | ADC clock can use the original clock from analog or the invert clock - 1’b0: ADC uses the original clock - 1'b1: ADC uses the invert clock | ##### AUDIO FM TX RX CLOCK CONTROL REGISTER (AUDIO_I2S1_TX_RX_CLK_CTRL) This register controls the audio SSPA and ADMA clock. Both share the same bus clock, while SSPA has a separate functional clock. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0882000+0x40
BitsFieldTypeResetDescription
31:18RSVDRO0x0Reserved
17:16I2S1_SSPA_FCLK_SRC_SELRW0x0
SSPA function clock source
- 2'b0: SSPA_FCLK_SRC = 24.576M
- 2'b1: SSPA_FCLK_SRC = 245.6M
15RSVDRO0x0Reserved
14:4I2S1_SSPA_FCLK_DIVRW0x9fSSPA function clock divider
sspa_fclk = SSPA_FCLK_SRC/( SSPA_FCLK_DIV+1)
3RSVDRO0x0Reserved
2I2S1_SSPA_FCLK_ENRW0x0- 1'b0: SSPA function clock gated
- 1'b1: SSPA function clock enable
1I2S1_TXRX_BUS_CLK_ENRW0x0- 1'b0: bus clock gated
- 1'b1: bus clock enable
0I2S1_TXRX_SW_RSTNRW0x0Reset control for audio SSPA and ADMA
- 1'b0: Software reset
- 1'b1: Release reset
+Offset: 0xC0882000+0x40 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:18 | RSVD | RO | 0x0 | Reserved | +| 17:16 | I2S1_SSPA_FCLK_SRC_SEL | RW | 0x0 | SSPA function clock source - 2'b0: SSPA_FCLK_SRC = 24.576M - 2'b1: SSPA_FCLK_SRC = 245.6M | +| 15 | RSVD | RO | 0x0 | Reserved | +| 14:4 | I2S1_SSPA_FCLK_DIV | RW | 0x9f | SSPA function clock dividersspa_fclk = SSPA_FCLK_SRC/( SSPA_FCLK_DIV+1) | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | I2S1_SSPA_FCLK_EN | RW | 0x0 | - 1'b0: SSPA function clock gated - 1'b1: SSPA function clock enable | +| 1 | I2S1_TXRX_BUS_CLK_EN | RW | 0x0 | - 1'b0: bus clock gated - 1'b1: bus clock enable | +| 0 | I2S1_TXRX_SW_RSTN | RW | 0x0 | Reset control for audio SSPA and ADMA - 1'b0: Software reset - 1'b1: Release reset | ##### AUDIO I2S TX RX CLOCK CONTROL REGISTER (AUDIO_HDMI_CLK_CTRL) This register controls the audio SSPA and ADMA clock. Both share the same bus clock, while SSPA has a separate functional clock. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0882000+0x44
BitsFieldTypeResetDescription
31:18RSVDRO0x0Reserved
17:16HDMI_SSPA_FCLK_SRC_SELRW0x0
SSPA function clock source
- 2'b0: SSPA_FCLK_SRC = 24.576M
- 2'b1: SSPA_FCLK_SRC = 245.76M
15RSVDRO0x0Reserved
14:4HDMI_SSPA_FCLK_DIVRW0x9fSSPA function clock divider
sspa_fclk = SSPA_FCLK_SRC/( SSPA_FCLK_DIV+1)
3RSVDRO0x0Reserved
2HDMI_SSPA_FCLK_ENRW0x0- 1'b0: SSPA function clock gated
- 1'b1: SSPA function clock enable
1HDMI_BUS_CLK_ENRW0x0- 1'b0: bus clock gated
- 1'b1: bus clock enable
0HDMI_SW_RSTNRW0x0Reset control for audio SSPA and ADMA
- 1'b0: Software reset
- 1'b1: Release reset
+Offset: 0xC0882000+0x44 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:18 | RSVD | RO | 0x0 | Reserved | +| 17:16 | HDMI_SSPA_FCLK_SRC_SEL | RW | 0x0 | SSPA function clock source - 2'b0: SSPA_FCLK_SRC = 24.576M - 2'b1: SSPA_FCLK_SRC = 245.76M | +| 15 | RSVD | RO | 0x0 | Reserved | +| 14:4 | HDMI_SSPA_FCLK_DIV | RW | 0x9f | SSPA function clock dividersspa_fclk = SSPA_FCLK_SRC/( SSPA_FCLK_DIV+1) | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | HDMI_SSPA_FCLK_EN | RW | 0x0 | - 1'b0: SSPA function clock gated - 1'b1: SSPA function clock enable | +| 1 | HDMI_BUS_CLK_EN | RW | 0x0 | - 1'b0: bus clock gated - 1'b1: bus clock enable | +| 0 | HDMI_SW_RSTN | RW | 0x0 | Reset control for audio SSPA and ADMA- 1'b0: Software reset - 1'b1: Release reset | ##### AUDIO FM TX RX CLOCK CONTROL REGISTER (AUDIO_I2S0_TX_RX_CLK_CTRL) This register controls the audio SSPA and ADMA clock. Both share the same bus clock, while SSPA has a separate functional clock. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0882000+0x60
BitsFieldTypeResetDescription
31:18RSVDRO0x0Reserved
17:16I2S0_SSPA_FCLK_SRC_SELRW0x0
SSPA function clock source
- 2'b0: SSPA_FCLK_SRC = 24.576M
- 2'b1: SSPA_FCLK_SRC = 245.76M
15RSVDRO0x0Reserved
14:4I2S0_SSPA_FCLK_DIVRW0x9fSSPA function clock divider
sspa_fclk = SSPA_FCLK_SRC/( SSPA_FCLK_DIV+1)
3RSVDRO0x0Reserved
2I2S0_SSPA_FCLK_ENRW0x0- 1'b0: SSPA function clock gated
- 1'b1: SSPA function clock enable
1I2S0_TXRX_BUS_CLK_ENRW0x0- 1'b0: bus clock gated
- 1'b1: bus clock enable
0I2S0_TXRX_SW_RSTNRW0x0Reset control for audio SSPA and ADMA
- 1'b0: Software reset
- 1'b1: Release reset
+Offset: 0xC0882000+0x60 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:18 | RSVD | RO | 0x0 | Reserved | +| 17:16 | I2S0_SSPA_FCLK_SRC_SEL | RW | 0x0 | SSPA function clock source - 2'b0: SSPA_FCLK_SRC = 24.576M - 2'b1: SSPA_FCLK_SRC = 245.76M | +| 15 | RSVD | RO | 0x0 | Reserved | +| 14:4 | I2S0_SSPA_FCLK_DIV | RW | 0x9f | SSPA function clock dividersspa_fclk = SSPA_FCLK_SRC/( SSPA_FCLK_DIV+1) | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | I2S0_SSPA_FCLK_EN | RW | 0x0 | - 1'b0: SSPA function clock gated - 1'b1: SSPA function clock enable | +| 1 | I2S0_TXRX_BUS_CLK_EN | RW | 0x0 | - 1'b0: bus clock gated - 1'b1: bus clock enable | +| 0 | I2S0_TXRX_SW_RSTN | RW | 0x0 | Reset control for audio SSPA and ADMA - 1'b0: Software reset - 1'b1: Release reset | ##### RCPU PWMx CLOCK CONTROL REGISTER (R_PWMx_CLK_RST) x=0/1/2/3/4/5/6/7/8/9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0888000+0x0/0x4/0x8/0xC/0x10/0x14/0x18/0x1C/0x20/0x24
BitsFieldTypeResetDescription
31:19RSVDRO0x0Reserved
18:8FNCLKDIVRW0x0
This field defines the division factor for the functional clock source.
7:6RSVDRO0x0Reserved
5:4
FNCLKSELRW0x0
Functional Clock Selection:
- 2'b0: 245.76 MHz
- 2'b1: 24.576 MHz
- All others are reserved
3RSVDRO0x0Reserved
2RSTRW0x1
PWM Reset Generation
This field resets both APB and Functional domains
- 1'b0: No Reset
- 1'b1: Reset
1FNCLKRW0x0PWM Functional Clock Enable/Disable
- 1'b0: Clock off
- 1'b1: Clock on
0APBCLKRW0x0PWM APB Bus Clock Enable/Disable
- 1'b0: Clock off
- 1'b1: Clock on
+Offset: 0xC0888000+0x0/0x4/0x8/0xC/0x10/0x14/0x18/0x1C/0x20/0x24 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:19 | RSVD | RO | 0x0 | Reserved | +| 18:8 | FNCLKDIV | RW | 0x0 | This field defines the division factor for the functional clock source. | +| 7:6 | RSVD | RO | 0x0 | Reserved | +| 5:4 | FNCLKSEL | RW | 0x0 | Functional Clock Selection:- 2'b0: 245.76 MHz- 2'b1: 24.576 MHz - All others are reserved | +| 3 | RSVD | RO | 0x0 | Reserved | +| 2 | RST | RW | 0x1 | PWM Reset GenerationThis field resets both APB and Functional domains- 1'b0: No Reset- 1'b1: Reset | +| 1 | FNCLK | RW | 0x0 | PWM Functional Clock Enable/Disable- 1'b0: Clock off- 1'b1: Clock on | +| 0 | APBCLK | RW | 0x0 | PWM APB Bus Clock Enable/Disable- 1'b0: Clock off- 1'b1: Clock on | ## 9.3 JTAG @@ -7137,26 +1701,10 @@ and they can be selected and configured to connect to either X60™ or RCPU proc - **Primary JTAG** is enabled at default - **Secondary JTAG** can be configured as follows: - - - - - - - - - - - - - - - - - - - -
CORE_SEL=0CORE_SEL=1
JTAG_SEL=0Secondary JTAG disabledSecondary JTAG disabled
JTAG_SEL=1Secondary JTAG routes to X60™Secondary JTAG routes to RCPU
+ | | CORE_SEL=0 | CORE_SEL=1 | +| --- | --- | --- | +| JTAG_SEL=0 | Secondary JTAG disabled | Secondary JTAG disabled | +| JTAG_SEL=1 | Secondary JTAG routes to X60™ | Secondary JTAG routes to RCPU | The typical scenario for both JTAG usage is that one JTAG connects to X60™ and the other connects to RCPU for debugging simultaneously. @@ -7170,45 +1718,12 @@ DMA enables faster and more efficient data transfer bypassing the involvement of In DMA transactions, every DMA request from a peripheral device generates a bus transaction. The DMA controller can manage different data transfer types in DMA Flow-Through Mode through 16 configurable DMA channels as tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Internal MemoryExternal MemoryInternal PeripheralExternal Peripheral
Internal MemoryFlow-Through Mode ___ ___ ___
External MemoryFlow-Through ModeFlow-Through Mode ___ ___
Internal PeripheralFlow-Through ModeFlow-Through Mode______
External PeripheralFlow-Through ModeFlow-Through Mode______
+| | Internal Memory | External Memory | Internal Peripheral | External Peripheral | +| --- | --- | --- | --- | --- | +| Internal Memory | Flow-Through Mode | ___ | ___ | ___ | +| External Memory | Flow-Through Mode | Flow-Through Mode | ___ | ___ | +| Internal Peripheral | Flow-Through Mode | Flow-Through Mode | ___ | ___ | +| External Peripheral | Flow-Through Mode | Flow-Through Mode | ___ | ___ | ### 9.4.2 Features @@ -7251,40 +1766,12 @@ DMA channels are divided into **4 sets**, each containing **4 channels**, as fol Details about channel priority are tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SetChannelsPriorityNumber of Times Served
00, 1, 2, 3Highest4 / 8
1
4, 5, 6, 7
Higher than 2 and 3. Lower than 0.2 / 8
2
8, 9, 10,11
Higher than 3. Lower than 0 and 1.1 / 8
312, 13, 14, 15Lowest1/ 8
+| Set | Channels | Priority | Number of Times Served | +| --- | --- | --- | --- | +| 0 | 0, 1, 2, 3 | Highest | 4 / 8 | +| 1 | 4, 5, 6, 7 | Higher than 2 and 3. Lower than 0. | 2 / 8 | +| 2 | 8, 9, 10,11 | Higher than 3. Lower than 0 and 1. | 1 / 8 | +| 3 | 12, 13, 14, 15 | Lowest | 1/ 8 | Channels within each set follow a **round-robin priority**. When all channels are active: @@ -7307,15 +1794,15 @@ The following states apply to the DMA channels: - **Descriptor-fetch transfer** A valid descriptor is loaded into the DMA Descriptor Address Registers. The \ field is cleared when the DMA Controller updates the DMA Descriptor Address Registers. - + - **No-Descriptor-fetch transfer** The DMA Source Address Registers, DMA Target Address Registers and DMA Command Registers are programmed, but \ remains set until the channel starts running. - + - **Running**, then two transfers are possible as follows: - **Descriptor-fetch transfer** After programming DDADR_H/DDADR_L and setting \, the DMA fetches eight words of descriptors from memory, keeping \ clear. - + - **No-Descriptor-fetch transfer** After programming the DMA Source Address Registers, DMA Target Address Registers, DMA Command Registers (if accessing memory beyond the 4GB limit, then configure the high-level address registers in the same sequence as the first four address registers) and setting \, the channel clears \, skips the Descriptor-fetch Running state and enters either the “Wait for Request” or “Transfer Data” state. @@ -7338,130 +1825,34 @@ The following states apply to the DMA channels: The summary of the DMA channel states is tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Descriptor ModeSoftware Configuration<Run><Stop interrupt>Resulting
Channel State
Descriptor-Fetch modePower-up01Uninitialized
Write to DDADR before DCSR[RUN] is set (recommended)00Valid Descriptor, not running
Set DCSR[RUN] after writing to DDADR (recommended)10Running
Set DCSR[RUN] before
writing to DDADR(not recommended)		11Invalid
Write to DDADR after DCSR[RUN] is set (not recommended)10Descriptor fetch, running.
Stop running channel by clearing DCSR[RUN] and DCSR[MASKRUN]00 -> 1Channel, if not immediately, eventually switches to a stopped state (identified by DCSR[STOPINTR] toggling from low to high).
No-Descriptor- Fetch mode


Power-on
01Uninitialized
Write to DSADR, DTADR and DCMD before DCSR[RUN] is set(recommended)01Valid Descriptor, not running
Set DCSR[RUN] after configuring DSADR, DTADR, and DCMD(recommended)10Running
Set DCSR[RUN] before configuring DSADR, DTADR, and DCMD (not recommended)10Wait for Request, running. Channel uses current DSADR, DTADR and DCMD for the transfer, potentially leading to unpredictable results.
Stop running channel, by clearing DCSR[RUN] and DCSR[MASKRUN00 -> 1Channel, if not immediately, eventually switches to a stopped state (identified by DCSR[STOPINTR] toggling from low to high)
+| Descriptor Mode | Software Configuration | | | Resulting Channel State | +| --- | --- | --- | --- | --- | +| Descriptor-Fetch mode | Power-up | 0 | 1 | Uninitialized | +| Write to DDADR before DCSR[RUN] is set (recommended) | 0 | 0 | Valid Descriptor, not running | +| Set DCSR[RUN] after writing to DDADR (recommended) | 1 | 0 | Running | +| Set DCSR[RUN] beforewriting to DDADR(not recommended) | 1 | 1 | Invalid | +| Write to DDADR after DCSR[RUN] is set (not recommended) | 1 | 0 | Descriptor fetch, running. | +| Stop running channel by clearing DCSR[RUN] and DCSR[MASKRUN] | 0 | 0 -> 1 | Channel, if not immediately, eventually switches to a stopped state (identified by DCSR[STOPINTR] toggling from low to high). | +| No-Descriptor- Fetch mode | Power-on | 0 | 1 | Uninitialized | +| Write to DSADR, DTADR and DCMD before DCSR[RUN] is set(recommended) | 0 | 1 | Valid Descriptor, not running | +| Set DCSR[RUN] after configuring DSADR, DTADR, and DCMD(recommended) | 1 | 0 | Running | +| Set DCSR[RUN] before configuring DSADR, DTADR, and DCMD (not recommended) | 1 | 0 | Wait for Request, running. Channel uses current DSADR, DTADR and DCMD for the transfer, potentially leading to unpredictable results. | +| Stop running channel, by clearing DCSR[RUN] and DCSR[MASKRUN | 0 | 0 -> 1 | Channel, if not immediately, eventually switches to a stopped state (identified by DCSR[STOPINTR] toggling from low to high) | #### DMA Descriptors A DMA Descriptor is an 8-word block (32-bits per word) aligned to a 32-byte boundary in memory. Details are tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Word IndexDescription
Word [0]DMA Descriptor Address Register + Flag Bit
Word [1]DMA Source Address Register
Word [2]DMA Target Address Register
Word [3]DMA Command Register
Word [4]High 32-bit Descriptor Address Register
Word [5]High 32-bit Source Address Register
Word [6]High 32-bit Target Address Register
Word [7]Reserved
+| Word Index | Description | +| --- | --- | +| Word [0] | DMA Descriptor Address Register + Flag Bit | +| Word [1] | DMA Source Address Register | +| Word [2] | DMA Target Address Register | +| Word [3] | DMA Command Register | +| Word [4] | High 32-bit Descriptor Address Register | +| Word [5] | High 32-bit Source Address Register | +| Word [6] | High 32-bit Target Address Register | +| Word [7] | Reserved | The DMAC can operate in two distinct modes based on the DCSR[NODESCFETCH] bit as follows: @@ -7624,8 +2015,8 @@ A flowthrough DMA Read begins when an on-chip peripheral sends a request to a ch Use the following settings for the DMAC register bits for a flowthrough DMA Read from an internal peripheral: -- \ field and \ in the DMA Source Address High/Low register = memory address -- \ field and \ in the DMA Target Address High/Low register = internal peripheral address +- \ field and \ in the DMA Source Address High/Low register = memory address +- \ field and \ in the DMA Target Address High/Low register = internal peripheral address - \ field in the DMA Command Registers = 1 - \ field in the DMA Command Registers = 0 - \ field in the DMA Command Registers = 0 @@ -7643,8 +2034,8 @@ When the request is recognized, the following process begins: Use the following settings for the DMAC register bits for a flowthrough-DMA Write from an internal peripheral: -- \ field and \ = internal peripheral address -- \ field and \ = memory address +- \ field and \ = internal peripheral address +- \ field and \ = memory address - \ = 0 - \ = 1 - \ = 1 @@ -7664,8 +2055,8 @@ A flowthrough DMA memory-to-memory Read or Write begins when the processor the D Use the following settings for the DMAC register bits for flowthrough memory-to-memory moves: -- \ field and \ = internal peripheral address -- \ field and \ = memory address +- \ field and \ = internal peripheral address +- \ field and \ = memory address - \ = 1 - \ = 1 - \ = 0 @@ -7732,13 +2123,13 @@ DMA normally transfers bytes equal to the transaction size specified by \ = 0 and \ = 1. DMA signals the peripheral on an EOC and the peripheral interrupts the CPU to retrieve any trailing bytes. EOC is the only trailing-bytes case that requires programmed I/O to retrieve data. - + - **Request-after-channel-stops (RAS)** Status bit in the DMA Channel Control/Status Register 0-15. This bit is set when a peripheral asserts a DMA request after the channel to which the peripheral is mapped has stopped. Refer to Section [RNG BYTE COUNT REGISTER](#rng-byte-count-register) for DMA Channel Control/Status Register 0-15 for details. @@ -7767,459 +2158,100 @@ The Direct-Memory Access Controller (DMAC) transfers data to and from memory in The **DMA request numbers** for **non-secure DMA** peripherals are tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
DRQDescriptionComments
3Request for UART0 TxReqUART0 (0xD4017000)
4Request for UART0 RxReqUART0 (0xD4017000)
5Request for UART2 TxReqUART2 (0xD4017100)
6Request for UART2 RxReqUART2 (0xD4017100)
7Request for UART3 TxReqUART3 (0xD4017200)
8Request for UART3 RxReqUART3 (0xD4017200)
9Request for UART4 TxReqUART4 (0xD4017300)
10Request for UART4 RxReqUART4 (0xD4017300)
11Request for I2C0 TxReqI2C0 (0xD4010800)
12Request for I2C0 RxReqI2C0 (0xD4010800)
13Request for I2C1 TxReqI2C1 (0xD4011000)
14Request for I2C1 RxReqI2C1 (0xD4011000)
15Request for I2C2 TxReqI2C2 (0xD4012000)
16Request for I2C2 RxReqI2C2 (0xD4012000)
17Request for I2C4 TxReqI2C4 (0xD4012800)
18Request for I2C4 RxReqI2C4 (0xD4012800)
19Request for SPI3 TxReqSPI3 (0xD401C000)
20Request for SPI3 RxReqSPI3 (0xD401C000)
21Request for I2S0 TxReqI2S0 (0xD4026000)
22Request for I2S0 RxReqI2S0 (0xD4026000)
23Request for I2S1 TxReqI2S1 (0xD4026800)
24Request for I2S1 RxReqI2S1 (0xD4026800)
25Request for UART5 TxReqUART5 (0xD4017400)
26Request for UART5 RxReqUART5 (0xD4017400)
27Request for UART6 TxReqUART6 (0xD4017500)
28Request for UART6 RxReqUART6 (0xD4017500)
29Request for UART7 TxReqUART7 (0xD4017600)
30Request for UART7 RxReqUART7 (0xD4017600)
31Request for UART8 TxReqUART8 (0xD4017700)
32Request for UART8 RxReqUART8 (0xD4017700)
33Request for UART9 TxReqUART9 (0xD4017800)
34Request for UART9 RxReqUART9 (0xD4017800)
35Request for I2C5 TxReqI2C5 (0xD4013800)
36Request for I2C5 RxReqI2C5 (0xD4013800)
37Request for I2C6 TxReqI2C6 (0xD4018800)
38Request for I2C6 RxReqI2C6 (0xD4018800)
39Request for I2C7 TxReqI2C7 (0xD401d000)
40Request for I2C7 RxReqI2C7 (0xD401d000)
41Request for I2C8 TxReqI2C8 (0xD401d800)
42Request for I2C8 RxReqI2C8 (0xD401d800)
43Request for CAN0 RxReqCAN0 (0xD4028000)
44Request for QSPI RxReqQSPI (0xD420_C000)
45Request for QSPI TxReqQSPI (0xD420_C000)
+| DRQ | Description | Comments | +| --- | --- | --- | +| 3 | Request for UART0 TxReq | UART0 (0xD4017000) | +| 4 | Request for UART0 RxReq | UART0 (0xD4017000) | +| 5 | Request for UART2 TxReq | UART2 (0xD4017100) | +| 6 | Request for UART2 RxReq | UART2 (0xD4017100) | +| 7 | Request for UART3 TxReq | UART3 (0xD4017200) | +| 8 | Request for UART3 RxReq | UART3 (0xD4017200) | +| 9 | Request for UART4 TxReq | UART4 (0xD4017300) | +| 10 | Request for UART4 RxReq | UART4 (0xD4017300) | +| 11 | Request for I2C0 TxReq | I2C0 (0xD4010800) | +| 12 | Request for I2C0 RxReq | I2C0 (0xD4010800) | +| 13 | Request for I2C1 TxReq | I2C1 (0xD4011000) | +| 14 | Request for I2C1 RxReq | I2C1 (0xD4011000) | +| 15 | Request for I2C2 TxReq | I2C2 (0xD4012000) | +| 16 | Request for I2C2 RxReq | I2C2 (0xD4012000) | +| 17 | Request for I2C4 TxReq | I2C4 (0xD4012800) | +| 18 | Request for I2C4 RxReq | I2C4 (0xD4012800) | +| 19 | Request for SPI3 TxReq | SPI3 (0xD401C000) | +| 20 | Request for SPI3 RxReq | SPI3 (0xD401C000) | +| 21 | Request for I2S0 TxReq | I2S0 (0xD4026000) | +| 22 | Request for I2S0 RxReq | I2S0 (0xD4026000) | +| 23 | Request for I2S1 TxReq | I2S1 (0xD4026800) | +| 24 | Request for I2S1 RxReq | I2S1 (0xD4026800) | +| 25 | Request for UART5 TxReq | UART5 (0xD4017400) | +| 26 | Request for UART5 RxReq | UART5 (0xD4017400) | +| 27 | Request for UART6 TxReq | UART6 (0xD4017500) | +| 28 | Request for UART6 RxReq | UART6 (0xD4017500) | +| 29 | Request for UART7 TxReq | UART7 (0xD4017600) | +| 30 | Request for UART7 RxReq | UART7 (0xD4017600) | +| 31 | Request for UART8 TxReq | UART8 (0xD4017700) | +| 32 | Request for UART8 RxReq | UART8 (0xD4017700) | +| 33 | Request for UART9 TxReq | UART9 (0xD4017800) | +| 34 | Request for UART9 RxReq | UART9 (0xD4017800) | +| 35 | Request for I2C5 TxReq | I2C5 (0xD4013800) | +| 36 | Request for I2C5 RxReq | I2C5 (0xD4013800) | +| 37 | Request for I2C6 TxReq | I2C6 (0xD4018800) | +| 38 | Request for I2C6 RxReq | I2C6 (0xD4018800) | +| 39 | Request for I2C7 TxReq | I2C7 (0xD401d000) | +| 40 | Request for I2C7 RxReq | I2C7 (0xD401d000) | +| 41 | Request for I2C8 TxReq | I2C8 (0xD401d800) | +| 42 | Request for I2C8 RxReq | I2C8 (0xD401d800) | +| 43 | Request for CAN0 RxReq | CAN0 (0xD4028000) | +| 44 | Request for QSPI RxReq | QSPI (0xD420_C000) | +| 45 | Request for QSPI TxReq | QSPI (0xD420_C000) | Instead, the **DMA request numbers** for **secure DMA** peripherals are tabled below. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
DRQDescriptionComments
0Request for UART1 RxReqUART1 (0xF0612000)
1Request for UART1 TxReqUART1 (0xF0612000)
2Request for SPI2 RxReqSPI2(0xF0613000)
3Request for SPI2 TxReqSPI2 (0xF0613000)
4Request for I2C3 TxReqI2C3 (0xF0614000)
5Request for I2C3 RxReqI2C3 (0xF0614000)
+| DRQ | Description | Comments | +| --- | --- | --- | +| 0 | Request for UART1 RxReq | UART1 (0xF0612000) | +| 1 | Request for UART1 TxReq | UART1 (0xF0612000) | +| 2 | Request for SPI2 RxReq | SPI2(0xF0613000) | +| 3 | Request for SPI2 TxReq | SPI2 (0xF0613000) | +| 4 | Request for I2C3 TxReq | I2C3 (0xF0614000) | +| 5 | Request for I2C3 RxReq | I2C3 (0xF0614000) | ### 9.4.4 Register Description The base addresses of DMA registers are tabled below. - - - - - - - - - - - - - - - -
NameAddress
DMA_BASE 0xD4000000
DMA2_BASE0xF0600000
+| Name | Address | +| --- | --- | +| DMA_BASE | 0xD4000000 | +| DMA2_BASE | 0xF0600000 | #### DCSR_x REGISTER DMA channel control/status registers. These read/write registers contain the control and status bits for the channels. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0/0x4/0x8/0xC/0x10/0x14/0x18/0x1C/0x20/0x24/0x28/0x2C/0x30/0x34/0x38/0x3C
BitsFieldTypeResetDescription
31RUN
R/W0x0This field allows software to start or stop the DMA channel.
0: Stop the channel
1: Start the channel.
If it is cleared during a burst transfer, the burst completes before stopping.
If the channel is in a descriptor-fetch transfer and this field is set before writing a valid descriptor address to the DMA Descriptor Address Registers, no descriptor fetch occurs.
This bit automatically resets when cleared or when the channel stops normally. After stopping, the <STOPINTR> field is set. Software must poll <STOPINTR> to check the channel status or set <STOPIRQEN> to receive an interrupt when the channel stops.
30NODESCFETCHR/W0x0No-Descriptor Fetch
0: Descriptor-fetch transfer
1: No-descriptor-fetch transfer
This bit determines whether the channel operates with or without descriptors:
- When set (1), the channel functions as a simple channel with no descriptors. The DMA does not fetch descriptors when the <RUN> field is set or when the current transfer’s byte count reaches zero.
1. In this mode, software must manually configure the channel by writing to the DMA Source Address Registers, DMA Target Address Registers, and DMA Command Registers.
2. The DMA Descriptor Address Registers are not used and must not be written.
3. The <RUN> field must be set to start the transfer.
- When cleared (0), the DMAC initiates descriptor fetches:
1. When software writes to the DMA Descriptor Address Registers.
2. When the byte count for the current transfer reaches zero.
29STOPIRQENR/W0x0Stop Interrupt Enabled
This field controls whether an interrupt is generated when the <STOPINTR> field is set.
0: No interrupt is generated if the channel is uninitialized or stopped.
1: An interrupt is generated when the channel is uninitialized or stopped.
> Note. After a system reset, <STOPINTR> is set. If <STOPIRQEN> is already enabled before starting the channel, an interrupt is triggered immediately.
28EORIRQENR/W0x0Setting the End-of-Receive interrupt enable
This field triggers an interrupt on an EOR condition. Clearing this bit does not generate an EOR-related interrupt.
0: No interrupt is triggered even if the <EORINT> field is set
1: An Interrupt is triggered when <EORINT> is set
27EORJMPENR/W0x0Jump to the next descriptor on EOR
This field controls the descriptor flow when the mapped peripheral signals an EOR to the DMAC. See Descriptor Behavior on End-of-Receive (EOR) for the behavior of the descriptor during this condition.
> Note. This control bit has no effect on the channel for no-descriptor-fetch transfers (<NODESCFETCH> set). The DMAC completes the peripheral-to-memory data transfer on an EOR, regardless of this field.
0: DMAC holds the current descriptor and waits for the mapped peripheral to make another receive request.
1 = DMAC jumps to the channel's next descriptor on receiving an EOR from the mapped peripheral.
26EORSTOPENR/W0x0Stop channel on EOR
> Note. This field has no effect on the channel for no-descriptor-fetch transfers (<NODESCFETCH> set). The DMAC completes the peripheral-to-memory data transfer on an EOR, regardless of this field.
Setting this field causes the DMAC to stop the channel on an EOR and set the corresponding <STOPINTR> field. If the <STOPIRQEN> field is set when this field is set, an interrupt occurs.
0: DMAC holds the current descriptor and waits for the mapped peripheral to make another receive request.
1: DMAC stops the channel that receives an EOR from the mapped peripheral.
25SETCMPSTW0x0Set descriptor Compare Status
0: No effect on <CMPST>
1: Set <CMPST>，regardless of whether the descriptor is in compare mode (<CMPEN> = 0 in DMA Command Registers).
24CLRCMPSTW0x0Clear descriptor Compare Status
0: No effect on <CMPST>
1: Clear <CMPST>，regardless of compare mode configuration
23RASIRQENR/W0x0Request after channel stopped interrupt enable
0: No interrupt when a peripheral requests DMA after the channel stops
1: Triggers an interrupt in <CHLINTR> (DMA Interrupt Register) when a peripheral requests DMA after the channel stops.
22MASKRUNW0x0Mask <RUN> during a programmed I/O write to this register
0: Software (programmed I/O write) can modify <RUN> during a write transaction
1: Software (programmed I/O write) can not modify <RUN> during a write transaction
21
LPAE_ENR/W0x0Long Physical Address Extension (LPAE) enable
This bit enable Long Physical Address Extension feature for both descriptor mode and nondescriptor modes.
0: LPAE feature is disabled.
- For Descriptor mode, no need to program DDADR_H register. Descriptors should remain 4 words (32bits per word, aligned on a 16-byte boundary in memory).
- For Non-descriptor mode, no need to program DTADR_H and DSADR_H registers. No software SW changes required.
1: LPAE feature is enabled.
- For Descriptor mode, Software must program DADR_H register and prepare the 8 words (32bits per word, aligned on a 32-byte boundary in memory).
- For Non-descriptor mode, Software must program DTADR_H and DSADR_H registers.
- LPAE is a feature that can enable or disable DMA transfer. LPAE and non-LPAE transfers can be interleaved.
20:11RSVDR0Reserved for future use
10CMPSTR0x0Descriptor Compare Status
This field reflects the result of the most recent source and target compare operation in descriptor compare mode (CMPEN = 1 in the DMA Command Registers)
0: Indicates an unsuccessful address compare in descriptor-compare mode.
1: Indicates a successful compare of the current descriptor source and target addresses in descriptor-compare mode.
9EORINTR/W1C0x0End of Receive Interrupt EORINT pertains only to internal peripherals.
This field indicates the status of the mapped peripheral's receive data. It is set after the DMAC reads out the last trailing sample from the peripheral's receive FIFO. The Descriptor Behavior on End-of-Receive (EOR) figure illustrates the behavior of the descriptor during this condition.
0 = DMA continues with current descriptor because the internal peripheral is still actively receiving data
1 = Channel mapped internal peripheral has no data remaining in its receive FIFO and has completed all receive transactions. Refer to the description of <EORJMPEN> for the behavior of the DMAC during this condition.
- CMPST is updated only when CMPEN = 1.
- This field can be manually set by SETCMPST and cleared by CLRCMPST.
- If both SETCMPST and CLRCMPST are written simultaneously, SETCMPST takes priority.
- Do not modify this field while the channel is running (RUN = 1), as it may cause faulty descriptor behavior. Always stop the channel before updating this field.
8REQPENDR0x0Request Pending
This field indicates a pending request for the DMA channel.
0: No request is pending for the channel
1: A request is pending for the channel
- REQPEND is cleared for a channel if that channel has no pending request or the request has just been issued to the memory interface in case of a read or write from the external companion chip to memory.
- If the DREQ assertion sets REQPEND and <RUN> is cleared to stop that channel, REQPEND and the internal registers that hold the DREQ assertion information, do not remain set.
- If the channel is restarted, REQPEND must be reset by a descriptor that transfers dummy data (for example, a memory-to-memory transfer from a temporary location to another temporary location).
7:5RSVDR0Reserved for future use
4RASINTRR/W0x0Request after channel stopped
0: No interrupt
1: Interrupt occurred due to a peripheral request after the channel stopped
- This bit is reset by writing a 1.
3STOPINTRR0x1Stop Interrupt
This bit indicates the current state of the channel:
0: Channel is running
1: Channel is in uninitialized or stopped state
This is a read-only bit that reflects the channel state.
- Software must clear <STOPIRQEN> to reset the interrupt.
- Reprogramming the DMA Descriptor Address Registers and setting <RUN> restarts the channel.
- If <STOPIRQEN> is set, the DMAC generates an interrupt.
2ENDINTRR/W1C0x0End Interrupt
This field indicates that the current descriptor finished successfully and <ENDIRQEN> in the DMA Command Registers is set.
This field indicates the successful completion of the current descriptor in a DMA operation
0: No interrupt
1: An nterrupt occured due to the successful completion of the current transaction, and <LEN> field in DMA Command Registers is set to 0
1STARTINTRR/W1C0x0Start Interrupt
This field indicates the successful loading of the current descriptor in a DMA operation
0: No interrupt
1: An interrupt occurred due to the successful descriptor fetching, and <STARTIRQEN> in the DMA Command Registers is set
0BUSERRINTRR/W1C0x0Bus Error Interrupt
This field indicates an error during data transfer on the internal bus, potentially caused by an invalid descriptor source or target address (any address that is in the non-burstable or reserved space can cause a bus error on the system bus). Only one error per channel is logged, and the affected channel will not be updated until it is reprogrammed and the corresponding <RUN> field is set.
0 = No interrupt
1 = An Interrupt occurred due to a bus error
+Offset: 0x0/0x4/0x8/0xC/0x10/0x14/0x18/0x1C/0x20/0x24/0x28/0x2C/0x30/0x34/0x38/0x3C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | RUN | R/W | 0x0 | This field allows software to start or stop the DMA channel.0: Stop the channel1: Start the channel.If it is cleared during a burst transfer, the burst completes before stopping.If the channel is in a descriptor-fetch transfer and this field is set before writing a valid descriptor address to the DMA Descriptor Address Registers, no descriptor fetch occurs.This bit automatically resets when cleared or when the channel stops normally. After stopping, the field is set. Software must poll to check the channel status or set to receive an interrupt when the channel stops. | +| 30 | NODESCFETCH | R/W | 0x0 | No-Descriptor Fetch 0: Descriptor-fetch transfer 1: No-descriptor-fetch transferThis bit determines whether the channel operates with or without descriptors:- When set (1), the channel functions as a simple channel with no descriptors. The DMA does not fetch descriptors when the field is set or when the current transfer’s byte count reaches zero. 1. In this mode, software must manually configure the channel by writing to the DMA Source Address Registers, DMA Target Address Registers, and DMA Command Registers. 2. The DMA Descriptor Address Registers are not used and must not be written. 3. The field must be set to start the transfer.- When cleared (0), the DMAC initiates descriptor fetches: 1. When software writes to the DMA Descriptor Address Registers. 2. When the byte count for the current transfer reaches zero. | +| 29 | STOPIRQEN | R/W | 0x0 | Stop Interrupt Enabled This field controls whether an interrupt is generated when the field is set.0: No interrupt is generated if the channel is uninitialized or stopped.1: An interrupt is generated when the channel is uninitialized or stopped.> Note. After a system reset, is set. If is already enabled before starting the channel, an interrupt is triggered immediately. | +| 28 | EORIRQEN | R/W | 0x0 | Setting the End-of-Receive interrupt enableThis field triggers an interrupt on an EOR condition. Clearing this bit does not generate an EOR-related interrupt. 0: No interrupt is triggered even if the field is set 1: An Interrupt is triggered when is set | +| 27 | EORJMPEN | R/W | 0x0 | Jump to the next descriptor on EOR This field controls the descriptor flow when the mapped peripheral signals an EOR to the DMAC. See Descriptor Behavior on End-of-Receive (EOR) for the behavior of the descriptor during this condition. > Note. This control bit has no effect on the channel for no-descriptor-fetch transfers ( set). The DMAC completes the peripheral-to-memory data transfer on an EOR, regardless of this field. 0: DMAC holds the current descriptor and waits for the mapped peripheral to make another receive request. 1 = DMAC jumps to the channel's next descriptor on receiving an EOR from the mapped peripheral. | +| 26 | EORSTOPEN | R/W | 0x0 | Stop channel on EOR > Note. This field has no effect on the channel for no-descriptor-fetch transfers ( set). The DMAC completes the peripheral-to-memory data transfer on an EOR, regardless of this field. Setting this field causes the DMAC to stop the channel on an EOR and set the corresponding field. If the field is set when this field is set, an interrupt occurs. 0: DMAC holds the current descriptor and waits for the mapped peripheral to make another receive request. 1: DMAC stops the channel that receives an EOR from the mapped peripheral. | +| 25 | SETCMPST | W | 0x0 | Set descriptor Compare Status 0: No effect on 1: Set ，regardless of whether the descriptor is in compare mode ( = 0 in DMA Command Registers). | +| 24 | CLRCMPST | W | 0x0 | Clear descriptor Compare Status 0: No effect on 1: Clear ，regardless of compare mode configuration | +| 23 | RASIRQEN | R/W | 0x0 | Request after channel stopped interrupt enable 0: No interrupt when a peripheral requests DMA after the channel stops1: Triggers an interrupt in (DMA Interrupt Register) when a peripheral requests DMA after the channel stops. | +| 22 | MASKRUN | W | 0x0 | Mask during a programmed I/O write to this register 0: Software (programmed I/O write) can modify during a write transaction 1: Software (programmed I/O write) can not modify during a write transaction | +| 21 | LPAE_EN | R/W | 0x0 | Long Physical Address Extension (LPAE) enable This bit enable Long Physical Address Extension feature for both descriptor mode and nondescriptor modes. 0: LPAE feature is disabled. - For Descriptor mode, no need to program DDADR_H register. Descriptors should remain 4 words (32bits per word, aligned on a 16-byte boundary in memory). - For Non-descriptor mode, no need to program DTADR_H and DSADR_H registers. No software SW changes required. 1: LPAE feature is enabled. - For Descriptor mode, Software must program DADR_H register and prepare the 8 words (32bits per word, aligned on a 32-byte boundary in memory). - For Non-descriptor mode, Software must program DTADR_H and DSADR_H registers. - LPAE is a feature that can enable or disable DMA transfer. LPAE and non-LPAE transfers can be interleaved. | +| 20:11 | RSVD | R | 0 | Reserved for future use | +| 10 | CMPST | R | 0x0 | Descriptor Compare Status This field reflects the result of the most recent source and target compare operation in descriptor compare mode (CMPEN = 1 in the DMA Command Registers)0: Indicates an unsuccessful address compare in descriptor-compare mode. 1: Indicates a successful compare of the current descriptor source and target addresses in descriptor-compare mode. | +| 9 | EORINT | R/W1C | 0x0 | End of Receive Interrupt EORINT pertains only to internal peripherals. This field indicates the status of the mapped peripheral's receive data. It is set after the DMAC reads out the last trailing sample from the peripheral's receive FIFO. The Descriptor Behavior on End-of-Receive (EOR) figure illustrates the behavior of the descriptor during this condition. 0 = DMA continues with current descriptor because the internal peripheral is still actively receiving data 1 = Channel mapped internal peripheral has no data remaining in its receive FIFO and has completed all receive transactions. Refer to the description of for the behavior of the DMAC during this condition. - CMPST is updated only when CMPEN = 1.- This field can be manually set by SETCMPST and cleared by CLRCMPST.- If both SETCMPST and CLRCMPST are written simultaneously, SETCMPST takes priority.- Do not modify this field while the channel is running (RUN = 1), as it may cause faulty descriptor behavior. Always stop the channel before updating this field. | +| 8 | REQPEND | R | 0x0 | Request Pending This field indicates a pending request for the DMA channel. 0: No request is pending for the channel 1: A request is pending for the channel- REQPEND is cleared for a channel if that channel has no pending request or the request has just been issued to the memory interface in case of a read or write from the external companion chip to memory. - If the DREQ assertion sets REQPEND and is cleared to stop that channel, REQPEND and the internal registers that hold the DREQ assertion information, do not remain set. - If the channel is restarted, REQPEND must be reset by a descriptor that transfers dummy data (for example, a memory-to-memory transfer from a temporary location to another temporary location). | +| 7:5 | RSVD | R | 0 | Reserved for future use | +| 4 | RASINTR | R/W | 0x0 | Request after channel stopped 0: No interrupt 1: Interrupt occurred due to a peripheral request after the channel stopped - This bit is reset by writing a 1. | +| 3 | STOPINTR | R | 0x1 | Stop Interrupt This bit indicates the current state of the channel:0: Channel is running 1: Channel is in uninitialized or stopped stateThis is a read-only bit that reflects the channel state. - Software must clear to reset the interrupt. - Reprogramming the DMA Descriptor Address Registers and setting restarts the channel. - If is set, the DMAC generates an interrupt. | +| 2 | ENDINTR | R/W1C | 0x0 | End Interrupt This field indicates that the current descriptor finished successfully and in the DMA Command Registers is set. This field indicates the successful completion of the current descriptor in a DMA operation0: No interrupt 1: An nterrupt occured due to the successful completion of the current transaction, and field in DMA Command Registers is set to 0 | +| 1 | STARTINTR | R/W1C | 0x0 | Start Interrupt This field indicates the successful loading of the current descriptor in a DMA operation 0: No interrupt 1: An interrupt occurred due to the successful descriptor fetching, and in the DMA Command Registers is set | +| 0 | BUSERRINTR | R/W1C | 0x0 | Bus Error Interrupt This field indicates an error during data transfer on the internal bus, potentially caused by an invalid descriptor source or target address (any address that is in the non-burstable or reserved space can cause a bus error on the system bus). Only one error per channel is logged, and the affected channel will not be updated until it is reprogrammed and the corresponding field is set.0 = No interrupt 1 = An Interrupt occurred due to a bus error | #### DALGN REGISTER @@ -8234,74 +2266,22 @@ Clearing a bit position in this register will cause the DMAC to treat the corres This register must be updated before setting the \ field in the DMA Channel Control/Status Registers and then must not be altered until the channel stops. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xA0
BitsFieldTypeResetDescription
31:16RSVDR0Reserved for future use
15:0DALGNXR/W0x0Alignment control for channel x
0: Source and target addresses of channel x follow the default alignment (internal peripherals default to 4 byte alignment, external bus addresses default to 8 byte alignment)
1: Source and target addresses of channel x follow user-defined alignment (byte aligned)
+Offset: 0xA0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RSVD | R | 0 | Reserved for future use | +| 15:0 | DALGNX | R/W | 0x0 | Alignment control for channel x 0: Source and target addresses of channel x follow the default alignment (internal peripherals default to 4 byte alignment, external bus addresses default to 8 byte alignment) 1: Source and target addresses of channel x follow user-defined alignment (byte aligned) | #### DPCSR REGISTER DMA programmed I/O control status register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xA4
BitsFieldTypeResetDescription
31BRGSPLITR/W0x1Activate posted writes and split reads. Don’t care
30:1RSVDR0Reserved for future use
0BRGBUSYR0x0Bridge busy status. Don‘t care
+Offset: 0xA4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | BRGSPLIT | R/W | 0x1 | Activate posted writes and split reads. Don’t care | +| 30:1 | RSVD | R | 0 | Reserved for future use | +| 0 | BRGBUSY | R | 0x0 | Bridge busy status. Don‘t care | #### DRQSR REGISTER @@ -8313,48 +2293,13 @@ DMA Request Status Register. This register tracks the number of pending requests - The external companion chip must not exceed 31 pending requests at a given time. - This is a read/write register. Ignore reads from reserved bits. Write 0x0 to reserved bits. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xE0
BitsFieldTypeResetDescription
31:9RSVDR0Reserved for future use
8CLRW0x0Clearing pending request
This field clears all pending requests registered in <REQPEND>, which were made by the external DMA request pin (DREQ).
- Writing 0x1 to this field clears the <REQPEND> field to remove all pending requests.
- Writing 0x0 to this field has no effect.
Notes:
- This field can be used for clearing the requests if the channel mapped to DREQ was prematurely stopped by software.
- This field must be set only after the mapped channel has stopped (<STOPINTR> field in the DMA Channel Control/Status Registers is set).
- Clearing the requests of a running channel can cause unpredictable behavior.
0 = No effect on <REQPEND>
1 = Clear all pending requests registered in <REQPEND>
7:5RSVDR0Reserved for future use
4:0REQPENDR0x0Request pending
Indicates the number of pending requests on DREQ.
+Offset: 0xE0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:9 | RSVD | R | 0 | Reserved for future use | +| 8 | CLR | W | 0x0 | Clearing pending request This field clears all pending requests registered in , which were made by the external DMA request pin (DREQ).- Writing 0x1 to this field clears the field to remove all pending requests. - Writing 0x0 to this field has no effect. Notes:- This field can be used for clearing the requests if the channel mapped to DREQ was prematurely stopped by software. - This field must be set only after the mapped channel has stopped ( field in the DMA Channel Control/Status Registers is set). - Clearing the requests of a running channel can cause unpredictable behavior. 0 = No effect on 1 = Clear all pending requests registered in | +| 7:5 | RSVD | R | 0 | Reserved for future use | +| 4:0 | REQPEND | R | 0x0 | Request pending Indicates the number of pending requests on DREQ. | #### DINT REGISTER @@ -8369,81 +2314,23 @@ DMA Interrupt Register. This read-only register tracks the interrupt information All DMAC interrupts, except the one that corresponds to the \ field in the DMA Channel Control/Status Registers, are cleared by writing 1 to the corresponding interrupt bit in the DMA Channel Control/Status Registers. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xF0
BitsFieldTypeResetDescription
31:16RSVDR0Reserved for future use
15:0CHLINTRXR0x0Channel interrupt
This field indicates that DMA channel x has been interrupted.
0: No interrupt
1: Interrupt
+Offset: 0xF0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | RSVD | R | 0 | Reserved for future use | +| 15:0 | CHLINTRX | R | 0x0 | Channel interrupt This field indicates that DMA channel x has been interrupted. 0: No interrupt 1: Interrupt | #### DRCMR_x REGISTER DMA request to channel mapping registers. These registers map the DMA request to a channel. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x100/0x104/0x108/0x10C/0x110/0x114/0x118/0x11C/0x120/0x124/0x128/0x12C/
0x130/0x134/0x138/0x13C/0x140/0x144/0x148/0x14C/0x150/0x154/0x158/0x15C/
0x160/0x164/0x168/0x16C/0x170/0x174/0x178/0x17C/0x180/0x184/0x188/0x18C/
0x190/0x194/0x198/0x19C/0x1A0/0x1A4/0x1A8/0x1AC/0x1B0/0x1B4/0x1B8/0x1BC/
0x1C0/0x1C4/0x1C8/0x1CC
BitsFieldTypeResetDescription
31:8RSVDR0Reserved for future use
7MAPVLDR/W0x0Map valid channel
Defines whether the request is mapped to a valid channel.
0: Request is unmapped
1: Request is mapped to a valid channel indicated by <Channel number>
This bit can also be used to mask the request.
6:5RSVDR0Reserved for future use
4:0CHLNUMR/W0x0Channel number
Indicates the valid channel number if <Map valid channel> is set.
Note: Do not map two active requests to the same channel since it produces unpredictable results.
+Offset: 0x100/0x104/0x108/0x10C/0x110/0x114/0x118/0x11C/0x120/0x124/0x128/0x12C/0x130/0x134/0x138/0x13C/0x140/0x144/0x148/0x14C/0x150/0x154/0x158/0x15C/0x160/0x164/0x168/0x16C/0x170/0x174/0x178/0x17C/0x180/0x184/0x188/0x18C/0x190/0x194/0x198/0x19C/0x1A0/0x1A4/0x1A8/0x1AC/0x1B0/0x1B4/0x1B8/0x1BC/0x1C0/0x1C4/0x1C8/0x1CC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | RSVD | R | 0 | Reserved for future use | +| 7 | MAPVLD | R/W | 0x0 | Map valid channel Defines whether the request is mapped to a valid channel. 0: Request is unmapped 1: Request is mapped to a valid channel indicated by This bit can also be used to mask the request. | +| 6:5 | RSVD | R | 0 | Reserved for future use | +| 4:0 | CHLNUM | R/W | 0x0 | Channel number Indicates the valid channel number if is set. Note: Do not map two active requests to the same channel since it produces unpredictable results. | #### DDADR_L_x REGISTER @@ -8457,48 +2344,13 @@ DMA Descriptor Address Registers. These registers store the memory address of th These registers are reserved if the channel is performing a no-descriptor-fetch transaction. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x200/0x210/0x220/0x230/0x240/0x250/0x260/0x270/0x280/0x290/0x2A0/0x2B0/0x2C0/0x2D0/0x2E0/0x2F0
BitsFieldTypeResetDescription
31:4DDADR_LR/W0x0Descriptor address
It contains the address of the next descriptor.
3:2RSVDR0Reserved for future use
1BRENR/W0x0Enable Descriptor Branch
This field controls descriptor branching and works with the <Descriptor compare status> field in the DMA Channel Control/Status Registers (0-31) to determine which descriptor is fetched next.
- If both this field and <Descriptor compare status> are set, the DMAC fetches the next descriptor from (DDADRx + 32 bytes).
- If either of the bits is cleared, DMAC fetches the next descriptor from the DMA Descriptor Address Registers.
- This field is relevant only for descriptor-fetch transactions (when <No-Descriptor Fetch> field in the DMA Channel Control/Status Registers 0-31 = 0).
0: Disable descriptor branching. Fetch the next descriptor from DDADRx.
1: Enable descriptor branching. Fetch the next descriptor from DDADRx + 32 bytes
0STOPR/W0x0Stop
It controls whether the channel stops after processing the current descriptor
0: Continue running.
1: Stop after completing the current descriptor (when <Length of the transfer in bytes> field in DMA Command Registers 0-31 = 0).
+Offset: 0x200/0x210/0x220/0x230/0x240/0x250/0x260/0x270/0x280/0x290/0x2A0/0x2B0/0x2C0/0x2D0/0x2E0/0x2F0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | DDADR_L | R/W | 0x0 | Descriptor address It contains the address of the next descriptor. | +| 3:2 | RSVD | R | 0 | Reserved for future use | +| 1 | BREN | R/W | 0x0 | Enable Descriptor Branch This field controls descriptor branching and works with the field in the DMA Channel Control/Status Registers (0-31) to determine which descriptor is fetched next. - If both this field and are set, the DMAC fetches the next descriptor from (DDADRx + 32 bytes). - If either of the bits is cleared, DMAC fetches the next descriptor from the DMA Descriptor Address Registers. - This field is relevant only for descriptor-fetch transactions (when field in the DMA Channel Control/Status Registers 0-31 = 0). 0: Disable descriptor branching. Fetch the next descriptor from DDADRx. 1: Enable descriptor branching. Fetch the next descriptor from DDADRx + 32 bytes | +| 0 | STOP | R/W | 0x0 | Stop It controls whether the channel stops after processing the current descriptor0: Continue running.1: Stop after completing the current descriptor (when field in DMA Command Registers 0-31 = 0). | #### DSADR_L_x REGISTER @@ -8513,41 +2365,12 @@ DMA source address registers. These registers are read-only for descriptor-fetch If the source address refers to a memory location and the Alignment register is properly configured, it can be aligned to a byte boundary (refer to Section [RNG SOURCE ADDRESS REGISTER](#rng-source-address-register) for DMA Alignment Register for more details). Otherwise, if the Alignment register is not configured correctly, the source address defaults to an 8-byte boundary. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x204/0x214/0x224/0x234/0x244/0x254/0x264/0x274/0x284/0x294/0x2A4/0x2B4/0x2C4/0x2D4/0x2E4/0x2F4
BitsFieldTypeResetDescription
31:3SRCADDRR/W0x0Source address of the on-chip peripheral, external peripheral, companion chip, or address of a memory location
2SRCADDR2R/W0x0
Relevant if <Source address> is a memory location and alignment register is configured.
Refer to Section [RNG SOURCE ADDRESS REGISTER](#rng-source-address-register)for DMA Alignment Register for programming details and restrictions.
1:0SRCADDR0R/W0x0Relevant if <Source address> is a memory location and alignment register is configured.
Refer to Section [RNG SOURCE ADDRESS REGISTER](#rng-source-address-register) for DMA Alignment Register for programming details and restrictions.
+Offset: 0x204/0x214/0x224/0x234/0x244/0x254/0x264/0x274/0x284/0x294/0x2A4/0x2B4/0x2C4/0x2D4/0x2E4/0x2F4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | SRCADDR | R/W | 0x0 | Source address of the on-chip peripheral, external peripheral, companion chip, or address of a memory location | +| 2 | SRCADDR2 | R/W | 0x0 | Relevant if is a memory location and alignment register is configured. Refer to Section [RNG SOURCE ADDRESS REGISTER](#rng-source-address-register)for DMA Alignment Register for programming details and restrictions. | +| 1:0 | SRCADDR0 | R/W | 0x0 | Relevant if is a memory location and alignment register is configured. Refer to Section [RNG SOURCE ADDRESS REGISTER](#rng-source-address-register) for DMA Alignment Register for programming details and restrictions. | #### DTADR_L_x REGISTER @@ -8562,165 +2385,35 @@ DMA Target Address registers. These registers are read-only for descriptor-fetch If the source address refers to a memory location and the Alignment register is properly configured, it can be aligned to a byte boundary (refer to Section [RNG SOURCE ADDRESS REGISTER](#rng-source-address-register) about DMA Alignment Register for more details). Otherwise, if the Alignment register is not configured correctly, the source address defaults to an 8-byte boundary. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x208/0x218/0x228/0x238/0x248/0x258/0x268/0x278/0x288/0x298/0x2A8/0x2B8/0x2C8/0x2D8/0x2E8/0x2F8
BitsFieldTypeResetDescription
31:3TRGADDRR/W0x0Target address of the on-chip peripheral, external peripheral, companion chip, or address of a memory location
2TRGADDR2R/W0x0Relevant if <Target address> is a memory location and alignment register is configured.
Refer to Section [RNG SOURCE ADDRESS REGISTER](#rng-source-address-register) for DMA Alignment Register for programming details and restrictions.
1:0TRGADDR0R/W0x0Relevant if <Target address> is a memory location and alignment register is configured.
Refer to Section [RNG SOURCE ADDRESS REGISTER](#rng-source-address-register) for DMA Alignment Register for programming details and restrictions.
+Offset: 0x208/0x218/0x228/0x238/0x248/0x258/0x268/0x278/0x288/0x298/0x2A8/0x2B8/0x2C8/0x2D8/0x2E8/0x2F8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | TRGADDR | R/W | 0x0 | Target address of the on-chip peripheral, external peripheral, companion chip, or address of a memory location | +| 2 | TRGADDR2 | R/W | 0x0 | Relevant if is a memory location and alignment register is configured. Refer to Section [RNG SOURCE ADDRESS REGISTER](#rng-source-address-register) for DMA Alignment Register for programming details and restrictions. | +| 1:0 | TRGADDR0 | R/W | 0x0 | Relevant if is a memory location and alignment register is configured. Refer to Section [RNG SOURCE ADDRESS REGISTER](#rng-source-address-register) for DMA Alignment Register for programming details and restrictions. | #### DCMD_x REGISTER DMA Command registers. These read-only registers are for descriptor-fetch transfers and read/write for no-descriptor-fetch transfers. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x20C/0x21C/0x22C/0x23C/0x24C/0x25C/0x26C/0x27C/0x28C/0x29C/0x2AC/0x2BC/0x2CC/0x2DC/0x2EC/0x2FC
BitsFieldTypeResetDescription
31INCSRCADDRR/W0x0Source address increment
Controls whether the source address increments on each successive access.
0: No increment (use for internal peripheral FIFO or external I/O addresses).
1: Increment source address.
30INCTRGADDRR/W0x0Target address increment
Controls whether the target address increments on each successive access.
0: No increment (use for internal peripheral FIFO or external I/O addresses).
1: Increment target address.
29FLOWSRCR/W0x0Source flow control
Use when the source is an on-chip peripheral or external companion chip.
0: Start data transfer without waiting for request signals
1: Wait for a request signal before initiating the data transfer
> Note. Do not set this field if <FLOWSRC> is already set , as it may cause unpredictable behavior.
28FLOWTRGR/W0x0Target flow control
Use when the target is an on-chip peripheral or external companion chip.
0: Start data transfer without waiting for request signals
1: Wait for a request signal before initiating the data transfer
> Note. Do not set this field if <FLOWTAG> is already set, as it may cause unpredictable behavior.
27:26RSVDR0Reserved for future use
25CMPENR/W0x0Descriptor Compare enable
This field must be cleared for normal DMA operations. Setting the field enables the descriptor-compare mode, in which the DMAC treats the current descriptor as a special case and compares data that corresponds to the source and target fields. <ADDRMODE> is used to determine the addressing mode before the Compare operation.
0: DMA does not perform any address-compare operations
1: DMA recognizes the current descriptor as a special case and compares data based on the source address and target address fields.
- If the compare is true, the channel's <CMPST> field in the DMA Channel Control/Status Registers is set.
- If the compare is false, <CMPST> is cleared.
24RSVDR0Reserved for future use
23ADDRMODER/W0x0Addressing mode
This field controls the addressing mode for descriptor comparison and is valid only in the descriptor compare mode (<CMPEN> = 1).
- Reserved if <CMPEN> = 0.
- If <CMPEN> is set, this bit specifies the addressing modes of the source address and target address fields.
- If either field contains an address, the DMAC fetches the data at that address and uses it for the compare operation.
0: Source address field contains address, and target address field contains address
1: Source address field contains address, and target address field contains data
- If DALGN is clear, then the lowest three bits of immediate data are forced to be 0 before comparison.
- If DALGN is set, then the lowest three bits of immediate data are not forced to be 0 before comparison.
22STARTIRQENR/W0x0Start interrupt enable
This field indicates that the interrupt is enabled when the descriptor is loaded. In no-descriptor-fetch transfers, this field is reserved.
0: Interrupt is not triggered after descriptor is loaded
1: Sets interrupt bit for the channel in the <CHLINTRX> field in the DMA Interrupt Register when the descriptor for the channel is loaded
21ENDIRQENR/W0x0End interrupt enable
0: Interrupt is not triggered when LENGTH decrements to zero.
1: Sets the DINT interrupt bit for the channel when LENGTH decrements to zero.
20:19RSVDR0Reserved for future use
18:16DMA_SIZER/W0x0Maximum burst size
Maximum burst size of each data transfer
- 0x0 = Reserved
- 0x1 = 8 bytes
- 0x2 = 16 bytes
- 0x3 = 32 bytes
- 0x4 = 64 bytes
The size must be less than or equal to the serviced peripheral FIFO trigger threshold to properly handle the respective FIFO trailing bytes.
15:14WIDTHR/W0x0Width of the on-chip peripheral
This field is reserved for operations that do not involve on-chip peripherals, such as memory-to-memory moves and companion-chip-related operations.
0x0 = Reserved for on-chip peripheral-related transactions
0x1 = 1 byte
0x2 = half-word (2 bytes)
0x3 = word (4 bytes)
Note: For memory-to-memory moves or companion-chip-related operations, this field must be set to 0x0.
13RSVDR0Reserved for future use
12:0LENR/W0x0Length of the transfer in bytes
This field is the length of transfer in bytes.
- LEN = 0:
1. In descriptor-fetch mode, LEN = 0 signifies no byte transfer. when <CMPEN> is clear (normal data transfer mode) causes the channel to immediately discard the descriptor after it is fetched from memory. If the descriptor chain has more descriptors, the channel fetches the next valid descriptor. The channel stops if the descriptor chain has no more descriptors.
2. In no-descriptor-fetch mode, LEN = 0 is an invalid setting.
- Maximum Transfer Length:
1. The maximum transfer length is (8K-1) bytes.
2. If the transfer is of the memory-to-memory type, the length of the transfer may be any value (except for the LEN = 0 restriction in no-descriptor-fetch mode) up to a maximum of (8K -1) bytes.
- For memory-to-memory:
1. The length of the transfer may be any value (except for the LEN = 0 restriction in no-descriptor-fetch mode) up to a maximum of (8K -1) bytes.
- For Peripherals:
1. The length of the transfer must be an integer multiple of the peripheral FIFO threshold (or water-mark).
+Offset: 0x20C/0x21C/0x22C/0x23C/0x24C/0x25C/0x26C/0x27C/0x28C/0x29C/0x2AC/0x2BC/0x2CC/0x2DC/0x2EC/0x2FC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | INCSRCADDR | R/W | 0x0 | Source address increment Controls whether the source address increments on each successive access.0: No increment (use for internal peripheral FIFO or external I/O addresses).1: Increment source address. | +| 30 | INCTRGADDR | R/W | 0x0 | Target address increment Controls whether the target address increments on each successive access.0: No increment (use for internal peripheral FIFO or external I/O addresses).1: Increment target address. | +| 29 | FLOWSRC | R/W | 0x0 | Source flow control Use when the source is an on-chip peripheral or external companion chip.0: Start data transfer without waiting for request signals1: Wait for a request signal before initiating the data transfer> Note. Do not set this field if is already set , as it may cause unpredictable behavior. | +| 28 | FLOWTRG | R/W | 0x0 | Target flow control Use when the target is an on-chip peripheral or external companion chip. 0: Start data transfer without waiting for request signals 1: Wait for a request signal before initiating the data transfer > Note. Do not set this field if is already set, as it may cause unpredictable behavior. | +| 27:26 | RSVD | R | 0 | Reserved for future use | +| 25 | CMPEN | R/W | 0x0 | Descriptor Compare enable This field must be cleared for normal DMA operations. Setting the field enables the descriptor-compare mode, in which the DMAC treats the current descriptor as a special case and compares data that corresponds to the source and target fields. is used to determine the addressing mode before the Compare operation. 0: DMA does not perform any address-compare operations 1: DMA recognizes the current descriptor as a special case and compares data based on the source address and target address fields. - If the compare is true, the channel's field in the DMA Channel Control/Status Registers is set. - If the compare is false, is cleared. | +| 24 | RSVD | R | 0 | Reserved for future use | +| 23 | ADDRMODE | R/W | 0x0 | Addressing mode This field controls the addressing mode for descriptor comparison and is valid only in the descriptor compare mode ( = 1). - Reserved if = 0. - If is set, this bit specifies the addressing modes of the source address and target address fields. - If either field contains an address, the DMAC fetches the data at that address and uses it for the compare operation. 0: Source address field contains address, and target address field contains address 1: Source address field contains address, and target address field contains data - If DALGN is clear, then the lowest three bits of immediate data are forced to be 0 before comparison. - If DALGN is set, then the lowest three bits of immediate data are not forced to be 0 before comparison. | +| 22 | STARTIRQEN | R/W | 0x0 | Start interrupt enable This field indicates that the interrupt is enabled when the descriptor is loaded. In no-descriptor-fetch transfers, this field is reserved. 0: Interrupt is not triggered after descriptor is loaded 1: Sets interrupt bit for the channel in the field in the DMA Interrupt Register when the descriptor for the channel is loaded | +| 21 | ENDIRQEN | R/W | 0x0 | End interrupt enable 0: Interrupt is not triggered when LENGTH decrements to zero. 1: Sets the DINT interrupt bit for the channel when LENGTH decrements to zero. | +| 20:19 | RSVD | R | 0 | Reserved for future use | +| 18:16 | DMA_SIZE | R/W | 0x0 | Maximum burst size Maximum burst size of each data transfer - 0x0 = Reserved - 0x1 = 8 bytes - 0x2 = 16 bytes - 0x3 = 32 bytes - 0x4 = 64 bytes The size must be less than or equal to the serviced peripheral FIFO trigger threshold to properly handle the respective FIFO trailing bytes. | +| 15:14 | WIDTH | R/W | 0x0 | Width of the on-chip peripheral This field is reserved for operations that do not involve on-chip peripherals, such as memory-to-memory moves and companion-chip-related operations. 0x0 = Reserved for on-chip peripheral-related transactions 0x1 = 1 byte 0x2 = half-word (2 bytes) 0x3 = word (4 bytes) Note: For memory-to-memory moves or companion-chip-related operations, this field must be set to 0x0. | +| 13 | RSVD | R | 0 | Reserved for future use | +| 12:0 | LEN | R/W | 0x0 | Length of the transfer in bytes This field is the length of transfer in bytes. - LEN = 0: 1. In descriptor-fetch mode, LEN = 0 signifies no byte transfer. when is clear (normal data transfer mode) causes the channel to immediately discard the descriptor after it is fetched from memory. If the descriptor chain has more descriptors, the channel fetches the next valid descriptor. The channel stops if the descriptor chain has no more descriptors. 2. In no-descriptor-fetch mode, LEN = 0 is an invalid setting.- Maximum Transfer Length: 1. The maximum transfer length is (8K-1) bytes. 2. If the transfer is of the memory-to-memory type, the length of the transfer may be any value (except for the LEN = 0 restriction in no-descriptor-fetch mode) up to a maximum of (8K -1) bytes. - For memory-to-memory: 1. The length of the transfer may be any value (except for the LEN = 0 restriction in no-descriptor-fetch mode) up to a maximum of (8K -1) bytes. - For Peripherals: 1. The length of the transfer must be an integer multiple of the peripheral FIFO threshold (or water-mark). | #### DDADR_H_x REGISTER @@ -8728,34 +2421,11 @@ DMA descriptor address higher bits registers. These registers contain the higher > **Note.** These registers can not contain addresses of any other internal peripheral register or DMA register, as this will cause a bus error. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x300/0x310/0x320/0x330/0x340/0x350/0x360/0x370/0x380/0x390/0x3A0/0x3B0/0x3C0/0x3D0/0x3E0/0x3F0
BitsFieldTypeResetDescription
31:8RSVDR0Reserved for future use
7:0DDADR_HR/W0x0Descriptor address higher bits [39:32].
Contains address of next descriptor higher bits [39:32]
+Offset: 0x300/0x310/0x320/0x330/0x340/0x350/0x360/0x370/0x380/0x390/0x3A0/0x3B0/0x3C0/0x3D0/0x3E0/0x3F0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | RSVD | R | 0 | Reserved for future use | +| 7:0 | DDADR_H | R/W | 0x0 | Descriptor address higher bits [39:32]. Contains address of next descriptor higher bits [39:32] | #### DSADR_H_x REGISTER @@ -8768,34 +2438,11 @@ DMA source address higher bits registers. These registers are read-only for desc > **Note.** These registers can not contain addresses of any other internal peripheral register or DMA register, as this will cause a bus error. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x304/0x314/0x324/0x334/0x344/0x354/0x364/0x374/0x384/0x394/0x3A4/0x3B4/0x3C4/0x3D4/0x3E4/0x3F4
BitsFieldTypeResetDescription
31:8RSVDR0Reserved for future use
7:0SOURCE_ADD_RESS_HR/W0x0Source address higher bits[39:32]
Contains address of source higher bits[39:32].
+Offset: 0x304/0x314/0x324/0x334/0x344/0x354/0x364/0x374/0x384/0x394/0x3A4/0x3B4/0x3C4/0x3D4/0x3E4/0x3F4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | RSVD | R | 0 | Reserved for future use | +| 7:0 | SOURCE_ADD_RESS_H | R/W | 0x0 | Source address higher bits[39:32] Contains address of source higher bits[39:32]. | #### DTADR_H_x REGISTER @@ -8808,34 +2455,11 @@ DMA target address higher bits registers. These registers are read-only for desc > **Note.** These registers can not contain addresses of any other internal peripheral register or DMA register, as this will cause a bus error. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x308/0x318/0x328/0x338/0x348/0x358/0x368/0x378/0x388/0x398/0x3A8/0x3B8/0x3C8/0x3D8/0x3E8/0x3F8
BitsFieldTypeResetDescription
31:8RSVDR0Reserved for future use
7:0TARGET_ADD_RESS_HR/W0x0Target address higher bits[39:32]
Contains address of target higher bits[39:32].
+Offset: 0x308/0x318/0x328/0x338/0x348/0x358/0x368/0x378/0x388/0x398/0x3A8/0x3B8/0x3C8/0x3D8/0x3E8/0x3F8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | RSVD | R | 0 | Reserved for future use | +| 7:0 | TARGET_ADD_RESS_H | R/W | 0x0 | Target address higher bits[39:32] Contains address of target higher bits[39:32]. | ## 9.5 Crypto @@ -8860,636 +2484,147 @@ The base address of TRNG registers is **0xF0703800**. #### RNG BYTE COUNT REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31:16ReservedRO
0x0Reserved
15:0RNG Byte CountRW0x0Bytes of data that the DMA channel must transfer.
+Offset: 0x4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0x0 | Reserved | +| 15:0 | RNG Byte Count | RW | 0x0 | Bytes of data that the DMA channel must transfer. | #### RNG SOURCE ADDRESS REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14
BitsFieldTypeResetDescription
31:0
RNG sourceaddressRW0x0Not used.
All data is from the RNG generator engine inside the RNG module.
+Offset: 0x14 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RNG sourceaddress | RW | 0x0 | Not used. All data is from the RNG generator engine inside the RNG module. | #### RNG DESTINATION ADDRESS REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x24
BitsFieldTypeResetDescription
31:0RNG destination addressRW0x0RNG data output destination address.
+Offset: 0x24 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RNG destination address | RW | 0x0 | RNG data output destination address. | #### RNG NEXT DESCRIPTOR POINTER REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x34
BitsFieldTypeResetDescription
31:0RNG next descriptor pointer addressRW
0x0
Channel 0 next descriptor pointer address.
- This must be 16 bytes aligned.
- The register contains a 32-bit address where the value for the next DMA channel descriptor can be loaded for chain operation.
- The next descriptor can be stored in either SDRAM or SRAM.
- The byte count, source address, destination address, and next descriptor pointer must be located at sequential addresses.
- This register is only used when the channel is configured for Chain mode.
+Offset: 0x34 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RNG next descriptor pointer address | RW | 0x0 | Channel 0 next descriptor pointer address. - This must be 16 bytes aligned. - The register contains a 32-bit address where the value for the next DMA channel descriptor can be loaded for chain operation. - The next descriptor can be stored in either SDRAM or SRAM. - The byte count, source address, destination address, and next descriptor pointer must be located at sequential addresses. - This register is only used when the channel is configured for Chain mode. | #### RNG CONTROL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x44
BitsFieldTypeResetDescription
31ReservedRO
0x0Reserved
30RNG fifo clearWO0x0Write to clear RNG RX FIFO
29:22RNG fifo thresholdRW0xfThe threshold of FIFO for data transmit request
21:17ReservedRO
0x0Reserved
16Channel abortRW0x0- Setting this bit to 1 forces the DMA to abort the current transfer immediately.
- This bit is automatically cleared by the DMA hardware after the abort operation is completed.
15Close descriptor enableRW0x0If enabled, the DMA writes the remainder byte count into bits [31:16] of the byte count field.
0: Disable
1: Enable
14Source/Destination address alignmentRW0x00: Alignment towards the source. After the DMA's first read, all reads will be to 128-bit aligned address.
1: Alignment towards the destination. After the first write, the following writes will be with all Byte Enables asserted.
13DMA channel activeRO0x00: Channel is not active
1: Channel is active
12Fetch next descriptorRW0x01: Force a fetch of the next descriptor.
This field is automatically cleared after the fetch completes.
11TransModRW0x00: External DMA_REQ access mode
10Interrupt modeRW0x00: Interrupt asserted every time the DMA byte count reaches 0
1: Interrupt asserted only when the next descriptor pointer value is NULL and the DMA byte count reaches 0
9Chain modeRW0x00: Chain mode
1: Non-chain mode
8:6Burst Limit in each DMA accessRW0x0- 0x0: 1 byte
- 0x1: 2 byte
- 0x2: 4 byte
- 0x3: 8 byte
- 0x4: 16 byte
- 0x5: 32 byte
- 0x6: 64 byte
- 0x7: 128 byte
5:4Destination directionRW0x0- 0x0: Increment destination address
- 0x1: Decrement destination address
- 0x2: Hold in the same value
- 0x3: Reserved
3:2Source direction RW0x0- 0x0: Increment source address
- 0x1: Decrement source address
- 0x2: Hold in the same value
- 0x3: Reserved
1SSPModRW0x01: SSP FIFO access
0Channel EnableRW0x01: Activates the channel. This bit is automatically cleared when the DMA transfer is complete.
0: Suspends the channel.
> Note. If the channel is suspended, setting this bit to 1 again allows the DMA transfer to continue.
+Offset: 0x44 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Reserved | RO | 0x0 | Reserved | +| 30 | RNG fifo clear | WO | 0x0 | Write to clear RNG RX FIFO | +| 29:22 | RNG fifo threshold | RW | 0xf | The threshold of FIFO for data transmit request | +| 21:17 | Reserved | RO | 0x0 | Reserved | +| 16 | Channel abort | RW | 0x0 | - Setting this bit to 1 forces the DMA to abort the current transfer immediately.- This bit is automatically cleared by the DMA hardware after the abort operation is completed. | +| 15 | Close descriptor enable | RW | 0x0 | If enabled, the DMA writes the remainder byte count into bits [31:16] of the byte count field. 0: Disable1: Enable | +| 14 | Source/Destination address alignment | RW | 0x0 | 0: Alignment towards the source. After the DMA's first read, all reads will be to 128-bit aligned address.1: Alignment towards the destination. After the first write, the following writes will be with all Byte Enables asserted. | +| 13 | DMA channel active | RO | 0x0 | 0: Channel is not active1: Channel is active | +| 12 | Fetch next descriptor | RW | 0x0 | 1: Force a fetch of the next descriptor. This field is automatically cleared after the fetch completes. | +| 11 | TransMod | RW | 0x0 | 0: External DMA_REQ access mode | +| 10 | Interrupt mode | RW | 0x0 | 0: Interrupt asserted every time the DMA byte count reaches 01: Interrupt asserted only when the next descriptor pointer value is NULL and the DMA byte count reaches 0 | +| 9 | Chain mode | RW | 0x0 | 0: Chain mode1: Non-chain mode | +| 8:6 | Burst Limit in each DMA access | RW | 0x0 | - 0x0: 1 byte- 0x1: 2 byte- 0x2: 4 byte- 0x3: 8 byte- 0x4: 16 byte- 0x5: 32 byte- 0x6: 64 byte- 0x7: 128 byte | +| 5:4 | Destination direction | RW | 0x0 | - 0x0: Increment destination address- 0x1: Decrement destination address- 0x2: Hold in the same value- 0x3: Reserved | +| 3:2 | Source direction | RW | 0x0 | - 0x0: Increment source address- 0x1: Decrement source address- 0x2: Hold in the same value- 0x3: Reserved | +| 1 | SSPMod | RW | 0x0 | 1: SSP FIFO access | +| 0 | Channel Enable | RW | 0x0 | 1: Activates the channel. This bit is automatically cleared when the DMA transfer is complete.0: Suspends the channel.> Note. If the channel is suspended, setting this bit to 1 again allows the DMA transfer to continue. | #### RNG CURRENT DESCRIPTOR POINTER REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x74
BitsFieldTypeResetDescription
31:0RNG current descriptor pointer addressRO0x0This register is used for closing the current descriptor before fetching the next descriptor.
- When the processor writes the next descriptor pointer register, the current descriptor pointer register will reload itself with the same value written to the next descriptor pointer register.
- After processing a descriptor, the DMA channel:
1. updates the current descriptor using the current descriptor pointer register.
2. saves the next descriptor pointer register into the current descriptor pointer register.
3. and fetches a new descriptor for processing.
+Offset: 0x74 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | RNG current descriptor pointer address | RO | 0x0 | This register is used for closing the current descriptor before fetching the next descriptor. - When the processor writes the next descriptor pointer register, the current descriptor pointer register will reload itself with the same value written to the next descriptor pointer register. - After processing a descriptor, the DMA channel: 1. updates the current descriptor using the current descriptor pointer register. 2. saves the next descriptor pointer register into the current descriptor pointer register. 3. and fetches a new descriptor for processing. | #### RNG INTERRUPT MASK REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x84
BitsFieldTypeResetDescription
31:2ReservedRO0x0Reserved
1RNG DMA aborted interrupt maskRW0x01: Channel 1 DMA aborted interrupt is enabled
0RNG interrupt done maskRW0x01: Channel 1 Comp interrupt is enabled
+Offset: 0x84 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | RO | 0x0 | Reserved | +| 1 | RNG DMA aborted interrupt mask | RW | 0x0 | 1: Channel 1 DMA aborted interrupt is enabled | +| 0 | RNG interrupt done mask | RW | 0x0 | 1: Channel 1 Comp interrupt is enabled | #### RNG RESET SELECT REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x94
BitsFieldTypeResetDescription
31:2ReservedRO0x0Reserved
1:0RNG reset select addressRW0x0The bits in this register correspond to the bits in the RNT_INT_STATUS register.
Setting a bit to 1 enables its corresponding RNT_INT_STATUS bit read clear function.
+Offset: 0x94 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | RO | 0x0 | Reserved | +| 1:0 | RNG reset select address | RW | 0x0 | The bits in this register correspond to the bits in the RNT_INT_STATUS register.Setting a bit to 1 enables its corresponding RNT_INT_STATUS bit read clear function. | #### RNG INTERRUPT STATUS REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xA4
BitsFieldTypeResetDescription
31:2ReservedRO0x0Reserved
1DMA abort interrupt status and clearRW0x0Read clear in this field is enabled through the corresponding RSR bit setting in the RNG_RSR register.
0Interrupt doneRW0x0Read clear in this field is enabled through the corresponding RSR bit setting in the RNG_RSR register.
+Offset: 0xA4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | RO | 0x0 | Reserved | +| 1 | DMA abort interrupt status and clear | RW | 0x0 | Read clear in this field is enabled through the corresponding RSR bit setting in the RNG_RSR register. | +| 0 | Interrupt done | RW | 0x0 | Read clear in this field is enabled through the corresponding RSR bit setting in the RNG_RSR register. | #### PRNG CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0
BitsFieldTypeResetDescription
31
PRNG validRO0x01'b1: PRNG is valid, and PRNG data can be read from PRNG result low and high registers.
30:9
ReservedRO0x0Reserved
8:1
PRNG Register CTRLRW0x1APlease keep the default value for current design.
0PRNG enableRW0x0Enable PRNG
+Offset: 0xC0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | PRNG valid | RO | 0x0 | 1'b1: PRNG is valid, and PRNG data can be read from PRNG result low and high registers. | +| 30:9 | Reserved | RO | 0x0 | Reserved | +| 8:1 | PRNG Register CTRL | RW | 0x1A | Please keep the default value for current design. | +| 0 | PRNG enable | RW | 0x0 | Enable PRNG | #### PRNG LOW REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC4
BitsFieldTypeResetDescription
31:0
PRNG data low bitsRO0x0PRNG result data bit [31:0].
+Offset: 0xC4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | PRNG data low bits | RO | 0x0 | PRNG result data bit [31:0]. | #### PRNG HIGH REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC8
BitsFieldTypeResetDescription
31:8
ReservedRO0x0Reserved
7:0
PRNG data high bitsRO0x0PRNG result data bit [39:32].
+Offset: 0xC8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | Reserved | RO | 0x0 | Reserved | +| 7:0 | PRNG data high bits | RO | 0x0 | PRNG result data bit [39:32]. | #### TRNG CTRL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD0
BitsFieldTypeResetDescription
31:20
ReservedRO0x0Reserved
19
TRNG data search doneRO0x0TRNG data search done.
18:16TRNG data search
value		RO0x0TRNG data search value.
15:8ReservedRO0x0Reserved
7TRNG_REG_LDO_CAL_STARTRW0x0TRNG LDO calibration start
6TRNG_REG_LDO_PURW0x0LDO PU on
5TRNG_REG_LDO_RECALRW0x0LDO re-calibration
4TRNG_REG_SELRW0x00: Use PRNG (Default)
1: Use TRNG
3:2TRNG_REG_MODERW0x0- 0: 4 bit mode
- 1: 2 bit mode
- 2: 1 bit mode
- 3: debug mode
1
TRNG CLK ONRW0x0TRNG 24M reference clock turn on
0TRNG enableRW0x0Enable TRNG
+Offset: 0xD0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:20 | Reserved | RO | 0x0 | Reserved | +| 19 | TRNG data search done | RO | 0x0 | TRNG data search done. | +| 18:16 | TRNG data searchvalue | RO | 0x0 | TRNG data search value. | +| 15:8 | Reserved | RO | 0x0 | Reserved | +| 7 | TRNG_REG_LDO_CAL_START | RW | 0x0 | TRNG LDO calibration start | +| 6 | TRNG_REG_LDO_PU | RW | 0x0 | LDO PU on | +| 5 | TRNG_REG_LDO_RECAL | RW | 0x0 | LDO re-calibration | +| 4 | TRNG_REG_SEL | RW | 0x0 | 0: Use PRNG (Default)1: Use TRNG | +| 3:2 | TRNG_REG_MODE | RW | 0x0 | - 0: 4 bit mode- 1: 2 bit mode- 2: 1 bit mode- 3: debug mode | +| 1 | TRNG CLK ON | RW | 0x0 | TRNG 24M reference clock turn on | +| 0 | TRNG enable | RW | 0x0 | Enable TRNG | #### TRNG REG REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4
BitsFieldTypeResetDescription
31:24ReservedRO0x0Reserved
23:16
TRNG_REG_REG3RW0xD9TRNG_REG_REG3
15:8
TRNG_REG_REG2RW0x81TRNG_REG_REG2
7:0
TRNG_REG_REG1RW0x81TRNG_REG_REG1
+Offset: 0xD4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | Reserved | RO | 0x0 | Reserved | +| 23:16 | TRNG_REG_REG3 | RW | 0xD9 | TRNG_REG_REG3 | +| 15:8 | TRNG_REG_REG2 | RW | 0x81 | TRNG_REG_REG2 | +| 7:0 | TRNG_REG_REG1 | RW | 0x81 | TRNG_REG_REG1 | #### TRNG DATA REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD8
BitsFieldTypeResetDescription
31:0TRNG data register valueRO0x0TRNG result data bit [31:0]
+Offset: 0xD8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | TRNG data register value | RO | 0x0 | TRNG result data bit [31:0] | ## 9.6 Timer & Watchdog @@ -9627,93 +2762,30 @@ Offset: 0xC #### Timer Match Register - - - - - - - - - - - - - - - - - - - - -
Offset: 0x10~0x18(0x4)/0x20~0x28(0x4)/0x30~0x38(0x4)
BitsFieldTypeResetDescription
31:0TMR_TN_MMRW0xFFFFFFFFTimer n Match register m value.
This register holds the value used for the match comparison for Timer n (where n is the timer number, e.g., Timer 0, Timer 1, or Timer 2). When the timer counter reaches this value, a match event occurs.
+Offset: 0x10~0x18(0x4)/0x20~0x28(0x4)/0x30~0x38(0x4) +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | TMR_TN_MM | RW | 0xFFFFFFFF | Timer n Match register m value.This register holds the value used for the match comparison for Timer n (where n is the timer number, e.g., Timer 0, Timer 1, or Timer 2). When the timer counter reaches this value, a match event occurs. | #### Timer Preload Value Register Each TCR has a 32-bit-wide Preload Value register that loads the TCRn when a match occurs between TMR_Tn_Mm and TCRn. The corresponding TPLCRn register selects the match comparator. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x40~0x48(0x4)
BitsFieldTypeResetDescription
31:0TPLVRnRW0x0Timer n preload value that is loaded into TCRn when a match occurs between TMR_Tn_Tm and TCRn. The corresponding TPLCRn register selects the match comparator.
+Offset: 0x40~0x48(0x4) +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | TPLVRn | RW | 0x0 | Timer n preload value that is loaded into TCRn when a match occurs between TMR_Tn_Tm and TCRn. The corresponding TPLCRn register selects the match comparator. | #### Timer Preload Control Register Each TCR has a Preload Control register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x50~0x58(0x4)
BitsFieldTypeResetDescription
31:3ReservedRO0x0Reserved for future use
2CRPDRW0x0Disable preload when counter restar
- 0x0: Preload the PLCR to counter when the restart bit is set;
- 0x1: Disable preload of the PLCR to counter when the restart bit is set.
1:0MCSRW0x0Match comparator selection:
- 0x0: Free running mode (up to max value)
- 0x1: Enable preload with match comparator 0
- 0x2: Enable preload with match comparator 1
- 0x3: Enable preload with match comparator 2
+Offset: 0x50~0x58(0x4) +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | Reserved | RO | 0x0 | Reserved for future use | +| 2 | CRPD | RW | 0x0 | Disable preload when counter restar- 0x0: Preload the PLCR to counter when the restart bit is set;- 0x1: Disable preload of the PLCR to counter when the restart bit is set. | +| 1:0 | MCS | RW | 0x0 | Match comparator selection:- 0x0: Free running mode (up to max value)- 0x1: Enable preload with match comparator 0- 0x2: Enable preload with match comparator 1- 0x3: Enable preload with match comparator 2 | #### Timer Interrupt Enable Register @@ -9721,48 +2793,13 @@ Each of these three counter registers contain one enable bit, which determines w > **Note**. Clearing an enable bit does not reset the corresponding interrupt status bit if it has already been set. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x60~0x68(0x4)
BitsFieldTypeResetDescription
31:3ReservedRO0x0Reserved for future use.
2IE2RW0x0Interrupt enable for match comparator 2.
0: Disable interrupt for match between Match register 2 and its OS timer (no interrupt assertion).
1: Enable interrupt for match between Match register 2 and its OS timer (interrupt assertion in TSRn or timer#_irq output).
1IE1RW0x0Interrupt enable for match comparator 1.
0: Disable interrupt for match between Match register 1 and its OS timer (no interrupt assertion).
1: Enable interrupt for match between Match register 1 and its OS timer (interrupt assertion in TSRn or timer#_irq output).
0IE0RW0x0Interrupt enable for match comparator 0.
0: Disable interrupt for match between Match register 0 and its OS timer (no interrupt assertion).
1: Enable interrupt for match between Match register 0 and its OS timer (interrupt assertion in TSRn or timer#_irq output).
+Offset: 0x60~0x68(0x4) +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | Reserved | RO | 0x0 | Reserved for future use. | +| 2 | IE2 | RW | 0x0 | Interrupt enable for match comparator 2.0: Disable interrupt for match between Match register 2 and its OS timer (no interrupt assertion).1: Enable interrupt for match between Match register 2 and its OS timer (interrupt assertion in TSRn or timer#_irq output). | +| 1 | IE1 | RW | 0x0 | Interrupt enable for match comparator 1.0: Disable interrupt for match between Match register 1 and its OS timer (no interrupt assertion).1: Enable interrupt for match between Match register 1 and its OS timer (interrupt assertion in TSRn or timer#_irq output). | +| 0 | IE0 | RW | 0x0 | Interrupt enable for match comparator 0.0: Disable interrupt for match between Match register 0 and its OS timer (no interrupt assertion).1: Enable interrupt for match between Match register 0 and its OS timer (interrupt assertion in TSRn or timer#_irq output). | #### Timer Interrupt Clear Register @@ -9770,48 +2807,13 @@ These three registers contain a separate clear bit for each interrupt source, wh > **Note.** This register is not applicable for edge-sensitive interrupts. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x70~0x78(0x4)
BitsFieldTypeResetDescription
31:3ReservedRO0x0Reserved for future use.
2TCLR2WO0x0Interrupt clear for match comparator 2
0: No affect
1: Clear the level interrupt and corresponding status bit
1TCLR1WO0x0Interrupt clear for match comparator 1
0: No affect
1: Clear the level interrupt and corresponding status bit
0TCLR0WO0x0Interrupt clear for match comparator 0
0: No affect
1: Clear the level interrupt and corresponding status bit
+Offset: 0x70~0x78(0x4) +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | Reserved | RO | 0x0 | Reserved for future use. | +| 2 | TCLR2 | WO | 0x0 | Interrupt clear for match comparator 20: No affect1: Clear the level interrupt and corresponding status bit | +| 1 | TCLR1 | WO | 0x0 | Interrupt clear for match comparator 10: No affect1: Clear the level interrupt and corresponding status bit | +| 0 | TCLR0 | WO | 0x0 | Interrupt clear for match comparator 00: No affect1: Clear the level interrupt and corresponding status bit | #### Timer Status Register @@ -9822,48 +2824,13 @@ These three Status registers contain status bits indicating whether a match has This register reflects level-sensitive interrupt status only, edge-sensitive interrupts are not captured in this register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x80~0x88(0x4)
BitsFieldTypeResetDescription
31:3ReservedRO0x0Reserved for future use.
2M2RO0x0Match status of TMR_Tn_M2.
0: Timer Match register TMR_Tn_M2 has not matched the counter since the last interrupt clear.
1: Timer Match register TMR_Tn_M2 has matched the counter since the last interrupt clear
1M1RO0x0Match status of TMR_Tn_M1.
0: Timer Match register TMR_Tn_M1 has not matched the counter since the last interrupt clear.
1: Timer Match register TMR_Tn_M1 has matched the counter since the last interrupt clear
0M0RO0x0Match status of TMR_Tn_M0.
0: Timer Match register TMR_Tn_M0 has not matched the counter since the last interrupt clear.
1: Timer Match register TMR_Tn_M0 has matched the counter since the last interrupt clear.
+Offset: 0x80~0x88(0x4) +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:3 | Reserved | RO | 0x0 | Reserved for future use. | +| 2 | M2 | RO | 0x0 | Match status of TMR_Tn_M2.0: Timer Match register TMR_Tn_M2 has not matched the counter since the last interrupt clear.1: Timer Match register TMR_Tn_M2 has matched the counter since the last interrupt clear | +| 1 | M1 | RO | 0x0 | Match status of TMR_Tn_M1.0: Timer Match register TMR_Tn_M1 has not matched the counter since the last interrupt clear.1: Timer Match register TMR_Tn_M1 has matched the counter since the last interrupt clear | +| 0 | M0 | RO | 0x0 | Match status of TMR_Tn_M0.0: Timer Match register TMR_Tn_M0 has not matched the counter since the last interrupt clear.1: Timer Match register TMR_Tn_M0 has matched the counter since the last interrupt clear. | #### Timer Count Register @@ -9873,162 +2840,47 @@ Three read-only Timer Count registers (TCRn, where n = 0, 1, 2) are 32-bit count - The counters are pre-loaded with a value from the TPLVR register. When enabled, counters start from pre-loaded values (defined in the corresponding TPLCRn register), and count up to either a maximum or matched value. - This request requires up to three timer clock cycles. If the selected timer is working at a slow clock, the request could take longer. - - - - - - - - - - - - - - - - - - - - -
Offset: 0x90~0x98(0x4)
BitsFieldTypeResetDescription
31:0TCRNRO0x0Timer n count register.
- The counter is incremented on the rising edge of the selected clock.
- These registers have been synchronized to APB clock domain.
+Offset: 0x90~0x98(0x4) +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | TCRN | RO | 0x0 | Timer n count register.- The counter is incremented on the rising edge of the selected clock. - These registers have been synchronized to APB clock domain. | #### Timer Watchdog First Access Register - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xB0
BitsFieldTypeResetDescription
31:16ReservedRO0x0Reserved for future use.
15:0KEYWO0x0Watchdog access key.
Writing the value of 0xBABA to this register matches the key.
+Offset: 0xB0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0x0 | Reserved for future use. | +| 15:0 | KEY | WO | 0x0 | Watchdog access key.Writing the value of 0xBABA to this register matches the key. | #### Timer Watchdog Second Access Register - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xB4
BitsFieldTypeResetDescription
31:16ReservedRO0x0Reserved for future use.
15:0KEYWO0x0Watchdog access key.
Writing the value of 0xEB10 to this register matches the key.
+Offset: 0xB4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0x0 | Reserved for future use. | +| 15:0 | KEY | WO | 0x0 | Watchdog access key.Writing the value of 0xEB10 to this register matches the key. | #### Timer Watchdog Match Enable Register The Watchdog Enable register contains a WDT enable bit that can only be set by the user. The write access to this register is protected by the TWFAR and TWSAR Access Registers. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xB8
BitsFieldTypeResetDescription
31:2ReservedRO0x0Reserved for future use.
1WRIERW0x0Watchdog reset/interrupt enable.
0: Watchdog timer expiration generates a watchdog interrupt (no watchdog timer reset)
1: Watchdog timer expiration generates a watchdog timer reset, (no watchdog interrupt)
0WERW0x0WDT count enable.
0 = Disable WDT count, reset WDT's value to zero.
1 = Enable counting, the WDT always starts from zero.
> Note. Due to the chain of synchronizers that transform this signal from domain to domain, the WDT timer enable and disable operation do not occur immediately.
+Offset: 0xB8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:2 | Reserved | RO | 0x0 | Reserved for future use. | +| 1 | WRIE | RW | 0x0 | Watchdog reset/interrupt enable.0: Watchdog timer expiration generates a watchdog interrupt (no watchdog timer reset)1: Watchdog timer expiration generates a watchdog timer reset, (no watchdog interrupt) | +| 0 | WE | RW | 0x0 | WDT count enable.0 = Disable WDT count, reset WDT's value to zero.1 = Enable counting, the WDT always starts from zero.> Note. Due to the chain of synchronizers that transform this signal from domain to domain, the WDT timer enable and disable operation do not occur immediately. | #### Timer Watchdog Match Register This Match register is compared to the watchdog timer. The watchdog timer resets the processor when a match occurs and the TWER[WRIE] bit is set. - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xBC
BitsFieldTypeResetDescription
31:16ReservedRO0x0Reserved for future use.
15:0WTMRW0xFFFF16-bit watchdot timer match value
+Offset: 0xBC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0x0 | Reserved for future use. | +| 15:0 | WTM | RW | 0xFFFF | 16-bit watchdot timer match value | #### Timer Watchdog Status Register @@ -10038,127 +2890,35 @@ This register indicates whether a WDT reset has occurred and caused a system res - It is cleared by writing a logical 0 to this register - Clearing this bit is not required for the WDT to be re-activated after a WDT reset event - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC0
BitsFieldTypeResetDescription
31:1ReservedRO0x0Reserved for future use.
0WTSRW0x0Watchdog timer reset indication.
Indicates that reset was caused by the WDT.
Read:
0: Watchdog timer did not cause reset because this bit was cleared.
1: Watchdog timer caused a reset.
Write:
0: Clears the WDT reset status.
1: No affect.
+Offset: 0xC0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:1 | Reserved | RO | 0x0 | Reserved for future use. | +| 0 | WTS | RW | 0x0 | Watchdog timer reset indication.Indicates that reset was caused by the WDT.Read:0: Watchdog timer did not cause reset because this bit was cleared.1: Watchdog timer caused a reset.Write:0: Clears the WDT reset status.1: No affect. | #### Timer Watchdog Interrupt Clear Register - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC4
BitsFieldTypeResetDescription
31:1ReservedRO0x0Reserved for future use.
0WICLRWO0x0WDT Interrupt clear.
Write:
0: No affect.
1: Clear interrupt.
+Offset: 0xC4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:1 | Reserved | RO | 0x0 | Reserved for future use. | +| 0 | WICLR | WO | 0x0 | WDT Interrupt clear.Write:0: No affect.1: Clear interrupt. | #### Timer Watchdog Counter Reset Register - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC8
BitsFieldTypeResetDescription
31:1ReservedRO0x0Reserved for future use.
0WCRWO0x0Watchdog timer counter value reset.
Write:
0: No effect.
1: Clears the value of WDT counter.
+Offset: 0xC8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:1 | Reserved | RO | 0x0 | Reserved for future use. | +| 0 | WCR | WO | 0x0 | Watchdog timer counter value reset.Write:0: No effect.1: Clears the value of WDT counter. | #### Timer Watchdog Value Register - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xCC
BitsFieldTypeResetDescription
31:16ReservedRO0x0Reserved for future use.
15:0WTVRO0x0Watchdog timer value.
Read the current value of WDT.
Since the register may be in transition during a read operation, software must perform a double read and compare the two values to ensure accuracy.
+Offset: 0xCC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | Reserved | RO | 0x0 | Reserved for future use. | +| 15:0 | WTV | RO | 0x0 | Watchdog timer value.Read the current value of WDT. Since the register may be in transition during a read operation, software must perform a double read and compare the two values to ensure accuracy. | ## 9.7 RTC @@ -10192,222 +2952,60 @@ The secure RTC is only accessible by the secured core, and is reseted by power-o The base addresses of RTC registers are tabled below. - - - - - - - - - - - - - - - -
NameAddress
Non-secure RTC0xD401_0000
Secure RTC0xD401_0400
+| Name | Address | +| --- | --- | +| Non-secure RTC | 0xD401_0000 | +| Secure RTC | 0xD401_0400 | #### RTC COUNTER REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31:0Time CountRW
0x0Time Count of the real time counter, updated at a 1-Hz clock rate.
+Offset: 0x0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | Time Count | RW | 0x0 | Time Count of the real time counter, updated at a 1-Hz clock rate. | #### RTC ALARM REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31:0Alarm Time RW
0x0Alarm Time for interrupt generation.
+Offset: 0x4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | Alarm Time | RW | 0x0 | Alarm Time for interrupt generation. | #### RTC STATUS REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8
BitsFieldTypeResetDescription
31:4ReservedRO
0x0Reserved
31-Hz interrupt enableRW
0x0Enables 1-Hz interrupt:
0x0: Not Enabled
0x1: Enabled
2RTC alarm interrupt enableRW
0x0Enables RTC alarm interrupt:
0x0: Not Enabled
0x1: Enabled
11-Hz rising edge detectedW1C0x0Flag indicating detection of an 1-Hz rising edge.
Writing 1 clears the 1-Hz interrupt.
0RTC alarm detectedW1C0x0Flag indicating detection of an RTC alarm.
Writing 1 clears the RTC alarm interrupt.
+Offset: 0x8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:4 | Reserved | RO | 0x0 | Reserved | +| 3 | 1-Hz interrupt enable | RW | 0x0 | Enables 1-Hz interrupt:0x0: Not Enabled0x1: Enabled | +| 2 | RTC alarm interrupt enable | RW | 0x0 | Enables RTC alarm interrupt:0x0: Not Enabled0x1: Enabled | +| 1 | 1-Hz rising edge detected | W1C | 0x0 | Flag indicating detection of an 1-Hz rising edge.Writing 1 clears the 1-Hz interrupt. | +| 0 | RTC alarm detected | W1C | 0x0 | Flag indicating detection of an RTC alarm.Writing 1 clears the RTC alarm interrupt. | #### RTC TRIM REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC
BitsFieldTypeResetDescription
31Locking bit for the trim valueRW
0x0Locking bit for the trim value.
30:26ReservedRO
0x0Reserved
25:16Trim delete countRW
0x0This value represents the number of 32-kHz clocks to delete when clock trimming begins.
15:0Clock divider countRW
0x7FFFThis value is the integer portion of the clock trim logic.
+Offset: 0xC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Locking bit for the trim value | RW | 0x0 | Locking bit for the trim value. | +| 30:26 | Reserved | RO | 0x0 | Reserved | +| 25:16 | Trim delete count | RW | 0x0 | This value represents the number of 32-kHz clocks to delete when clock trimming begins. | +| 15:0 | Clock divider count | RW | 0x7FFF | This value is the integer portion of the clock trim logic. | #### RTC CONTROL REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x10
BitsFieldTypeResetDescription
31:1ReservedRO
0x0Reserved
0Controls the ALARM signalRW
0x0This bit enables software control on the ALARM signal that is generated by the processor, and signals any external device that is currently running. So the ALARM signal could be asserted by either software or hardware.
0x0: off (ALARM negated)
0x1: on (ALARM asserted)
+Offset: 0x10 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:1 | Reserved | RO | 0x0 | Reserved | +| 0 | Controls the ALARM signal | RW | 0x0 | This bit enables software control on the ALARM signal that is generated by the processor, and signals any external device that is currently running. So the ALARM signal could be asserted by either software or hardware.0x0: off (ALARM negated)0x1: on (ALARM asserted) | #### RTC BACKUP REGISTERS - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14~0x24
BitsFieldTypeResetDescription
31:0Backup dataRW
0x0The processor RTC has five back-up registers that store erasable data. The processor can read and write all five 32-bit registers.
+Offset: 0x14~0x24 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | Backup data | RW | 0x0 | The processor RTC has five back-up registers that store erasable data. The processor can read and write all five 32-bit registers. | ## 9.8 MailBox @@ -10437,175 +3035,49 @@ With reference to the previous **[6. Address Mapping](6.Address_Mapping.md)** & #### ISRR REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x0
BitsFieldTypeResetDescription
31:16reservedR0x0Reserved
15:0APB_MBOX_ISRRR
0x0Used to obtain the ISRW value of the other side Mailbox.
+Offset: 0x0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | reserved | R | 0x0 | Reserved | +| 15:0 | APB_MBOX_ISRR | R | 0x0 | Used to obtain the ISRW value of the other side Mailbox. | #### WDR REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x4
BitsFieldTypeResetDescription
31:0APB_MBOX_WDRW
0x0Write Data
Includes a 32-bit control word to be transferred to the other side (that will poll it). The content of this word is defined by application.
+Offset: 0x4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | APB_MBOX_WDR | W | 0x0 | Write DataIncludes a 32-bit control word to be transferred to the other side (that will poll it). The content of this word is defined by application. | #### ISRW REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0x8
BitsFieldTypeResetDescription
31:16reservedR0x0Reserved
15:0APB_MBOX_ISRWW0x0Interrupt Set
This register allows setting 4 different interrupts in the other side's interrupt controller.
An interrupt can be set by writing 1 to the corresponding interrupt bit in this register, as described below:
- Setting bit [10] would generate a SET_GP_INT in the other side's interrupt controller.
- Setting bit [9] would generate a SET_MSG_INT in the other side's interrupt controller.
- Setting bit [8] would generate a SET_CMD_INT in the other side's interrupt controller.
- Setting any one of bits [7:0] would generate a single interrupt called DATA_ACK interrupt.
Once an interrupt is set, the corresponding bit is automatically cleared by hardware.
+Offset: 0x8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | reserved | R | 0x0 | Reserved | +| 15:0 | APB_MBOX_ISRW | W | 0x0 | Interrupt SetThis register allows setting 4 different interrupts in the other side's interrupt controller.An interrupt can be set by writing 1 to the corresponding interrupt bit in this register, as described below:- Setting bit [10] would generate a SET_GP_INT in the other side's interrupt controller.- Setting bit [9] would generate a SET_MSG_INT in the other side's interrupt controller.- Setting bit [8] would generate a SET_CMD_INT in the other side's interrupt controller.- Setting any one of bits [7:0] would generate a single interrupt called DATA_ACK interrupt.Once an interrupt is set, the corresponding bit is automatically cleared by hardware. | #### ICR REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC
BitsFieldTypeResetDescription
31:16reservedR0x0Reserved
15:0APB_MBOX_ICRW0x0Interrupt Clear
Used to clear an interrupt asserted by the other side.
- Writing 1 to a specific bit clears the corresponding interrupt.
- No need to write 0 after 1 — the bit is cleared automatically.
+Offset: 0xC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | reserved | R | 0x0 | Reserved | +| 15:0 | APB_MBOX_ICR | W | 0x0 | Interrupt ClearUsed to clear an interrupt asserted by the other side. - Writing 1 to a specific bit clears the corresponding interrupt. - No need to write 0 after 1 — the bit is cleared automatically. | #### IIR REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xC
BitsFieldTypeResetDescription
31:16reservedRSVD0xXReserved
Reserved. Always write 0. Ignore read value.
15:0APB_MBOX_IIRRO0x0This register is used to read the interrupt source received from the other side. If the Mailbox was identified as the interrupt source, the Interrupt Identification Register can be read to identify which of the 11 possible Mailbox interrupts was asserted.
> Notes.
> - When [10:8] were the only bits to be asserted, reading the Interrupt Identification Register is redundant, since there is a one-to-one mapping between the interrupt source and interrupt representation on the Interrupt Identification Register. However, when the received interrupt is DATA_ACK interrupt, the Interrupt Identification Register must be read to identify the interrupt cause.
> - Before reading this register, a dummy write operation (to any Mailbox address range) must be performed to latch the data to the read register. Without performing the write before the read operation, data will not be updated and old data will be read.
+Offset: 0xC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | reserved | RSVD | 0xX | ReservedReserved. Always write 0. Ignore read value. | +| 15:0 | APB_MBOX_IIR | RO | 0x0 | This register is used to read the interrupt source received from the other side. If the Mailbox was identified as the interrupt source, the Interrupt Identification Register can be read to identify which of the 11 possible Mailbox interrupts was asserted.> Notes.> - When [10:8] were the only bits to be asserted, reading the Interrupt Identification Register is redundant, since there is a one-to-one mapping between the interrupt source and interrupt representation on the Interrupt Identification Register. However, when the received interrupt is DATA_ACK interrupt, the Interrupt Identification Register must be read to identify the interrupt cause.> - Before reading this register, a dummy write operation (to any Mailbox address range) must be performed to latch the data to the read register. Without performing the write before the read operation, data will not be updated and old data will be read. | #### RDR REGISTER - - - - - - - - - - - - - - - - - - - - -
Offset: 0x14
BitsFieldTypeResetDescription
31:0APB_MBOX_RDRRO0x0This register is used to poll the Write Data Register of the other side.
> Note. Before reading this register, a dummy write operation (to any Mailbox address range) must be performed to latch the data to the read register. Without performing the write before the read operation, data will not be updated and old data will be read.
+Offset: 0x14 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:0 | APB_MBOX_RDR | RO | 0x0 | This register is used to poll the Write Data Register of the other side.> Note. Before reading this register, a dummy write operation (to any Mailbox address range) must be performed to latch the data to the read register. Without performing the write before the read operation, data will not be updated and old data will be read. | ## 9.9 Power Management & Lower Power Mode Control @@ -10635,7 +3107,7 @@ A two-level power management strategy is implemented to control various granular - RISCV X60™ Processor clock and low-power mode state machine. This state machine controls clock generation for the RISCV X60™ processors. It also generates the sequence of entry into and exit of the RISCV X60™ processor low-power modes. - AXI Fabric and DDR clocking and low power mode state machine. - This state machine controls clock generation for both bus-matrix and DDR. Once the RISCV X60™ processor state machine is in low-power mode, it controls the entry and exit sequence into and out of the bus and DDR low-power modes. + This state machine controls clock generation for both bus-matrix and DDR. Once the RISCV X60™ processor state machine is in low-power mode, it controls the entry and exit sequence into and out of the bus and DDR low-power modes. The Application Subsystem PMU takes in charge of X60™ and AXI/DDR power management. Once the Application Subsystem PMU enters into low power mode, the Main PMU then takes over control and may place K1 in chip-level sleep mode according to the Main PMU controls. @@ -10663,50 +3135,15 @@ All those power domains, except AON, can be powered off depending on specific ap In order to achieve the minimal power consumption, different power states are designed as tabled below: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
No.Power State NameDescription
1ACTIVE The system is alive and active, with all power domains on, except those power domains with power switches that can be turned off selectively and independently.
2CORE-IDLEEach core stops executing instructions and enters an idle state, with clock gating automatically after a Wait-for-Interrupt (WFI) execution. The core exits this state when receiving an interrupt routed to it and continues execution.
3Core-Power-OffEach core, when voted, enters a power-off state after Core-Idle sleep mode. The core exits this state when receiving an interrupt, with power turned on and reset released.
4CPU-Cluster-Power-Off
Each CPU cluster, when voted, enters this low-power state after all cores within this cluster have entered the Core-Power-Off state, with L2/TCM memory also shut down.
Any active interrupt routing to CPU cores in this cluster would bring CPU cluster out of this state, then power on, clock resume and reset release.
5Home-ScreenThe main bus fabric AXI clock is gated off (if voted) after both CPU clusters enter CPU-Cluster-Power-Off mode.
Any interrupt will wake up the chip from this state by resuming the main bus AXI clock, and powering up the corresponding CPU cluster and CPU core to which the interrupt is routed, resuming the CPU clock, and releasing the reset to service the interrupt routine.
6Chip-SleepThis is the most ultra-low power state, with all PLLs/Power islands off. Only 32K RTC clock remains alive, and the 24M VCXO can be configured to be on or off.
In this state only the logic/IO in AON domain alives, and a pin named SLEEP_OUT connected to PMIC would be deasserted to signal PMIC to lower the VCC power supply voltage to reduce lower power comsumption.
7RCPU with SOC LPRCPU power domain is an independent power island and can function in any of above PMU states. RCPU can vote for different SoC low-power states according to its specific scenario requirements.
The RCPU itself has four low-power states as follows:
- Active Mode: Clock running
- ClkGate Mode: Clock gating
- PLL Off Mode: PLL powered off
- Power Off Mode: RCPU power is shut down, but the RCPU AON domain remains alive
+| No. | Power State Name | Description | +| --- | --- | --- | +| 1 | ACTIVE | The system is alive and active, with all power domains on, except those power domains with power switches that can be turned off selectively and independently. | +| 2 | CORE-IDLE | Each core stops executing instructions and enters an idle state, with clock gating automatically after a Wait-for-Interrupt (WFI) execution. The core exits this state when receiving an interrupt routed to it and continues execution. | +| 3 | Core-Power-Off | Each core, when voted, enters a power-off state after Core-Idle sleep mode. The core exits this state when receiving an interrupt, with power turned on and reset released. | +| 4 | CPU-Cluster-Power-Off | Each CPU cluster, when voted, enters this low-power state after all cores within this cluster have entered the Core-Power-Off state, with L2/TCM memory also shut down. Any active interrupt routing to CPU cores in this cluster would bring CPU cluster out of this state, then power on, clock resume and reset release. | +| 5 | Home-Screen | The main bus fabric AXI clock is gated off (if voted) after both CPU clusters enter CPU-Cluster-Power-Off mode.Any interrupt will wake up the chip from this state by resuming the main bus AXI clock, and powering up the corresponding CPU cluster and CPU core to which the interrupt is routed, resuming the CPU clock, and releasing the reset to service the interrupt routine. | +| 6 | Chip-Sleep | This is the most ultra-low power state, with all PLLs/Power islands off. Only 32K RTC clock remains alive, and the 24M VCXO can be configured to be on or off. In this state only the logic/IO in AON domain alives, and a pin named SLEEP_OUT connected to PMIC would be deasserted to signal PMIC to lower the VCC power supply voltage to reduce lower power comsumption. | +| 7 | RCPU with SOC LP | RCPU power domain is an independent power island and can function in any of above PMU states. RCPU can vote for different SoC low-power states according to its specific scenario requirements. The RCPU itself has four low-power states as follows: - Active Mode: Clock running- ClkGate Mode: Clock gating - PLL Off Mode: PLL powered off- Power Off Mode: RCPU power is shut down, but the RCPU AON domain remains alive | > **Note. **VPU, GPU, ISP, DPU power islands can be turned on or off by software, and are independent of the power states No. 1~5 in the table above @@ -10732,1646 +3169,293 @@ In the **RCPU Power-Off State**, the following interrupts or events can wake-up #### POWER MODE STATUS REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4050000+0x1030
BitsFieldTypeResetDescription
31:16PWRMODE_STATUSRO0x0This field indicates which low power state the system has entered or exited. Each bit corresponds to a different low power mode. If set to 1, it indicates that the respective low power mode has occurred. The status is cleared by setting the corresponding bit in CLR_PWRMODE_STATUS to 1.
- bit0: D1P mode
- bit1: D1PP mode
- bit2: D1 mode
- bit3: D2 mode
- bit4: D2P
- bit5: D2PP mode
- bit6: cluster0 M2
- bit7: cluster1 M2
- bit8: cluster2 M2
- bit9: cr5 C2
- bit10: comm_top D2
15:0CLR_PWRMODE_STATUSRW0x0Clear Power Mode Status.
Set 1 to clear the corresponding PWRMODE_STATUS bit.
+Offset: 0xD4050000+0x1030 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | PWRMODE_STATUS | RO | 0x0 | This field indicates which low power state the system has entered or exited. Each bit corresponds to a different low power mode. If set to 1, it indicates that the respective low power mode has occurred. The status is cleared by setting the corresponding bit in CLR_PWRMODE_STATUS to 1.- bit0: D1P mode - bit1: D1PP mode - bit2: D1 mode - bit3: D2 mode - bit4: D2P - bit5: D2PP mode - bit6: cluster0 M2 - bit7: cluster1 M2 - bit8: cluster2 M2 - bit9: cr5 C2 - bit10: comm_top D2 | +| 15:0 | CLR_PWRMODE_STATUS | RW | 0x0 | Clear Power Mode Status. Set 1 to clear the corresponding PWRMODE_STATUS bit. | #### WAKEUP AND CLOCK RESUME LINES STATUS REGISTER (AWUCRS) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4050000+0x1048
BitsFieldTypeResetDescription
31AudioRW0x0Audio wake-up
30RSVDRO0x0Reserved
29RSVDRO0x0Reserved
28RSVDRO0x0Reserved
27RSVDRO0x0Reserved
26RSVDRO0x0Reserved
25RSVDRO0x0Reserved
24RSVDRO0x0Reserved
23SDH1_AUDIORO0x0SDH1 wake-up
22SDH2_SDH3RO0x0SDH2/SDH3 wake-up
21KEYPRESSRO0x0Key press
20RSVDRO0x0Reserved
19RSVDRO0x0Reserved
18WDTRO0x0WDT
17RTC_ALARMRO0x0RTC ALARM
16PMU_TIMER_3RO0x0PMU Timer 3
15PMU_TIMER_2RO0x0PMU Timer 2
14PMU_TIMER_1RO0x0PMU Timer 1
13AP2_TIMER_3RO0x0AP2 Timer 3
12AP2_TIMER_2RO0x0AP2 Timer 2
11AP2_TIMER_1RO0x0AP2 Timer 1
10AP1_2_TIMER_3RO0x0AP1 Timer 3 and SEC Timer 3
9AP1_2_TIMER_2RO0x0AP1 Timer 2 and SEC Timer 2
8AP1_2_TIMER_1RO0x0AP1 Timer 1 and SEC Timer 1
7WAKEUP7RO0x0Wakeup7 line in status
6WAKEUP6RO0x0Wakeup6 line in status
5WAKEUP5RO0x0Wakeup5 line in status
4WAKEUP4RO0x0Wakeup4 line in status
3WAKEUP3RO0x0Wakeup3 line in status
2WAKEUP2RO0x0Wakeup2 line in status
1WAKEUP1RO0x0Wakeup1 line in status
0WAKEUP0RO0x0Wakeup0 line in status
+Offset: 0xD4050000+0x1048 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | Audio | RW | 0x0 | Audio wake-up | +| 30 | RSVD | RO | 0x0 | Reserved | +| 29 | RSVD | RO | 0x0 | Reserved | +| 28 | RSVD | RO | 0x0 | Reserved | +| 27 | RSVD | RO | 0x0 | Reserved | +| 26 | RSVD | RO | 0x0 | Reserved | +| 25 | RSVD | RO | 0x0 | Reserved | +| 24 | RSVD | RO | 0x0 | Reserved | +| 23 | SDH1_AUDIO | RO | 0x0 | SDH1 wake-up | +| 22 | SDH2_SDH3 | RO | 0x0 | SDH2/SDH3 wake-up | +| 21 | KEYPRESS | RO | 0x0 | Key press | +| 20 | RSVD | RO | 0x0 | Reserved | +| 19 | RSVD | RO | 0x0 | Reserved | +| 18 | WDT | RO | 0x0 | WDT | +| 17 | RTC_ALARM | RO | 0x0 | RTC ALARM | +| 16 | PMU_TIMER_3 | RO | 0x0 | PMU Timer 3 | +| 15 | PMU_TIMER_2 | RO | 0x0 | PMU Timer 2 | +| 14 | PMU_TIMER_1 | RO | 0x0 | PMU Timer 1 | +| 13 | AP2_TIMER_3 | RO | 0x0 | AP2 Timer 3 | +| 12 | AP2_TIMER_2 | RO | 0x0 | AP2 Timer 2 | +| 11 | AP2_TIMER_1 | RO | 0x0 | AP2 Timer 1 | +| 10 | AP1_2_TIMER_3 | RO | 0x0 | AP1 Timer 3 and SEC Timer 3 | +| 9 | AP1_2_TIMER_2 | RO | 0x0 | AP1 Timer 2 and SEC Timer 2 | +| 8 | AP1_2_TIMER_1 | RO | 0x0 | AP1 Timer 1 and SEC Timer 1 | +| 7 | WAKEUP7 | RO | 0x0 | Wakeup7 line in status | +| 6 | WAKEUP6 | RO | 0x0 | Wakeup6 line in status | +| 5 | WAKEUP5 | RO | 0x0 | Wakeup5 line in status | +| 4 | WAKEUP4 | RO | 0x0 | Wakeup4 line in status | +| 3 | WAKEUP3 | RO | 0x0 | Wakeup3 line in status | +| 2 | WAKEUP2 | RO | 0x0 | Wakeup2 line in status | +| 1 | WAKEUP1 | RO | 0x0 | Wakeup1 line in status | +| 0 | WAKEUP0 | RO | 0x0 | Wakeup0 line in status | #### WAKEUP AND CLOCK RESUME LINES MASK REGISTER (AWUCRM1) - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4050000+0x1044
BitsFieldTypeResetDescription
31:1RSVDRO0x0Reserved
0IPC_AP2AUD_INTRW0x0Enable ipc_ap2aud_int
+Offset: 0xD4050000+0x1044 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:1 | RSVD | RO | 0x0 | Reserved | +| 0 | IPC_AP2AUD_INT | RW | 0x0 | Enable ipc_ap2aud_int | #### WAKEUP AND CLOCK RESUME LINES STATUS REGISTER (AAWUCRM0) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4050000+0x104C
BitsFieldTypeResetDescription
31AUDIO_WAKEUPRW0x0Enable audio wake-up
30RSVDRW0x0Reserved
29RSVDRW0x0Reserved
28RSVDRW0x0Reserved
27RSVDRW0x0Reserved
26RSVDRW0x0Reserved
25RSVDRW0x0Reserved
24RSVDRW0x0Reserved
23SDH1_AUDIORW0x0Enable SDH1 wake-up
22SDH2_SDH3RW0x0Enable SDH2/SDH3 wake-up
21KEYPRESSRW0x0Enable key press wake-up
20RSVDRW0x0Reserved
19RSVDRW0x0Reserved
18WDTRW0x0Enable WDT
17RTC_ALARMRW0x0Enable RTC ALARM
16PMU_TIMER_3RW0x0Enable PMU Timer 3
15PMU_TIMER_2RW0x0Enable PMU Timer 2
14PMU_TIMER_1RW0x0Enable PMU Timer 1
13AP2_TIMER_3RW0x0Enable AP2 Timer 3
12AP2_TIMER_2RW0x0Enable AP2 Timer 2
11AP2_TIMER_1RW0x0Enable AP2 Timer 1
10AP1_2_TIMER_3RW0x0Enable AP1 Timer 3 and SEC Timer 3
9AP1_2_TIMER_2RW0x0Enable AP1 Timer 2 and SEC Timer 2
8AP1_2_TIMER_1RW0x0Enable AP1 Timer 1 and SEC Timer 1
7WAKEUP7RW0x0Enable Wakeup7 input to Pm_clkres
6WAKEUP6RW0x0Enable Wakeup6 input to Pm_clkres
5WAKEUP5RW0x0Enable Wakeup5 input to Pm_clkres
4WAKEUP4RW0x0Enable Wakeup4 input to Pm_clkres
3WAKEUP3RW0x0Enable Wakeup3 input to Pm_clkres
2WAKEUP2RW0x0Enable Wakeup2 input to Pm_clkres
1WAKEUP1RW0x0Enable Wakeup1input to Pm_clkres
0WAKEUP0RW0x0Enable Wakeup0 input to Pm_clkres
+Offset: 0xD4050000+0x104C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | AUDIO_WAKEUP | RW | 0x0 | Enable audio wake-up | +| 30 | RSVD | RW | 0x0 | Reserved | +| 29 | RSVD | RW | 0x0 | Reserved | +| 28 | RSVD | RW | 0x0 | Reserved | +| 27 | RSVD | RW | 0x0 | Reserved | +| 26 | RSVD | RW | 0x0 | Reserved | +| 25 | RSVD | RW | 0x0 | Reserved | +| 24 | RSVD | RW | 0x0 | Reserved | +| 23 | SDH1_AUDIO | RW | 0x0 | Enable SDH1 wake-up | +| 22 | SDH2_SDH3 | RW | 0x0 | Enable SDH2/SDH3 wake-up | +| 21 | KEYPRESS | RW | 0x0 | Enable key press wake-up | +| 20 | RSVD | RW | 0x0 | Reserved | +| 19 | RSVD | RW | 0x0 | Reserved | +| 18 | WDT | RW | 0x0 | Enable WDT | +| 17 | RTC_ALARM | RW | 0x0 | Enable RTC ALARM | +| 16 | PMU_TIMER_3 | RW | 0x0 | Enable PMU Timer 3 | +| 15 | PMU_TIMER_2 | RW | 0x0 | Enable PMU Timer 2 | +| 14 | PMU_TIMER_1 | RW | 0x0 | Enable PMU Timer 1 | +| 13 | AP2_TIMER_3 | RW | 0x0 | Enable AP2 Timer 3 | +| 12 | AP2_TIMER_2 | RW | 0x0 | Enable AP2 Timer 2 | +| 11 | AP2_TIMER_1 | RW | 0x0 | Enable AP2 Timer 1 | +| 10 | AP1_2_TIMER_3 | RW | 0x0 | Enable AP1 Timer 3 and SEC Timer 3 | +| 9 | AP1_2_TIMER_2 | RW | 0x0 | Enable AP1 Timer 2 and SEC Timer 2 | +| 8 | AP1_2_TIMER_1 | RW | 0x0 | Enable AP1 Timer 1 and SEC Timer 1 | +| 7 | WAKEUP7 | RW | 0x0 | Enable Wakeup7 input to Pm_clkres | +| 6 | WAKEUP6 | RW | 0x0 | Enable Wakeup6 input to Pm_clkres | +| 5 | WAKEUP5 | RW | 0x0 | Enable Wakeup5 input to Pm_clkres | +| 4 | WAKEUP4 | RW | 0x0 | Enable Wakeup4 input to Pm_clkres | +| 3 | WAKEUP3 | RW | 0x0 | Enable Wakeup3 input to Pm_clkres | +| 2 | WAKEUP2 | RW | 0x0 | Enable Wakeup2 input to Pm_clkres | +| 1 | WAKEUP1 | RW | 0x0 | Enable Wakeup1input to Pm_clkres | +| 0 | WAKEUP0 | RW | 0x0 | Enable Wakeup0 input to Pm_clkres | #### WAKEUP AND CLOCK RESUME LINES STATUS REGISTER (AWUCRS1) - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4050000+0x1064
BitsFieldTypeResetDescription
31:1RSVDRO0x0Reserved for future use
0IPC_AP2AUD_INTRO0x0IPC_AP2AUD_INT
+Offset: 0xD4050000+0x1064 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:1 | RSVD | RO | 0x0 | Reserved for future use | +| 0 | IPC_AP2AUD_INT | RO | 0x0 | IPC_AP2AUD_INT | #### CLUSTER 0 POWER CONTROL REGISTER (APCR_CLUSTER0) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4050000+0x1090
BitsFieldTypeResetDescription
31AXISDDRW0x0Allows AXI bus and agents to shut down after ASR<var Processor: Application> cores enters idle state.
1'b0: AXI shutdown not allowed
1'b1: AXI shutdown allowed
30RSVDRO0Must be 1
29RSVDRO0Must be 1
28RSVDRO0Reserved
27DDRCORSDRW0x0Allow ASR <var Processor: Application MP> core and TC DDR clocks to shut down.
The clocks are halted when CPCR[DDRCORSD], APCR[DDRCORSD] & DPCR[DDRCORSD] are set, and ASR <var Processor: Application MP> core is in idle mode.
1'b0: ASR <var Processor: Application MP> core and TC DDR clocks shutdown not allowed
1'b1: ASR <var Processor: Application MP> core and TC DDR clocks shutdown allowed
26APBSDRW0x0Allow PMU to shut down APB clocks to all of its recipients, overriding other per-module fields.
The APB clock is shut down once the ASR <var Processor: Application> cores are idle and CPCR[APBSD], APCR[APBSD] & DPCR[APBSD] are set.
1'b0: APB clock shutdown not allowed
1'b1: APB clock shutdown allowed
25RSVDRO0Must be 1
24:20RSVDRO0Reserved
19VCTCXOSDRW0x0Allow VCTCXO shutdown when the system is in sleep mode.
VCTCXO is shutdown when CPCR[VCTCXOSD], APCR[VCTCXOSD] & DPCR[VCTCXOSD] are set & the system enters sleep mode
1'b0: VCTCXO shutdown not allowed
1'b1: VCTCXO shutdown allowed
18:15RSVDRO0Reserved
14RSVDRO0must be 1
13STBYENRW0x1Allow Apps Subsystem to shutdown and go into UDR-mode when AP subsystem is in sleep mode.
UDR is enabled when CPCR[STBYEN], APCR[STBYEN] are both set & AP subsystem enters AP Sleep.
12:4RSVDRO0Reserved
3C0_VOTE_AP_SLPENRW0x1Cluster1 vote APMU sleep enable
2:0RSVDRO0Reserved
+Offset: 0xD4050000+0x1090 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | AXISDD | RW | 0x0 | Allows AXI bus and agents to shut down after ASR cores enters idle state. 1'b0: AXI shutdown not allowed1'b1: AXI shutdown allowed | +| 30 | RSVD | RO | 0 | Must be 1 | +| 29 | RSVD | RO | 0 | Must be 1 | +| 28 | RSVD | RO | 0 | Reserved | +| 27 | DDRCORSD | RW | 0x0 | Allow ASR core and TC DDR clocks to shut down. The clocks are halted when CPCR[DDRCORSD], APCR[DDRCORSD] & DPCR[DDRCORSD] are set, and ASR core is in idle mode.1'b0: ASR core and TC DDR clocks shutdown not allowed 1'b1: ASR core and TC DDR clocks shutdown allowed | +| 26 | APBSD | RW | 0x0 | Allow PMU to shut down APB clocks to all of its recipients, overriding other per-module fields. The APB clock is shut down once the ASR cores are idle and CPCR[APBSD], APCR[APBSD] & DPCR[APBSD] are set.1'b0: APB clock shutdown not allowed1'b1: APB clock shutdown allowed | +| 25 | RSVD | RO | 0 | Must be 1 | +| 24:20 | RSVD | RO | 0 | Reserved | +| 19 | VCTCXOSD | RW | 0x0 | Allow VCTCXO shutdown when the system is in sleep mode. VCTCXO is shutdown when CPCR[VCTCXOSD], APCR[VCTCXOSD] & DPCR[VCTCXOSD] are set & the system enters sleep mode 1'b0: VCTCXO shutdown not allowed1'b1: VCTCXO shutdown allowed | +| 18:15 | RSVD | RO | 0 | Reserved | +| 14 | RSVD | RO | 0 | must be 1 | +| 13 | STBYEN | RW | 0x1 | Allow Apps Subsystem to shutdown and go into UDR-mode when AP subsystem is in sleep mode. UDR is enabled when CPCR[STBYEN], APCR[STBYEN] are both set & AP subsystem enters AP Sleep. | +| 12:4 | RSVD | RO | 0 | Reserved | +| 3 | C0_VOTE_AP_SLPEN | RW | 0x1 | Cluster1 vote APMU sleep enable | +| 2:0 | RSVD | RO | 0 | Reserved | #### CLUSTER 1 POWER CONTROL REGISTER (APCR_CLUSTER0) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4050000+0x1094
BitsFieldTypeResetDescription
31AXISDDRW0x0Allows AXI bus and agents to shut down after ASR<var Processor: Application> cores enters idle state.
1'b0: AXI shutdown not allowed
1'b1: AXI shutdown allowed
30RSVDRO0Must be 1
29RSVDRO0Must be 1
28RSVDRO0Reserved
27DDRCORSDRW0x0Allow ASR <var Processor: Application MP> core and TC DDR clocks shutdown.
The clocks are halted when CPCR[DDRCORSD], APCR[DDRCORSD] & DPCR[DDRCORSD] are set and ASR <var Processor: Application MP> core is in idle mode.
1'b0: ASR <var Processor: Application MP> core and TC DDR clocks shutdown not allowed
1'b1: ASR <var Processor: Application MP> core and TC DDR clocks shutdown allowed
26APBSDRW0x0Allow PMU to shut down APB clocks to all of its recipients, overriding other per-module fields.
The APB clock is actually shut down once the ASR <var Processor: Application> cores are idle and CPCR[APBSD], APCR[APBSD] & DPCR[APBSD] are set.
1'b0: APB clock shutdown not allowed
1'b1: APB clock shutdown allowed
25RSVDRO0must be 1
24:20RSVDRO0Reserved
19VCTCXOSDRW0x0Allow VCTCXO shutdown when the system is in sleep mode.
VCTCXO is shutdown when CPCR[VCTCXOSD], APCR[VCTCXOSD] & DPCR[VCTCXOSD] are set & the system enters sleep mode
1'b0: VCTCXO shutdown not allowed
1'b1: VCTCXO shutdown allowed
18:15RSVDRO0Reserved
14RSVDRO0Must be 1
13STBYENRW0x1Allow Apps Subsystem to shutdown and go into UDR-mode when AP subsystem is in sleep mode.
UDR is enabled when CPCR[STBYEN], APCR[STBYEN] are both set & AP subsystem enters AP Sleep.
12:4RSVDRO0Reserved
3C1_VOTE_AP_SLPENRW0x1Cluster1 vote APMU sleep enable
2:0RSVDRO0Reserved
+Offset: 0xD4050000+0x1094 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | AXISDD | RW | 0x0 | Allows AXI bus and agents to shut down after ASR cores enters idle state. 1'b0: AXI shutdown not allowed1'b1: AXI shutdown allowed | +| 30 | RSVD | RO | 0 | Must be 1 | +| 29 | RSVD | RO | 0 | Must be 1 | +| 28 | RSVD | RO | 0 | Reserved | +| 27 | DDRCORSD | RW | 0x0 | Allow ASR core and TC DDR clocks shutdown. The clocks are halted when CPCR[DDRCORSD], APCR[DDRCORSD] & DPCR[DDRCORSD] are set and ASR core is in idle mode.1'b0: ASR core and TC DDR clocks shutdown not allowed 1'b1: ASR core and TC DDR clocks shutdown allowed | +| 26 | APBSD | RW | 0x0 | Allow PMU to shut down APB clocks to all of its recipients, overriding other per-module fields. The APB clock is actually shut down once the ASR cores are idle and CPCR[APBSD], APCR[APBSD] & DPCR[APBSD] are set.1'b0: APB clock shutdown not allowed1'b1: APB clock shutdown allowed | +| 25 | RSVD | RO | 0 | must be 1 | +| 24:20 | RSVD | RO | 0 | Reserved | +| 19 | VCTCXOSD | RW | 0x0 | Allow VCTCXO shutdown when the system is in sleep mode. VCTCXO is shutdown when CPCR[VCTCXOSD], APCR[VCTCXOSD] & DPCR[VCTCXOSD] are set & the system enters sleep mode 1'b0: VCTCXO shutdown not allowed1'b1: VCTCXO shutdown allowed | +| 18:15 | RSVD | RO | 0 | Reserved | +| 14 | RSVD | RO | 0 | Must be 1 | +| 13 | STBYEN | RW | 0x1 | Allow Apps Subsystem to shutdown and go into UDR-mode when AP subsystem is in sleep mode. UDR is enabled when CPCR[STBYEN], APCR[STBYEN] are both set & AP subsystem enters AP Sleep. | +| 12:4 | RSVD | RO | 0 | Reserved | +| 3 | C1_VOTE_AP_SLPEN | RW | 0x1 | Cluster1 vote APMU sleep enable | +| 2:0 | RSVD | RO | 0 | Reserved | #### ASR PERIPHERAL 1 POWER CONTROL REGISTER (APCR_PER) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4050000+0x1098
BitsFieldTypeResetDescription
31AXISDDRW0x0Allow AXI bus and agents to shut down after ASR<var Processor: Application> cores enters idle state.
1'b0: AXI shutdown not allowed
1'b1: AXI shutdown allowed
30RSVDRO0x0must be 1
29RSVDRO0x0must be 1
28RSVDRO0x0Reserved
27DDRCORSDRW0x0Allow ASR <var Processor: Application MP> core and TC DDR clocks shutdown.
The clocks are halted when CPCR[DDRCORSD], APCR[DDRCORSD] & DPCR[DDRCORSD] are set and ASR <var Processor: Application MP> core is in idle mode.
1'b0: ASR <var Processor: Application MP> core and TC DDR clocks shutdown not allowed
1'b1: ASR<var Processor: Application MP> core and TC DDR clocks shutdown allowed
26APBSDRW0x0Allow PMU to shut down APB clocks to all of its recipients, overriding other per-module fields.
The APB clock is actually shut down once the ASR <var Processor: Comm>/ <var Processor: Application> cores are idle and CPCR[APBSD], APCR[APBSD] & DPCR[APBSD] are set.
1'b0: APB clock shutdown not allowed
1'b1: APB clock shutdown allowed
25RSVDRO0x0must be 1
24:20RSVDRO0x0Reserved
19VCTCXOSDRW0x0Allow VCTCXO shutdown when the system is in sleep mode.
VCTCXO is shutdown when CPCR[VCTCXOSD], APCR[VCTCXOSD] & DPCR[VCTCXOSD] are set & the system enters sleep mode
0: VCTCXO shutdown not allowed
1: VCTCXO shutdown allowed
18:15RSVDRO0x0Reserved
14RSVDRO0x0Must be 1
13STBYENRW0x1Allow Apps Subsystem to shutdown and go into UDR-mode when AP subsystem is in sleep mode.
UDR is enabled when CPCR[STBYEN], APCR[STBYEN] are both set & AP subsystem enters AP Sleep.
12:4RSVDRO0x0Reserved
3PE_VOTE_AP_SLPENRW0x1PE vote APMU sleep enable
2:0RSVDRO0x0Reserved
+Offset: 0xD4050000+0x1098 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | AXISDD | RW | 0x0 | Allow AXI bus and agents to shut down after ASR cores enters idle state. 1'b0: AXI shutdown not allowed1'b1: AXI shutdown allowed | +| 30 | RSVD | RO | 0x0 | must be 1 | +| 29 | RSVD | RO | 0x0 | must be 1 | +| 28 | RSVD | RO | 0x0 | Reserved | +| 27 | DDRCORSD | RW | 0x0 | Allow ASR core and TC DDR clocks shutdown. The clocks are halted when CPCR[DDRCORSD], APCR[DDRCORSD] & DPCR[DDRCORSD] are set and ASR core is in idle mode.1'b0: ASR core and TC DDR clocks shutdown not allowed 1'b1: ASR core and TC DDR clocks shutdown allowed | +| 26 | APBSD | RW | 0x0 | Allow PMU to shut down APB clocks to all of its recipients, overriding other per-module fields. The APB clock is actually shut down once the ASR / cores are idle and CPCR[APBSD], APCR[APBSD] & DPCR[APBSD] are set.1'b0: APB clock shutdown not allowed 1'b1: APB clock shutdown allowed | +| 25 | RSVD | RO | 0x0 | must be 1 | +| 24:20 | RSVD | RO | 0x0 | Reserved | +| 19 | VCTCXOSD | RW | 0x0 | Allow VCTCXO shutdown when the system is in sleep mode. VCTCXO is shutdown when CPCR[VCTCXOSD], APCR[VCTCXOSD] & DPCR[VCTCXOSD] are set & the system enters sleep mode 0: VCTCXO shutdown not allowed 1: VCTCXO shutdown allowed | +| 18:15 | RSVD | RO | 0x0 | Reserved | +| 14 | RSVD | RO | 0x0 | Must be 1 | +| 13 | STBYEN | RW | 0x1 | Allow Apps Subsystem to shutdown and go into UDR-mode when AP subsystem is in sleep mode. UDR is enabled when CPCR[STBYEN], APCR[STBYEN] are both set & AP subsystem enters AP Sleep. | +| 12:4 | RSVD | RO | 0x0 | Reserved | +| 3 | PE_VOTE_AP_SLPEN | RW | 0x1 | PE vote APMU sleep enable | +| 2:0 | RSVD | RO | 0x0 | Reserved | #### Basing on \ ##### SDIO/ROTARY WAKE CLEAR REGISTER (PMU_USB_SD_ROT_WAKE_CLR) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x7C
BitsFieldTypeResetDescription
31USB_WK_INT_STATUSRO0x0USB Wake up status
30:29RSVDRO0x0Reserved0
28USB_CHGDET_WK_STATUSRO0x0USB Line charge detect wake up status
27USB_ID_WK_STATUSRO0x0USB Line ID wake up status
26USB_VBUS_WK_STATUSRO0x0USB Line vbus valid wake up status
25USB_LINE1_WK_STATUSRO0x0USB Line state1 wake up status
24USB_LINE0_WK_STATUSRO0x0USB Line state0 wake up status
23USB_IDDIG_OVRD_VALUERO0x0USB IDDIG OVERRIDE VALUE
22USB_IDDIG_OVRD_ENRO0x0USB IDDIG OVERRIDE ENABLE
21USB_VBUS_DRVRO0x0USB VBUS DRV
20USB_CHGDET_WK_CLRRW0x0USB Line charge detect wake up Clear.
1'b1: Clear
This bit is self-cleared by hardware
19USB_ID_WK_CLRRW0x0USB Line ID wake up Clear.
1'b1: Clear
This bit is self-cleared by hardware
18USB_VBUS_WK_CLRRW0x0USB Line vbus valid wake up Clear.
1'b1: Clear
This bit is self-cleared by hardware
17USB_LINE1_WK_CLRRW0x0USB Line state1 wake up Clear
1'b1: Clear
This bit is self-cleared by hardware
16USB_LINE0_WK_CLRRW0x0USB Line state0 wake up Clear
1'b1: Clear
This bit is self-cleared by hardware
15USB_WK_INT_MASKRW0x0USB Wakeup Interrupt Enable.
1'b1: Enable
14:13RSVDRO0Reserved
12USB_CHGDET_WK_MASKRW0x0USB Line charge detect wake up Enable.
1'b1: Enable
11USB_ID_WK_MASKRW0x0USB Line ID wake up Enable.
1'b1: Enable
10USB_VBUS_WK_MASKRW0x0USB Line vbus valid wake up Enable
1'b1: Enable
9USB_LINE1_WK_MASKRW0x0USB Line state1 wake up Enable
1'b1: Enable
8USB_LINE0_WK_MASKRW0x0USB Line state0 wake up Enable
1'b1: Enable
7CS_WK_STATUSRO0x0CS wake up status
6SDH2_WK_CLRRW0x1SDH2 Wake Clear.
1'b1: SDH2 wake event clear
This bit is self-cleared by hardware
5CS_WK_CLRRW0x0Clear of DAP Power Wake Up Request (DAP CSYSPWRUPREQ).
1'b1: Clear DAP_REQ wakeup
4CS_WK_MASKRW0x0DAP Power Wake Up Enable (DAP CSYSPWRUPREQ)
1'b1: Enable
3KB_WK_CLRRW0x1Keypad Wake Clear.
1'b1: ROT wake event clear
This bit is self-cleared by hardware
2ROT_WK_CLRRW0x1Rotary Wake Clear.
1'b1: ROT wake event clear
This bit is self-cleared by hardware
1SDH1_WK_CLRRW0x1SDH1 Wake Clear.
1'b1: SDH1 wake event clear
This bit is self-cleared by hardware
0SDH0_WK_CLRRW0x1SDH0 Wake Clear.
1'b1: SDH0 wake event clear
This bit is self-cleared by hardware
+Offset: 0xD4282800+0x7C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | USB_WK_INT_STATUS | RO | 0x0 | USB Wake up status | +| 30:29 | RSVD | RO | 0x0 | Reserved0 | +| 28 | USB_CHGDET_WK_STATUS | RO | 0x0 | USB Line charge detect wake up status | +| 27 | USB_ID_WK_STATUS | RO | 0x0 | USB Line ID wake up status | +| 26 | USB_VBUS_WK_STATUS | RO | 0x0 | USB Line vbus valid wake up status | +| 25 | USB_LINE1_WK_STATUS | RO | 0x0 | USB Line state1 wake up status | +| 24 | USB_LINE0_WK_STATUS | RO | 0x0 | USB Line state0 wake up status | +| 23 | USB_IDDIG_OVRD_VALUE | RO | 0x0 | USB IDDIG OVERRIDE VALUE | +| 22 | USB_IDDIG_OVRD_EN | RO | 0x0 | USB IDDIG OVERRIDE ENABLE | +| 21 | USB_VBUS_DRV | RO | 0x0 | USB VBUS DRV | +| 20 | USB_CHGDET_WK_CLR | RW | 0x0 | USB Line charge detect wake up Clear.1'b1: Clear This bit is self-cleared by hardware | +| 19 | USB_ID_WK_CLR | RW | 0x0 | USB Line ID wake up Clear.1'b1: ClearThis bit is self-cleared by hardware | +| 18 | USB_VBUS_WK_CLR | RW | 0x0 | USB Line vbus valid wake up Clear. 1'b1: ClearThis bit is self-cleared by hardware | +| 17 | USB_LINE1_WK_CLR | RW | 0x0 | USB Line state1 wake up Clear1'b1: ClearThis bit is self-cleared by hardware | +| 16 | USB_LINE0_WK_CLR | RW | 0x0 | USB Line state0 wake up Clear1'b1: ClearThis bit is self-cleared by hardware | +| 15 | USB_WK_INT_MASK | RW | 0x0 | USB Wakeup Interrupt Enable.1'b1: Enable | +| 14:13 | RSVD | RO | 0 | Reserved | +| 12 | USB_CHGDET_WK_MASK | RW | 0x0 | USB Line charge detect wake up Enable.1'b1: Enable | +| 11 | USB_ID_WK_MASK | RW | 0x0 | USB Line ID wake up Enable.1'b1: Enable | +| 10 | USB_VBUS_WK_MASK | RW | 0x0 | USB Line vbus valid wake up Enable1'b1: Enable | +| 9 | USB_LINE1_WK_MASK | RW | 0x0 | USB Line state1 wake up Enable 1'b1: Enable | +| 8 | USB_LINE0_WK_MASK | RW | 0x0 | USB Line state0 wake up Enable1'b1: Enable | +| 7 | CS_WK_STATUS | RO | 0x0 | CS wake up status | +| 6 | SDH2_WK_CLR | RW | 0x1 | SDH2 Wake Clear.1'b1: SDH2 wake event clearThis bit is self-cleared by hardware | +| 5 | CS_WK_CLR | RW | 0x0 | Clear of DAP Power Wake Up Request (DAP CSYSPWRUPREQ).1'b1: Clear DAP_REQ wakeup | +| 4 | CS_WK_MASK | RW | 0x0 | DAP Power Wake Up Enable (DAP CSYSPWRUPREQ)1'b1: Enable | +| 3 | KB_WK_CLR | RW | 0x1 | Keypad Wake Clear.1'b1: ROT wake event clearThis bit is self-cleared by hardware | +| 2 | ROT_WK_CLR | RW | 0x1 | Rotary Wake Clear.1'b1: ROT wake event clearThis bit is self-cleared by hardware | +| 1 | SDH1_WK_CLR | RW | 0x1 | SDH1 Wake Clear.1'b1: SDH1 wake event clearThis bit is self-cleared by hardware | +| 0 | SDH0_WK_CLR | RW | 0x1 | SDH0 Wake Clear.1'b1: SDH0 wake event clearThis bit is self-cleared by hardware | ##### POWER STABLE TIMER REGISTER (PMU_PWR_STBL_TIMER) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x7C
BitsFieldTypeResetDescription
31:24RSVDRO0x0Reserved
23:16PWR_CLK_PRERW0x02Clock Prescaler for Timer Count.
0x0 = Divide by 1
0x1 = Divide by 1
0x2 = Divide by 2
All other values use an incremental divider.
15:8PWR_UP_STBL_TIMERRW0x40Power-Up Stable Timer
Defines the stable time required for power-up during core idle mode in 24 MHz unit
7:0PWR_DWN_STBL_TIMERRW0x00Power Down Stable Timer
Defines the stable time required for power-down during core idle mode in 24 MHz unit
+Offset: 0xD4282800+0x7C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:24 | RSVD | RO | 0x0 | Reserved | +| 23:16 | PWR_CLK_PRE | RW | 0x02 | Clock Prescaler for Timer Count.0x0 = Divide by 10x1 = Divide by 10x2 = Divide by 2 All other values use an incremental divider. | +| 15:8 | PWR_UP_STBL_TIMER | RW | 0x40 | Power-Up Stable Timer Defines the stable time required for power-up during core idle mode in 24 MHz unit | +| 7:0 | PWR_DWN_STBL_TIMER | RW | 0x00 | Power Down Stable Timer Defines the stable time required for power-down during core idle mode in 24 MHz unit | ##### CORE STATUS REGISTER (PMU_CORE_STATUS) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x90
BitsFieldTypeResetDescription
31AP_CORE7_C2RO0x1CORE7 in C2 Mode Indication.
Indicates whether CORE7 is in C2 mode.
1'b1: CORE7 is in C2 mode
30AP_CORE7_C1RO0x0CORE7 in C1 Mode Indication.
Indicates whether CORE7 is in C1 mode (external mode).
1'b1: CORE7 is in C1 mode
29AP_CORE7_WFI_FLAGRO0x1CORE7 WFI Flag
Reflects the WFI flag generated by CORE7
When CORE7 enters WFI, this field is set
28AP_CORE6_C2RO0x1CORE6 in C2 Mode Indication.
Indicates whether CORE6 is in C2 mode.
1'b1: CORE6 is in C2 mode
27AP_CORE6_C1RO0x0CORE6 in C1 Mode Indication.
Indicates whether CORE6 is in C1 mode (external mode).
1'b1: CORE6 is in C1 mode
26AP_CORE6_WFI_FLAGRO0x1CORE6 WFI Flag
Reflects the WFI flag generated by CORE6
When CORE6 enters WFI, this field is set
25AP_CORE5_C2RO0x1CORE5 in C2 Mode Indication.
Indicates whether CORE5 is in C2 mode.
1'b1: CORE5 is in C2 mode
24AP_CORE5_C1RO0x0CORE5 in C1 Mode Indication.
Indicates whether CORE5 is in C1 mode (external mode).
1'b1: CORE5 is in C1 mode
23AP_CORE5_WFI_FLAGRO0x1CORE5 WFI Flag
Reflects the WFI flag generated by CORE5
When CORE5 enters WFI, this field is set
22AP_CORE4_C2RO0x1CORE4 in C2 Mode Indication.
Indicates whether CORE4 is in C2 mode.
1'b1: CORE4 is in C2 mode
21AP_CORE4_C1RO0x0CORE4 in C1 Mode Indication.
Indicates whether CORE4 is in C1 mode (external mode).
1'b1: CORE4 is in C1 mode
20AP_CORE4_WFI_FLAGRO0x1CORE4 WFI Flag
Reflects the WFI flag generated by CORE4
When CORE4 enters WFI, this field is set
19AP_C1_MPSUB_M2RO0x1Cluster1 Subsystem idle mode Indication.
Indicates whether cluster1 Subsystem is in M2 mode.
1'b1: Cluster1 Subsystem is in M2 mode
18AP_C1_MPSUB_M1RO0x0Cluster1 Subsystem in M1 Mode Indication
Indicates whether Cluster1 Subsystem is in M1 mode (external idle mode).
1'b1: Cluster1 Subsystem is in M1 mode
17AP_C1_MPSUB_IDLE_FLAGRO0x1Cluster1 Subsystem Idle Flag
Reflects the AND logic value of SCU_IDLE and L2CLKSTOPPED generated for Cluster1 Subsystem.
1'b1: core0/core1/core2/core3/scu/L2 are all in idle state
16SP_IDLERO0x1Core idle mode Indication
Indicates whether Core is in "core idle mode" mode.
1'b1: Core is in core idle mode
15AP_CORE3_C2RO0x1CORE3 in C2 Mode Indication.
Indicate whether CORE3 is in C2 mode.
1'b1: CORE3 is in C2 mode
14AP_CORE3_C1RO0x0CORE3 in C1 Mode Indication.
Indicate whether CORE3 is in C1 mode (external idle mode).
1'b1: CORE3 is in C1 mode
13AP_CORE3_WFI_FLAGRO0x1CORE3 WFI Flag
Reflects the WFI flag generated by CORE3.
When CORE3 enters WFI, this field is set.
12AP_CORE2_C2RO0x1CORE2 in C2 Mode Indication.
Indicate whether CORE2 is in C2 mode.
1'b1: CORE2 is in C2 mode
11AP_CORE2_C1RO0x0CORE2 in C1 Mode Indication.
Indicate whether CORE2 is in C1 mode (external idle mode).
1'b1: CORE2 is in C1 mode
10AP_CORE2_WFI_FLAGRO0x1CORE2 WFI Flag
Reflects the WFI flag generated by CORE2.
When CORE2 enters WFI, this field is set.
9AP_CORE1_C2RO0x1CORE1 in C2 Mode Indication.
Indicate whether CORE1 is in C2 mode.
1'b1: CORE1 is in C2 mode
8AP_CORE1_C1RO0x0CORE1 in C1 Mode Indication.
Indicate whether CORE1 is in C1 mode (external idle mode).
1'b1: CORE1 is in C1 mode
7AP_CORE1_WFI_FLAGRO0x1CORE1 WFI Flag
Reflects the WFI flag generated by CORE1.
When CORE1 enters WFI, this field is set.
6AP_CORE0_C2RO0x0CORE0 in C2 Mode Indication.
Indicate whether CORE0 is in C2 mode.
1'b1: CORE0 is in C2 mode
5AP_CORE0_C1RO0x0CORE0 in C1 Mode Indication.
Indicate whether CORE0 is in C1 mode (external idle mode).
1'b1: CORE0 is in C1 mode
4AP_CORE0_WFI_FLAGRO0x0CORE0 WFI Flag
Reflects the WFI flag generated by CORE0.
When CORE0 enters WFI, this field is set.
3AP_C0_MPSUB_M2RO0x0Cluster0 Subsystem idle mode Indication.
Indicates whether Cluster1 MP Subsystem is in M2 mode.
1'b1: Cluster0 MP Subsystem is in M2 mode
2AP_C0_MPSUB_M1RO0x0Cluster0 Subsystem in M1 Mode Indication
Indicates whether Cluster0 MP Subsystem is in M1 mode (external idle mode).
1'b1: Cluster0 MP Subsystem is in M1 mode
1AP_C0_MPSUB_IDLE_FLAGRO0x0Cluster0 Subsystem Idle Flag.
Reflects the AND logic value of SCU_IDLE and L2CLKSTOPPED generated in the Cluster0 MP Subsystem.
1'b1: core0/core1/core2/core3/scu/L2 are all in idle state
0RSVDRO0x0Reserved
+Offset: 0xD4282800+0x90 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | AP_CORE7_C2 | RO | 0x1 | CORE7 in C2 Mode Indication. Indicates whether CORE7 is in C2 mode. 1'b1: CORE7 is in C2 mode | +| 30 | AP_CORE7_C1 | RO | 0x0 | CORE7 in C1 Mode Indication. Indicates whether CORE7 is in C1 mode (external mode). 1'b1: CORE7 is in C1 mode | +| 29 | AP_CORE7_WFI_FLAG | RO | 0x1 | CORE7 WFI Flag Reflects the WFI flag generated by CORE7When CORE7 enters WFI, this field is set | +| 28 | AP_CORE6_C2 | RO | 0x1 | CORE6 in C2 Mode Indication. Indicates whether CORE6 is in C2 mode. 1'b1: CORE6 is in C2 mode | +| 27 | AP_CORE6_C1 | RO | 0x0 | CORE6 in C1 Mode Indication. Indicates whether CORE6 is in C1 mode (external mode). 1'b1: CORE6 is in C1 mode | +| 26 | AP_CORE6_WFI_FLAG | RO | 0x1 | CORE6 WFI Flag Reflects the WFI flag generated by CORE6When CORE6 enters WFI, this field is set | +| 25 | AP_CORE5_C2 | RO | 0x1 | CORE5 in C2 Mode Indication. Indicates whether CORE5 is in C2 mode. 1'b1: CORE5 is in C2 mode | +| 24 | AP_CORE5_C1 | RO | 0x0 | CORE5 in C1 Mode Indication. Indicates whether CORE5 is in C1 mode (external mode). 1'b1: CORE5 is in C1 mode | +| 23 | AP_CORE5_WFI_FLAG | RO | 0x1 | CORE5 WFI Flag Reflects the WFI flag generated by CORE5When CORE5 enters WFI, this field is set | +| 22 | AP_CORE4_C2 | RO | 0x1 | CORE4 in C2 Mode Indication. Indicates whether CORE4 is in C2 mode. 1'b1: CORE4 is in C2 mode | +| 21 | AP_CORE4_C1 | RO | 0x0 | CORE4 in C1 Mode Indication. Indicates whether CORE4 is in C1 mode (external mode). 1'b1: CORE4 is in C1 mode | +| 20 | AP_CORE4_WFI_FLAG | RO | 0x1 | CORE4 WFI Flag Reflects the WFI flag generated by CORE4When CORE4 enters WFI, this field is set | +| 19 | AP_C1_MPSUB_M2 | RO | 0x1 | Cluster1 Subsystem idle mode Indication. Indicates whether cluster1 Subsystem is in M2 mode.1'b1: Cluster1 Subsystem is in M2 mode | +| 18 | AP_C1_MPSUB_M1 | RO | 0x0 | Cluster1 Subsystem in M1 Mode Indication Indicates whether Cluster1 Subsystem is in M1 mode (external idle mode).1'b1: Cluster1 Subsystem is in M1 mode | +| 17 | AP_C1_MPSUB_IDLE_FLAG | RO | 0x1 | Cluster1 Subsystem Idle Flag Reflects the AND logic value of SCU_IDLE and L2CLKSTOPPED generated for Cluster1 Subsystem. 1'b1: core0/core1/core2/core3/scu/L2 are all in idle state | +| 16 | SP_IDLE | RO | 0x1 | Core idle mode Indication Indicates whether Core is in "core idle mode" mode. 1'b1: Core is in core idle mode | +| 15 | AP_CORE3_C2 | RO | 0x1 | CORE3 in C2 Mode Indication. Indicate whether CORE3 is in C2 mode. 1'b1: CORE3 is in C2 mode | +| 14 | AP_CORE3_C1 | RO | 0x0 | CORE3 in C1 Mode Indication. Indicate whether CORE3 is in C1 mode (external idle mode). 1'b1: CORE3 is in C1 mode | +| 13 | AP_CORE3_WFI_FLAG | RO | 0x1 | CORE3 WFI Flag Reflects the WFI flag generated by CORE3. When CORE3 enters WFI, this field is set. | +| 12 | AP_CORE2_C2 | RO | 0x1 | CORE2 in C2 Mode Indication. Indicate whether CORE2 is in C2 mode. 1'b1: CORE2 is in C2 mode | +| 11 | AP_CORE2_C1 | RO | 0x0 | CORE2 in C1 Mode Indication. Indicate whether CORE2 is in C1 mode (external idle mode). 1'b1: CORE2 is in C1 mode | +| 10 | AP_CORE2_WFI_FLAG | RO | 0x1 | CORE2 WFI Flag Reflects the WFI flag generated by CORE2. When CORE2 enters WFI, this field is set. | +| 9 | AP_CORE1_C2 | RO | 0x1 | CORE1 in C2 Mode Indication. Indicate whether CORE1 is in C2 mode. 1'b1: CORE1 is in C2 mode | +| 8 | AP_CORE1_C1 | RO | 0x0 | CORE1 in C1 Mode Indication. Indicate whether CORE1 is in C1 mode (external idle mode). 1'b1: CORE1 is in C1 mode | +| 7 | AP_CORE1_WFI_FLAG | RO | 0x1 | CORE1 WFI Flag Reflects the WFI flag generated by CORE1. When CORE1 enters WFI, this field is set. | +| 6 | AP_CORE0_C2 | RO | 0x0 | CORE0 in C2 Mode Indication. Indicate whether CORE0 is in C2 mode. 1'b1: CORE0 is in C2 mode | +| 5 | AP_CORE0_C1 | RO | 0x0 | CORE0 in C1 Mode Indication. Indicate whether CORE0 is in C1 mode (external idle mode). 1'b1: CORE0 is in C1 mode | +| 4 | AP_CORE0_WFI_FLAG | RO | 0x0 | CORE0 WFI Flag Reflects the WFI flag generated by CORE0. When CORE0 enters WFI, this field is set. | +| 3 | AP_C0_MPSUB_M2 | RO | 0x0 | Cluster0 Subsystem idle mode Indication. Indicates whether Cluster1 MP Subsystem is in M2 mode.1'b1: Cluster0 MP Subsystem is in M2 mode | +| 2 | AP_C0_MPSUB_M1 | RO | 0x0 | Cluster0 Subsystem in M1 Mode Indication Indicates whether Cluster0 MP Subsystem is in M1 mode (external idle mode).1'b1: Cluster0 MP Subsystem is in M1 mode | +| 1 | AP_C0_MPSUB_IDLE_FLAG | RO | 0x0 | Cluster0 Subsystem Idle Flag. Reflects the AND logic value of SCU_IDLE and L2CLKSTOPPED generated in the Cluster0 MP Subsystem. 1'b1: core0/core1/core2/core3/scu/L2 are all in idle state | +| 0 | RSVD | RO | 0x0 | Reserved | #### RESUME FROM SLEEP CLEAR REGISTER (PMU_RES_FRM_SLP_CLR) - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x94
BitsFieldTypeResetDescription
31:1RSVDRO0x0Reserved
0CLR_RSM_FRM_SLPRW0x0Clear Resume from Sleep Indication
1'b1: Clear the status signal in CIU sys_boot_cntr[14]
+Offset: 0xD4282800+0x94 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:1 | RSVD | RO | 0x0 | Reserved | +| 0 | CLR_RSM_FRM_SLP | RW | 0x0 | Clear Resume from Sleep Indication1'b1: Clear the status signal in CIU sys_boot_cntr[14] | ##### VPU POWER CONTROL REGISTER (PMU_VPU_PWR_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0xA8
BitsFieldTypeResetDescription
31:5RSVDRO0x0Reserved
4RSVDRW0x0Reserved
3VPU_SLEEP2RW0x0VPU Power Switch Sleep2
2VPU_SLEEP1RW0x0VPU Power Switch Sleep1
1VPU_ISOBRW0x0VPU Isolation Wrapper
1'b0: Enable isolation (VPU power-down mode)
1'b1: disable isolation (VPU active mode)
0RSVDRW0x0Reserved
+Offset: 0xD4282800+0xA8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:5 | RSVD | RO | 0x0 | Reserved | +| 4 | RSVD | RW | 0x0 | Reserved | +| 3 | VPU_SLEEP2 | RW | 0x0 | VPU Power Switch Sleep2 | +| 2 | VPU_SLEEP1 | RW | 0x0 | VPU Power Switch Sleep1 | +| 1 | VPU_ISOB | RW | 0x0 | VPU Isolation Wrapper 1'b0: Enable isolation (VPU power-down mode) 1'b1: disable isolation (VPU active mode) | +| 0 | RSVD | RW | 0x0 | Reserved | ##### GPU POWER CONTROL REGISTER (PMU_GPU_PWR_CTRL) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0xD0
BitsFieldTypeResetDescription
31:5RSVDRO0x0Reserved
4RSVDRW0x0Reserved
3GPU_SLEEP2RW0x0GPU Power Switch Sleep2
2GPU_SLEEP1RW0x0GPU Power Switch Sleep1
1GPU_ISOBRW0x0GPU Isolation Wrapper
1'b0: Enable isolation (GPU power-down mode)
1'b1: disable isolation (GPU active mode)
0RSVDRW0x0Reserved
+Offset: 0xD4282800+0xD0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:5 | RSVD | RO | 0x0 | Reserved | +| 4 | RSVD | RW | 0x0 | Reserved | +| 3 | GPU_SLEEP2 | RW | 0x0 | GPU Power Switch Sleep2 | +| 2 | GPU_SLEEP1 | RW | 0x0 | GPU Power Switch Sleep1 | +| 1 | GPU_ISOB | RW | 0x0 | GPU Isolation Wrapper 1'b0: Enable isolation (GPU power-down mode) 1'b1: disable isolation (GPU active mode) | +| 0 | RSVD | RW | 0x0 | Reserved | ##### BLOCK POWER TIMER REGISTER (PMUA_PWR_BLK_TMR_REG) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0xDC
BitsFieldTypeResetDescription
31:16PWR_ON1_TIMERRW0x8Delay for GPU/VPU/ISP/Audio auto-power on from Sleep1 to Sleep2
15:8PWR_ON2_TIMERRW0x64Delay for GPU/VPU/ISP/Audio auto-power on from Sleep2 to clock_en
7:0PWR_OFF_TIMERRW0x0Delay for GPU/VPU/ISP/Audio auto-power off from Sleep2 to Sleep1
+Offset: 0xD4282800+0xDC +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:16 | PWR_ON1_TIMER | RW | 0x8 | Delay for GPU/VPU/ISP/Audio auto-power on from Sleep1 to Sleep2 | +| 15:8 | PWR_ON2_TIMER | RW | 0x64 | Delay for GPU/VPU/ISP/Audio auto-power on from Sleep2 to clock_en | +| 7:0 | PWR_OFF_TIMER | RW | 0x0 | Delay for GPU/VPU/ISP/Audio auto-power off from Sleep2 to Sleep1 | ##### CLUSTER0 MP IDLE CONFIGURATION REGISTER FOR CORE X (PMU_C0_CAPMP_IDLE_CFGX_X;X=0/1/2/3) @@ -12379,484 +3463,86 @@ This register is used by cluster0 core x to vote MP subsystem low power mode. PMU_C0_IDLE_CFGx (x=0,1,2,3) are fully symmetric. Each bit of the register takes effect only when all corresponding bits of PMU_C0__IDLE_CFGx are set to 1. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x120/0xE4/0x150/0x154
BitsFieldTypeResetDescription
31:20RSVDRO0Reserved
19DIS_MP_L2_SLPRW0x0Disable L2 Power Switch
Disables the MP L2 power switch sleep power down during MP power down mode.
1'b1: Disable MP L2 power switch
18DIS_MP_SLPRW0x0Disable MP Power Switch.
Disables the MP power switch sleep power down during MP subsystem power down mode.
1'b1: Disable MP power switch sleep
17RSVDRO0
16FRC_L2_SRAM_OffRW0x0Frequency Change L2 SRAM Off.
1'b1: L2 Frequency Change is off
15:14RSVDRO0Reserved
13L2_HW_CACHE_FLUSH_ENRW0x0L2 Hardware Cache Flush Enable.
1'b1: Enable
12MASK_SRAM_REPAIR_DONE_CHECKRW0x0Mask SRAM Repair Done Check.
1'b1: Mask SRAM repair done check
11MASK_CLK_OFF_CHECKRW0x0Mask the MP Clock Off State Check.
Masks the MP clock off check during the MP idle process.
10MASK_CLK_STBL_CHECKRW0x0Mask MP clock stable State Check.
Masks the MP clock stable check during MP wakeup.
9MASK_JTAG_IDLE_CHECKRW0x0Mask JTAG Idle State Check.
Masks the JTAG idle check during the MP idle entry.
1'b1: Mask JTAG idle check
8MASK_IDLE_CHECKRW0x0Mask the MP Idle State Check.
7ACINACTM_HW_CTRLRW0x0ACINACTM Hardware Control.
1'b0: low power state machine does not control ACINACTM port. 1'b1: low power state machine controls ACINACTM port of MP. When M2/M1 low power mode is entered, ACINACTM port will be high
6RSVDRO0Reserved
5DIS_MC_SW_REQRW0x0Disable Memory Controller Software Request.
Disables the Memory Controller entry to idle mode using the Memory Controller sleep request bits. The Memory Controller will always enter into idle mode based on the hardware state machine
4MP_WAKE_MC_ENRW0x0MP Wake Memory Controller Enable.
Wakes up the Memory Controller when the MP wakes up from idle mode. The Memory Controller is woken up before the interrupt to the core is released.
1'b0: Memory Controller wakes up if MP wakes up from idle mode
3MP_SCU_SRAM_PWRDWNRW0x0No Used.
SCU SRAM does not support retention
2L2_SRAM_PWRDWNRW0x0L2 Cache SRAM Power Down
This field does not take effect if MP_PWRDWN is 0.
1'b1: When MP is idle, L2 SRAM power will be off.
1'b0: When MP is idle, L2 SRAM is in retention mode
1MP_PWRDWNRW0x0MP Power Down.
This field does not take effect if MP_IDLE is 0.
1'b1: When MP is idle, MP will go into deep sleep mode and the MP logic will be power-gated
0MP_IDLERW0x0MP Idle.
1'b1: When MP is idle, the MP clocks will be gated externally
+Offset: 0xD4282800+0x120/0xE4/0x150/0x154 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:20 | RSVD | RO | 0 | Reserved | +| 19 | DIS_MP_L2_SLP | RW | 0x0 | Disable L2 Power SwitchDisables the MP L2 power switch sleep power down during MP power down mode. 1'b1: Disable MP L2 power switch | +| 18 | DIS_MP_SLP | RW | 0x0 | Disable MP Power Switch. Disables the MP power switch sleep power down during MP subsystem power down mode.1'b1: Disable MP power switch sleep | +| 17 | RSVD | RO | 0 | | +| 16 | FRC_L2_SRAM_Off | RW | 0x0 | Frequency Change L2 SRAM Off.1'b1: L2 Frequency Change is off | +| 15:14 | RSVD | RO | 0 | Reserved | +| 13 | L2_HW_CACHE_FLUSH_EN | RW | 0x0 | L2 Hardware Cache Flush Enable.1'b1: Enable | +| 12 | MASK_SRAM_REPAIR_DONE_CHECK | RW | 0x0 | Mask SRAM Repair Done Check.1'b1: Mask SRAM repair done check | +| 11 | MASK_CLK_OFF_CHECK | RW | 0x0 | Mask the MP Clock Off State Check.Masks the MP clock off check during the MP idle process. | +| 10 | MASK_CLK_STBL_CHECK | RW | 0x0 | Mask MP clock stable State Check.Masks the MP clock stable check during MP wakeup. | +| 9 | MASK_JTAG_IDLE_CHECK | RW | 0x0 | Mask JTAG Idle State Check.Masks the JTAG idle check during the MP idle entry. 1'b1: Mask JTAG idle check | +| 8 | MASK_IDLE_CHECK | RW | 0x0 | Mask the MP Idle State Check. | +| 7 | ACINACTM_HW_CTRL | RW | 0x0 | ACINACTM Hardware Control.1'b0: low power state machine does not control ACINACTM port. 1'b1: low power state machine controls ACINACTM port of MP. When M2/M1 low power mode is entered, ACINACTM port will be high | +| 6 | RSVD | RO | 0 | Reserved | +| 5 | DIS_MC_SW_REQ | RW | 0x0 | Disable Memory Controller Software Request. Disables the Memory Controller entry to idle mode using the Memory Controller sleep request bits. The Memory Controller will always enter into idle mode based on the hardware state machine | +| 4 | MP_WAKE_MC_EN | RW | 0x0 | MP Wake Memory Controller Enable. Wakes up the Memory Controller when the MP wakes up from idle mode. The Memory Controller is woken up before the interrupt to the core is released. 1'b0: Memory Controller wakes up if MP wakes up from idle mode | +| 3 | MP_SCU_SRAM_PWRDWN | RW | 0x0 | No Used. SCU SRAM does not support retention | +| 2 | L2_SRAM_PWRDWN | RW | 0x0 | L2 Cache SRAM Power Down This field does not take effect if MP_PWRDWN is 0. 1'b1: When MP is idle, L2 SRAM power will be off.1'b0: When MP is idle, L2 SRAM is in retention mode | +| 1 | MP_PWRDWN | RW | 0x0 | MP Power Down. This field does not take effect if MP_IDLE is 0. 1'b1: When MP is idle, MP will go into deep sleep mode and the MP logic will be power-gated | +| 0 | MP_IDLE | RW | 0x0 | MP Idle.1'b1: When MP is idle, the MP clocks will be gated externally | ##### POWER STATUS REGISTER (PMUA_PWR_STATUS_REG) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0xF0
BitsFieldTypeResetDescription
31:13RSVDRO0x0Reserved
12LCD_HW_PWR_STATRO0x0HW Power Mode updates the status when the LCD enters/exits its LPM.
11AUDIO_HW_PWR_STATRO0x0HW Power Mode updates the status when the Audio enters/exits its LPM.
1'b0: Audio is powered off
1'b1: Audio is powered on
10ISP_HW_PWR_STATRO0x0HW Power Mode updates the status when the ISP enters/exits its LPM.
9VPU_HW_PWR_STATRO0x0HW Power Mode updates the status when the VPU enters/exits its LPM.
8GPU_HW_PWR_STATRO0x0HW Power Mode updates the status when the GPU enters/exits its LPM.
7:5RSVDRO0Reserved
4LCD_PWR_STATUSRO0x0LCD power state including both HW and SW power mode.
1'b1: Power on
1'b0: Power off
3AUDIO_PWR_STATUSRO0x0Audio Power State including both HW and SW power mode.
1'b1: Power on
1'b0: Power off
2ISP_PWR_STATUSRO0x0ISP power state including both HW and SW power mode.
1'b1: Power on
1'b0: Power off
1VPU_PWR_STATUSRO0x0 VPU power state including both HW and SW power mode.
1'b1: Power on.
1'b0: Power off
0GPU_PWR_STATUSRO0x0GPU power state including both HW and SW power mode.
1'b1: Power on.
1'b0: Power off
+Offset: 0xD4282800+0xF0 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:13 | RSVD | RO | 0x0 | Reserved | +| 12 | LCD_HW_PWR_STAT | RO | 0x0 | HW Power Mode updates the status when the LCD enters/exits its LPM. | +| 11 | AUDIO_HW_PWR_STAT | RO | 0x0 | HW Power Mode updates the status when the Audio enters/exits its LPM. 1'b0: Audio is powered off1'b1: Audio is powered on | +| 10 | ISP_HW_PWR_STAT | RO | 0x0 | HW Power Mode updates the status when the ISP enters/exits its LPM. | +| 9 | VPU_HW_PWR_STAT | RO | 0x0 | HW Power Mode updates the status when the VPU enters/exits its LPM. | +| 8 | GPU_HW_PWR_STAT | RO | 0x0 | HW Power Mode updates the status when the GPU enters/exits its LPM. | +| 7:5 | RSVD | RO | 0 | Reserved | +| 4 | LCD_PWR_STATUS | RO | 0x0 | LCD power state including both HW and SW power mode.1'b1: Power on1'b0: Power off | +| 3 | AUDIO_PWR_STATUS | RO | 0x0 | Audio Power State including both HW and SW power mode.1'b1: Power on1'b0: Power off | +| 2 | ISP_PWR_STATUS | RO | 0x0 | ISP power state including both HW and SW power mode.1'b1: Power on1'b0: Power off | +| 1 | VPU_PWR_STATUS | RO | 0x0 | VPU power state including both HW and SW power mode.1'b1: Power on.1'b0: Power off | +| 0 | GPU_PWR_STATUS | RO | 0x0 | GPU power state including both HW and SW power mode. 1'b1: Power on.1'b0: Power off | ##### USB PHY READ REGISTER (PMUA_USB_PHY_READ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x118
BitsFieldTypeResetDescription
31:22RSVD3RO0x0Reserved
21USB3_PHY_RXELECIDLERO0x0USB3 PHY RXELECIDLE output
20:19USB3_PHY_LINESTATERO0x0USB3 PHY line_state[1:0] output
18USB3_PHY_VBUSVALIDRO0x0USB3 PHY Vbus Valid output
17USB3_PHY_IDDIGRO0x0USB3 PHY ID DIG output
16USB3_PHY_CHGDECTRO0x0USB3 PHY CHGDECT output
15:13RSVD1RO0x0Reserved
12:11USBP1_PHY_LINESTATERO0x0USBP1 PHY line_state[1:0] output
10USBP1_PHY_VBUSVALIDRO0x0USBP1 PHY VbusValid output
9USBP1_PHY_IDDIGRO0x0USBP1 PHY ID DIG output
8USBP1_PHY_CHGDECTRO0x0USBP1 PHY CHGDECT output
7:5RSVD0RO0x0Reserved
4:3USB_PHY_LINESTATERO0x0USB PHY line_state[1:0] output
2USB_PHY_VBUSVALIDRO0x0USB PHY VbusValid output
1USB_PHY_IDDIGRO0x0USB PHY ID DIG output
0USB_PHY_CHGDECTRO0x0USB PHY CHGDECT output
- -##### CORE X IDLE CONFIGURATION REGISTER (PMU_CAP_COREX_IDLE_CFG_X) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x124/0x128/0x160/0x164/0x304/0x308/0x30C/0x310
BitsFieldTypeResetDescription
31:12RSVDRO0x0Reserved
11MASK_CLK_OFF_CHECKRW0x0Mask core clock off check during core idle process.
10MASK_CLK_STBL_CHECKRW0x0Mask core clock stable check during core wakeup.
9MASK_JTAG_IDLE_CHECKRW0x0Mask the JTAG idle check during MP idle entry.
1'b1: Mask the JTAG idle check.
8MASK_CORE_WFI_IDLE_CHECKRW0x0Mask the Core WFI IDLE check during MP idle entry.
1'b1: Mask the core wait for interrupt idle check
7:5RSVDRO0x0Reserved
4MASK_GIC_NFIQ_TO_CORERW0x0Mask nFIQ generated in GIC for CORE.
Software can set this bit before CORE enter C2.
APMU hardware will automatically clear this bit when CORE enters C2
3MASK_GIC_NIRQ_TO_CORERW0x0Mask nIRQ generated in GIC for CORE.
Software can set this bit before CORE enter C2.
APMU hardware will automatically clear this bit when CORE enters C2
2RSVDRO0x0Reserved
1CORE_PWRDWNRW0x0Core Power Down.
This bit does not takes effect if CORE_IDLE is 0.
1'b1: When core issues WFI idle, core goes into deep sleep mode and power is off.
This bit will not take effect if dbgnopwrdwn is set
0CORE_IDLERW0x0Core Idle.
1'b1: When core issues WFI idle, the core clock will be gated externally.
This bit will not take effect if dbgnopwrdwn is set
+Offset: 0xD4282800+0x118 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:22 | RSVD3 | RO | 0x0 | Reserved | +| 21 | USB3_PHY_RXELECIDLE | RO | 0x0 | USB3 PHY RXELECIDLE output | +| 20:19 | USB3_PHY_LINESTATE | RO | 0x0 | USB3 PHY line_state[1:0] output | +| 18 | USB3_PHY_VBUSVALID | RO | 0x0 | USB3 PHY Vbus Valid output | +| 17 | USB3_PHY_IDDIG | RO | 0x0 | USB3 PHY ID DIG output | +| 16 | USB3_PHY_CHGDECT | RO | 0x0 | USB3 PHY CHGDECT output | +| 15:13 | RSVD1 | RO | 0x0 | Reserved | +| 12:11 | USBP1_PHY_LINESTATE | RO | 0x0 | USBP1 PHY line_state[1:0] output | +| 10 | USBP1_PHY_VBUSVALID | RO | 0x0 | USBP1 PHY VbusValid output | +| 9 | USBP1_PHY_IDDIG | RO | 0x0 | USBP1 PHY ID DIG output | +| 8 | USBP1_PHY_CHGDECT | RO | 0x0 | USBP1 PHY CHGDECT output | +| 7:5 | RSVD0 | RO | 0x0 | Reserved | +| 4:3 | USB_PHY_LINESTATE | RO | 0x0 | USB PHY line_state[1:0] output | +| 2 | USB_PHY_VBUSVALID | RO | 0x0 | USB PHY VbusValid output | +| 1 | USB_PHY_IDDIG | RO | 0x0 | USB PHY ID DIG output | +| 0 | USB_PHY_CHGDECT | RO | 0x0 | USB PHY CHGDECT output | + +##### CORE X IDLE CONFIGURATION REGISTER (PMU_CAP_COREX_IDLE_CFG_X) + +Offset: 0xD4282800+0x124/0x128/0x160/0x164/0x304/0x308/0x30C/0x310 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:12 | RSVD | RO | 0x0 | Reserved | +| 11 | MASK_CLK_OFF_CHECK | RW | 0x0 | Mask core clock off check during core idle process. | +| 10 | MASK_CLK_STBL_CHECK | RW | 0x0 | Mask core clock stable check during core wakeup. | +| 9 | MASK_JTAG_IDLE_CHECK | RW | 0x0 | Mask the JTAG idle check during MP idle entry.1'b1: Mask the JTAG idle check. | +| 8 | MASK_CORE_WFI_IDLE_CHECK | RW | 0x0 | Mask the Core WFI IDLE check during MP idle entry.1'b1: Mask the core wait for interrupt idle check | +| 7:5 | RSVD | RO | 0x0 | Reserved | +| 4 | MASK_GIC_NFIQ_TO_CORE | RW | 0x0 | Mask nFIQ generated in GIC for CORE. Software can set this bit before CORE enter C2. APMU hardware will automatically clear this bit when CORE enters C2 | +| 3 | MASK_GIC_NIRQ_TO_CORE | RW | 0x0 | Mask nIRQ generated in GIC for CORE. Software can set this bit before CORE enter C2. APMU hardware will automatically clear this bit when CORE enters C2 | +| 2 | RSVD | RO | 0x0 | Reserved | +| 1 | CORE_PWRDWN | RW | 0x0 | Core Power Down. This bit does not takes effect if CORE_IDLE is 0. 1'b1: When core issues WFI idle, core goes into deep sleep mode and power is off. This bit will not take effect if dbgnopwrdwn is set | +| 0 | CORE_IDLE | RW | 0x0 | Core Idle.1'b1: When core issues WFI idle, the core clock will be gated externally. This bit will not take effect if dbgnopwrdwn is set | ##### CORE X WAKEUP REGISTER (PMU_CAP_COREX_WAKEUP_X) @@ -12864,83 +3550,18 @@ This register is used by Core x software to wake up other cores in Cluster0/1. To avoid software lock issues, other cores in the MP subsystem should not write to this register. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x12C/0x130/0x134/0x138/0x324/0x328/0x32C/0x330
BitsFieldTypeResetDescription
31:8RSVDRO0Reserved
7WAKEUP_CORE7RW0x0Wakeup Core7
- Writing 1 to this field:
1. Wakes up Core 7
2. Has no effect if Core 7 is in C0 mode
- Writing 0 to this field: No effect
The PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode.
6WAKEUP_CORE6RW0x0Wakeup Core6
- Writing 1 to this field:
1. Wakes up Core 6
2. Has no effect if Core 6 is in C0 mode
- Writing 0 to this field: No effect
The PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode.
5WAKEUP_CORE5RW0x0Wakeup Core5
- Writing 1 to this field:
1. Wakes up Core 5
2. Has no effect if Core 5 is in C0 mode
- Writing 0 to this field: No effect
The PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode.
4WAKEUP_CORE4RW0x0Wakeup Core 4
- Writing 1 to this field:
1. Wakes up Core 4
2. Has no effect if Core 4 is in C0 mode
- Writing 0 to this field: No effect
The PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode.
3WAKEUP_CORE3RW0x0Wakeup Core3
- Writing 1 to this field:
1. Wakes up Core 3
2. Has no effect if Core 3 is in C0 mode
- Writing 0 to this field: No effect
The PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode.
2WAKEUP_CORE2RW0x0Wakeup Core2
- Writing 1 to this field:
1. Wakes up Core 2
2. Has no effect if Core 2 is in C0 mode
- Writing 0 to this field: No effect
The PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode.
1WAKEUP_CORE1RW0x0Wakeup Core1
- Writing 1 to this field:
1. Wakes up Core 1
2. Has no effect if Core 1 is in C0 mode
- Writing 0 to this field: No effect
The PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode.
0WAKEUP_CORE0RW0x0Wakeup Core 0
- Writing 1 to this field:
1. Wakes up Core 0
2. Has no effect if Core 0 is in C0 mode
- Writing 0 to this field: No effect
The PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode.
+Offset: 0xD4282800+0x12C/0x130/0x134/0x138/0x324/0x328/0x32C/0x330 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:8 | RSVD | RO | 0 | Reserved | +| 7 | WAKEUP_CORE7 | RW | 0x0 | Wakeup Core7 - Writing 1 to this field: 1. Wakes up Core 7 2. Has no effect if Core 7 is in C0 mode- Writing 0 to this field: No effectThe PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode. | +| 6 | WAKEUP_CORE6 | RW | 0x0 | Wakeup Core6 - Writing 1 to this field: 1. Wakes up Core 6 2. Has no effect if Core 6 is in C0 mode- Writing 0 to this field: No effectThe PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode. | +| 5 | WAKEUP_CORE5 | RW | 0x0 | Wakeup Core5 - Writing 1 to this field: 1. Wakes up Core 5 2. Has no effect if Core 5 is in C0 mode- Writing 0 to this field: No effectThe PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode. | +| 4 | WAKEUP_CORE4 | RW | 0x0 | Wakeup Core 4 - Writing 1 to this field: 1. Wakes up Core 4 2. Has no effect if Core 4 is in C0 mode- Writing 0 to this field: No effectThe PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode. | +| 3 | WAKEUP_CORE3 | RW | 0x0 | Wakeup Core3 - Writing 1 to this field: 1. Wakes up Core 3 2. Has no effect if Core 3 is in C0 mode- Writing 0 to this field: No effectThe PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode. | +| 2 | WAKEUP_CORE2 | RW | 0x0 | Wakeup Core2 - Writing 1 to this field: 1. Wakes up Core 2 2. Has no effect if Core 2 is in C0 mode- Writing 0 to this field: No effectThe PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode. | +| 1 | WAKEUP_CORE1 | RW | 0x0 | Wakeup Core1 - Writing 1 to this field: 1. Wakes up Core 1 2. Has no effect if Core 1 is in C0 mode- Writing 0 to this field: No effectThe PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode. | +| 0 | WAKEUP_CORE0 | RW | 0x0 | Wakeup Core 0 - Writing 1 to this field: 1. Wakes up Core 0 2. Has no effect if Core 0 is in C0 mode- Writing 0 to this field: No effectThe PMU hardware automatically clears this bit when Core 3 exits C1/C2 mode. | ##### CLUSTER1 MP IDLE CONFIGURATION REGISTER FOR CORE X (PMU_C1_CAPMP_IDLE_CFGX_X) @@ -12949,763 +3570,134 @@ This register is used by Cluster 1 - Core x to vote for MP subsystem low power m - PMU_C1_IDLE_CFGx (x=0,1,2,3) registers are fully symmetric. - Each bit in the register takes effect only when all corresponding bits of PMU_C1__IDLE_CFGx are set to 1. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x314/0x318/0x31C/0x320
BitsFieldTypeResetDescription
31:20RSVDRO0Reserved
19DIS_MP_L2_SLPRW0x0Disable L2 Power Switch.
Disables the MP L2 power switch sleep power down during MP power down mode.
1'b1: Disables MP L2 power switch
18DIS_MP_SLPRW0x0Disable MP Power Switch.
Disables the MP power switch sleep power down during MP subsystem power down mode.
1'b1: Disables MP power switch sleep
17RSVDRO0
16FRC_L2_SRAM_OffRW0x0Frequency Change L2 SRAM Off.
1'b1: L2 Frequency change is off
15:14RSVDRO0Reserved
13L2_HW_CACHE_FLUSH_ENRW0x0L2 Hardware Cache Flush Enable
1'b1: Enable
12MASK_SRAM_REPAIR_DONE_CHECKRW0x0Mask SRAM Repair Done Check
1'b1: Mask SRAM repair done check
11MASK_CLK_OFF_CHECKRW0x0Mask the MP Clock Off State Check.
Masks the MP clock off check during the MP idle process
10MASK_CLK_STBL_CHECKRW0x0Mask MP clock stable State Check.
Masks the MP clock stable check during MP wakeup.
9MASK_JTAG_IDLE_CHECKRW0x0
8MASK_IDLE_CHECKRW0x0Mask the MP Idle State Check.
7ACINACTM_HW_CTRLRW0x0ACINACTM Hardware Control
1'b0: The low-power state machine does not control the ACINACTM port.
1'b1: The low-power state machine controls the ACINACTM port of MP. When M2/M1 low-power mode is entered, ACINACTM port will be set high
6RSVDRO0Reserved
5DIS_MC_SW_REQRW0x0Disable Memory Controller Software Request
Disables the Memory Controller entry to idle mode using the Memory Controller sleep request bits.
The Memory Controller will always enter into idle mode based on the hardware state machine
4MP_WAKE_MC_ENRW0x0MP Wake Memory Controller Enable
The Memory Controller will wake up before the interrupt to the core is released.
1'b0: Memory Controller will wake up when MP wakes up from idle mode
3MP_SCU_SRAM_PWRDWNRW0x0No Used
SCU SRAM does not support retention
2L2_SRAM_PWRDWNRW0x0L2 Cache SRAM Power Down
This field does not take effect if MP_PWRDWN is 0.
1'b1: When MP is idle, L2 SRAM power will be off
1'b0: When MP is idle, L2 SRAM is in retention mode
1MP_PWRDWNRW0x0MP Power Down
This field does not take effect if MP_IDLE is 0.
1'b1: When the MP is idle, MP enters deep sleep mode and the MP logic will be power-gated
0MP_IDLERW0x0MP Idle
1'b1: When MP is idle, the MP clocks will be gated externally
+Offset: 0xD4282800+0x314/0x318/0x31C/0x320 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:20 | RSVD | RO | 0 | Reserved | +| 19 | DIS_MP_L2_SLP | RW | 0x0 | Disable L2 Power Switch. Disables the MP L2 power switch sleep power down during MP power down mode.1'b1: Disables MP L2 power switch | +| 18 | DIS_MP_SLP | RW | 0x0 | Disable MP Power Switch. Disables the MP power switch sleep power down during MP subsystem power down mode.1'b1: Disables MP power switch sleep | +| 17 | RSVD | RO | 0 | | +| 16 | FRC_L2_SRAM_Off | RW | 0x0 | Frequency Change L2 SRAM Off.1'b1: L2 Frequency change is off | +| 15:14 | RSVD | RO | 0 | Reserved | +| 13 | L2_HW_CACHE_FLUSH_EN | RW | 0x0 | L2 Hardware Cache Flush Enable1'b1: Enable | +| 12 | MASK_SRAM_REPAIR_DONE_CHECK | RW | 0x0 | Mask SRAM Repair Done Check1'b1: Mask SRAM repair done check | +| 11 | MASK_CLK_OFF_CHECK | RW | 0x0 | Mask the MP Clock Off State Check.Masks the MP clock off check during the MP idle process | +| 10 | MASK_CLK_STBL_CHECK | RW | 0x0 | Mask MP clock stable State Check.Masks the MP clock stable check during MP wakeup. | +| 9 | MASK_JTAG_IDLE_CHECK | RW | 0x0 | | +| 8 | MASK_IDLE_CHECK | RW | 0x0 | Mask the MP Idle State Check. | +| 7 | ACINACTM_HW_CTRL | RW | 0x0 | ACINACTM Hardware Control1'b0: The low-power state machine does not control the ACINACTM port. 1'b1: The low-power state machine controls the ACINACTM port of MP. When M2/M1 low-power mode is entered, ACINACTM port will be set high | +| 6 | RSVD | RO | 0 | Reserved | +| 5 | DIS_MC_SW_REQ | RW | 0x0 | Disable Memory Controller Software RequestDisables the Memory Controller entry to idle mode using the Memory Controller sleep request bits. The Memory Controller will always enter into idle mode based on the hardware state machine | +| 4 | MP_WAKE_MC_EN | RW | 0x0 | MP Wake Memory Controller EnableThe Memory Controller will wake up before the interrupt to the core is released. 1'b0: Memory Controller will wake up when MP wakes up from idle mode | +| 3 | MP_SCU_SRAM_PWRDWN | RW | 0x0 | No UsedSCU SRAM does not support retention | +| 2 | L2_SRAM_PWRDWN | RW | 0x0 | L2 Cache SRAM Power Down This field does not take effect if MP_PWRDWN is 0.1'b1: When MP is idle, L2 SRAM power will be off1'b0: When MP is idle, L2 SRAM is in retention mode | +| 1 | MP_PWRDWN | RW | 0x0 | MP Power DownThis field does not take effect if MP_IDLE is 0.1'b1: When the MP is idle, MP enters deep sleep mode and the MP logic will be power-gated | +| 0 | MP_IDLE | RW | 0x0 | MP Idle1'b1: When MP is idle, the MP clocks will be gated externally | ##### AUDIO POWER CONTROL REGISTER (PMUA_PWR_CTRL_AUDIO) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x378
BitsFieldTypeResetDescription
31:5RSVDRO0x0Reserved
4HW_MODERW0x0Hardware Control Mode for AUD Power Up and Power Down
3AUD_SLEEP2RW0x0AUD Power Switch Sleep2
2AUD_SLEEP1RW0x0AUD Power Switch Sleep1
1AUD_ISOBRW0x0AUD Isolation Wrapper
1'b0: Enable isolation (AUD power-down mode)
1'b1: Disable isolation (AUD active mode)
0AUD_AUTO_PWR_ONRW0x0AUD Auto Power On
1: Triggers a request to power on the ISP power island.
0: Triggers a request to power down the ISP power island, but only if PWR_CTRL_AUD[4] is set.
+Offset: 0xD4282800+0x378 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:5 | RSVD | RO | 0x0 | Reserved | +| 4 | HW_MODE | RW | 0x0 | Hardware Control Mode for AUD Power Up and Power Down | +| 3 | AUD_SLEEP2 | RW | 0x0 | AUD Power Switch Sleep2 | +| 2 | AUD_SLEEP1 | RW | 0x0 | AUD Power Switch Sleep1 | +| 1 | AUD_ISOB | RW | 0x0 | AUD Isolation Wrapper1'b0: Enable isolation (AUD power-down mode)1'b1: Disable isolation (AUD active mode) | +| 0 | AUD_AUTO_PWR_ON | RW | 0x0 | AUD Auto Power On 1: Triggers a request to power on the ISP power island.0: Triggers a request to power down the ISP power island, but only if PWR_CTRL_AUD[4] is set. | ##### ISP POWER CONTROL REGISTER (PMUA_PWR_CTRL_ISP) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x37C
BitsFieldTypeResetDescription
31:5RSVDRO0x0Reserved
4HW_MODERW0x0Hardware Control Mode for ISP Power Up and Power Down
3ISP_SLEEP2RW0x0ISP Power Switch Sleep2
2ISP_SLEEP1RW0x0ISP Power Switch Sleep1
1ISP_ISOBRW0x0ISP Isolation Wrapper.
1'b0: Enable isolation (ISP power-down mode).
1'b1: Disable isolation (ISP active mode)
0ISP_AUTO_PWR_ONRW0x0ISP Auto Power On
1: Triggers a request to power on the ISP power island.
0: Triggers a request to power down the ISP power island, but only if PWR_CTRL_ISP[4] is set.
+Offset: 0xD4282800+0x37C +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:5 | RSVD | RO | 0x0 | Reserved | +| 4 | HW_MODE | RW | 0x0 | Hardware Control Mode for ISP Power Up and Power Down | +| 3 | ISP_SLEEP2 | RW | 0x0 | ISP Power Switch Sleep2 | +| 2 | ISP_SLEEP1 | RW | 0x0 | ISP Power Switch Sleep1 | +| 1 | ISP_ISOB | RW | 0x0 | ISP Isolation Wrapper.1'b0: Enable isolation (ISP power-down mode).1'b1: Disable isolation (ISP active mode) | +| 0 | ISP_AUTO_PWR_ON | RW | 0x0 | ISP Auto Power On 1: Triggers a request to power on the ISP power island.0: Triggers a request to power down the ISP power island, but only if PWR_CTRL_ISP[4] is set. | ##### LCD POWER CONTROL REGISTER (PMUA_PWR_CTRL_LCD) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x380
BitsFieldTypeResetDescription
31:5RSVDRO0x0Reserved
4HW_MODERW0x0Hardware Control Mode for LCD Power Up and Power Down
3LCD_SLEEP2RW0x0LCD Power Switch Sleep2
2LCD_SLEEP1RW0x0LCD Power Switch Sleep1
1LCD_ISOBRW0x0LCD Isolation Wrapper.
1'b0: Enable isolation (LCD power-down mode).
1'b1: Disable isolation (LCD active mode)
0LCD_AUTO_PWR_ONRW0x0LCD Auto Power On
1: Triggers a request to power on the ISP power island.
0: Triggers a request to power down the ISP power island, but only if PWR_CTRL_LCD[4] is set.
+Offset: 0xD4282800+0x380 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:5 | RSVD | RO | 0x0 | Reserved | +| 4 | HW_MODE | RW | 0x0 | Hardware Control Mode for LCD Power Up and Power Down | +| 3 | LCD_SLEEP2 | RW | 0x0 | LCD Power Switch Sleep2 | +| 2 | LCD_SLEEP1 | RW | 0x0 | LCD Power Switch Sleep1 | +| 1 | LCD_ISOB | RW | 0x0 | LCD Isolation Wrapper.1'b0: Enable isolation (LCD power-down mode).1'b1: Disable isolation (LCD active mode) | +| 0 | LCD_AUTO_PWR_ON | RW | 0x0 | LCD Auto Power On 1: Triggers a request to power on the ISP power island.0: Triggers a request to power down the ISP power island, but only if PWR_CTRL_LCD[4] is set. | ##### HDMI POWER CONTROL REGISTER (PMUA_PWR_CTRL_HDMI) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3F4
BitsFieldTypeResetDescription
31:5RSVDRO0x0Reserved
4HW_MODERW0x0Hardware Control Mode for HDMI Power Up and Power Down
3HDMI_SLEEP2RW0x0HDMI Power Switch Sleep2
2HDMI_SLEEP1RW0x0HDMI
1HDMI_ISOBRW0x0HDMI Isolation Wrapper.
1'b0: Enable isolation (HDMI power-down mode)
1'b1: Disable isolation (HDMI active mode)
0HDMI_AUTO_PWR_ONRW0x0HDMI Auto Power On
1: Triggers a request to power on the ISP power island.
0: Triggers a request to power down the ISP power island, but only if PWR_CTRL_HDMI[4] is set.
+Offset: 0xD4282800+0x3F4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31:5 | RSVD | RO | 0x0 | Reserved | +| 4 | HW_MODE | RW | 0x0 | Hardware Control Mode for HDMI Power Up and Power Down | +| 3 | HDMI_SLEEP2 | RW | 0x0 | HDMI Power Switch Sleep2 | +| 2 | HDMI_SLEEP1 | RW | 0x0 | HDMI | +| 1 | HDMI_ISOB | RW | 0x0 | HDMI Isolation Wrapper.1'b0: Enable isolation (HDMI power-down mode)1'b1: Disable isolation (HDMI active mode) | +| 0 | HDMI_AUTO_PWR_ON | RW | 0x0 | HDMI Auto Power On 1: Triggers a request to power on the ISP power island.0: Triggers a request to power down the ISP power island, but only if PWR_CTRL_HDMI[4] is set. | ##### USB WAKE CLEAR REGISTER (PMU_USBP1_WAKE_CLR) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3C4
BitsFieldTypeResetDescription
31USBP1_WK_INT_STATUSRO0x0USBP1 Wake up status
30:29RSVDRO0x0Reserved
28USBP1_CHGDET_WK_STATUSRO0x0
USBP1 Line charge detect wake up status
27USBP1_ID_WK_STATUSRO0x0USBP1 Line ID wake up status
26USBP1_VBUS_WK_STATUSRO0x0USBP1 Line vbus valid wake up status
25USBP1_LINE1_WK_STATUSRO0x0USBP1 Line state1 wake up status
24USBP1_LINE0_WK_STATUSRO0x0USBP1 Line state0 wake up status
23USBP1_IDDIG_OVRD_VALUERO0x0USBP1 IDDIG OVERRIDE VALUE
22USBP1_IDDIG_OVRD_ENRO0x0USBP1 IDDIG OVERRIDE ENABLE
21USBP1_VBUS_DRVRO0x0USBP1 VBUS DRV
20USBP1_CHGDET_WK_CLRRW0x0USBP1 Line charge detect wake up Clear
1'b1: Clear
This bit is self-cleared by hardware
19USBP1_ID_WK_CLRRW0x0USBP1 Line ID wake up Clear
1'b1: Clear
This bit is self-cleared by hardware
18USBP1_VBUS_WK_CLRRW0x0USBP1 Line vbus valid wake up Clear
1'b1: Clear. This bit is self-cleared by hardware
17USBP1_LINE1_WK_CLRRW0x0USBP1 Line state1 wake up Clear
1'b1: Clear
This bit is self-cleared by hardware
16USBP1_LINE0_WK_CLRRW0x0USBP1 Line state0 wake up Clear
1'b1: Clear
This bit is self-cleared by hardware
15USBP1_WK_INT_MASKRW0x0USBP1 Wakeup Interrupt Enable
1’b1: Enable
14:13RSVDRO0x0Reserved
12USBP1_CHGDET_WK_MASKRW0x0
USBP1 Line charge detect wake up Enable
1’b1: Enable
11USBP1_ID_WK_MASKRW0x0USBP1 Line ID wake up Enable
1’b1: Enable
10USBP1_VBUS_WK_MASKRW0x0USBP1 Line vbus valid wake up Enable
1’b1: Enable
9USBP1_LINE1_WK_MASKRW0x0USBP1 Line state1 wake up Enable
1’b1: Enable
8USBP1_LINE0_WK_MASKRW0x0USBP1 Line state0 wake up Enable
1’b1: Enable
7:0RSVDRO0x0Reserved
+Offset: 0xD4282800+0x3C4 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | USBP1_WK_INT_STATUS | RO | 0x0 | USBP1 Wake up status | +| 30:29 | RSVD | RO | 0x0 | Reserved | +| 28 | USBP1_CHGDET_WK_STATUS | RO | 0x0 | USBP1 Line charge detect wake up status | +| 27 | USBP1_ID_WK_STATUS | RO | 0x0 | USBP1 Line ID wake up status | +| 26 | USBP1_VBUS_WK_STATUS | RO | 0x0 | USBP1 Line vbus valid wake up status | +| 25 | USBP1_LINE1_WK_STATUS | RO | 0x0 | USBP1 Line state1 wake up status | +| 24 | USBP1_LINE0_WK_STATUS | RO | 0x0 | USBP1 Line state0 wake up status | +| 23 | USBP1_IDDIG_OVRD_VALUE | RO | 0x0 | USBP1 IDDIG OVERRIDE VALUE | +| 22 | USBP1_IDDIG_OVRD_EN | RO | 0x0 | USBP1 IDDIG OVERRIDE ENABLE | +| 21 | USBP1_VBUS_DRV | RO | 0x0 | USBP1 VBUS DRV | +| 20 | USBP1_CHGDET_WK_CLR | RW | 0x0 | USBP1 Line charge detect wake up Clear1'b1: ClearThis bit is self-cleared by hardware | +| 19 | USBP1_ID_WK_CLR | RW | 0x0 | USBP1 Line ID wake up Clear1'b1: ClearThis bit is self-cleared by hardware | +| 18 | USBP1_VBUS_WK_CLR | RW | 0x0 | USBP1 Line vbus valid wake up Clear1'b1: Clear. This bit is self-cleared by hardware | +| 17 | USBP1_LINE1_WK_CLR | RW | 0x0 | USBP1 Line state1 wake up Clear1'b1: ClearThis bit is self-cleared by hardware | +| 16 | USBP1_LINE0_WK_CLR | RW | 0x0 | USBP1 Line state0 wake up Clear1'b1: ClearThis bit is self-cleared by hardware | +| 15 | USBP1_WK_INT_MASK | RW | 0x0 | USBP1 Wakeup Interrupt Enable1’b1: Enable | +| 14:13 | RSVD | RO | 0x0 | Reserved | +| 12 | USBP1_CHGDET_WK_MASK | RW | 0x0 | USBP1 Line charge detect wake up Enable1’b1: Enable | +| 11 | USBP1_ID_WK_MASK | RW | 0x0 | USBP1 Line ID wake up Enable1’b1: Enable | +| 10 | USBP1_VBUS_WK_MASK | RW | 0x0 | USBP1 Line vbus valid wake up Enable1’b1: Enable | +| 9 | USBP1_LINE1_WK_MASK | RW | 0x0 | USBP1 Line state1 wake up Enable1’b1: Enable | +| 8 | USBP1_LINE0_WK_MASK | RW | 0x0 | USBP1 Line state0 wake up Enable1’b1: Enable | +| 7:0 | RSVD | RO | 0x0 | Reserved | ##### USB3 WAKE CLEAR REGISTER (PMU_USB3_WAKE_CLR) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Offset: 0xD4282800+0x3C8
BitsFieldTypeResetDescription
31USB3_WK_INT_STATUSRO0x0USB3 Wake up status
30RSVDRO0x0Reserved
29USB3_LFPS_WK_STATUSRO0x0USB3 LFPS wake up status
28USB3_CHGDET_WK_STATUSRO0x0USB3 Line charge detect wake up status
27USB3_ID_WK_STATUSRO0x0USB3 Line ID wake up status
26
USB3_VBUS_WK_STATUSRO0x0USB3 Line vbus valid wake up status
25USB3_LINE1_WK_STATUSRO0x0
USB3 Line state1 wake up status
24USB3_LINE0_WK_STATUSRO0x0USB3 Line state0 wake up status
23USB3_IDDIG_OVRD_VALUERO0x0USB3 IDDIG OVERRIDE VALUE
22USB3_IDDIG_OVRD_ENRO0x0USB3 IDDIG OVERRIDE ENABLE
21USB3_VBUS_DRVRO0x0USB3 VBUS DRV
20USB3_CHGDET_WK_CLRRW0x0USB3 Line charge detect wake up Clear
1'b1: Clear
This bit is self-cleared by hardware.
19USB3_ID_WK_CLRRW0x0USB3 Line ID wake up Clear.
1'b1: Clear
This bit is self-cleared by hardware.
18
USB3_VBUS_WK_CLRRW0x0USB3 Line vbus valid wake up Clear
1'b1: Clear
This bit is self-cleared by hardware.
17USB3_LINE1_WK_CLRRW
0x0USB3 Line state1 wake up Clear
1'b1: Clear
This bit is self-cleared by hardware.
16USB3_LINE0_WK_CLRRW0x0USB3 Line state0 wake up Clear
1'b1: Clear
This bit is self-cleared by hardware.
15USB3_WK_INT_MASKRW0x0USB3 Wakeup Interrupt Enable
1'b1: Enable
14USB3_LFPS_WK_CLRRW0x0USB3 LFPS wake up Clear
1'b1: Clear
This bit is self-cleared by hardware.
13USB3_LFPS_WK_MASKRW0x0USB3 LFPS wake up Enable
1'b1: Enable
12USB3_CHGDET_WK_MASKRW0x0USB3 Line charge detect wake up Enable
1'b1: Enable
11USB3_ID_WK_MASKRW0x0USB3 Line ID wake up Enable
1'b1: Enable
10USB3_VBUS_WK_MASKRW0x0USB3 Line vbus valid wake up Enable
1'b1: Enable
9USB3_LINE1_WK_MASKRW0x0USB3 Line state1 wake up Enable
1'b1: Enable
8USB3_LINE0_WK_MASKRW0x0USB3 Line state0 wake up Enable
1'b1: Enable
7:0RSVDRO0x0Reserved
+Offset: 0xD4282800+0x3C8 +| Bits | Field | Type | Reset | Description | +| --- | --- | --- | --- | --- | +| 31 | USB3_WK_INT_STATUS | RO | 0x0 | USB3 Wake up status | +| 30 | RSVD | RO | 0x0 | Reserved | +| 29 | USB3_LFPS_WK_STATUS | RO | 0x0 | USB3 LFPS wake up status | +| 28 | USB3_CHGDET_WK_STATUS | RO | 0x0 | USB3 Line charge detect wake up status | +| 27 | USB3_ID_WK_STATUS | RO | 0x0 | USB3 Line ID wake up status | +| 26 | USB3_VBUS_WK_STATUS | RO | 0x0 | USB3 Line vbus valid wake up status | +| 25 | USB3_LINE1_WK_STATUS | RO | 0x0 | USB3 Line state1 wake up status | +| 24 | USB3_LINE0_WK_STATUS | RO | 0x0 | USB3 Line state0 wake up status | +| 23 | USB3_IDDIG_OVRD_VALUE | RO | 0x0 | USB3 IDDIG OVERRIDE VALUE | +| 22 | USB3_IDDIG_OVRD_EN | RO | 0x0 | USB3 IDDIG OVERRIDE ENABLE | +| 21 | USB3_VBUS_DRV | RO | 0x0 | USB3 VBUS DRV | +| 20 | USB3_CHGDET_WK_CLR | RW | 0x0 | USB3 Line charge detect wake up Clear 1'b1: ClearThis bit is self-cleared by hardware. | +| 19 | USB3_ID_WK_CLR | RW | 0x0 | USB3 Line ID wake up Clear. 1'b1: ClearThis bit is self-cleared by hardware. | +| 18 | USB3_VBUS_WK_CLR | RW | 0x0 | USB3 Line vbus valid wake up Clear1'b1: ClearThis bit is self-cleared by hardware. | +| 17 | USB3_LINE1_WK_CLR | RW | 0x0 | USB3 Line state1 wake up Clear1'b1: ClearThis bit is self-cleared by hardware. | +| 16 | USB3_LINE0_WK_CLR | RW | 0x0 | USB3 Line state0 wake up Clear1'b1: ClearThis bit is self-cleared by hardware. | +| 15 | USB3_WK_INT_MASK | RW | 0x0 | USB3 Wakeup Interrupt Enable1'b1: Enable | +| 14 | USB3_LFPS_WK_CLR | RW | 0x0 | USB3 LFPS wake up Clear1'b1: ClearThis bit is self-cleared by hardware. | +| 13 | USB3_LFPS_WK_MASK | RW | 0x0 | USB3 LFPS wake up Enable1'b1: Enable | +| 12 | USB3_CHGDET_WK_MASK | RW | 0x0 | USB3 Line charge detect wake up Enable 1'b1: Enable | +| 11 | USB3_ID_WK_MASK | RW | 0x0 | USB3 Line ID wake up Enable1'b1: Enable | +| 10 | USB3_VBUS_WK_MASK | RW | 0x0 | USB3 Line vbus valid wake up Enable1'b1: Enable | +| 9 | USB3_LINE1_WK_MASK | RW | 0x0 | USB3 Line state1 wake up Enable 1'b1: Enable | +| 8 | USB3_LINE0_WK_MASK | RW | 0x0 | USB3 Line state0 wake up Enable1'b1: Enable | +| 7:0 | RSVD | RO | 0x0 | Reserved | diff --git a/en/key_stone/k3/k3_docs/k3_ds.md b/en/key_stone/k3/k3_docs/k3_ds.md index 76bc7ce..f981329 100644 --- a/en/key_stone/k3/k3_docs/k3_ds.md +++ b/en/key_stone/k3/k3_docs/k3_ds.md @@ -22,6 +22,7 @@ The content of this document may be periodically updated due to product version | Version | Date | Notes | | --- | --- | --- | +| **V1.4** | 2026.06.10 | Added Part Number information | | **V1.3** | 2026.05.21 | Updated A100 interrupt description | | **V1.2** | 2026.05.19 | Updated video subsystem parameters| | **V1.1** | 2026.05.08 | Updated image features | @@ -1641,6 +1642,12 @@ The related package outline drawing (POD) is depicted in the following section. +### 3.3 Part Number + +The figure below shows the K3 part number structure and field definitions. + + + ## 4. Pinout ### 4.1 Pinout Diagram & Description diff --git a/en/key_stone/k3/k3_docs/k3_usermanual/00_preface.md b/en/key_stone/k3/k3_docs/k3_usermanual/00_preface.md index d810599..001848c 100644 --- a/en/key_stone/k3/k3_docs/k3_usermanual/00_preface.md +++ b/en/key_stone/k3/k3_docs/k3_usermanual/00_preface.md @@ -24,7 +24,7 @@ The content of this document may be periodically updated due to product version | Version | Date | Notes | | --- | --- | --- | -| **V1.4** | 2026.06.01 | Fixed some typo issues | +| **V1.4** | 2026.06.10 | Added Part Number information | | **V1.3** | 2026.05.21 | Updated A100 interrupt description | | **V1.2** | 2026.05.19 | Updated video subsystem parameters| | **V1.1** | 2026.05.08 | Updated image features | diff --git a/en/key_stone/k3/k3_docs/k3_usermanual/02_package.md b/en/key_stone/k3/k3_docs/k3_usermanual/02_package.md index 8d56f1c..abf3159 100644 --- a/en/key_stone/k3/k3_docs/k3_usermanual/02_package.md +++ b/en/key_stone/k3/k3_docs/k3_usermanual/02_package.md @@ -18,4 +18,10 @@ The package outline drawing (POD) is shown below. K3 package outline drawing, view 1 -K3 package outline drawing, view 2 \ No newline at end of file +K3 package outline drawing, view 2 + +## 2.3 Part Number + +The figure below shows the K3 part number structure and field definitions. + + \ No newline at end of file diff --git a/en/key_stone/k3/k3_docs/k3_usermanual/15_security.md b/en/key_stone/k3/k3_docs/k3_usermanual/15_security.md index a60f105..6b0e416 100644 --- a/en/key_stone/k3/k3_docs/k3_usermanual/15_security.md +++ b/en/key_stone/k3/k3_docs/k3_usermanual/15_security.md @@ -224,8 +224,8 @@ Offset: 0x10 To configure the SID for the GPU: -1. Set **NASID_CTRL1** (offset: 0x14) bit [30] = 1. -2. Specify the SID via **NASID_CTRL1** bits [19:16]. +1. Set **NSAID_CTRL1** (offset: 0x14) bit [30] = 1. +2. Specify the SID via **NSAID_CTRL1** bits [19:16]. ###### NSAID CONTROL REGISTER1 @@ -250,15 +250,15 @@ Offset: 0x14 To configure the SID for the VPU: -1. Set **NASID_CTRL1** (offset: 0x14) bit [31] = 0. -2. Specify the SID via **NASID_CTRL1** bits [23:20]. +1. Set **NSAID_CTRL1** (offset: 0x14) bit [31] = 0. +2. Specify the SID via **NSAID_CTRL1** bits [23:20]. ##### V2D To configure the SID for the V2D: 1. Set **MAS_SEC_CTRL** (offset: 0x8) bit [31] = 1. -2. Specify the SID via **NASID_CTRL1** (offset: 0x14) bits [11:8]. +2. Specify the SID via **NSAID_CTRL1** (offset: 0x14) bits [11:8]. ###### MASTER SECURE CONTROL REGISTER @@ -331,14 +331,14 @@ The SID is configured via the **DDRPORT_USER_CTRL** register (offset: 0x78) bits ##### ISP -The SID is configured via the **NASID_CTRL1** register (offset: 0x14) bits [3:0]. +The SID is configured via the **NSAID_CTRL1** register (offset: 0x14) bits [3:0]. ##### LCD0 To configure the SID for LCD0: -- Set **NASID_CTRL1** (offset: 0x14) bit [28] = 0. -- Specify the SID via **NASID_CTRL1** (offset: 0x14) bits [7:4]. +- Set **NSAID_CTRL1** (offset: 0x14) bit [28] = 0. +- Specify the SID via **NSAID_CTRL1** (offset: 0x14) bits [7:4]. ##### LCD1 diff --git a/en/key_stone/k3/k3_docs/k3_usermanual/17_clock_reset.md b/en/key_stone/k3/k3_docs/k3_usermanual/17_clock_reset.md index 72d86f0..53459ff 100644 --- a/en/key_stone/k3/k3_docs/k3_usermanual/17_clock_reset.md +++ b/en/key_stone/k3/k3_docs/k3_usermanual/17_clock_reset.md @@ -356,7 +356,7 @@ Offset:0x100 | 15:8 | PLL1_REG2 | RW | 0x0C | PLL1 Register 2 Configuration | | 7:0 | PLL1_REG1 | RW | 0xCC | PLL1 Register 1 Configuration | -##### PLL1 SW CONTROL REGISTER +##### PLL1 SW CONTROL REGISTER APB_SPARE2_REG Offset:0x104 @@ -1057,7 +1057,7 @@ Offset:0x50 | 6 | RSVD | RO | 0 | Reserved for future use | | 5 | CCIC1_PHYCLK_EN | RW | 0x0 | CCIC1 PHY Clock Enable:
0x0 = Disable
0x1 = Enable | | 4 | CCIC_CLK4X_EN | RW | 0x0 | CMOS Camera Interface Controller Peripheral Clock Enable:
0x0 = Disable
0x1 = Enable | -| 3 | SC2_HCLK_EN | RW | 0x0 | SC2_HCLK Enable
0x0 = disable
0x1 = enable | +| 3 | SC2_HCLK_EN | RW | 0x0 | SC2_HCLK Enable:
0x0 = Disable
0x1 = Enable | | 2 | CCIC1_PHYCLK_RST | RW | 0x0 | CCIC1 PHY Clock Reset
This clock is also used for DPHY reset.
0 = Reset
1 = Release Reset | | 1 | CCIC_CLK4X_RST | RW | 0x0 | CMOS Camera Interface Controller Peripheral Reset
0 = Reset
1 = Release Reset | | 0 | SC2_HCLK_RST | RW | 0x0 | SC2_HCLK Reset
0 = Reset
1 = Release Reset | diff --git a/en/key_stone/k3/k3_docs/static/k3_partno.png b/en/key_stone/k3/k3_docs/static/k3_partno.png new file mode 100644 index 0000000..fe09658 Binary files /dev/null and b/en/key_stone/k3/k3_docs/static/k3_partno.png differ diff --git a/en/key_stone/k3/k3_hw/index.md b/en/key_stone/k3/k3_hw/index.md index 3ceec1a..357a460 100644 --- a/en/key_stone/k3/k3_hw/index.md +++ b/en/key_stone/k3/k3_hw/index.md @@ -2,6 +2,7 @@ sidebar_position: 2 # Hardware Design Resources & Guide +- [Single-Root Thermal Design Reference](k3_sr_thermal_design.md) - [Hardware Design Guide](k3_hw_design_guide.md) - [Hardware Design Resources](k3_hw_resources.md) - [Hardware FAQ](k3_hw_faq.md) diff --git a/en/key_stone/k3/k3_hw/k3_hw_design_guide.md b/en/key_stone/k3/k3_hw/k3_hw_design_guide.md index 6d726a7..2521fe7 100644 --- a/en/key_stone/k3/k3_hw/k3_hw_design_guide.md +++ b/en/key_stone/k3/k3_hw/k3_hw_design_guide.md @@ -1,5 +1,5 @@ --- -sidebar_position: 1 +sidebar_position: 2 --- # K3 Hardware Design Guidelines and PCB Layout Manual diff --git a/en/key_stone/k3/k3_hw/k3_hw_faq.md b/en/key_stone/k3/k3_hw/k3_hw_faq.md index 986f72a..ec06ebf 100644 --- a/en/key_stone/k3/k3_hw/k3_hw_faq.md +++ b/en/key_stone/k3/k3_hw/k3_hw_faq.md @@ -1,4 +1,6 @@ -sidebar_position: 3 +--- +sidebar_position: 4 +--- # K3 Hardware FAQ diff --git a/en/key_stone/k3/k3_hw/k3_hw_resources.md b/en/key_stone/k3/k3_hw/k3_hw_resources.md index 4e02257..eddc751 100644 --- a/en/key_stone/k3/k3_hw/k3_hw_resources.md +++ b/en/key_stone/k3/k3_hw/k3_hw_resources.md @@ -1,5 +1,5 @@ --- -sidebar_position: 2 +sidebar_position: 3 --- # K3 Hardware Resources diff --git a/en/key_stone/k3/k3_hw/k3_sr_thermal_design.md b/en/key_stone/k3/k3_hw/k3_sr_thermal_design.md new file mode 100644 index 0000000..bcfb7f9 --- /dev/null +++ b/en/key_stone/k3/k3_hw/k3_sr_thermal_design.md @@ -0,0 +1,7 @@ +--- +sidebar_position: 1 +--- + +# K3 Single-Root Thermal Design Reference + +> Coming soon ... \ No newline at end of file diff --git a/zh/key_stone/k3/k3_docs/k3_ds.md b/zh/key_stone/k3/k3_docs/k3_ds.md index 228807a..1e9739e 100644 --- a/zh/key_stone/k3/k3_docs/k3_ds.md +++ b/zh/key_stone/k3/k3_docs/k3_ds.md @@ -23,6 +23,7 @@ sidebar_position: 2 | 版本号 | 日期 | 修订说明 | | --- | --- | --- | +| **V1.4** | 2026.06.10 | 增添 Part Number 描述 | | **V1.3** | 2026.05.21 | 更新 A100 中断描述 | | **V1.2** | 2026.05.19 | 更新视频子系统参数 | | **V1.1** | 2026.05.08 | 更新图像子系统特性 | @@ -1676,6 +1677,12 @@ K3 提供以下封装选项： +### 3.3 Part Number + +下图给出了 K3 Part Number 的组成及字段定义。 + + + ## 4. 引脚定义（Pinout） ### 4.1 引脚分布图与说明 diff --git a/zh/key_stone/k3/k3_docs/static/k3_partno.png b/zh/key_stone/k3/k3_docs/static/k3_partno.png new file mode 100644 index 0000000..cfcf1b9 Binary files /dev/null and b/zh/key_stone/k3/k3_docs/static/k3_partno.png differ diff --git a/zh/key_stone/k3/k3_hw/index.md b/zh/key_stone/k3/k3_hw/index.md index 4e1667d..8fa6d14 100644 --- a/zh/key_stone/k3/k3_hw/index.md +++ b/zh/key_stone/k3/k3_hw/index.md @@ -2,6 +2,7 @@ sidebar_position: 2 # 硬件设计资源与指南 +- [单路热设计参考方案](k3_sr_thermal_design.md) - [硬件设计指南](k3_hw_design_guide.md) - [硬件设计资源](k3_hw_resources.md) - [硬件方案 FAQ](k3_hw_faq.md) diff --git a/zh/key_stone/k3/k3_hw/k3_hw_design_guide.md b/zh/key_stone/k3/k3_hw/k3_hw_design_guide.md index 66cc232..64d36eb 100644 --- a/zh/key_stone/k3/k3_hw/k3_hw_design_guide.md +++ b/zh/key_stone/k3/k3_hw/k3_hw_design_guide.md @@ -1,5 +1,5 @@ --- -sidebar_position: 1 +sidebar_position: 2 --- # K3 硬件设计指南和 Layout 指导手册 diff --git a/zh/key_stone/k3/k3_hw/k3_hw_faq.md b/zh/key_stone/k3/k3_hw/k3_hw_faq.md index daf92a9..a13eb1a 100644 --- a/zh/key_stone/k3/k3_hw/k3_hw_faq.md +++ b/zh/key_stone/k3/k3_hw/k3_hw_faq.md @@ -1,4 +1,6 @@ -sidebar_position: 3 +--- +sidebar_position: 4 +--- # K3 硬件方案 FAQ diff --git a/zh/key_stone/k3/k3_hw/k3_hw_resources.md b/zh/key_stone/k3/k3_hw/k3_hw_resources.md index 9a94bf7..da06a82 100644 --- a/zh/key_stone/k3/k3_hw/k3_hw_resources.md +++ b/zh/key_stone/k3/k3_hw/k3_hw_resources.md @@ -1,5 +1,5 @@ --- -sidebar_position: 2 +sidebar_position: 3 --- # K3 硬件资源 diff --git a/zh/key_stone/k3/k3_hw/k3_sr_thermal_design.md b/zh/key_stone/k3/k3_hw/k3_sr_thermal_design.md new file mode 100644 index 0000000..b6e3c5b --- /dev/null +++ b/zh/key_stone/k3/k3_hw/k3_sr_thermal_design.md @@ -0,0 +1,7 @@ +--- +sidebar_position: 1 +--- + +# K3 单路热设计参考方案 + +> Coming soon... \ No newline at end of file