From 73ab2ec1aadd6afe4e06b44c50d6ae63fe6646d1 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 16 Dec 2019 18:56:47 -0800 Subject: [PATCH 1/3] uart: UARTDesignInput has clockNode --- src/main/scala/shell/UARTOverlay.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/shell/UARTOverlay.scala b/src/main/scala/shell/UARTOverlay.scala index 192680f2..4cae82df 100644 --- a/src/main/scala/shell/UARTOverlay.scala +++ b/src/main/scala/shell/UARTOverlay.scala @@ -7,13 +7,14 @@ import freechips.rocketchip.config._ import freechips.rocketchip.diplomacy._ import sifive.blocks.devices.uart._ import freechips.rocketchip.subsystem.{BaseSubsystem, PeripheryBus, PeripheryBusKey} +import freechips.rocketchip.prci._ import freechips.rocketchip.tilelink.TLBusWrapper import freechips.rocketchip.interrupts.IntInwardNode //dont make the controller here //move flowcontrol to shell input?? case class UARTShellInput() -case class UARTDesignInput(uartParams: UARTParams, divInit: Int, controlBus: TLBusWrapper, intNode: IntInwardNode)(implicit val p: Parameters) +case class UARTDesignInput(uartParams: UARTParams, divInit: Int, controlBus: TLBusWrapper, intNode: IntInwardNode, clockNode: ClockGroupBroadcastNode)(implicit val p: Parameters) case class UARTOverlayOutput(uart: TLUART) case object UARTOverlayKey extends Field[Seq[DesignPlacer[UARTDesignInput, UARTShellInput, UARTOverlayOutput]]](Nil) trait UARTShellPlacer[Shell] extends ShellPlacer[UARTDesignInput, UARTShellInput, UARTOverlayOutput] @@ -37,7 +38,7 @@ abstract class UARTPlacedOverlay( def ioFactory = new ShellUARTPortIO(flowControl) - val tluart = UART.attach(UARTAttachParams(di.uartParams, di.divInit, di.controlBus, di.intNode)) + val tluart = UART.attach(UARTAttachParams(di.uartParams, di.divInit, di.controlBus, di.intNode, di.clockNode)) val tluartSink = tluart.ioNode.makeSink val uartSource = BundleBridgeSource(() => new UARTPortIO()) val uartSink = shell { uartSource.makeSink } From b4f18fb237d4dc5f44da9e3e297ffaf6f604366b Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 8 Jan 2020 17:02:09 -0800 Subject: [PATCH 2/3] uart: use ClockGroupIdentityNode --- src/main/scala/shell/UARTOverlay.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/shell/UARTOverlay.scala b/src/main/scala/shell/UARTOverlay.scala index 4cae82df..a7a6ac89 100644 --- a/src/main/scala/shell/UARTOverlay.scala +++ b/src/main/scala/shell/UARTOverlay.scala @@ -14,7 +14,7 @@ import freechips.rocketchip.interrupts.IntInwardNode //dont make the controller here //move flowcontrol to shell input?? case class UARTShellInput() -case class UARTDesignInput(uartParams: UARTParams, divInit: Int, controlBus: TLBusWrapper, intNode: IntInwardNode, clockNode: ClockGroupBroadcastNode)(implicit val p: Parameters) +case class UARTDesignInput(uartParams: UARTParams, divInit: Int, controlBus: TLBusWrapper, intNode: IntInwardNode, clockNode: ClockGroupIdentityNode)(implicit val p: Parameters) case class UARTOverlayOutput(uart: TLUART) case object UARTOverlayKey extends Field[Seq[DesignPlacer[UARTDesignInput, UARTShellInput, UARTOverlayOutput]]](Nil) trait UARTShellPlacer[Shell] extends ShellPlacer[UARTDesignInput, UARTShellInput, UARTOverlayOutput] From e60b212682651b4f6acdd5d22dc218cefba97979 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 16 Jan 2020 12:11:34 -0800 Subject: [PATCH 3/3] uart: attach via Attachable --- src/main/scala/shell/UARTOverlay.scala | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/main/scala/shell/UARTOverlay.scala b/src/main/scala/shell/UARTOverlay.scala index a7a6ac89..b0178ccb 100644 --- a/src/main/scala/shell/UARTOverlay.scala +++ b/src/main/scala/shell/UARTOverlay.scala @@ -5,16 +5,13 @@ import chisel3._ import chisel3.experimental.Analog import freechips.rocketchip.config._ import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.subsystem.Attachable import sifive.blocks.devices.uart._ -import freechips.rocketchip.subsystem.{BaseSubsystem, PeripheryBus, PeripheryBusKey} -import freechips.rocketchip.prci._ -import freechips.rocketchip.tilelink.TLBusWrapper -import freechips.rocketchip.interrupts.IntInwardNode //dont make the controller here //move flowcontrol to shell input?? case class UARTShellInput() -case class UARTDesignInput(uartParams: UARTParams, divInit: Int, controlBus: TLBusWrapper, intNode: IntInwardNode, clockNode: ClockGroupIdentityNode)(implicit val p: Parameters) +case class UARTDesignInput(uartParams: UARTAttachParams, where: Attachable)(implicit val p: Parameters) case class UARTOverlayOutput(uart: TLUART) case object UARTOverlayKey extends Field[Seq[DesignPlacer[UARTDesignInput, UARTShellInput, UARTOverlayOutput]]](Nil) trait UARTShellPlacer[Shell] extends ShellPlacer[UARTDesignInput, UARTShellInput, UARTOverlayOutput] @@ -38,7 +35,7 @@ abstract class UARTPlacedOverlay( def ioFactory = new ShellUARTPortIO(flowControl) - val tluart = UART.attach(UARTAttachParams(di.uartParams, di.divInit, di.controlBus, di.intNode, di.clockNode)) + val tluart = di.uartParams.attachTo(di.where) val tluartSink = tluart.ioNode.makeSink val uartSource = BundleBridgeSource(() => new UARTPortIO()) val uartSink = shell { uartSource.makeSink }