diff --git a/src/main/scala/shell/UARTOverlay.scala b/src/main/scala/shell/UARTOverlay.scala
index 192680f2..b0178ccb 100644
--- a/src/main/scala/shell/UARTOverlay.scala
+++ b/src/main/scala/shell/UARTOverlay.scala
@@ -5,15 +5,13 @@ import chisel3._
 import chisel3.experimental.Analog
 import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.subsystem.Attachable
 import sifive.blocks.devices.uart._
-import freechips.rocketchip.subsystem.{BaseSubsystem, PeripheryBus, PeripheryBusKey}
-import freechips.rocketchip.tilelink.TLBusWrapper
-import freechips.rocketchip.interrupts.IntInwardNode
 
 //dont make the controller here
 //move flowcontrol to shell input?? 
 case class UARTShellInput()
-case class UARTDesignInput(uartParams: UARTParams, divInit: Int, controlBus: TLBusWrapper, intNode: IntInwardNode)(implicit val p: Parameters)
+case class UARTDesignInput(uartParams: UARTAttachParams, where: Attachable)(implicit val p: Parameters)
 case class UARTOverlayOutput(uart: TLUART)
 case object UARTOverlayKey extends Field[Seq[DesignPlacer[UARTDesignInput, UARTShellInput, UARTOverlayOutput]]](Nil)
 trait UARTShellPlacer[Shell] extends ShellPlacer[UARTDesignInput, UARTShellInput, UARTOverlayOutput]
@@ -37,7 +35,7 @@ abstract class UARTPlacedOverlay(
 
   def ioFactory = new ShellUARTPortIO(flowControl)
 
-  val tluart = UART.attach(UARTAttachParams(di.uartParams, di.divInit, di.controlBus, di.intNode))
+  val tluart = di.uartParams.attachTo(di.where)
   val tluartSink = tluart.ioNode.makeSink
   val uartSource = BundleBridgeSource(() => new UARTPortIO())
   val uartSink = shell { uartSource.makeSink }