Skip to content

Make some of the connector methods more flexible #41

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
Megan Wachs (mwachs5) wants to merge 8 commits into
base: master
Choose a base branch
from
Open

Make some of the connector methods more flexible #41

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
8 commits
Select commit Hold shift + click to select a range
57438f7
VC707 Shell: be more flexible with helper methods
mwachs5 Sep 24, 2018
1e88ad4
VC707: Switches are inputs, right?
mwachs5 Sep 24, 2018
d029994
Revert "VC707: Switches are inputs, right?"
mwachs5 Sep 24, 2018
172ba29
PCIE: Don't hard code PCIE constraints in case you don't have a PCIE
mwachs5 Sep 27, 2018
b0e1737
IBUFDS: Apparently IBUF_DELAY_VALUE is a string
mwachs5 Oct 3, 2018
1132c0e
VC707: add an ULPI_CLK asynchronous group
mwachs5 Oct 5, 2018
8a3bcb2
Merge commit 'a45fb1f' into shell-more-flexible
mwachs5 Oct 16, 2018
921f7eb
VC707 Old Shell: clocks for JTCK and ULPI
mwachs5 Nov 6, 2018
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions src/main/scala/ip/xilinx/Unisim.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ class IBUFDS(
CAPACITANCE : String = "DONT_CARE",
DIFF_TERM : Boolean = false,
DQS_BIAS : Boolean = false,
IBUF_DELAY_VALUE : Int = 0,
IBUF_DELAY_VALUE : String = "0",
IBUF_LOW_PWR : Boolean = true,
IFD_DELAY_VALUE : String = "AUTO",
IOSTANDARD : String = "DEFAULT"
Expand All @@ -32,7 +32,7 @@ extends BlackBox(
"CAPACITANCE" -> StringParam(CAPACITANCE),
"DIFF_TERM" -> booleanToVerilogStringParam(DIFF_TERM),
"DQS_BIAS" -> booleanToVerilogStringParam(DQS_BIAS),
"IBUF_DELAY_VALUE" -> IntParam(IBUF_DELAY_VALUE),
"IBUF_DELAY_VALUE" -> StringParam(IBUF_DELAY_VALUE),
"IBUF_LOW_PWR" -> booleanToVerilogStringParam(IBUF_LOW_PWR),
"IFD_DELAY_VALUE" -> StringParam(IFD_DELAY_VALUE),
"IOSTANDARD" -> StringParam(IOSTANDARD)
Expand Down
58 changes: 42 additions & 16 deletions src/main/scala/shell/xilinx/VC707Shell.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,27 @@ trait HasPCIe { this: VC707Shell =>

pcie <> dut.xilinxvc707pcie
}
ElaborationArtefacts.add(
"""vc707pcie.vivado.tcl""",
"""set vc707pcie_vivado_tcl_dir [file dirname [file normalize [info script]]]
add_files -fileset [current_fileset -constrset] [glob -directory $vc707pcie_vivado_tcl_dir {*.vc707pcie.xdc}]"""
)

ElaborationArtefacts.add(
"""vc707pcie.xdc""",
"""
set_property PACKAGE_PIN A10 [get_ports {pcie_REFCLK_rxp}]
set_property PACKAGE_PIN A9 [get_ports {pcie_REFCLK_rxn}]
create_clock -name pcie_ref_clk -period 10 [get_ports pcie_REFCLK_rxp]
set_input_jitter [get_clocks -of_objects [get_ports pcie_REFCLK_rxp]] 0.5

set_property PACKAGE_PIN H4 [get_ports {pcie_pci_exp_txp}]
set_property PACKAGE_PIN H3 [get_ports {pcie_pci_exp_txn}]

set_property PACKAGE_PIN G6 [get_ports {pcie_pci_exp_rxp}]
set_property PACKAGE_PIN G5 [get_ports {pcie_pci_exp_rxn}]
"""
)
}

trait HasDebugJTAG { this: VC707Shell =>
Expand All @@ -64,7 +85,7 @@ trait HasDebugJTAG { this: VC707Shell =>
val jtag_TDI = IO(Input(Bool()))
val jtag_TDO = IO(Output(Bool()))

def connectDebugJTAG(dut: HasPeripheryDebugModuleImp, fmcxm105: Boolean = true): SystemJTAGIO = {
def connectDebugJTAG(djtag: SystemJTAGIO, fmcxm105: Boolean, ndreset: Bool): SystemJTAGIO = {

ElaborationArtefacts.add(
"""debugjtag.vivado.tcl""",
Expand Down Expand Up @@ -104,12 +125,10 @@ trait HasDebugJTAG { this: VC707Shell =>
set_property -dict { PACKAGE_PIN AR38 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TMS}]
set_property -dict { PACKAGE_PIN AR39 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDI}]
set_property -dict { PACKAGE_PIN AT40 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDO}]
create_clock -add -name JTCK -period 100 -waveform {0 50} [get_ports {jtag_TCK}];"""
# create_clock -add -name JTCK -period 100 -waveform {0 50} [get_ports {jtag_TCK}];"""
)
}

val djtag = dut.debug.systemjtag.get

djtag.jtag.TCK := jtag_TCK
djtag.jtag.TMS := jtag_TMS
djtag.jtag.TDI := jtag_TDI
Expand All @@ -118,9 +137,14 @@ trait HasDebugJTAG { this: VC707Shell =>
djtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)

djtag.reset := PowerOnResetFPGAOnly(dut_clock)
dut_ndreset := dut.debug.ndreset
dut_ndreset := ndreset
djtag
}


def connectDebugJTAG(dut: HasPeripheryDebugModuleImp, fmcxm105: Boolean = true): SystemJTAGIO =
connectDebugJTAG(dut.debug.systemjtag.get, fmcxm105, dut.debug.ndreset)

}

trait HasVC707ChipLink { this: VC707Shell =>
Expand Down Expand Up @@ -558,25 +582,27 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {

uart_rtsn := false.B

def connectUART(dut: HasPeripheryUARTModuleImp): Unit = {
val uartParams = p(PeripheryUARTKey)
if (!uartParams.isEmpty) {
// uart connections
dut.uart(0).rxd := SyncResetSynchronizerShiftReg(uart_rx, 2, init = Bool(true), name=Some("uart_rxd_sync"))
uart_tx := dut.uart(0).txd
}
def connectUART(dut: HasPeripheryUARTModuleImp): Unit =
dut.uart.lift(0).map { connectUART(_)}

def connectUART(uart: UARTPortIO): Unit = {
uart.rxd := SyncResetSynchronizerShiftReg(uart_rx, 2, init = Bool(true), name=Some("uart_rxd_sync"))
uart_tx := uart.txd
}


//-----------------------------------------------------------------------
// SPI
//-----------------------------------------------------------------------

def connectSPI(dut: HasPeripherySPIModuleImp): Unit = {
dut.spi.lift(0).map { connectSPI(_) }
}
def connectSPI(spi: SPIPortIO): Unit = {
// SPI
sd_spi_sck := dut.spi(0).sck
sd_spi_cs := dut.spi(0).cs(0)
sd_spi_sck := spi.sck
sd_spi_cs := spi.cs(0)

dut.spi(0).dq.zipWithIndex.foreach {
spi.dq.zipWithIndex.foreach {
case(pin, idx) =>
sd_spi_dq_o(idx) := pin.o
pin.i := sd_spi_dq_i(idx)
Expand Down
7 changes: 7 additions & 0 deletions xilinx/vc707/tcl/clocks.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -31,20 +31,27 @@ set group_cl [get_clocks -quiet {chiplink_b2c_clock \
clk_out*_vc707_sys_clock_mmcm3}]
set group_pci [get_clocks -quiet {userclk1 txoutclk}]

create_clock -add -name JTCK -period 100 -waveform {0 50} [get_ports {jtag_TCK}]
create_clock -add -name ULPI_CLK -period 16.667 [get_ports {ulpi_clk}];

set group_jtag [get_clocks -quiet {JTCK}]

set group_ulpi [get_clocks -quiet {ULPI_CLK}]

puts "group_mem: $group_mem"
puts "group_sys: $group_sys"
puts "group_pci: $group_pci"
puts "group_cl: $group_cl"
puts "group_jtag: $group_jtag"
puts "group_ulpi: $group_ulpi"

set groups [list]
if { [llength $group_mem] > 0 } { lappend groups -group $group_mem }
if { [llength $group_sys] > 0 } { lappend groups -group $group_sys }
if { [llength $group_pci] > 0 } { lappend groups -group $group_pci }
if { [llength $group_cl] > 0 } { lappend groups -group $group_cl }
if { [llength $group_jtag] > 0 } { lappend groups -group $group_jtag }
if { [llength $group_ulpi] > 0 } { lappend groups -group $group_ulpi }

puts "set_clock_groups -asynchronous $groups"
set_clock_groups -asynchronous {*}$groups
12 changes: 0 additions & 12 deletions xilinx/vc707/tcl/ios.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -46,18 +46,6 @@ set_property PACKAGE_PIN AR34 [get_ports uart_rtsn]
set_property IOSTANDARD LVCMOS18 [get_ports uart_rtsn]
set_property IOB TRUE [get_ports uart_rtsn]

# PCI Express
#FMC 1 refclk
set_property PACKAGE_PIN A10 [get_ports {pcie_REFCLK_rxp}]
set_property PACKAGE_PIN A9 [get_ports {pcie_REFCLK_rxn}]
create_clock -name pcie_ref_clk -period 10 [get_ports pcie_REFCLK_rxp]
set_input_jitter [get_clocks -of_objects [get_ports pcie_REFCLK_rxp]] 0.5

set_property PACKAGE_PIN H4 [get_ports {pcie_pci_exp_txp}]
set_property PACKAGE_PIN H3 [get_ports {pcie_pci_exp_txn}]

set_property PACKAGE_PIN G6 [get_ports {pcie_pci_exp_rxp}]
set_property PACKAGE_PIN G5 [get_ports {pcie_pci_exp_rxn}]

# SDIO
set_property -dict { PACKAGE_PIN AN30 IOSTANDARD LVCMOS18 IOB TRUE } [get_ports {sdio_clk}]
Expand Down