I see in the Tests section of Readme, the authors said that they used riscv-tests to test the design. However when I did a research on this test, I realized that it was only a test written for Spike design. Therefore, I want to know how to use that test to verify a SystemVerilog-based Debug Module design. I have tried using Verilator to simulate this design, and then write my own Python target and config files to run riscv-tests. The OpenOCD was successfully connected, but the GDB always failed. Can anyone please describe in details the steps to run the riscv-tests for this design. I would be extremely grateful.
I see in the Tests section of Readme, the authors said that they used riscv-tests to test the design. However when I did a research on this test, I realized that it was only a test written for Spike design. Therefore, I want to know how to use that test to verify a SystemVerilog-based Debug Module design. I have tried using Verilator to simulate this design, and then write my own Python target and config files to run riscv-tests. The OpenOCD was successfully connected, but the GDB always failed. Can anyone please describe in details the steps to run the riscv-tests for this design. I would be extremely grateful.