From f560f03cacbb5082d7a5b30c6ec042f6bae526f4 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Sat, 5 Jul 2025 14:22:19 +0200 Subject: [PATCH 1/5] core: Fix default write-through HPDCache option in Cheshire cfg --- core/include/cv64a6_imafdchsclic_sv39_hpdcache_config_pkg.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/include/cv64a6_imafdchsclic_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdchsclic_sv39_hpdcache_config_pkg.sv index 6c0be6d2df..7e0adfcb9f 100644 --- a/core/include/cv64a6_imafdchsclic_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdchsclic_sv39_hpdcache_config_pkg.sv @@ -77,7 +77,7 @@ package cva6_config_pkg; localparam CVA6ConfigPerfCounterEn = 1; - localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE; + localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE_WT; localparam CVA6ConfigMmuPresent = 1; From 35de60b55bccca1d6c1e1e69773eebf375b79367 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Sat, 5 Jul 2025 14:23:07 +0200 Subject: [PATCH 2/5] core: Add write-back HPDCache config for Cheshire target --- ...mafdchsclic_sv39_hpdcache_wb_config_pkg.sv | 179 ++++++++++++++++++ 1 file changed, 179 insertions(+) create mode 100644 core/include/cv64a6_imafdchsclic_sv39_hpdcache_wb_config_pkg.sv diff --git a/core/include/cv64a6_imafdchsclic_sv39_hpdcache_wb_config_pkg.sv b/core/include/cv64a6_imafdchsclic_sv39_hpdcache_wb_config_pkg.sv new file mode 100644 index 0000000000..d00e4def04 --- /dev/null +++ b/core/include/cv64a6_imafdchsclic_sv39_hpdcache_wb_config_pkg.sv @@ -0,0 +1,179 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales +// +// Copyright 2023 Commissariat a l'Energie Atomique et aux Energies +// Alternatives (CEA) +// +// Author: Cesar Fuguet - CEA +// Date: August, 2023 +// Description: CVA6 configuration package using the HPDcache as cache subsystem (CLIC variant) + + +package cva6_config_pkg; + + localparam CVA6ConfigXlen = 64; + + localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigRVD = 1; + localparam CVA6ConfigF16En = 0; + localparam CVA6ConfigF16AltEn = 0; + localparam CVA6ConfigF8En = 0; + localparam CVA6ConfigF8AltEn = 0; + localparam CVA6ConfigFVecEn = 0; + + localparam CVA6ConfigCvxifEn = 0; + localparam CVA6ConfigCExtEn = 1; + localparam CVA6ConfigZcbExtEn = 1; + localparam CVA6ConfigZcmpExtEn = 0; + localparam CVA6ConfigAExtEn = 1; + localparam CVA6ConfigHExtEn = 1; + localparam CVA6ConfigBExtEn = 0; + localparam CVA6ConfigVExtEn = 0; + localparam CVA6ConfigRVZiCond = 1; + localparam CVA6ConfigSclicExtEn = 1; + + localparam CVA6ConfigAxiIdWidth = 4; + localparam CVA6ConfigAxiAddrWidth = 64; + localparam CVA6ConfigAxiDataWidth = 64; + localparam CVA6ConfigFetchUserEn = 0; + localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; + localparam CVA6ConfigDataUserEn = 0; + localparam CVA6ConfigDataUserWidth = 1; + + localparam CVA6ConfigIcacheByteSize = 16384; + localparam CVA6ConfigIcacheSetAssoc = 4; + localparam CVA6ConfigIcacheLineWidth = 128; + localparam CVA6ConfigDcacheByteSize = 32768; + localparam CVA6ConfigDcacheSetAssoc = 8; + localparam CVA6ConfigDcacheLineWidth = 128; + + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + + localparam CVA6ConfigDcacheIdWidth = 3; + localparam CVA6ConfigMemTidWidth = CVA6ConfigAxiIdWidth; + + localparam CVA6ConfigWtDcacheWbufDepth = 8; + + localparam CVA6ConfigNrScoreboardEntries = 8; + + localparam CVA6ConfigNrLoadPipeRegs = 1; + localparam CVA6ConfigNrStorePipeRegs = 0; + localparam CVA6ConfigNrLoadBufEntries = 8; + + localparam CVA6ConfigRASDepth = 2; + localparam CVA6ConfigBTBEntries = 32; + localparam CVA6ConfigBHTEntries = 128; + + localparam CVA6ConfigTvalEn = 1; + + localparam CVA6ConfigNrPMPEntries = 8; + + localparam CVA6ConfigPerfCounterEn = 1; + + localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE_WB; + + localparam CVA6ConfigMmuPresent = 1; + + localparam CVA6ConfigRvfiTrace = 1; + + localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(CVA6ConfigXlen), + VLEN: unsigned'(64), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) + TechnoCut: bit'(0), + SuperscalarEn: bit'(0), + NrCommitPorts: unsigned'(2), + AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), + AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), + AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), + AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), + NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), + RVF: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), + XF16: bit'(CVA6ConfigF16En), + XF16ALT: bit'(CVA6ConfigF16AltEn), + XF8: bit'(CVA6ConfigF8En), + XF8ALT: bit'(CVA6ConfigF8AltEn), + RVA: bit'(CVA6ConfigAExtEn), + RVB: bit'(CVA6ConfigBExtEn), + ZKN: bit'(0), + RVV: bit'(CVA6ConfigVExtEn), + RVC: bit'(CVA6ConfigCExtEn), + RVH: bit'(CVA6ConfigHExtEn), + RVZCB: bit'(CVA6ConfigZcbExtEn), + RVZCMT: bit'(0), + RVZCMP: bit'(CVA6ConfigZcmpExtEn), + XFVec: bit'(CVA6ConfigFVecEn), + CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, + RVZiCond: bit'(CVA6ConfigRVZiCond), + RVSCLIC: bit'(CVA6ConfigSclicExtEn), + RVZicntr: bit'(1), + RVZihpm: bit'(1), + NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), + PerfCounterEn: bit'(CVA6ConfigPerfCounterEn), + MmuPresent: bit'(CVA6ConfigMmuPresent), + RVS: bit'(1), + RVU: bit'(1), + SoftwareInterruptEn: bit'(1), + HaltAddress: 64'h800, + ExceptionAddress: 64'h808, + RASDepth: unsigned'(CVA6ConfigRASDepth), + BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, + BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), + DmBaseAddress: 64'h0, + TvalEn: bit'(CVA6ConfigTvalEn), + DirectVecOnly: bit'(0), + NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + CLICNumInterruptSrc: unsigned'(256), + NrNonIdempotentRules: unsigned'(2), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(3), + ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), + ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), + NrCachedRegionRules: unsigned'(1), + CachedRegionAddrBase: 1024'({64'h8000_0000}), + CachedRegionLength: 1024'({64'h40000000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(1), + AxiBurstWriteEn: bit'(0), + IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), + IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), + IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth), + DCacheType: CVA6ConfigDcacheType, + DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), + DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), + DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), + DataUserEn: unsigned'(CVA6ConfigDataUserEn), + WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), + FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), + FetchUserEn: unsigned'(CVA6ConfigFetchUserEn), + InstrTlbEntries: int'(16), + DataTlbEntries: int'(16), + UseSharedTlb: bit'(0), + SharedTlbDepth: int'(64), + NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), + NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), + DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth) + }; + +endpackage From b1a9e6248d6ace68df4d69b15d90d20a9646554e Mon Sep 17 00:00:00 2001 From: aottaviano Date: Sat, 5 Jul 2025 14:25:27 +0200 Subject: [PATCH 3/5] Bender.yml: Add write-back HPDCache files targeting Cheshire --- Bender.yml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Bender.yml b/Bender.yml index 770234eeb4..e5f1dca82c 100644 --- a/Bender.yml +++ b/Bender.yml @@ -45,6 +45,10 @@ sources: files: - core/include/cv64a6_imafdchsclic_sv39_hpdcache_config_pkg.sv + - target: cv64a6_imafdchsclic_sv39_hpdcache_wb + files: + - core/include/cv64a6_imafdchsclic_sv39_hpdcache_wb_config_pkg.sv + - target: cv64a6_imafdc_sv39_wb files: - core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -83,12 +87,12 @@ sources: - core/cva6_accel_first_pass_decoder_stub.sv # CLIC controller - - target: any(cv64a6_imafdchsclic_sv39, cv64a6_imafdchsclic_sv39_hpdcache, cv64a6_imafdchsclic_sv39_wb) + - target: any(cv64a6_imafdchsclic_sv39, cv64a6_imafdchsclic_sv39_hpdcache, cv64a6_imafdchsclic_sv39_wb, cv64a6_imafdchsclic_sv39_hpdcache_wb) files: - core/cva6_clic_controller.sv # MMU - - target: any(cv64a6_imafdcv_sv39, cv64a6_imafdc_sv39, cv64a6_imafdchsclic_sv39, cv64a6_imafdc_sv39_hpdcache, cv64a6_imafdchsclic_sv39_hpdcache, cv64a6_imafdc_sv39_wb, cv64a6_imafdchsclic_sv39_wb, cv64a6_imafdch_sv39, cv64a6_imafdch_sv39_wb, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32) + - target: any(cv64a6_imafdcv_sv39, cv64a6_imafdc_sv39, cv64a6_imafdchsclic_sv39, cv64a6_imafdc_sv39_hpdcache, cv64a6_imafdchsclic_sv39_hpdcache, cv64a6_imafdc_sv39_hpdcache_wb, cv64a6_imafdchsclic_sv39_hpdcache_wb, cv64a6_imafdc_sv39_wb, cv64a6_imafdchsclic_sv39_wb, cv64a6_imafdch_sv39, cv64a6_imafdch_sv39_wb, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32) files: - core/cva6_mmu/cva6_tlb.sv - core/cva6_mmu/cva6_shared_tlb.sv From 9614e896fb7dbf296df36848af339158adadaf95 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Sat, 5 Jul 2025 14:57:34 +0200 Subject: [PATCH 4/5] Bender.yml: Disable HPDCache assertions --- Bender.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Bender.yml b/Bender.yml index e5f1dca82c..70a8b741e8 100644 --- a/Bender.yml +++ b/Bender.yml @@ -22,6 +22,8 @@ sources: - include_dirs: - core/include - common/local/util + defines: + HPDCACHE_ASSERT_OFF: ~ files: - core/include/config_pkg.sv # Pick the right configuration by passing the right bender flag. From 6874c8af1005e19414e0842abe90897e3723e2f1 Mon Sep 17 00:00:00 2001 From: Cesar Fuguet Date: Fri, 18 Apr 2025 15:47:57 +0200 Subject: [PATCH 5/5] hpdcache: update submodule --- .gitlab-ci/scripts/report_benchmark.py | 6 +++--- Bender.yml | 2 ++ core/cache_subsystem/cva6_hpdcache_subsystem.sv | 3 +++ core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv | 4 +++- core/cache_subsystem/hpdcache | 2 +- 5 files changed, 12 insertions(+), 5 deletions(-) diff --git a/.gitlab-ci/scripts/report_benchmark.py b/.gitlab-ci/scripts/report_benchmark.py index 5bcaf61087..9383e540cb 100644 --- a/.gitlab-ci/scripts/report_benchmark.py +++ b/.gitlab-ci/scripts/report_benchmark.py @@ -23,9 +23,9 @@ "dhrystone_single": 22407, "coremark_dual": 981777, "coremark_single": 1294524, - "dhrystone_cv32a65x": 30056, - "dhrystone_cv32a60x": 37474, -} + "dhrystone_cv32a65x": 28823, + "dhrystone_cv32a60x": 36629, + for arg in sys.argv[1:]: if "--dhrystone" in arg or "--coremark" in arg: diff --git a/Bender.yml b/Bender.yml index 70a8b741e8..5be4702e1d 100644 --- a/Bender.yml +++ b/Bender.yml @@ -195,6 +195,7 @@ sources: - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_decoder.sv - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_1hot_to_binary.sv - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_1hot_encoder.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_bin_encoder.sv - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wmask.sv @@ -223,6 +224,7 @@ sources: - core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv - core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv - core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_cbuf.sv # HPDCache integration - core/cache_subsystem/cva6_hpdcache_if_adapter.sv - core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem.sv b/core/cache_subsystem/cva6_hpdcache_subsystem.sv index fa563a3193..ecfbcba6cc 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem.sv @@ -214,6 +214,8 @@ module cva6_hpdcache_subsystem userCfg.mshrSetsPerRam = CVA6Cfg.NrLoadBufEntries < 16 ? 1 : CVA6Cfg.NrLoadBufEntries / 2; userCfg.mshrRamByteEnable = 1'b1; userCfg.mshrUseRegbank = (CVA6Cfg.NrLoadBufEntries < 16); + /*FIXME we should add additional CVA6 config parameters (cbufEntries)*/ + userCfg.cbufEntries = 4; userCfg.refillCoreRspFeedthrough = 1'b1; userCfg.refillFifoDepth = 2; userCfg.wbufDirEntries = CVA6Cfg.WtDcacheWbufDepth; @@ -234,6 +236,7 @@ module cva6_hpdcache_subsystem userCfg.wbEn = (CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WB) || (CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT_WB); + userCfg.lowLatency = 1'b1; return userCfg; endfunction diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv b/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv index 901175f79c..50d9d31b04 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv @@ -278,7 +278,9 @@ module cva6_hpdcache_subsystem_axi_arbiter .mem_req_read_ready_i(mem_req_read_ready_arb), .mem_req_read_valid_o(mem_req_read_valid_arb), - .mem_req_read_o (mem_req_read_arb) + .mem_req_read_o (mem_req_read_arb), + + .gnt_index_o() ); // }}} diff --git a/core/cache_subsystem/hpdcache b/core/cache_subsystem/hpdcache index 04de808969..09d15ad526 160000 --- a/core/cache_subsystem/hpdcache +++ b/core/cache_subsystem/hpdcache @@ -1 +1 @@ -Subproject commit 04de80896981527c34fbbd35d7b1ef787a082d7c +Subproject commit 09d15ad52647d3c8575295e463746634abce8071