From 8881de311350764f646b29a96950995299d39f94 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 30 Jun 2024 10:25:58 +0200 Subject: [PATCH 1/6] [WIP]: add VCU118 flow. --- .gitignore | 9 + Bender.yml | 2 +- bender-xilinx.mk | 1 + carfield.mk | 2 +- sw/boot/carfield.dtsi | 151 +-- sw/boot/carfield_bd_vcu118.dts | 8 + sw/boot/carfield_bd_vcu128.dts | 4 +- sw/boot/carfield_pcie.dts | 26 + sw/boot/carfield_soc.dtsi | 174 +++ sw/sw.mk | 14 + target/xilinx/flavor_bd/.gitignore | 6 - .../xilinx/flavor_bd/constraints/vcu118.xdc | 37 + .../flavor_bd/constraints/vcu118_ext_jtag.xdc | 33 + target/xilinx/flavor_bd/flavor_bd.mk | 6 + .../flavor_bd/scripts/carfield_bd_vcu118.tcl | 381 ++++++ .../scripts/carfield_bd_vcu118_ext_jtag.tcl | 18 + .../flavor_bd/scripts/carfield_bd_vcu128.tcl | 100 +- ...ag.tcl => carfield_bd_vcu128_ext_jtag.tcl} | 0 target/xilinx/flavor_bd/scripts/run.tcl | 19 +- target/xilinx/flavor_vanilla/.gitignore | 10 - .../flavor_vanilla/constraints/vcu118.xdc | 72 ++ .../flavor_vanilla/constraints/zcu102.xdc | 1096 ----------------- .../xilinx/flavor_vanilla/flavor_vanilla.mk | 3 + target/xilinx/flavor_vanilla/scripts/run.tcl | 2 +- .../flavor_vanilla/sim/run_simulation.tcl | 42 + .../flavor_vanilla/sim/setup_simulation.tcl | 44 + target/xilinx/flavor_vanilla/sim/sim.mk | 67 + .../xilinx/flavor_vanilla/sim/sim_tb_top.diff | 61 + .../flavor_vanilla/src/carfield_top_xilinx.sv | 3 +- .../flavor_vanilla/src/dram_wrapper_xilinx.sv | 32 +- .../flavor_vanilla/src/phy_definitions.svh | 45 +- target/xilinx/scripts/bin2jtag.py | 100 ++ target/xilinx/scripts/flash_spi.tcl | 20 +- target/xilinx/scripts/overrides.sh | 16 +- target/xilinx/scripts/program.tcl | 4 +- target/xilinx/xilinx.mk | 16 +- .../constraints/carfield_xilinx_ip.xdc | 1 - .../constraints/ooc_carfield_ip.xdc | 8 +- .../carfield_ip/src/carfield_xilinx.sv | 2 +- .../xilinx/xilinx_ips/carfield_ip/tcl/run.tcl | 2 +- .../xilinx_ips/xlnx_clk_wiz/tcl/run.tcl | 35 + .../xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl | 19 + 42 files changed, 1311 insertions(+), 1380 deletions(-) create mode 100644 sw/boot/carfield_bd_vcu118.dts create mode 100644 sw/boot/carfield_pcie.dts create mode 100644 sw/boot/carfield_soc.dtsi delete mode 100644 target/xilinx/flavor_bd/.gitignore create mode 100644 target/xilinx/flavor_bd/constraints/vcu118.xdc create mode 100644 target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc create mode 100644 target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl create mode 100644 target/xilinx/flavor_bd/scripts/carfield_bd_vcu118_ext_jtag.tcl rename target/xilinx/flavor_bd/scripts/{carfield_bd_ext_jtag.tcl => carfield_bd_vcu128_ext_jtag.tcl} (100%) delete mode 100644 target/xilinx/flavor_vanilla/.gitignore create mode 100644 target/xilinx/flavor_vanilla/constraints/vcu118.xdc delete mode 100644 target/xilinx/flavor_vanilla/constraints/zcu102.xdc create mode 100644 target/xilinx/flavor_vanilla/sim/run_simulation.tcl create mode 100644 target/xilinx/flavor_vanilla/sim/setup_simulation.tcl create mode 100644 target/xilinx/flavor_vanilla/sim/sim.mk create mode 100644 target/xilinx/flavor_vanilla/sim/sim_tb_top.diff create mode 100644 target/xilinx/scripts/bin2jtag.py diff --git a/.gitignore b/.gitignore index 7433c473..738c2c49 100644 --- a/.gitignore +++ b/.gitignore @@ -11,6 +11,15 @@ spatz # Documentation site site/ +# Xilinx flow generated +target/xilinx/*/.Xil +target/xilinx/*/scripts/add_sources.tcl* +target/xilinx/*/scripts/add_includes.tcl +target/xilinx/*/out/ +probes.ltx +target/xilinx/*/carfield_vcu128/ +target/xilinx/*/carfield_vcu118/ + # sw auto-generated sw/tests/bare-metal/safed/*.h sw/tests/bare-metal/pulpd/*.h diff --git a/Bender.yml b/Bender.yml index 27ead1d2..7a75d788 100644 --- a/Bender.yml +++ b/Bender.yml @@ -99,7 +99,7 @@ sources: files: - hw/spatz_cluster_wrapper.sv - - target: test + - target: all(test, not(fpga)) files: - target/sim/src/hyp_vip/s27ks0641.v - target/sim/src/vip_carfield_soc.sv diff --git a/bender-xilinx.mk b/bender-xilinx.mk index 16f682e7..87d22988 100644 --- a/bender-xilinx.mk +++ b/bender-xilinx.mk @@ -6,6 +6,7 @@ # bender targets xilinx_targs_common += -t fpga +xilinx_targs_common += -t xilinx # bender defines xilinx_defs_common += -D PULP_FPGA_EMUL diff --git a/carfield.mk b/carfield.mk index bbf0bfc0..2b0bffad 100644 --- a/carfield.mk +++ b/carfield.mk @@ -47,7 +47,7 @@ include $(CAR_ROOT)/bender-safed.mk ###################### CAR_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:astral/astral-nonfree.git -CAR_NONFREE_COMMIT ?= e8e4354d084cf1cfe6eb9b3bae6af381ef9108b1 # branch: master +CAR_NONFREE_COMMIT ?= 616e11ac35e68477cf96cad5cd2297123911a28d # branch: vcu-118 ## @section Carfield platform nonfree components ## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC diff --git a/sw/boot/carfield.dtsi b/sw/boot/carfield.dtsi index 771b8316..06aae2b2 100644 --- a/sw/boot/carfield.dtsi +++ b/sw/boot/carfield.dtsi @@ -13,150 +13,7 @@ chosen { stdout-path = "/soc/serial@3002000:38400"; }; - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <1000000>; // 1 MHz - CPU0: cpu@0 { - device_type = "cpu"; - status = "okay"; - compatible = "eth,ariane", "riscv"; - clock-frequency = <50000000>; // 50 MHz - riscv,isa = "rv64imafdc"; - mmu-type = "riscv,sv39"; - tlb-split; - reg = <0>; - CPU0_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; - }; - sysclk: virt_50mhz { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - soc: soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "eth,carfield-soc", "eth,cheshire-bare-soc", "simple-bus"; - ranges; - debug@0 { - compatible = "riscv,debug-013"; - reg-names = "control"; - reg = <0x0 0x0 0x0 0x1000>; - }; - ctrl-regs@3000000 { - compatible = "eth,control-regs"; - reg = <0x0 0x3000000 0x0 0x1000>; - }; - axi_llc@3001000 { - compatible = "eth,axi-llc"; - reg = <0x0 0x3001000 0x0 0x5000>; - }; - ddr_link: memory-controller@3006000 { - compatible = "eth,ddr-link"; - reg = <0x0 0x3006000 0x0 0x1000>; - }; - serial@3002000 { - compatible = "ns16550a"; - clock-frequency = <50000000>; // 50 MHz - current-speed = <38400>; - interrupt-parent = <&PLIC0>; - interrupts = <1>; - reg = <0x0 0x3002000 0x0 0x1000>; - reg-shift = <2>; // regs are spaced on 32 bit boundary - reg-io-width = <4>; // only 32-bit access are supported - }; - spi@3004000 { - compatible = "opentitan,spi-host", "lowrisc,spi"; - interrupt-parent = <&PLIC0>; - interrupts = <17 18>; - reg = <0x0 0x3004000 0x0 0x1000>; - clock-frequency = <50000000>; - max-frequency = <20000000>; - #address-cells = <1>; - #size-cells = <0>; - boot-with = <1>; - nor@1 { - #address-cells = <0x1>; - #size-cells = <0x1>; - // Note : u-boot does not find mt25qu02g - compatible = "mt25qu02g", "jedec,spi-nor"; - reg = <0x1>; // CS - spi-max-frequency = <20000000>; - spi-rx-bus-width = <0x1>; - spi-tx-bus-width = <0x1>; - disable-wp; - partition@0 { - label = "all"; - reg = <0x0 0x6000000>; // 96 MB - read-only; - }; - }; - }; - clint@2040000 { - compatible = "riscv,clint0"; - interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>; - reg-names = "control"; - reg = <0x0 0x2040000 0x0 0x040000>; - }; - PLIC0: interrupt-controller@4000000 { - compatible = "riscv,plic0"; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; - riscv,max-priority = <7>; - riscv,ndev = <51>; - reg = <0x0 0x4000000 0x0 0x4000000>; - }; - gpio@3005000 { - compatible = "gpio,carfield"; - reg = <0x0 0x3005000 0x0 0x1000>; - interrupts-extended = <&PLIC0 19 &PLIC0 21 &PLIC0 22 &PLIC0 24>; - }; - tcdm@10000000 { - reg = <0x0 0x10000000 0x0 0x400000>; - }; - soc-ctrl@20010000 { - compatible = "soc-ctrl,carfield"; - reg = <0x0 0x20010000 0x0 0x1000>; - }; - l2-intl-0@78000000 { - compatible = "l2-intl,carfield"; - reg = <0x0 0x78000000 0x0 0x100000>; - }; - l2-cont-0@78100000 { - compatible = "l2-cont,carfield"; - reg = <0x0 0x78100000 0x0 0x100000>; - }; - l2-intl-1@78200000 { - compatible = "l2-intl,carfield"; - reg = <0x0 0x78200000 0x0 0x100000>; - }; - l2-cont-1@78300000 { - compatible = "l2-cont,carfield"; - reg = <0x0 0x78300000 0x0 0x100000>; - }; - safety-island@60000000 { - compatible = "safety-island,carfield"; - reg = <0x0 0x60000000 0x0 0x800000>; - }; - integer-cluster@50000000 { - compatible = "integer-cluster,carfield"; - reg = <0x0 0x50000000 0x0 0x800000>; - }; - spatz-cluster@51000000 { - compatible = "spatz-cluster,carfield"; - reg = <0x0 0x51000000 0x0 0x800000>; - }; - }; -}; + + /include/ "carfield_soc.dtsi" + +}; \ No newline at end of file diff --git a/sw/boot/carfield_bd_vcu118.dts b/sw/boot/carfield_bd_vcu118.dts new file mode 100644 index 00000000..0fe77b31 --- /dev/null +++ b/sw/boot/carfield_bd_vcu118.dts @@ -0,0 +1,8 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + + +/include/ "carfield.dtsi" \ No newline at end of file diff --git a/sw/boot/carfield_bd_vcu128.dts b/sw/boot/carfield_bd_vcu128.dts index 52f9121b..1b27f3f1 100644 --- a/sw/boot/carfield_bd_vcu128.dts +++ b/sw/boot/carfield_bd_vcu128.dts @@ -45,8 +45,8 @@ // interrupt and mac_irq interrupts-extended = <&PLIC0 19 &PLIC0 24>; //local-mac-address = [ 00 0A 35 04 E1 60 ]; // hero-vcu128-01 - local-mac-address = [ 00 0A 35 04 E1 52 ]; // hero-vcu128-02 - mac-address = [ 00 0A 35 04 E1 52 ]; + local-mac-address = [ 00 0A 35 07 D5 DD ]; // hero-vcu128-03 + mac-address = [ 00 0A 35 07 D5 DD ]; device_type = "network"; axistream-connected = <ð_dma0>; axistream-control-connected = <ð_dma0>; diff --git a/sw/boot/carfield_pcie.dts b/sw/boot/carfield_pcie.dts new file mode 100644 index 00000000..880786f9 --- /dev/null +++ b/sw/boot/carfield_pcie.dts @@ -0,0 +1,26 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + +/dts-v1/; +/plugin/; +&{/dev@0,0} { + axi-bus { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + /include/ "carfield_soc.dtsi" + + }; +}; + +&soc { + pcie-axi-bar@180000000 { + compatible = "xlnx,pcie-axi-bar"; + reg = <0x1 0x80000000 0x0 0x80000000>; + }; +}; \ No newline at end of file diff --git a/sw/boot/carfield_soc.dtsi b/sw/boot/carfield_soc.dtsi new file mode 100644 index 00000000..e77c3f3f --- /dev/null +++ b/sw/boot/carfield_soc.dtsi @@ -0,0 +1,174 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + + memory@80000000 { + // Give 1GiB to Linux management + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + }; + + reserved-memory { + ranges; + // Keep 1GiB memory for explicit management + reserved_dev_buffer: l3_buffer@0xc0000000 { + reg = <0x0 0xc0000000 0x0 0x40000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; // 1 MHz + CPU0: cpu@0 { + device_type = "cpu"; + status = "okay"; + compatible = "eth,ariane", "riscv"; + clock-frequency = <50000000>; // 50 MHz + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + tlb-split; + reg = <0>; + CPU0_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + sysclk: virt_50mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "eth,carfield-soc", "eth,cheshire-bare-soc", "simple-bus"; + ranges; + debug@0 { + compatible = "riscv,debug-013"; + reg-names = "control"; + reg = <0x0 0x0 0x0 0x1000>; + }; + idma@1000000 { + compatible = "eth,idma"; + reg = <0x0 0x1000000 0x0 0x1000>; + }; + ctrl-regs@3000000 { + compatible = "eth,control-regs"; + reg = <0x0 0x3000000 0x0 0x1000>; + }; + axi_llc@3001000 { + compatible = "eth,axi-llc"; + reg = <0x0 0x3001000 0x0 0x5000>; + }; + ddr_link: memory-controller@3006000 { + compatible = "eth,ddr-link"; + reg = <0x0 0x3006000 0x0 0x1000>; + }; + serial@3002000 { + compatible = "ns16550a"; + clock-frequency = <50000000>; // 50 MHz + current-speed = <38400>; + interrupt-parent = <&PLIC0>; + interrupts = <1>; + reg = <0x0 0x3002000 0x0 0x1000>; + reg-shift = <2>; // regs are spaced on 32 bit boundary + reg-io-width = <4>; // only 32-bit access are supported + }; + spi@3004000 { + compatible = "opentitan,spi-host", "lowrisc,spi"; + interrupt-parent = <&PLIC0>; + interrupts = <17 18>; + reg = <0x0 0x3004000 0x0 0x1000>; + clock-frequency = <50000000>; + max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <0>; + boot-with = <1>; + nor@1 { + #address-cells = <0x1>; + #size-cells = <0x1>; + // Note : u-boot does not find mt25qu02g + compatible = "mt25qu02g", "jedec,spi-nor"; + reg = <0x1>; // CS + spi-max-frequency = <20000000>; + spi-rx-bus-width = <0x1>; + spi-tx-bus-width = <0x1>; + disable-wp; + partition@0 { + label = "all"; + reg = <0x0 0x6000000>; // 96 MB + read-only; + }; + }; + }; + clint@2040000 { + compatible = "riscv,clint0"; + interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>; + reg-names = "control"; + reg = <0x0 0x2040000 0x0 0x040000>; + }; + PLIC0: interrupt-controller@4000000 { + compatible = "riscv,plic0"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; + riscv,max-priority = <7>; + riscv,ndev = <51>; + reg = <0x0 0x4000000 0x0 0x4000000>; + }; + gpio@3005000 { + compatible = "gpio,carfield"; + reg = <0x0 0x3005000 0x0 0x1000>; + interrupts-extended = <&PLIC0 19 &PLIC0 21 &PLIC0 22 &PLIC0 24>; + }; + tcdm@10000000 { + reg = <0x0 0x10000000 0x0 0x400000>; + }; + soc-ctrl@20010000 { + compatible = "soc-ctrl,carfield"; + reg = <0x0 0x20010000 0x0 0x1000>; + }; + l2-intl-0@78000000 { + compatible = "l2-intl,carfield"; + reg = <0x0 0x78000000 0x0 0x100000>; + }; + l2-cont-0@78100000 { + compatible = "l2-cont,carfield"; + reg = <0x0 0x78100000 0x0 0x100000>; + }; + l2-intl-1@78200000 { + compatible = "l2-intl,carfield"; + reg = <0x0 0x78200000 0x0 0x100000>; + }; + l2-cont-1@78300000 { + compatible = "l2-cont,carfield"; + reg = <0x0 0x78300000 0x0 0x100000>; + }; + safety-island@60000000 { + compatible = "safety-island,carfield"; + reg = <0x0 0x60000000 0x0 0x800000>; + // Link to the buffer for this device + memory-region = <&reserved_dev_buffer>; + }; + integer-cluster@50000000 { + compatible = "integer-cluster,carfield"; + reg = <0x0 0x50000000 0x0 0x800000>; + // Link to the buffer for this device + memory-region = <&reserved_dev_buffer>; + }; + spatz-cluster@51000000 { + compatible = "spatz-cluster,carfield"; + reg = <0x0 0x51000000 0x0 0x800000>; + // Link to the buffer for this device + memory-region = <&reserved_dev_buffer>; + }; + }; \ No newline at end of file diff --git a/sw/sw.mk b/sw/sw.mk index 66e95e02..e0e563c6 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -180,6 +180,20 @@ $(CAR_SW_DIR)/boot/linux_carfield_%.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CA dd if=$(word 2,$^) of=$@ bs=512 seek=128 conv=notrunc dd if=$(word 3,$^) of=$@ bs=512 seek=2048 conv=notrunc dd if=$(word 4,$^) of=$@ bs=512 seek=8192 conv=notrunc + dd if=sw/boot/linux_carfield_bd_vcu128.gpt.bin of=sw/boot/linux.gpt.min.bin bs=512 count=8192 && cp sw/boot/linux.gpt.min.bin sw/boot/linux_carfield_bd_vcu128.gpt.bin + +# Create Uboot disk image +$(CAR_SW_DIR)/boot/uboot_carfield_%.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CAR_SW_DIR)/boot/carfield_%.dtb $(CAR_SW_DIR)/boot/install64/fw_payload.bin + truncate -s $(CAR_SW_DISK_SIZE) $@ + sgdisk --clear -g --set-alignment=1 \ + --new=1:64:96 --typecode=1:$(CHS_SW_ZSL_TGUID) \ + --new=2:128:159 --typecode=2:$(CHS_SW_DTB_TGUID) \ + --new=3:2048:8191 --typecode=3:$(CHS_SW_FW_TGUID) \ + --new=4:8192:0 --typecode=4:8200 \ + $@ + dd if=$(word 1,$^) of=$@ bs=512 seek=64 conv=notrunc + dd if=$(word 2,$^) of=$@ bs=512 seek=128 conv=notrunc + dd if=$(word 3,$^) of=$@ bs=512 seek=2048 conv=notrunc ######################### # Linux app compilation # diff --git a/target/xilinx/flavor_bd/.gitignore b/target/xilinx/flavor_bd/.gitignore deleted file mode 100644 index c9a0ab54..00000000 --- a/target/xilinx/flavor_bd/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -.Xil -carfield_* -scripts/add_sources.tcl* -scripts/add_includes.tcl -out/ -probes.ltx \ No newline at end of file diff --git a/target/xilinx/flavor_bd/constraints/vcu118.xdc b/target/xilinx/flavor_bd/constraints/vcu118.xdc new file mode 100644 index 00000000..76f65cbb --- /dev/null +++ b/target/xilinx/flavor_bd/constraints/vcu118.xdc @@ -0,0 +1,37 @@ +# VIOs are asynchronous +set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}] + +# Create system clocks +#create_clock -period 4 -name sys_clk [get_pins design_1_i/util_ds_buf_0/IBUF_OUT] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins design_1_i/util_ds_buf_0/IBUF_OUT] +#create_clock -period 4 -name pcie_clk [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]] +#create_clock -period 4 -name pcie_clk_div [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]] +#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]] +#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]] + +# PCIe clock LOC +#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0P]] [get_ports pcie_refclk_clk_p[0]] +#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0N]] [get_ports pcie_refclk_clk_n[0]] + +# VCU128 Rev1.0 XDC +# Date: 01/24/2018 + +#### This file is a general .xdc for the VCU128 1 Rev. +#### To use it in a project: +#### - uncomment the lines corresponding to used pins +#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +set_property PACKAGE_PIN AW25 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property PACKAGE_PIN BB21 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 + +set_property PACKAGE_PIN L19 [get_ports reset] +set_property IOSTANDARD LVCMOS12 [get_ports reset] + +#set_property BOARD_PART_PIN default_250mhz_clk_n [get_ports sys_clk_clk_n[0]] +#set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_clk_n[0]] +#set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_clk_p[0]] +#set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_clk_p[0]] +#set_property PACKAGE_PIN BH51 [get_ports sys_clk_clk_p[0]] +#set_property PACKAGE_PIN BJ51 [get_ports sys_clk_clk_n[0]] diff --git a/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc new file mode 100644 index 00000000..f140c1e5 --- /dev/null +++ b/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc @@ -0,0 +1,33 @@ +# VDD, and GND are directly wired on VCU118 +# set_property PACKAGE_PIN P29 [get_ports jtag_trst_ni] ;# P29 (PMOD1_4_LS) - J53.2 - GND +# set_property IOSTANDARD LVCMOS12 [get_ports jtag_trst_ni] ; + +set_property PACKAGE_PIN N30 [get_ports jtag_tdo_o] ;# N30 (PMOD1_2_LS) - J53.5 - TDO +set_property IOSTANDARD LVCMOS12 [get_ports jtag_tdo_o] + +set_property PACKAGE_PIN P30 [get_ports jtag_tck_i] ;# P30 (PMOD1_3_LS) - J53.7 - TCK +set_property IOSTANDARD LVCMOS12 [get_ports jtag_tck_i] ; + +set_property PACKAGE_PIN N28 [get_ports jtag_tms_i] ;# N28 (PMOD1_0_LS) - J53.1 - TMS +set_property IOSTANDARD LVCMOS12 [get_ports jtag_tms_i] ; + +set_property PACKAGE_PIN M30 [get_ports jtag_tdi_i] ;# M30 (PMOD1_1_LS) - J53.3 - TDI +set_property IOSTANDARD LVCMOS12 [get_ports jtag_tdi_i] + +############################# +# Classic connection to J52 # +############################# +# set_property PACKAGE_PIN AV16 [get_ports jtag_trst_ni] ;# AV16 (PMOD0_4_LS) - J52.2 - GND +# set_property IOSTANDARD LVCMOS18 [get_ports jtag_trst_ni] ; + +# set_property PACKAGE_PIN AW15 [get_ports jtag_tdo_o] ;# AW15 (PMOD0_2_LS) - J52.5 - TDO +# set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] + +# set_property PACKAGE_PIN AV15 [get_ports jtag_tck_i] ;# AV15 (PMOD0_3_LS) - J52.7 - TCK +# set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] ; + +# set_property PACKAGE_PIN AY14 [get_ports jtag_tms_i] ;# AY14 (PMOD0_0_LS) - J52.1 - TMS +# set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] ; + +# set_property PACKAGE_PIN AY15 [get_ports jtag_tdi_i] ;# AY15 (PMOD0_1_LS) - J52.3 - TDI +# set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] ; diff --git a/target/xilinx/flavor_bd/flavor_bd.mk b/target/xilinx/flavor_bd/flavor_bd.mk index 4a21fc3b..49e729bf 100644 --- a/target/xilinx/flavor_bd/flavor_bd.mk +++ b/target/xilinx/flavor_bd/flavor_bd.mk @@ -46,8 +46,14 @@ $(CAR_XIL_DIR)/flavor_bd/out/%.bit: $(xilinx_ips_paths_bd) $(CAR_XIL_DIR)/flavor mkdir -p $(CAR_XIL_DIR)/flavor_bd/out cd $(CAR_XIL_DIR)/flavor_bd && $(vivado_env_bd) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl find $(CAR_XIL_DIR)/flavor_bd -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CAR_XIL_DIR)/flavor_bd/out + .PRECIOUS: $(CAR_XIL_DIR)/flavor_bd/out/%.bit +# This vivado script loads a binary device tree at 0x80000000 (for the Host PCIe driver to read) +# Generate me with: make `realpath target/xilinx/flavor_bd/scripts/send_dtb_carfield_pcie.tcl` +$(CAR_XIL_DIR)/flavor_bd/scripts/send_dtb_%.tcl: $(CAR_SW_DIR)/boot/%.dtb + $(PYTHON) $(CAR_XIL_DIR)/scripts/bin2jtag.py -c32 -b 80000000 -d hw_axi_1 $< > $@ + car-xil-clean-bd: cd $(CAR_XIL_DIR)/flavor_bd && rm -rf scripts/add_includes.tcl* *.log *.jou *.str *.mif carfield_$(XILINX_BOARD) .Xil/ diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl new file mode 100644 index 00000000..fe1f4ec4 --- /dev/null +++ b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl @@ -0,0 +1,381 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Cyril Koenig + +################################################################ +# This is a generated script based on design: design_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2020.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xcvu9p-flga2104-2L-e + set_property BOARD_PART xilinx.com:vcu118:part0:2.4 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name design_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +ethz.ch:user:carfield_xilinx_ip:1.0\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:ddr4:2.2\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:util_ds_buf:2.1\ +xilinx.com:ip:vio:3.0\ +xilinx.com:ip:smartconnect:1.0\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr4_sdram_c1_062 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c1_062 ] + + set default_250mhz_clk1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_250mhz_clk1 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {250000000} \ + ] $default_250mhz_clk1 + + set default_sysclk1_300 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_sysclk1_300 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {300000000} \ + ] $default_sysclk1_300 + + + # Create ports + set reset [ create_bd_port -dir I -type rst reset ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $reset + set uart_rx_i [ create_bd_port -dir I uart_rx_i ] + set uart_tx_o [ create_bd_port -dir O uart_tx_o ] + + # Create instance: carfield_xilinx_ip_0, and set properties + set carfield_xilinx_ip_0 [ create_bd_cell -type ip -vlnv ethz.ch:user:carfield_xilinx_ip:1.0 carfield_xilinx_ip_0 ] + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [ list \ + CONFIG.CLKIN1_JITTER_PS {33.330000000000005} \ + CONFIG.CLKOUT1_JITTER {160.570} \ + CONFIG.CLKOUT1_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.CLKOUT1_USED {true} \ + CONFIG.CLKOUT2_JITTER {140.023} \ + CONFIG.CLKOUT2_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_JITTER {116.415} \ + CONFIG.CLKOUT3_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_JITTER {101.475} \ + CONFIG.CLKOUT4_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + CONFIG.CLK_OUT1_PORT {clk_10} \ + CONFIG.CLK_OUT2_PORT {clk_20} \ + CONFIG.CLK_OUT3_PORT {clk_50} \ + CONFIG.CLK_OUT4_PORT {clk_100} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {4.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {3.333} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {120.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {60} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {24} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {12} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + CONFIG.USE_RESET {false} \ + ] $clk_wiz_0 + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {None} \ + CONFIG.C0.BANK_GROUP_WIDTH {1} \ + CONFIG.C0.DDR4_AxiAddressWidth {31} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_DataWidth {64} \ + CONFIG.C0.DDR4_InputClockPeriod {4000} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16LY-062E} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {default_250mhz_clk1} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c1_062} \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + ] $ddr4_0 + + # Create instance: high, and set properties + set high [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 high ] + + # Create instance: low, and set properties + set low [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 low ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + ] $low + + # Create instance: psr_10, and set properties + set psr_10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 psr_10 ] + set_property -dict [ list \ + CONFIG.C_AUX_RESET_HIGH {1} \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $psr_10 + + # Create instance: psr_300, and set properties + set psr_300 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 psr_300 ] + set_property -dict [ list \ + CONFIG.C_AUX_RESET_HIGH {1} \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + ] $psr_300 + + # Create instance: util_ds_buf_0, and set properties + set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0 ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDS} \ + CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {default_sysclk1_300} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $util_ds_buf_0 + + # Create instance: vio_0, and set properties + set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ] + set_property -dict [ list \ + CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ + CONFIG.C_NUM_PROBE_IN {0} \ + CONFIG.C_NUM_PROBE_OUT {3} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0x2} \ + CONFIG.C_PROBE_OUT0_WIDTH {2} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x2} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + ] $vio_0 + + # Create instance: xbar_dram, and set properties + set xbar_dram [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 xbar_dram ] + set_property -dict [ list \ + CONFIG.HAS_ARESETN {1} \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $xbar_dram + + # Create interface connections + connect_bd_intf_net -intf_net carfield_xilinx_ip_0_dram_axi [get_bd_intf_pins carfield_xilinx_ip_0/dram_axi] [get_bd_intf_pins xbar_dram/S00_AXI] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c1_062] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net default_250mhz_clk1_1 [get_bd_intf_ports default_250mhz_clk1] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net default_sysclk1_300_1 [get_bd_intf_ports default_sysclk1_300] [get_bd_intf_pins util_ds_buf_0/CLK_IN_D] + connect_bd_intf_net -intf_net xbar_dram_M00_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] [get_bd_intf_pins xbar_dram/M00_AXI] + + # Create port connections + connect_bd_net -net carfield_xilinx_ip_0_dram_axi_m_aclk [get_bd_pins carfield_xilinx_ip_0/dram_axi_m_aclk] [get_bd_pins xbar_dram/aclk] + connect_bd_net -net carfield_xilinx_ip_0_uart_tx_o [get_bd_ports uart_tx_o] [get_bd_pins carfield_xilinx_ip_0/uart_tx_o] + connect_bd_net -net clk_wiz_0_clk_10 [get_bd_pins carfield_xilinx_ip_0/clk_10] [get_bd_pins clk_wiz_0/clk_10] [get_bd_pins psr_10/slowest_sync_clk] + connect_bd_net -net clk_wiz_0_clk_20 [get_bd_pins carfield_xilinx_ip_0/clk_20] [get_bd_pins clk_wiz_0/clk_20] + connect_bd_net -net clk_wiz_0_clk_50 [get_bd_pins carfield_xilinx_ip_0/clk_50] [get_bd_pins clk_wiz_0/clk_50] [get_bd_pins vio_0/clk] + connect_bd_net -net clk_wiz_0_clk_100 [get_bd_pins carfield_xilinx_ip_0/clk_100] [get_bd_pins clk_wiz_0/clk_100] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins psr_300/slowest_sync_clk] [get_bd_pins xbar_dram/aclk1] + connect_bd_net -net high_dout [get_bd_pins carfield_xilinx_ip_0/jtag_trst_ni] [get_bd_pins high/dout] + connect_bd_net -net low_dout [get_bd_pins carfield_xilinx_ip_0/testmode_i] [get_bd_pins low/dout] + connect_bd_net -net psr_10_interconnect_aresetn [get_bd_pins psr_10/interconnect_aresetn] [get_bd_pins xbar_dram/aresetn] + connect_bd_net -net psr_10_mb_reset [get_bd_pins carfield_xilinx_ip_0/cpu_reset] [get_bd_pins psr_10/mb_reset] + connect_bd_net -net psr_333_peripheral_aresetn [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins psr_300/peripheral_aresetn] + connect_bd_net -net psr_333_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins psr_300/peripheral_reset] + connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins psr_10/ext_reset_in] [get_bd_pins psr_300/ext_reset_in] + connect_bd_net -net uart_rx_i_1 [get_bd_ports uart_rx_i] [get_bd_pins carfield_xilinx_ip_0/uart_rx_i] + connect_bd_net -net util_ds_buf_0_IBUF_OUT [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins util_ds_buf_0/IBUF_OUT] + connect_bd_net -net vio_0_probe_out0 [get_bd_pins carfield_xilinx_ip_0/boot_mode_i] [get_bd_pins vio_0/probe_out0] + connect_bd_net -net vio_0_probe_out1 [get_bd_pins carfield_xilinx_ip_0/boot_mode_safety_i] [get_bd_pins vio_0/probe_out1] + connect_bd_net -net vio_0_probe_out2 [get_bd_pins psr_10/aux_reset_in] [get_bd_pins psr_300/aux_reset_in] [get_bd_pins vio_0/probe_out2] + + # Create address segments + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/dram_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118_ext_jtag.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118_ext_jtag.tcl new file mode 100644 index 00000000..a5570104 --- /dev/null +++ b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118_ext_jtag.tcl @@ -0,0 +1,18 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +# VDD and GND are directly wired on VCU118 + +set jtag_tck_i [ create_bd_port -dir I jtag_tck_i ] +set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ] +set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ] +set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ] +set jtag_trst_ni [ create_bd_port -dir I jtag_trst_ni ] +connect_bd_net -net carfield_xilinx_ip_0_jtag_tdo_o [get_bd_ports jtag_tdo_o] [get_bd_pins carfield_xilinx_ip_0/jtag_tdo_o] +connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tck_i] +connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tdi_i] +connect_bd_net -net jtag_tms_i_1 [get_bd_ports jtag_tms_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tms_i] +connect_bd_net -net jtag_trst_ni_1 [get_bd_ports jtag_trst_ni] [get_bd_pins carfield_xilinx_ip_0/jtag_trst_ni] diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl index fcf40ed6..6da8e256 100644 --- a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl +++ b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl @@ -1,8 +1,8 @@ -# Copyright 2020 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 # -# This file was generated for vivado 2020.2 +# Cyril Koenig ################################################################ # This is a generated script based on design: design_1 @@ -136,6 +136,7 @@ xilinx.com:ip:clk_wiz:6.0\ xilinx.com:ip:xlconcat:2.1\ xilinx.com:ip:ddr4:2.2\ xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:jtag_axi:1.2\ xilinx.com:ip:proc_sys_reset:5.0\ xilinx.com:ip:util_ds_buf:2.1\ xilinx.com:ip:vio:3.0\ @@ -208,7 +209,7 @@ proc create_root_design { parentCell } { set mdio_mdc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio_mdc ] - set pci_express_x1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x1 ] + set pci_express_x4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x4 ] set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] set_property -dict [ list \ @@ -331,6 +332,9 @@ proc create_root_design { parentCell } { # Create instance: high, and set properties set high [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 high ] + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] + # Create instance: low, and set properties set low [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 low ] set_property -dict [ list \ @@ -392,7 +396,7 @@ proc create_root_design { parentCell } { set xbar_periph_in [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 xbar_periph_in ] set_property -dict [ list \ CONFIG.NUM_CLKS {2} \ - CONFIG.NUM_SI {4} \ + CONFIG.NUM_SI {5} \ ] $xbar_periph_in # Create instance: xbar_periph_out, and set properties @@ -406,32 +410,44 @@ proc create_root_design { parentCell } { # Create instance: xdma_0, and set properties set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ] set_property -dict [ list \ - CONFIG.PCIE_BOARD_INTERFACE {pci_express_x2} \ - CONFIG.PF0_DEVICE_ID_mqdma {9012} \ - CONFIG.PF2_DEVICE_ID_mqdma {9012} \ - CONFIG.PF3_DEVICE_ID_mqdma {9012} \ + CONFIG.PCIE_BOARD_INTERFACE {pci_express_x4} \ + CONFIG.PF0_DEVICE_ID_mqdma {9014} \ + CONFIG.PF2_DEVICE_ID_mqdma {9014} \ + CONFIG.PF3_DEVICE_ID_mqdma {9014} \ CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \ CONFIG.axi_addr_width {64} \ + CONFIG.axi_bypass_64bit_en {true} \ + CONFIG.axi_bypass_prefetchable {true} \ + CONFIG.axist_bypass_en {true} \ + CONFIG.axist_bypass_scale {Gigabytes} \ + CONFIG.axist_bypass_size {4} \ CONFIG.axisten_freq {125} \ - CONFIG.bar_indicator {BAR_1:0} \ - CONFIG.c_s_axi_supports_narrow_burst {false} \ - CONFIG.en_gt_selection {true} \ + CONFIG.bar_indicator {BAR_0} \ CONFIG.functional_mode {AXI_Bridge} \ - CONFIG.mode_selection {Advanced} \ - CONFIG.pf0_bar0_64bit {true} \ - CONFIG.pf0_bar0_scale {Gigabytes} \ - CONFIG.pf0_bar0_size {4} \ - CONFIG.pf0_base_class_menu {Processing_accelerators} \ - CONFIG.pf0_class_code {120000} \ - CONFIG.pf0_class_code_base {12} \ - CONFIG.pf0_class_code_interface {00} \ - CONFIG.pf0_device_id {9012} \ - CONFIG.pf0_msix_cap_pba_bir {BAR_1:0} \ - CONFIG.pf0_msix_cap_table_bir {BAR_1:0} \ - CONFIG.pf0_sub_class_interface_menu {Unknown} \ - CONFIG.pl_link_cap_max_link_speed {2.5_GT/s} \ - CONFIG.pl_link_cap_max_link_width {X2} \ - CONFIG.plltype {CPLL} \ + CONFIG.pciebar2axibar_0 {0x0000000020000000} \ + CONFIG.pciebar2axibar_1 {0x0000000060000000} \ + CONFIG.pf0_bar0_64bit {false} \ + CONFIG.pf0_bar0_enabled {true} \ + CONFIG.pf0_bar0_prefetchable {false} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {1} \ + CONFIG.pf0_bar1_enabled {true} \ + CONFIG.pf0_bar1_scale {Megabytes} \ + CONFIG.pf0_bar1_size {1} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_scale {Gigabytes} \ + CONFIG.pf0_bar2_size {1} \ + CONFIG.pf0_bar4_64bit {true} \ + CONFIG.pf0_bar4_enabled {true} \ + CONFIG.pf0_bar4_prefetchable {true} \ + CONFIG.pf0_bar4_scale {Gigabytes} \ + CONFIG.pf0_bar4_size {4} \ + CONFIG.pf0_device_id {9014} \ + CONFIG.pf0_msix_cap_pba_bir {BAR_0} \ + CONFIG.pf0_msix_cap_table_bir {BAR_0} \ + CONFIG.pl_link_cap_max_link_width {X4} \ + CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \ CONFIG.xdma_axilite_slave {true} \ ] $xdma_0 @@ -449,17 +465,18 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net carfield_xilinx_ip_0_dram_axi [get_bd_intf_pins carfield_xilinx_ip_0/dram_axi] [get_bd_intf_pins xbar_dram/S00_AXI] connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram] [get_bd_intf_pins ddr4_0/C0_DDR4] connect_bd_intf_net -intf_net diff_clock_rtl_1 [get_bd_intf_ports sys_clk] [get_bd_intf_pins util_ds_buf_0/CLK_IN_D] + connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins xbar_periph_in/S04_AXI] connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf_1/CLK_IN_D] connect_bd_intf_net -intf_net sgmii_phyclk_1 [get_bd_intf_ports sgmii_phyclk] [get_bd_intf_pins axi_ethernet_0/lvds_clk] connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] [get_bd_intf_pins xbar_dram/M00_AXI] connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins axi_ethernet_0/s_axi] [get_bd_intf_pins xbar_periph_out/M00_AXI] connect_bd_intf_net -intf_net smartconnect_2_M00_AXI [get_bd_intf_pins carfield_xilinx_ip_0/periph_axi_s] [get_bd_intf_pins xbar_periph_in/M00_AXI] connect_bd_intf_net -intf_net xbar_periph_out_M01_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins xbar_periph_out/M01_AXI] - connect_bd_intf_net -intf_net xbar_periph_out_M02_AXI [get_bd_intf_pins xbar_periph_out/M02_AXI] [get_bd_intf_pins xdma_0/S_AXI_B] - connect_bd_intf_net -intf_net xbar_periph_out_M03_AXI [get_bd_intf_pins xbar_periph_out/M03_AXI] [get_bd_intf_pins xdma_0/S_AXI_LITE] - connect_bd_intf_net -intf_net xbar_periph_out_M04_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] [get_bd_intf_pins xbar_periph_out/M04_AXI] + connect_bd_intf_net -intf_net xbar_periph_out_M02_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] [get_bd_intf_pins xbar_periph_out/M02_AXI] + connect_bd_intf_net -intf_net xbar_periph_out_M03_AXI [get_bd_intf_pins xbar_periph_out/M03_AXI] [get_bd_intf_pins xdma_0/S_AXI_B] + connect_bd_intf_net -intf_net xbar_periph_out_M04_AXI [get_bd_intf_pins xbar_periph_out/M04_AXI] [get_bd_intf_pins xdma_0/S_AXI_LITE] connect_bd_intf_net -intf_net xdma_0_M_AXI_B [get_bd_intf_pins xbar_periph_in/S03_AXI] [get_bd_intf_pins xdma_0/M_AXI_B] - connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x1] [get_bd_intf_pins xdma_0/pcie_mgt] + connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x4] [get_bd_intf_pins xdma_0/pcie_mgt] # Create port connections connect_bd_net -net Net [get_bd_pins carfield_xilinx_ip_0/pad_hyper_csn] @@ -480,17 +497,17 @@ proc create_root_design { parentCell } { connect_bd_net -net carfield_xilinx_ip_0_uart_tx_o [get_bd_ports uart_tx_o] [get_bd_pins carfield_xilinx_ip_0/uart_tx_o] connect_bd_net -net clk_wiz_0_clk_10 [get_bd_pins carfield_xilinx_ip_0/clk_10] [get_bd_pins clk_wiz_0/clk_10] [get_bd_pins psr_10/slowest_sync_clk] connect_bd_net -net clk_wiz_0_clk_20 [get_bd_pins carfield_xilinx_ip_0/clk_20] [get_bd_pins clk_wiz_0/clk_20] - connect_bd_net -net clk_wiz_0_clk_50 [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/m_axi_sg_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_ethernet_0/axis_clk] [get_bd_pins axi_ethernet_0/s_axi_lite_clk] [get_bd_pins carfield_xilinx_ip_0/clk_50] [get_bd_pins clk_wiz_0/clk_50] [get_bd_pins vio_0/clk] [get_bd_pins xbar_periph_in/aclk] [get_bd_pins xbar_periph_out/aclk1] + connect_bd_net -net clk_wiz_0_clk_50 [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/m_axi_sg_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_ethernet_0/axis_clk] [get_bd_pins axi_ethernet_0/s_axi_lite_clk] [get_bd_pins carfield_xilinx_ip_0/clk_50] [get_bd_pins clk_wiz_0/clk_50] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins vio_0/clk] [get_bd_pins xbar_periph_in/aclk] [get_bd_pins xbar_periph_out/aclk1] connect_bd_net -net clk_wiz_0_clk_100 [get_bd_pins carfield_xilinx_ip_0/clk_100] [get_bd_pins clk_wiz_0/clk_100] connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins psr_10/dcm_locked] connect_bd_net -net concat_irq_dout [get_bd_pins carfield_xilinx_ip_0/gpio_i] [get_bd_pins concat_irq/dout] - connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins psr_333/slowest_sync_clk] [get_bd_pins xbar_dram/aclk1] [get_bd_pins xbar_periph_out/aclk3] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins psr_333/slowest_sync_clk] [get_bd_pins xbar_dram/aclk1] [get_bd_pins xbar_periph_out/aclk2] connect_bd_net -net dummy_port_in_1 [get_bd_ports dummy_port_in] [get_bd_pins axi_ethernet_0/dummy_port_in] connect_bd_net -net high_dout [get_bd_pins carfield_xilinx_ip_0/jtag_trst_ni] [get_bd_pins high/dout] connect_bd_net -net low_dout [get_bd_pins carfield_xilinx_ip_0/testmode_i] [get_bd_pins low/dout] connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n] connect_bd_net -net psr_10_interconnect_aresetn [get_bd_pins psr_10/interconnect_aresetn] [get_bd_pins xbar_dram/aresetn] [get_bd_pins xbar_periph_in/aresetn] [get_bd_pins xbar_periph_out/aresetn] - connect_bd_net -net psr_10_peripheral_aresetn [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_ethernet_0/s_axi_lite_resetn] [get_bd_pins psr_10/peripheral_aresetn] + connect_bd_net -net psr_10_peripheral_aresetn [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_ethernet_0/s_axi_lite_resetn] [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins psr_10/peripheral_aresetn] connect_bd_net -net psr_333_peripheral_aresetn [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins psr_333/peripheral_aresetn] connect_bd_net -net psr_333_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins psr_333/peripheral_reset] connect_bd_net -net psr_50_mb_reset [get_bd_pins carfield_xilinx_ip_0/cpu_reset] [get_bd_pins psr_10/mb_reset] @@ -502,7 +519,7 @@ proc create_root_design { parentCell } { connect_bd_net -net vio_0_probe_out0 [get_bd_pins carfield_xilinx_ip_0/boot_mode_i] [get_bd_pins vio_0/probe_out0] connect_bd_net -net vio_0_probe_out1 [get_bd_pins carfield_xilinx_ip_0/boot_mode_safety_i] [get_bd_pins vio_0/probe_out1] connect_bd_net -net vio_0_probe_out2 [get_bd_pins psr_10/aux_reset_in] [get_bd_pins psr_333/aux_reset_in] [get_bd_pins vio_0/probe_out2] - connect_bd_net -net xdma_0_axi_aclk [get_bd_pins xbar_periph_in/aclk1] [get_bd_pins xbar_periph_out/aclk2] [get_bd_pins xdma_0/axi_aclk] + connect_bd_net -net xdma_0_axi_aclk [get_bd_pins xbar_periph_in/aclk1] [get_bd_pins xbar_periph_out/aclk3] [get_bd_pins xdma_0/axi_aclk] # Create address segments assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs carfield_xilinx_ip_0/periph_axi_s/reg0] -force @@ -511,18 +528,16 @@ proc create_root_design { parentCell } { assign_bd_address -offset 0x41E00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force assign_bd_address -offset 0x40C00000 -range 0x00040000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs axi_ethernet_0/s_axi/Reg0] -force assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/dram_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x70000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] -force + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs xdma_0/S_AXI_B/BAR0] -force + assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs xdma_0/S_AXI_LITE/CTL0] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs carfield_xilinx_ip_0/periph_axi_s/reg0] -force assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_B] [get_bd_addr_segs carfield_xilinx_ip_0/periph_axi_s/reg0] -force - # Exclude Address Segments - exclude_bd_addr_seg -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] - exclude_bd_addr_seg -offset 0x76000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs xdma_0/S_AXI_B/BAR0] - exclude_bd_addr_seg -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs xdma_0/S_AXI_LITE/CTL0] - # Restore current instance current_bd_instance $oldCurInst - validate_bd_design save_bd_design } # End of create_root_design() @@ -535,3 +550,4 @@ proc create_root_design { parentCell } { create_root_design "" +common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128_ext_jtag.tcl similarity index 100% rename from target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl rename to target/xilinx/flavor_bd/scripts/carfield_bd_vcu128_ext_jtag.tcl diff --git a/target/xilinx/flavor_bd/scripts/run.tcl b/target/xilinx/flavor_bd/scripts/run.tcl index 9a529a06..749de4c4 100644 --- a/target/xilinx/flavor_bd/scripts/run.tcl +++ b/target/xilinx/flavor_bd/scripts/run.tcl @@ -28,7 +28,7 @@ source scripts/carfield_bd_$::env(XILINX_BOARD).tcl # Add the ext_jtag pins to block design if {[info exists ::env(GEN_EXT_JTAG)] && ($::env(GEN_EXT_JTAG)==1)} { - source scripts/carfield_bd_ext_jtag.tcl + source scripts/carfield_bd_$::env(XILINX_BOARD)_ext_jtag.tcl import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_ext_jtag.xdc } @@ -50,17 +50,24 @@ create_ip_run [get_files *design_1.bd] # Make sure carfield.xdc (imported from IP) executes after carfield_islands.tcl (that generates the clocks) set_property processing_order LATE [get_files carfield.xdc] -# Start OOC synthesis of changed IPs +# Bet list of synthesis and OOO synthesis to do set synth_runs [get_runs *synth*] # Exclude the whole design (synth_1) and the carfield IP (bug) -set all_ooc_synth [lsearch -regexp -all -inline -not $synth_runs {^synth_1$|carfield}] +if { $rdi::mode == "gui" } { + # Exclude the whole design the carfield IP from GUI (todo: inspect GUI bug when only carfield ooc has changed) + set all_ooc_synth [lsearch -regexp -all -inline -not $synth_runs {^synth_1$|carfield}] +} else { + # Exclude the synth_1 from OOC synthesis + set all_ooc_synth [lsearch -regexp -all -inline -not $synth_runs {^synth_1$}] +} + set runs_queued {} foreach run $all_ooc_synth { if {[get_property PROGRESS [get_run $run]] != "100%"} { puts "Launching run $run" lappend runs_queued $run # Default synthesis strategy - # set_property strategy Flow_RuntimeOptimized [get_runs $run] + set_property strategy Flow_RuntimeOptimized [get_runs $run] } else { puts "Skipping 100% complete run: $run" } @@ -76,8 +83,8 @@ if {[llength $runs_queued] != 0} { reset_run synth_1 } -# set_property strategy Flow_RuntimeOptimized [get_runs synth_1] -# set_property strategy Flow_RuntimeOptimized [get_runs impl_1] +set_property strategy Flow_RuntimeOptimized [get_runs synth_1] +set_property strategy Flow_RuntimeOptimized [get_runs impl_1] set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] # Enable sfcu due to package conflicts diff --git a/target/xilinx/flavor_vanilla/.gitignore b/target/xilinx/flavor_vanilla/.gitignore deleted file mode 100644 index f34690f0..00000000 --- a/target/xilinx/flavor_vanilla/.gitignore +++ /dev/null @@ -1,10 +0,0 @@ -.Xil -carfield.cache -carfield.ip_user_files -carfield.hw -carfield.sim -carfield.srcs -scripts/add_sources.tcl* -scripts/add_includes.tcl -out/ -probes.ltx \ No newline at end of file diff --git a/target/xilinx/flavor_vanilla/constraints/vcu118.xdc b/target/xilinx/flavor_vanilla/constraints/vcu118.xdc new file mode 100644 index 00000000..77d9b211 --- /dev/null +++ b/target/xilinx/flavor_vanilla/constraints/vcu118.xdc @@ -0,0 +1,72 @@ +############################## +# BOARD SPECIFIC CONSTRAINTS # +############################## + +############# +# Sys clock # +############# + +# 250 MHz ref clock +set SYS_TCK 4 +create_clock -period $SYS_TCK -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] +set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk} + +############# +# Mig clock # +############# + +# Dram axi clock : 833ps * 4 +set MIG_TCK 3.332 +set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +create_clock -period $MIG_TCK -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk] +set_clock_groups -name dram_async -asynchronous -group {dram_axi_clk} +set_false_path -hold -through $MIG_RST +set_max_delay -through $MIG_RST $MIG_TCK + +######## +# CDCs # +######## + +set_max_delay -through [get_nets -of_objects [get_cells i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*] -filter {NAME=~*async*}] $MIG_TCK +#set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $MIG_TCK + +#-------------- MCS Generation ---------------------- +#set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design] +#set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +#set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] +#set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +#set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design] +#set_property CFGBVS GND [current_design] +#set_property CONFIG_VOLTAGE 1.8 [current_design] +#set_property CONFIG_MODE SPIx8 [current_design] + + +################################################################################# + +set_property PACKAGE_PIN AW25 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property PACKAGE_PIN BB21 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 + +set_property PACKAGE_PIN L19 [get_ports cpu_reset] +set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset] + +set_property PACKAGE_PIN N30 [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO +# Todo change invalid lvcmos +set_property IOSTANDARD LVCMOS12 [get_ports jtag_tdo_o] + +set_property PACKAGE_PIN P30 [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK +set_property IOSTANDARD LVCMOS12 [get_ports jtag_tck_i] ; + +set_property PACKAGE_PIN N28 [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS +set_property IOSTANDARD LVCMOS12 [get_ports jtag_tms_i] ; + +set_property PACKAGE_PIN M30 [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI +set_property IOSTANDARD LVCMOS12 [get_ports jtag_tdi_i] + +# Default 250MHz clk1 +set_property PACKAGE_PIN D12 [get_ports "sys_clk_n"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_47 +set_property IOSTANDARD DIFF_SSTL12 [get_ports "sys_clk_n"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_47 +set_property PACKAGE_PIN E12 [get_ports "sys_clk_p"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_47 +set_property IOSTANDARD DIFF_SSTL12 [get_ports "sys_clk_p"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_47 diff --git a/target/xilinx/flavor_vanilla/constraints/zcu102.xdc b/target/xilinx/flavor_vanilla/constraints/zcu102.xdc deleted file mode 100644 index c27d0f18..00000000 --- a/target/xilinx/flavor_vanilla/constraints/zcu102.xdc +++ /dev/null @@ -1,1096 +0,0 @@ -############################## -# BOARD SPECIFIC CONSTRAINTS # -############################## - -# JTAG - -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] -set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] - -# Hyperbus -# 10MHz -set period_hyperbus 100 -create_clock -period [expr $period_hyperbus] -name rwds0_clk [get_ports pad_hyper_rwds[0]] -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O] - - -set clk_rwds_delayed_pin [get_pins -of_objects [get_cells i_iguana/i_hyperbus/i_phy/i_phy/i_trx/i_delay_rx_rwds_90/i_delay] -filter {DIRECTION =~ OUT}] -set clk_rwds_delayed_inv_pin [get_pins i_iguana/i_hyperbus/i_phy/i_phy/i_trx/i_rx_rwds_cdc_fifo/src_clk_i] - - -set clk_rx_shift [expr $period_hyperbus/10] -set rwds_input_delay [expr $period_hyperbus/4] -create_generated_clock -name clk_rwds_delayed0 -edges {1 2 3} -edge_shift "$clk_rx_shift $clk_rx_shift $clk_rx_shift" \ - -source [get_ports FMC_hyper0_rwds] $clk_rwds_delayed_pin -set_clock_latency [expr ${rwds_input_delay}] clk_rwds_delayed0 - -create_generated_clock -name clk_rwds_sample0 -invert -divide_by 1 -source $clk_rwds_delayed_pin $clk_rwds_delayed_inv_pin -set_clock_latency [expr ${rwds_input_delay}] clk_rwds_sample0 - - -################################################################################# - -############### -# ASSIGN PINS # -############### - - -################################################# -### ZCU102 Rev1.0 Master XDC file 09-15-2016 #### -################################################# -#Other net PACKAGE_PIN W17 - SYSMON_DXN Bank 0 - DXN -#Other net PACKAGE_PIN T18 - FPGA_SYSMON_AVCC Bank 0 - VCCADC -#Other net PACKAGE_PIN T17 - SYSMON_AGND Bank 0 - GNDADC -#Other net PACKAGE_PIN W18 - SYSMON_DXP Bank 0 - DXP -#Other net PACKAGE_PIN V18 - SYSMON_VREFP Bank 0 - VREFP -#Other net PACKAGE_PIN U17 - SYSMON_AGND Bank 0 - VREFN -#Other net PACKAGE_PIN U18 - SYSMON_VP_R Bank 0 - VP -#Other net PACKAGE_PIN V17 - SYSMON_VN_R Bank 0 - VN -#Other net PACKAGE_PIN AD15 - 3N5822 Bank 0 - PUDC_B_0 -#Other net PACKAGE_PIN AD14 - 3N5824 Bank 0 - POR_OVERRIDE -#set_property PACKAGE_PIN J15 [get_ports "L12N_AD8N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L12N_AD8N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L12N_AD8N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L12N_AD8N_50 -#set_property PACKAGE_PIN J16 [get_ports "L12P_AD8P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L12P_AD8P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L12P_AD8P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L12P_AD8P_50 -#set_property PACKAGE_PIN G16 [get_ports "L11N_AD9N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L11N_AD9N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L11N_AD9N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L11N_AD9N_50 -#set_property PACKAGE_PIN H16 [get_ports "L11P_AD9P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L11P_AD9P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L11P_AD9P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L11P_AD9P_50 -#set_property PACKAGE_PIN H14 [get_ports "L10N_AD10N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L10N_AD10N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L10N_AD10N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L10N_AD10N_50 -#set_property PACKAGE_PIN J14 [get_ports "L10P_AD10P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L10P_AD10P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L10P_AD10P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L10P_AD10P_50 -#set_property PACKAGE_PIN G14 [get_ports "L9N_AD11N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L9N_AD11N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L9N_AD11N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L9N_AD11N_50 -#set_property PACKAGE_PIN G15 [get_ports "L9P_AD11P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L9P_AD11P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L9P_AD11P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L9P_AD11P_50 -#set_property PACKAGE_PIN G13 [get_ports "L8N_HDGC_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L8N_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L8N_HDGC_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L8N_HDGC_50 -#set_property PACKAGE_PIN H13 [get_ports "L8P_HDGC_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L8P_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "L8P_HDGC_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L8P_HDGC_50 -#set_property PACKAGE_PIN H12 [get_ports "HDMI_SI5324_LOL"] ;# Bank 50 VCCO - VCC3V3 - IO_L7N_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_SI5324_LOL"] ;# Bank 50 VCCO - VCC3V3 - IO_L7N_HDGC_50 -#set_property PACKAGE_PIN J12 [get_ports "HDMI_SI5324_RST"] ;# Bank 50 VCCO - VCC3V3 - IO_L7P_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_SI5324_RST"] ;# Bank 50 VCCO - VCC3V3 - IO_L7P_HDGC_50 -#set_property PACKAGE_PIN F11 [get_ports "HDMI_SI5324_INT_ALM"] ;# Bank 50 VCCO - VCC3V3 - IO_L6N_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_SI5324_INT_ALM"] ;# Bank 50 VCCO - VCC3V3 - IO_L6N_HDGC_50 -#set_property PACKAGE_PIN F12 [get_ports "34N8121"] ;# Bank 50 VCCO - VCC3V3 - IO_L6P_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "34N8121"] ;# Bank 50 VCCO - VCC3V3 - IO_L6P_HDGC_50 -#set_property PACKAGE_PIN G11 [get_ports "34N8125"] ;# Bank 50 VCCO - VCC3V3 - IO_L5N_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "34N8125"] ;# Bank 50 VCCO - VCC3V3 - IO_L5N_HDGC_50 -#set_property PACKAGE_PIN H11 [get_ports "34N8129"] ;# Bank 50 VCCO - VCC3V3 - IO_L5P_HDGC_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "34N8129"] ;# Bank 50 VCCO - VCC3V3 - IO_L5P_HDGC_50 -#set_property PACKAGE_PIN D10 [get_ports "34N8133"] ;# Bank 50 VCCO - VCC3V3 - IO_L4N_AD12N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "34N8133"] ;# Bank 50 VCCO - VCC3V3 - IO_L4N_AD12N_50 -#set_property PACKAGE_PIN D11 [get_ports "MSP430_GPIO_PL_0"] ;# Bank 50 VCCO - VCC3V3 - IO_L4P_AD12P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_0"] ;# Bank 50 VCCO - VCC3V3 - IO_L4P_AD12P_50 -#set_property PACKAGE_PIN E10 [get_ports "MSP430_GPIO_PL_1"] ;# Bank 50 VCCO - VCC3V3 - IO_L3N_AD13N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_1"] ;# Bank 50 VCCO - VCC3V3 - IO_L3N_AD13N_50 -#set_property PACKAGE_PIN F10 [get_ports "MSP430_GPIO_PL_2"] ;# Bank 50 VCCO - VCC3V3 - IO_L3P_AD13P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_2"] ;# Bank 50 VCCO - VCC3V3 - IO_L3P_AD13P_50 -#set_property PACKAGE_PIN G10 [get_ports "MSP430_GPIO_PL_3"] ;# Bank 50 VCCO - VCC3V3 - IO_L2N_AD14N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_3"] ;# Bank 50 VCCO - VCC3V3 - IO_L2N_AD14N_50 -#set_property PACKAGE_PIN H10 [get_ports "SFP_SI5328_INT_ALM"] ;# Bank 50 VCCO - VCC3V3 - IO_L2P_AD14P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "SFP_SI5328_INT_ALM"] ;# Bank 50 VCCO - VCC3V3 - IO_L2P_AD14P_50 -#set_property PACKAGE_PIN J10 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1N_AD15N_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1N_AD15N_50 -#set_property PACKAGE_PIN J11 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1P_AD15P_50 -#set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1P_AD15P_50 -set_property PACKAGE_PIN E13 [get_ports "uart_tx_o"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 -set_property IOSTANDARD LVCMOS33 [get_ports "uart_tx_o"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 -set_property PACKAGE_PIN F13 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 -set_property IOSTANDARD LVCMOS33 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 -#set_property PACKAGE_PIN D12 [get_ports "UART2_RTS_O_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "UART2_RTS_O_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49 -#set_property PACKAGE_PIN E12 [get_ports "UART2_CTS_I_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "UART2_CTS_I_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49 -#set_property PACKAGE_PIN B12 [get_ports "MSP430_UCA1_TXD"] ;# Bank 49 VCCO - VCC3V3 - IO_L10N_AD10N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_UCA1_TXD"] ;# Bank 49 VCCO - VCC3V3 - IO_L10N_AD10N_49 -#set_property PACKAGE_PIN C12 [get_ports "MSP430_UCA1_RXD"] ;# Bank 49 VCCO - VCC3V3 - IO_L10P_AD10P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_UCA1_RXD"] ;# Bank 49 VCCO - VCC3V3 - IO_L10P_AD10P_49 -#set_property PACKAGE_PIN A12 [get_ports "SFP0_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L9N_AD11N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "SFP0_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L9N_AD11N_49 -#set_property PACKAGE_PIN A13 [get_ports "SFP1_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L9P_AD11P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "SFP1_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L9P_AD11P_49 -#set_property PACKAGE_PIN B13 [get_ports "SFP2_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L8N_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "SFP2_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L8N_HDGC_49 -#set_property PACKAGE_PIN C13 [get_ports "SFP3_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L8P_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "SFP3_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L8P_HDGC_49 -#set_property PACKAGE_PIN B14 [get_ports "SYSMON_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L7N_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "SYSMON_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L7N_HDGC_49 -#set_property PACKAGE_PIN C14 [get_ports "SYSMON_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L7P_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "SYSMON_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L7P_HDGC_49 -#set_property PACKAGE_PIN D14 [get_ports "HDMI_RX_PWR_DET"] ;# Bank 49 VCCO - VCC3V3 - IO_L6N_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_PWR_DET"] ;# Bank 49 VCCO - VCC3V3 - IO_L6N_HDGC_49 -#set_property PACKAGE_PIN E14 [get_ports "HDMI_RX_HPD"] ;# Bank 49 VCCO - VCC3V3 - IO_L6P_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_HPD"] ;# Bank 49 VCCO - VCC3V3 - IO_L6P_HDGC_49 -#set_property PACKAGE_PIN D15 [get_ports "HDMI_RX_CEC_SINK"] ;# Bank 49 VCCO - VCC3V3 - IO_L5N_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_CEC_SINK"] ;# Bank 49 VCCO - VCC3V3 - IO_L5N_HDGC_49 -#set_property PACKAGE_PIN E15 [get_ports "HDMI_RX_SNK_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L5P_HDGC_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_SNK_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L5P_HDGC_49 -#set_property PACKAGE_PIN A15 [get_ports "HDMI_RX_SNK_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L4N_AD12N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_SNK_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L4N_AD12N_49 -#set_property PACKAGE_PIN B15 [get_ports "HDMI_TX_EN"] ;# Bank 49 VCCO - VCC3V3 - IO_L4P_AD12P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_EN"] ;# Bank 49 VCCO - VCC3V3 - IO_L4P_AD12P_49 -#set_property PACKAGE_PIN A16 [get_ports "HDMI_TX_CEC"] ;# Bank 49 VCCO - VCC3V3 - IO_L3N_AD13N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_CEC"] ;# Bank 49 VCCO - VCC3V3 - IO_L3N_AD13N_49 -#set_property PACKAGE_PIN B16 [get_ports "HDMI_TX_HPD"] ;# Bank 49 VCCO - VCC3V3 - IO_L3P_AD13P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_HPD"] ;# Bank 49 VCCO - VCC3V3 - IO_L3P_AD13P_49 -#set_property PACKAGE_PIN C16 [get_ports "HDMI_TX_SRC_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L2N_AD14N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_SRC_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L2N_AD14N_49 -#set_property PACKAGE_PIN D16 [get_ports "HDMI_TX_SRC_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L2P_AD14P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_SRC_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L2P_AD14P_49 -#set_property PACKAGE_PIN F15 [get_ports "HDMI_CTL_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L1N_AD15N_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_CTL_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L1N_AD15N_49 -#set_property PACKAGE_PIN F16 [get_ports "HDMI_CTL_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L1P_AD15P_49 -#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_CTL_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L1P_AD15P_49 -#set_property PACKAGE_PIN A18 [get_ports "TRACEDBGRQ"] ;# Bank 48 VCCO - VCC3V3 - IO_L12N_AD8N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDBGRQ"] ;# Bank 48 VCCO - VCC3V3 - IO_L12N_AD8N_48 -#set_property PACKAGE_PIN A17 [get_ports "TRACESRST_B"] ;# Bank 48 VCCO - VCC3V3 - IO_L12P_AD8P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACESRST_B"] ;# Bank 48 VCCO - VCC3V3 - IO_L12P_AD8P_48 -#set_property PACKAGE_PIN C19 [get_ports "TRACETDO"] ;# Bank 48 VCCO - VCC3V3 - IO_L11N_AD9N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETDO"] ;# Bank 48 VCCO - VCC3V3 - IO_L11N_AD9N_48 -#set_property PACKAGE_PIN C18 [get_ports "TRACERTCK"] ;# Bank 48 VCCO - VCC3V3 - IO_L11P_AD9P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACERTCK"] ;# Bank 48 VCCO - VCC3V3 - IO_L11P_AD9P_48 -#set_property PACKAGE_PIN B19 [get_ports "TRACETCK"] ;# Bank 48 VCCO - VCC3V3 - IO_L10N_AD10N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETCK"] ;# Bank 48 VCCO - VCC3V3 - IO_L10N_AD10N_48 -#set_property PACKAGE_PIN B18 [get_ports "TRACETMS"] ;# Bank 48 VCCO - VCC3V3 - IO_L10P_AD10P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETMS"] ;# Bank 48 VCCO - VCC3V3 - IO_L10P_AD10P_48 -#set_property PACKAGE_PIN C17 [get_ports "TRACETDI"] ;# Bank 48 VCCO - VCC3V3 - IO_L9N_AD11N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETDI"] ;# Bank 48 VCCO - VCC3V3 - IO_L9N_AD11N_48 -#set_property PACKAGE_PIN D17 [get_ports "TRACETRST_B"] ;# Bank 48 VCCO - VCC3V3 - IO_L9P_AD11P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETRST_B"] ;# Bank 48 VCCO - VCC3V3 - IO_L9P_AD11P_48 -#set_property PACKAGE_PIN E18 [get_ports "TRACEDATA15"] ;# Bank 48 VCCO - VCC3V3 - IO_L8N_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA15"] ;# Bank 48 VCCO - VCC3V3 - IO_L8N_HDGC_48 -#set_property PACKAGE_PIN E17 [get_ports "TRACEDATA14"] ;# Bank 48 VCCO - VCC3V3 - IO_L8P_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA14"] ;# Bank 48 VCCO - VCC3V3 - IO_L8P_HDGC_48 -#set_property PACKAGE_PIN D19 [get_ports "TRACEDATA13"] ;# Bank 48 VCCO - VCC3V3 - IO_L7N_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA13"] ;# Bank 48 VCCO - VCC3V3 - IO_L7N_HDGC_48 -#set_property PACKAGE_PIN E19 [get_ports "TRACEDATA12"] ;# Bank 48 VCCO - VCC3V3 - IO_L7P_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA12"] ;# Bank 48 VCCO - VCC3V3 - IO_L7P_HDGC_48 -#set_property PACKAGE_PIN F18 [get_ports "TRACEDATA11"] ;# Bank 48 VCCO - VCC3V3 - IO_L6N_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA11"] ;# Bank 48 VCCO - VCC3V3 - IO_L6N_HDGC_48 -#set_property PACKAGE_PIN F17 [get_ports "TRACEDATA10"] ;# Bank 48 VCCO - VCC3V3 - IO_L6P_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA10"] ;# Bank 48 VCCO - VCC3V3 - IO_L6P_HDGC_48 -#set_property PACKAGE_PIN G19 [get_ports "TRACEDATA9"] ;# Bank 48 VCCO - VCC3V3 - IO_L5N_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA9"] ;# Bank 48 VCCO - VCC3V3 - IO_L5N_HDGC_48 -#set_property PACKAGE_PIN G18 [get_ports "TRACEDATA8"] ;# Bank 48 VCCO - VCC3V3 - IO_L5P_HDGC_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA8"] ;# Bank 48 VCCO - VCC3V3 - IO_L5P_HDGC_48 -#set_property PACKAGE_PIN K17 [get_ports "TRACECLKA"] ;# Bank 48 VCCO - VCC3V3 - IO_L4N_AD12N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACECLKA"] ;# Bank 48 VCCO - VCC3V3 - IO_L4N_AD12N_48 -#set_property PACKAGE_PIN L17 [get_ports "TRACEDBGACK"] ;# Bank 48 VCCO - VCC3V3 - IO_L4P_AD12P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDBGACK"] ;# Bank 48 VCCO - VCC3V3 - IO_L4P_AD12P_48 -#set_property PACKAGE_PIN K18 [get_ports "TRACEEXTTRIG"] ;# Bank 48 VCCO - VCC3V3 - IO_L3N_AD13N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEEXTTRIG"] ;# Bank 48 VCCO - VCC3V3 - IO_L3N_AD13N_48 -#set_property PACKAGE_PIN L18 [get_ports "TRACEDATA7"] ;# Bank 48 VCCO - VCC3V3 - IO_L3P_AD13P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA7"] ;# Bank 48 VCCO - VCC3V3 - IO_L3P_AD13P_48 -#set_property PACKAGE_PIN H17 [get_ports "TRACEDATA6"] ;# Bank 48 VCCO - VCC3V3 - IO_L2N_AD14N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA6"] ;# Bank 48 VCCO - VCC3V3 - IO_L2N_AD14N_48 -#set_property PACKAGE_PIN J17 [get_ports "TRACEDATA5"] ;# Bank 48 VCCO - VCC3V3 - IO_L2P_AD14P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA5"] ;# Bank 48 VCCO - VCC3V3 - IO_L2P_AD14P_48 -#set_property PACKAGE_PIN H19 [get_ports "TRACEDATA4"] ;# Bank 48 VCCO - VCC3V3 - IO_L1N_AD15N_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA4"] ;# Bank 48 VCCO - VCC3V3 - IO_L1N_AD15N_48 -#set_property PACKAGE_PIN H18 [get_ports "TRACEDATA3"] ;# Bank 48 VCCO - VCC3V3 - IO_L1P_AD15P_48 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA3"] ;# Bank 48 VCCO - VCC3V3 - IO_L1P_AD15P_48 -#set_property PACKAGE_PIN A20 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 -#set_property PACKAGE_PIN B20 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 -#set_property PACKAGE_PIN A22 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 -#set_property PACKAGE_PIN A21 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 -#set_property PACKAGE_PIN B21 [get_ports "PMOD0_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47 -#set_property PACKAGE_PIN C21 [get_ports "PMOD0_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47 -#set_property PACKAGE_PIN C22 [get_ports "PMOD0_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47 -#set_property PACKAGE_PIN D21 [get_ports "PMOD0_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47 -set_property PACKAGE_PIN D20 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 -set_property PACKAGE_PIN E20 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 -set_property PACKAGE_PIN D22 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 -set_property PACKAGE_PIN E22 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_47 -#set_property PACKAGE_PIN F20 [get_ports "PMOD1_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_47 -#set_property PACKAGE_PIN G20 [get_ports "PMOD1_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_47 -#set_property PACKAGE_PIN F21 [get_ports "CLK_125_N"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -#set_property IOSTANDARD LVDS_25 [get_ports "CLK_125_N"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -#set_property PACKAGE_PIN G21 [get_ports "CLK_125_P"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 -#set_property IOSTANDARD LVDS_25 [get_ports "CLK_125_P"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 -#set_property PACKAGE_PIN J20 [get_ports "PMOD1_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L4N_AD8N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L4N_AD8N_47 -#set_property PACKAGE_PIN J19 [get_ports "PMOD1_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L4P_AD8P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L4P_AD8P_47 -#set_property PACKAGE_PIN H21 [get_ports "TRACEDATA2"] ;# Bank 47 VCCO - VCC3V3 - IO_L3N_AD9N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA2"] ;# Bank 47 VCCO - VCC3V3 - IO_L3N_AD9N_47 -#set_property PACKAGE_PIN J21 [get_ports "TRACEDATA1"] ;# Bank 47 VCCO - VCC3V3 - IO_L3P_AD9P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA1"] ;# Bank 47 VCCO - VCC3V3 - IO_L3P_AD9P_47 -#set_property PACKAGE_PIN K19 [get_ports "TRACECTL"] ;# Bank 47 VCCO - VCC3V3 - IO_L2N_AD10N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACECTL"] ;# Bank 47 VCCO - VCC3V3 - IO_L2N_AD10N_47 -#set_property PACKAGE_PIN L19 [get_ports "TRACEDATA0"] ;# Bank 47 VCCO - VCC3V3 - IO_L2P_AD10P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA0"] ;# Bank 47 VCCO - VCC3V3 - IO_L2P_AD10P_47 -#set_property PACKAGE_PIN K20 [get_ports "PL_I2C1_SCL_LS"] ;# Bank 47 VCCO - VCC3V3 - IO_L1N_AD11N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C1_SCL_LS"] ;# Bank 47 VCCO - VCC3V3 - IO_L1N_AD11N_47 -#set_property PACKAGE_PIN L20 [get_ports "PL_I2C1_SDA_LS"] ;# Bank 47 VCCO - VCC3V3 - IO_L1P_AD11P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C1_SDA_LS"] ;# Bank 47 VCCO - VCC3V3 - IO_L1P_AD11P_47 -#set_property PACKAGE_PIN AE14 [get_ports "GPIO_SW_E"] ;# Bank 44 VCCO - VCC3V3 - IO_L12N_AD0N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_E"] ;# Bank 44 VCCO - VCC3V3 - IO_L12N_AD0N_44 -#set_property PACKAGE_PIN AE15 [get_ports "GPIO_SW_S"] ;# Bank 44 VCCO - VCC3V3 - IO_L12P_AD0P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_S"] ;# Bank 44 VCCO - VCC3V3 - IO_L12P_AD0P_44 -#set_property PACKAGE_PIN AG15 [get_ports "GPIO_SW_N"] ;# Bank 44 VCCO - VCC3V3 - IO_L11N_AD1N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_N"] ;# Bank 44 VCCO - VCC3V3 - IO_L11N_AD1N_44 -#set_property PACKAGE_PIN AF15 [get_ports "GPIO_SW_W"] ;# Bank 44 VCCO - VCC3V3 - IO_L11P_AD1P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_W"] ;# Bank 44 VCCO - VCC3V3 - IO_L11P_AD1P_44 -#set_property PACKAGE_PIN AG13 [get_ports "GPIO_SW_C"] ;# Bank 44 VCCO - VCC3V3 - IO_L10N_AD2N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_C"] ;# Bank 44 VCCO - VCC3V3 - IO_L10N_AD2N_44 -#set_property PACKAGE_PIN AG14 [get_ports "GPIO_LED_0"] ;# Bank 44 VCCO - VCC3V3 - IO_L10P_AD2P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_0"] ;# Bank 44 VCCO - VCC3V3 - IO_L10P_AD2P_44 -#set_property PACKAGE_PIN AF13 [get_ports "GPIO_LED_1"] ;# Bank 44 VCCO - VCC3V3 - IO_L9N_AD3N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_1"] ;# Bank 44 VCCO - VCC3V3 - IO_L9N_AD3N_44 -#set_property PACKAGE_PIN AE13 [get_ports "GPIO_LED_2"] ;# Bank 44 VCCO - VCC3V3 - IO_L9P_AD3P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_2"] ;# Bank 44 VCCO - VCC3V3 - IO_L9P_AD3P_44 -#set_property PACKAGE_PIN AJ14 [get_ports "GPIO_LED_3"] ;# Bank 44 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_3"] ;# Bank 44 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_44 -#set_property PACKAGE_PIN AJ15 [get_ports "GPIO_LED_4"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_4"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44 -#set_property PACKAGE_PIN AH13 [get_ports "GPIO_LED_5"] ;# Bank 44 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_5"] ;# Bank 44 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_44 -#set_property PACKAGE_PIN AH14 [get_ports "GPIO_LED_6"] ;# Bank 44 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_6"] ;# Bank 44 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_44 -#set_property PACKAGE_PIN AL12 [get_ports "GPIO_LED_7"] ;# Bank 44 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_7"] ;# Bank 44 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_44 -#set_property PACKAGE_PIN AK13 [get_ports "GPIO_DIP_SW7"] ;# Bank 44 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW7"] ;# Bank 44 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_44 -#set_property PACKAGE_PIN AK14 [get_ports "CLK_74_25_N"] ;# Bank 44 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_44 -#set_property IOSTANDARD LVDS_25 [get_ports "CLK_74_25_N"] ;# Bank 44 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_44 -#set_property PACKAGE_PIN AK15 [get_ports "CLK_74_25_P"] ;# Bank 44 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_44 -#set_property IOSTANDARD LVDS_25 [get_ports "CLK_74_25_P"] ;# Bank 44 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_44 -set_property PACKAGE_PIN AM13 [get_ports "cpu_reset"] ;# Bank 44 VCCO - VCC3V3 - IO_L4N_AD8N_44 -set_property IOSTANDARD LVCMOS33 [get_ports "cpu_reset"] ;# Bank 44 VCCO - VCC3V3 - IO_L4N_AD8N_44 -#set_property PACKAGE_PIN AL13 [get_ports "GPIO_DIP_SW6"] ;# Bank 44 VCCO - VCC3V3 - IO_L4P_AD8P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW6"] ;# Bank 44 VCCO - VCC3V3 - IO_L4P_AD8P_44 -#set_property PACKAGE_PIN AP12 [get_ports "GPIO_DIP_SW5"] ;# Bank 44 VCCO - VCC3V3 - IO_L3N_AD9N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW5"] ;# Bank 44 VCCO - VCC3V3 - IO_L3N_AD9N_44 -#set_property PACKAGE_PIN AN12 [get_ports "GPIO_DIP_SW4"] ;# Bank 44 VCCO - VCC3V3 - IO_L3P_AD9P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW4"] ;# Bank 44 VCCO - VCC3V3 - IO_L3P_AD9P_44 -#set_property PACKAGE_PIN AN13 [get_ports "GPIO_DIP_SW3"] ;# Bank 44 VCCO - VCC3V3 - IO_L2N_AD10N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW3"] ;# Bank 44 VCCO - VCC3V3 - IO_L2N_AD10N_44 -#set_property PACKAGE_PIN AM14 [get_ports "GPIO_DIP_SW2"] ;# Bank 44 VCCO - VCC3V3 - IO_L2P_AD10P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW2"] ;# Bank 44 VCCO - VCC3V3 - IO_L2P_AD10P_44 -#set_property PACKAGE_PIN AP14 [get_ports "GPIO_DIP_SW1"] ;# Bank 44 VCCO - VCC3V3 - IO_L1N_AD11N_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW1"] ;# Bank 44 VCCO - VCC3V3 - IO_L1N_AD11N_44 -#set_property PACKAGE_PIN AN14 [get_ports "GPIO_DIP_SW0"] ;# Bank 44 VCCO - VCC3V3 - IO_L1P_AD11P_44 -#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW0"] ;# Bank 44 VCCO - VCC3V3 - IO_L1P_AD11P_44 -#set_property PACKAGE_PIN K15 [get_ports "FMC_HPC0_LA26_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L24N_T3U_N11_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA26_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L24N_T3U_N11_67 -#set_property PACKAGE_PIN L15 [get_ports "FMC_HPC0_LA26_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L24P_T3U_N10_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA26_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L24P_T3U_N10_67 -#set_property PACKAGE_PIN K13 [get_ports "FMC_HPC0_LA19_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L23N_T3U_N9_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA19_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L23N_T3U_N9_67 -#set_property PACKAGE_PIN L13 [get_ports "FMC_HPC0_LA19_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L23P_T3U_N8_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA19_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L23P_T3U_N8_67 -set_property PACKAGE_PIN M13 [get_ports "pad_hyper_dq[0][7]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_67 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][7]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_67 -set_property PACKAGE_PIN N13 [get_ports "pad_hyper_dq[0][6]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_67 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][6]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_67 -#set_property PACKAGE_PIN N12 [get_ports "FMC_HPC0_LA21_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA21_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_67 -#set_property PACKAGE_PIN P12 [get_ports "FMC_HPC0_LA21_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA21_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_67 -set_property PACKAGE_PIN M14 [get_ports "pad_hyper_csn[0][0]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_67 # J20 - 9 = gray -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0][0]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_67 -#set_property PACKAGE_PIN M15 [get_ports "FMC_HPC0_LA22_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA22_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_67 -#set_property PACKAGE_PIN K16 [get_ports "FMC_HPC0_LA23_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA23_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_67 -#set_property PACKAGE_PIN L16 [get_ports "FMC_HPC0_LA23_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA23_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_67 -#set_property PACKAGE_PIN K14 [get_ports "7N8557"] ;# Bank 67 VCCO - VADJ_FMC - IO_T3U_N12_67 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8557"] ;# Bank 67 VCCO - VADJ_FMC - IO_T3U_N12_67 -#set_property PACKAGE_PIN K10 [get_ports "7N8560"] ;# Bank 67 VCCO - VADJ_FMC - IO_T2U_N12_67 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8560"] ;# Bank 67 VCCO - VADJ_FMC - IO_T2U_N12_67 -#set_property PACKAGE_PIN K12 [get_ports "FMC_HPC0_LA24_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA24_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_67 -#set_property PACKAGE_PIN L12 [get_ports "FMC_HPC0_LA24_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA24_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_67 -#set_property PACKAGE_PIN L11 [get_ports "FMC_HPC0_LA25_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA25_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_67 -set_property PACKAGE_PIN M11 [get_ports "pad_hyper_reset[0]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_67 # J20 - 6 = violet -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_reset[0]"] ;# Bank 67 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_67 -#set_property PACKAGE_PIN N8 [get_ports "FMC_HPC0_LA18_CC_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA18_CC_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_67 -#set_property PACKAGE_PIN N9 [get_ports "FMC_HPC0_LA18_CC_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA18_CC_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_67 -#set_property PACKAGE_PIN L10 [get_ports "FMC_HPC0_LA27_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA27_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_67 -#set_property PACKAGE_PIN M10 [get_ports "FMC_HPC0_LA27_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA27_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_67 -#set_property PACKAGE_PIN P9 [get_ports "FMC_HPC1_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_67 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_67 -#set_property PACKAGE_PIN P10 [get_ports "FMC_HPC1_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_67 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_67 -#set_property PACKAGE_PIN N11 [get_ports "FMC_HPC0_LA17_CC_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA17_CC_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_67 -#set_property PACKAGE_PIN P11 [get_ports "FMC_HPC0_LA17_CC_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA17_CC_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_67 -#set_property PACKAGE_PIN R8 [get_ports "FMC_HPC0_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_67 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_67 -#set_property PACKAGE_PIN T8 [get_ports "FMC_HPC0_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_67 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_67 -#set_property PACKAGE_PIN R9 [get_ports "SFP_REC_CLOCK_C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67 -#set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67 -#set_property PACKAGE_PIN R10 [get_ports "SFP_REC_CLOCK_C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67 -#set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67 -#set_property PACKAGE_PIN T6 [get_ports "FMC_HPC0_LA28_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA28_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67 -#set_property PACKAGE_PIN T7 [get_ports "FMC_HPC0_LA28_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA28_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67 -#set_property PACKAGE_PIN U8 [get_ports "FMC_HPC0_LA29_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA29_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_67 -#set_property PACKAGE_PIN U9 [get_ports "FMC_HPC0_LA29_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA29_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_67 -#set_property PACKAGE_PIN U6 [get_ports "FMC_HPC0_LA30_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA30_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_67 -#set_property PACKAGE_PIN V6 [get_ports "FMC_HPC0_LA30_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA30_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_67 -#set_property PACKAGE_PIN V7 [get_ports "FMC_HPC0_LA31_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA31_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_67 -#set_property PACKAGE_PIN V8 [get_ports "FMC_HPC0_LA31_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA31_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_67 -#set_property PACKAGE_PIN V9 [get_ports "7N8563"] ;# Bank 67 VCCO - VADJ_FMC - IO_T1U_N12_67 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8563"] ;# Bank 67 VCCO - VADJ_FMC - IO_T1U_N12_67 -#set_property PACKAGE_PIN W10 [get_ports "7N8566"] ;# Bank 67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8566"] ;# Bank 67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67 -#set_property PACKAGE_PIN T11 [get_ports "FMC_HPC0_LA32_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA32_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_67 -#set_property PACKAGE_PIN U11 [get_ports "FMC_HPC0_LA32_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA32_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_67 -#set_property PACKAGE_PIN V11 [get_ports "FMC_HPC0_LA33_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA33_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_67 -#set_property PACKAGE_PIN V12 [get_ports "FMC_HPC0_LA33_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA33_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_67 -#set_property PACKAGE_PIN R12 [get_ports "FMC_HPC1_LA26_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA26_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67 -#set_property PACKAGE_PIN T12 [get_ports "FMC_HPC1_LA26_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA26_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67 -#set_property PACKAGE_PIN T10 [get_ports "FMC_HPC1_LA27_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA27_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67 -#set_property PACKAGE_PIN U10 [get_ports "FMC_HPC1_LA27_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA27_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67 -#set_property PACKAGE_PIN R13 [get_ports "FMC_HPC1_LA28_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA28_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67 -#set_property PACKAGE_PIN T13 [get_ports "FMC_HPC1_LA28_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA28_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67 -#set_property PACKAGE_PIN W11 [get_ports "FMC_HPC1_LA29_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA29_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67 -#set_property PACKAGE_PIN W12 [get_ports "FMC_HPC1_LA29_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA29_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67 -#Other net PACKAGE_PIN N14 - 7N8332 Bank 67 - VREF_67 -set_property PACKAGE_PIN W1 [get_ports "pad_hyper_dq[0][3]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L24N_T3U_N11_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][3]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L24N_T3U_N11_66 -set_property PACKAGE_PIN W2 [get_ports "pad_hyper_dq[0][2]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L24P_T3U_N10_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][2]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L24P_T3U_N10_66 -#set_property PACKAGE_PIN V1 [get_ports "FMC_HPC0_LA02_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L23N_T3U_N9_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA02_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L23N_T3U_N9_66 -set_property PACKAGE_PIN V2 [get_ports "pad_hyper_csn[0][1]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L23P_T3U_N8_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0][1]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L23P_T3U_N8_66 -#set_property PACKAGE_PIN Y1 [get_ports "FMC_HPC0_LA03_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA03_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_66 -#set_property PACKAGE_PIN Y2 [get_ports "FMC_HPC0_LA03_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA03_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_66 -#set_property PACKAGE_PIN AA1 [get_ports "FMC_HPC0_LA04_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA04_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_66 -#set_property PACKAGE_PIN AA2 [get_ports "FMC_HPC0_LA04_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA04_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_66 -set_property PACKAGE_PIN AC3 [get_ports "pad_hyper_dq[0][1]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][1]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_66 -set_property PACKAGE_PIN AB3 [get_ports "pad_hyper_dq[0][0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_66 -#set_property PACKAGE_PIN AC1 [get_ports "FMC_HPC0_LA06_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA06_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_66 -#set_property PACKAGE_PIN AC2 [get_ports "FMC_HPC0_LA06_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA06_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_66 -#set_property PACKAGE_PIN AB1 [get_ports "7N8545"] ;# Bank 66 VCCO - VADJ_FMC - IO_T3U_N12_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8545"] ;# Bank 66 VCCO - VADJ_FMC - IO_T3U_N12_66 -#set_property PACKAGE_PIN AA3 [get_ports "7N8548"] ;# Bank 66 VCCO - VADJ_FMC - IO_T2U_N12_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8548"] ;# Bank 66 VCCO - VADJ_FMC - IO_T2U_N12_66 -#set_property PACKAGE_PIN U4 [get_ports "FMC_HPC0_LA07_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA07_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_66 -#set_property PACKAGE_PIN U5 [get_ports "FMC_HPC0_LA07_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA07_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_66 -#set_property PACKAGE_PIN V3 [get_ports "FMC_HPC0_LA08_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA08_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_66 -#set_property PACKAGE_PIN V4 [get_ports "FMC_HPC0_LA08_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA08_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_66 -set_property PACKAGE_PIN AC4 [get_ports "pad_hyper_ckn[0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ckn[0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_66 -set_property PACKAGE_PIN AB4 [get_ports "pad_hyper_ck[0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ck[0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_66 -#set_property PACKAGE_PIN W4 [get_ports "FMC_HPC0_LA10_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA10_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_66 -#set_property PACKAGE_PIN W5 [get_ports "FMC_HPC0_LA10_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA10_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_66 -#set_property PACKAGE_PIN AA5 [get_ports "FMC_HPC1_LA17_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA17_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_66 -#set_property PACKAGE_PIN Y5 [get_ports "FMC_HPC1_LA17_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA17_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_66 -#set_property PACKAGE_PIN Y3 [get_ports "FMC_HPC0_LA00_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA00_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_66 -#set_property PACKAGE_PIN Y4 [get_ports "FMC_HPC0_LA00_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA00_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_66 -#set_property PACKAGE_PIN AA6 [get_ports "FMC_HPC0_CLK0_M2C_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_66 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK0_M2C_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_66 -#set_property PACKAGE_PIN AA7 [get_ports "FMC_HPC0_CLK0_M2C_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_66 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK0_M2C_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_66 -#set_property PACKAGE_PIN Y7 [get_ports "FMC_HPC1_LA18_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_66 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA18_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_66 -#set_property PACKAGE_PIN Y8 [get_ports "FMC_HPC1_LA18_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_66 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA18_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_66 -#set_property PACKAGE_PIN AB5 [get_ports "FMC_HPC0_LA11_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA11_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_66 -#set_property PACKAGE_PIN AB6 [get_ports "FMC_HPC0_LA11_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA11_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_66 -#set_property PACKAGE_PIN W6 [get_ports "FMC_HPC0_LA12_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA12_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_66 -#set_property PACKAGE_PIN W7 [get_ports "FMC_HPC0_LA12_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA12_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_66 -#set_property PACKAGE_PIN AC8 [get_ports "FMC_HPC0_LA13_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA13_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_66 -set_property PACKAGE_PIN AB8 [get_ports "pad_hyper_rwds[0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds[0]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_66 -#set_property PACKAGE_PIN AC6 [get_ports "FMC_HPC0_LA14_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA14_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_66 -#set_property PACKAGE_PIN AC7 [get_ports "FMC_HPC0_LA14_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA14_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_66 -#set_property PACKAGE_PIN AA8 [get_ports "7N8551"] ;# Bank 66 VCCO - VADJ_FMC - IO_T1U_N12_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8551"] ;# Bank 66 VCCO - VADJ_FMC - IO_T1U_N12_66 -#set_property PACKAGE_PIN W9 [get_ports "7N8554"] ;# Bank 66 VCCO - VADJ_FMC - IO_T0U_N12_VRP_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "7N8554"] ;# Bank 66 VCCO - VADJ_FMC - IO_T0U_N12_VRP_66 -#set_property PACKAGE_PIN Y9 [get_ports "FMC_HPC0_LA15_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA15_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_66 -#set_property PACKAGE_PIN Y10 [get_ports "FMC_HPC0_LA15_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA15_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_66 -set_property PACKAGE_PIN AA12 [get_ports "pad_hyper_dq[0][5]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][5]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_66 -set_property PACKAGE_PIN Y12 [get_ports "pad_hyper_dq[0][4]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_66 -set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][4]"] ;# Bank 66 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_66 -#set_property PACKAGE_PIN AC9 [get_ports "7N8645"] ;# Bank 66 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "7N8645"] ;# Bank 66 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_66 -#set_property PACKAGE_PIN AB9 [get_ports "7N8643"] ;# Bank 66 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "7N8643"] ;# Bank 66 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_66 -#set_property PACKAGE_PIN AA10 [get_ports "FMC_HPC1_LA19_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA19_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_66 -#set_property PACKAGE_PIN AA11 [get_ports "FMC_HPC1_LA19_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA19_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_66 -#set_property PACKAGE_PIN AB10 [get_ports "FMC_HPC1_LA20_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L2N_T0L_N3_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA20_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L2N_T0L_N3_66 -#set_property PACKAGE_PIN AB11 [get_ports "FMC_HPC1_LA20_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L2P_T0L_N2_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA20_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L2P_T0L_N2_66 -#set_property PACKAGE_PIN AC11 [get_ports "FMC_HPC1_LA21_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA21_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_66 -#set_property PACKAGE_PIN AC12 [get_ports "FMC_HPC1_LA21_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_66 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA21_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_66 -#Other net PACKAGE_PIN AD12 - 7N8282 Bank 66 - VREF_66 -#set_property PACKAGE_PIN AE1 [get_ports "FMC_HPC1_LA09_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L24N_T3U_N11_PERSTN0_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA09_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L24N_T3U_N11_PERSTN0_65 -#set_property PACKAGE_PIN AE2 [get_ports "FMC_HPC1_LA09_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA09_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 -#set_property PACKAGE_PIN AD1 [get_ports "FMC_HPC1_LA02_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L23N_T3U_N9_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA02_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L23N_T3U_N9_65 -#set_property PACKAGE_PIN AD2 [get_ports "FMC_HPC1_LA02_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L23P_T3U_N8_I2C_SCLK_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA02_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L23P_T3U_N8_I2C_SCLK_65 -#set_property PACKAGE_PIN AJ1 [get_ports "FMC_HPC1_LA03_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA03_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_65 -#set_property PACKAGE_PIN AH1 [get_ports "FMC_HPC1_LA03_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA03_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_65 -#set_property PACKAGE_PIN AF1 [get_ports "FMC_HPC1_LA04_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA04_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_65 -#set_property PACKAGE_PIN AF2 [get_ports "FMC_HPC1_LA04_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA04_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_65 -#set_property PACKAGE_PIN AH3 [get_ports "FMC_HPC1_LA05_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA05_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_65 -#set_property PACKAGE_PIN AG3 [get_ports "FMC_HPC1_LA05_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA05_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_65 -#set_property PACKAGE_PIN AJ2 [get_ports "FMC_HPC1_LA06_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA06_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_65 -#set_property PACKAGE_PIN AH2 [get_ports "FMC_HPC1_LA06_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA06_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_65 -#set_property PACKAGE_PIN AG1 [get_ports "6N9904"] ;# Bank 65 VCCO - VADJ_FMC - IO_T3U_N12_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "6N9904"] ;# Bank 65 VCCO - VADJ_FMC - IO_T3U_N12_65 -#set_property PACKAGE_PIN AD5 [get_ports "6N9901"] ;# Bank 65 VCCO - VADJ_FMC - IO_T2U_N12_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "6N9901"] ;# Bank 65 VCCO - VADJ_FMC - IO_T2U_N12_65 -#set_property PACKAGE_PIN AE4 [get_ports "FMC_HPC1_LA07_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA07_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_65 -#set_property PACKAGE_PIN AD4 [get_ports "FMC_HPC1_LA07_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA07_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_65 -#set_property PACKAGE_PIN AF3 [get_ports "FMC_HPC1_LA08_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA08_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_65 -#set_property PACKAGE_PIN AE3 [get_ports "FMC_HPC1_LA08_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA08_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_65 -#set_property PACKAGE_PIN AJ5 [get_ports "FMC_HPC1_LA01_CC_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA01_CC_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_65 -#set_property PACKAGE_PIN AJ6 [get_ports "FMC_HPC1_LA01_CC_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA01_CC_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_65 -#set_property PACKAGE_PIN AJ4 [get_ports "FMC_HPC1_LA10_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA10_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_65 -#set_property PACKAGE_PIN AH4 [get_ports "FMC_HPC1_LA10_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA10_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_65 -#set_property PACKAGE_PIN AG4 [get_ports "HDMI_REC_CLOCK_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "HDMI_REC_CLOCK_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_65 -#set_property PACKAGE_PIN AG5 [get_ports "HDMI_REC_CLOCK_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "HDMI_REC_CLOCK_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 -#set_property PACKAGE_PIN AF5 [get_ports "FMC_HPC1_LA00_CC_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA00_CC_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_65 -#set_property PACKAGE_PIN AE5 [get_ports "FMC_HPC1_LA00_CC_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA00_CC_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_65 -#set_property PACKAGE_PIN AF7 [get_ports "FMC_HPC1_CLK0_M2C_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_65 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_65 -#set_property PACKAGE_PIN AE7 [get_ports "FMC_HPC1_CLK0_M2C_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_65 -#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_65 -#set_property PACKAGE_PIN AG6 [get_ports "HDMI_TX_LVDS_OUT_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_65 -#set_property IOSTANDARD LVDS [get_ports "HDMI_TX_LVDS_OUT_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_65 -#set_property PACKAGE_PIN AF6 [get_ports "HDMI_TX_LVDS_OUT_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_65 -#set_property IOSTANDARD LVDS [get_ports "HDMI_TX_LVDS_OUT_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_65 -#set_property PACKAGE_PIN AF8 [get_ports "FMC_HPC1_LA11_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA11_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_65 -#set_property PACKAGE_PIN AE8 [get_ports "FMC_HPC1_LA11_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA11_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_65 -#set_property PACKAGE_PIN AD6 [get_ports "FMC_HPC1_LA12_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA12_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_65 -#set_property PACKAGE_PIN AD7 [get_ports "FMC_HPC1_LA12_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA12_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_65 -#set_property PACKAGE_PIN AH8 [get_ports "FMC_HPC1_LA13_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA13_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_65 -#set_property PACKAGE_PIN AG8 [get_ports "pad_hyper_rwds[0]"] ;# Bank 65 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds[0]"] ;# Bank 65 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_65 -#set_property PACKAGE_PIN AH6 [get_ports "FMC_HPC1_LA14_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA14_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_65 -#set_property PACKAGE_PIN AH7 [get_ports "FMC_HPC1_LA14_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA14_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_65 -#set_property PACKAGE_PIN AH9 [get_ports "DDR4_RESET_B_LS"] ;# Bank 65 VCCO - VADJ_FMC - IO_T1U_N12_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "DDR4_RESET_B_LS"] ;# Bank 65 VCCO - VADJ_FMC - IO_T1U_N12_65 -#set_property PACKAGE_PIN AD9 [get_ports "VRP_65"] ;# Bank 65 VCCO - VADJ_FMC - IO_T0U_N12_VRP_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_65"] ;# Bank 65 VCCO - VADJ_FMC - IO_T0U_N12_VRP_65 -#set_property PACKAGE_PIN AE9 [get_ports "FMC_HPC1_LA15_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA15_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_65 -#set_property PACKAGE_PIN AD10 [get_ports "FMC_HPC1_LA15_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA15_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_65 -#set_property PACKAGE_PIN AG9 [get_ports "FMC_HPC1_LA16_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA16_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_65 -#set_property PACKAGE_PIN AG10 [get_ports "FMC_HPC1_LA16_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA16_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_65 -#set_property PACKAGE_PIN AG11 [get_ports "FMC_HPC1_LA22_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA22_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_65 -#set_property PACKAGE_PIN AF11 [get_ports "FMC_HPC1_LA22_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA22_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 -#set_property PACKAGE_PIN AF12 [get_ports "FMC_HPC1_LA23_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA23_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_65 -#set_property PACKAGE_PIN AE12 [get_ports "FMC_HPC1_LA23_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA23_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_65 -#set_property PACKAGE_PIN AH11 [get_ports "FMC_HPC1_LA24_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L2N_T0L_N3_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA24_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L2N_T0L_N3_65 -#set_property PACKAGE_PIN AH12 [get_ports "FMC_HPC1_LA24_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L2P_T0L_N2_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA24_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L2P_T0L_N2_65 -#set_property PACKAGE_PIN AF10 [get_ports "FMC_HPC1_LA25_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA25_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_65 -#set_property PACKAGE_PIN AE10 [get_ports "FMC_HPC1_LA25_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_65 -#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA25_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_65 -#Other net PACKAGE_PIN AD11 - 6N9689 Bank 65 - VREF_65 -#set_property PACKAGE_PIN AK2 [get_ports "DDR4_DQ8"] ;# Bank 64 VCCO - VCC1V2 - IO_L24N_T3U_N11_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ8"] ;# Bank 64 VCCO - VCC1V2 - IO_L24N_T3U_N11_64 -#set_property PACKAGE_PIN AK3 [get_ports "DDR4_DQ9"] ;# Bank 64 VCCO - VCC1V2 - IO_L24P_T3U_N10_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ9"] ;# Bank 64 VCCO - VCC1V2 - IO_L24P_T3U_N10_64 -#set_property PACKAGE_PIN AL1 [get_ports "DDR4_DQ10"] ;# Bank 64 VCCO - VCC1V2 - IO_L23N_T3U_N9_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ10"] ;# Bank 64 VCCO - VCC1V2 - IO_L23N_T3U_N9_64 -#set_property PACKAGE_PIN AK1 [get_ports "DDR4_DQ11"] ;# Bank 64 VCCO - VCC1V2 - IO_L23P_T3U_N8_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ11"] ;# Bank 64 VCCO - VCC1V2 - IO_L23P_T3U_N8_64 -#set_property PACKAGE_PIN AL2 [get_ports "DDR4_DQS1_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L22N_T3U_N7_DBC_AD0N_64 -#set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS1_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L22N_T3U_N7_DBC_AD0N_64 -#set_property PACKAGE_PIN AL3 [get_ports "DDR4_DQS1_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L22P_T3U_N6_DBC_AD0P_64 -#set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS1_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L22P_T3U_N6_DBC_AD0P_64 -#set_property PACKAGE_PIN AN1 [get_ports "DDR4_DQ12"] ;# Bank 64 VCCO - VCC1V2 - IO_L21N_T3L_N5_AD8N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ12"] ;# Bank 64 VCCO - VCC1V2 - IO_L21N_T3L_N5_AD8N_64 -#set_property PACKAGE_PIN AM1 [get_ports "DDR4_DQ13"] ;# Bank 64 VCCO - VCC1V2 - IO_L21P_T3L_N4_AD8P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ13"] ;# Bank 64 VCCO - VCC1V2 - IO_L21P_T3L_N4_AD8P_64 -#set_property PACKAGE_PIN AP3 [get_ports "DDR4_DQ14"] ;# Bank 64 VCCO - VCC1V2 - IO_L20N_T3L_N3_AD1N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ14"] ;# Bank 64 VCCO - VCC1V2 - IO_L20N_T3L_N3_AD1N_64 -#set_property PACKAGE_PIN AN3 [get_ports "DDR4_DQ15"] ;# Bank 64 VCCO - VCC1V2 - IO_L20P_T3L_N2_AD1P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ15"] ;# Bank 64 VCCO - VCC1V2 - IO_L20P_T3L_N2_AD1P_64 -#set_property PACKAGE_PIN AP2 [get_ports "DDR4_CS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_CS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_64 -#set_property PACKAGE_PIN AN2 [get_ports "DDR4_DM1"] ;# Bank 64 VCCO - VCC1V2 - IO_L19P_T3L_N0_DBC_AD9P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM1"] ;# Bank 64 VCCO - VCC1V2 - IO_L19P_T3L_N0_DBC_AD9P_64 -#set_property PACKAGE_PIN AP1 [get_ports "DDR4_PAR"] ;# Bank 64 VCCO - VCC1V2 - IO_T3U_N12_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_PAR"] ;# Bank 64 VCCO - VCC1V2 - IO_T3U_N12_64 -#set_property PACKAGE_PIN AM3 [get_ports "DDR4_CKE"] ;# Bank 64 VCCO - VCC1V2 - IO_T2U_N12_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_CKE"] ;# Bank 64 VCCO - VCC1V2 - IO_T2U_N12_64 -#set_property PACKAGE_PIN AK4 [get_ports "DDR4_DQ0"] ;# Bank 64 VCCO - VCC1V2 - IO_L18N_T2U_N11_AD2N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ0"] ;# Bank 64 VCCO - VCC1V2 - IO_L18N_T2U_N11_AD2N_64 -#set_property PACKAGE_PIN AK5 [get_ports "DDR4_DQ1"] ;# Bank 64 VCCO - VCC1V2 - IO_L18P_T2U_N10_AD2P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ1"] ;# Bank 64 VCCO - VCC1V2 - IO_L18P_T2U_N10_AD2P_64 -#set_property PACKAGE_PIN AN4 [get_ports "DDR4_DQ2"] ;# Bank 64 VCCO - VCC1V2 - IO_L17N_T2U_N9_AD10N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ2"] ;# Bank 64 VCCO - VCC1V2 - IO_L17N_T2U_N9_AD10N_64 -#set_property PACKAGE_PIN AM4 [get_ports "DDR4_DQ3"] ;# Bank 64 VCCO - VCC1V2 - IO_L17P_T2U_N8_AD10P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ3"] ;# Bank 64 VCCO - VCC1V2 - IO_L17P_T2U_N8_AD10P_64 -#set_property PACKAGE_PIN AP6 [get_ports "DDR4_DQS0_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L16N_T2U_N7_QBC_AD3N_64 -#set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS0_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L16N_T2U_N7_QBC_AD3N_64 -#set_property PACKAGE_PIN AN6 [get_ports "DDR4_DQS0_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L16P_T2U_N6_QBC_AD3P_64 -#set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS0_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L16P_T2U_N6_QBC_AD3P_64 -#set_property PACKAGE_PIN AP4 [get_ports "DDR4_DQ4"] ;# Bank 64 VCCO - VCC1V2 - IO_L15N_T2L_N5_AD11N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ4"] ;# Bank 64 VCCO - VCC1V2 - IO_L15N_T2L_N5_AD11N_64 -#set_property PACKAGE_PIN AP5 [get_ports "DDR4_DQ5"] ;# Bank 64 VCCO - VCC1V2 - IO_L15P_T2L_N4_AD11P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ5"] ;# Bank 64 VCCO - VCC1V2 - IO_L15P_T2L_N4_AD11P_64 -#set_property PACKAGE_PIN AM5 [get_ports "DDR4_DQ6"] ;# Bank 64 VCCO - VCC1V2 - IO_L14N_T2L_N3_GC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ6"] ;# Bank 64 VCCO - VCC1V2 - IO_L14N_T2L_N3_GC_64 -#set_property PACKAGE_PIN AM6 [get_ports "DDR4_DQ7"] ;# Bank 64 VCCO - VCC1V2 - IO_L14P_T2L_N2_GC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ7"] ;# Bank 64 VCCO - VCC1V2 - IO_L14P_T2L_N2_GC_64 -#set_property PACKAGE_PIN AL5 [get_ports "DDR4_A15_CAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A15_CAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_64 -#set_property PACKAGE_PIN AL6 [get_ports "DDR4_DM0"] ;# Bank 64 VCCO - VCC1V2 - IO_L13P_T2L_N0_GC_QBC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM0"] ;# Bank 64 VCCO - VCC1V2 - IO_L13P_T2L_N0_GC_QBC_64 -#set_property PACKAGE_PIN AL7 [get_ports "USER_SI570_N"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_N"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 -#set_property PACKAGE_PIN AL8 [get_ports "USER_SI570_P"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_P"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 -#set_property PACKAGE_PIN AK7 [get_ports "DDR4_BG0"] ;# Bank 64 VCCO - VCC1V2 - IO_L11N_T1U_N9_GC_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BG0"] ;# Bank 64 VCCO - VCC1V2 - IO_L11N_T1U_N9_GC_64 -#set_property PACKAGE_PIN AK8 [get_ports "DDR4_ACT_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L11P_T1U_N8_GC_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ACT_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L11P_T1U_N8_GC_64 -#set_property PACKAGE_PIN AP7 [get_ports "DDR4_CK_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L10N_T1U_N7_QBC_AD4N_64 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CK_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L10N_T1U_N7_QBC_AD4N_64 -#set_property PACKAGE_PIN AN7 [get_ports "DDR4_CK_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CK_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 -#set_property PACKAGE_PIN AK9 [get_ports "DDR4_ODT"] ;# Bank 64 VCCO - VCC1V2 - IO_L9N_T1L_N5_AD12N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ODT"] ;# Bank 64 VCCO - VCC1V2 - IO_L9N_T1L_N5_AD12N_64 -#set_property PACKAGE_PIN AJ9 [get_ports "DDR4_A16_RAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L9P_T1L_N4_AD12P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A16_RAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L9P_T1L_N4_AD12P_64 -#set_property PACKAGE_PIN AM8 [get_ports "DDR4_A0"] ;# Bank 64 VCCO - VCC1V2 - IO_L8N_T1L_N3_AD5N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A0"] ;# Bank 64 VCCO - VCC1V2 - IO_L8N_T1L_N3_AD5N_64 -#set_property PACKAGE_PIN AM9 [get_ports "DDR4_A1"] ;# Bank 64 VCCO - VCC1V2 - IO_L8P_T1L_N2_AD5P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A1"] ;# Bank 64 VCCO - VCC1V2 - IO_L8P_T1L_N2_AD5P_64 -#set_property PACKAGE_PIN AP8 [get_ports "DDR4_A2"] ;# Bank 64 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A2"] ;# Bank 64 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_64 -#set_property PACKAGE_PIN AN8 [get_ports "DDR4_A3"] ;# Bank 64 VCCO - VCC1V2 - IO_L7P_T1L_N0_QBC_AD13P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A3"] ;# Bank 64 VCCO - VCC1V2 - IO_L7P_T1L_N0_QBC_AD13P_64 -#set_property PACKAGE_PIN AJ7 [get_ports "DDR4_A14_WE_B"] ;# Bank 64 VCCO - VCC1V2 - IO_T1U_N12_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A14_WE_B"] ;# Bank 64 VCCO - VCC1V2 - IO_T1U_N12_64 -#set_property PACKAGE_PIN AN11 [get_ports "VRP_64"] ;# Bank 64 VCCO - VCC1V2 - IO_T0U_N12_VRP_64 -#set_property IOSTANDARD [get_ports "VRP_64"] ;# Bank 64 VCCO - VCC1V2 - IO_T0U_N12_VRP_64 -#set_property PACKAGE_PIN AK10 [get_ports "DDR4_A4"] ;# Bank 64 VCCO - VCC1V2 - IO_L6N_T0U_N11_AD6N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A4"] ;# Bank 64 VCCO - VCC1V2 - IO_L6N_T0U_N11_AD6N_64 -#set_property PACKAGE_PIN AJ10 [get_ports "DDR4_A5"] ;# Bank 64 VCCO - VCC1V2 - IO_L6P_T0U_N10_AD6P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A5"] ;# Bank 64 VCCO - VCC1V2 - IO_L6P_T0U_N10_AD6P_64 -#set_property PACKAGE_PIN AP9 [get_ports "DDR4_A6"] ;# Bank 64 VCCO - VCC1V2 - IO_L5N_T0U_N9_AD14N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A6"] ;# Bank 64 VCCO - VCC1V2 - IO_L5N_T0U_N9_AD14N_64 -#set_property PACKAGE_PIN AN9 [get_ports "DDR4_A7"] ;# Bank 64 VCCO - VCC1V2 - IO_L5P_T0U_N8_AD14P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A7"] ;# Bank 64 VCCO - VCC1V2 - IO_L5P_T0U_N8_AD14P_64 -#set_property PACKAGE_PIN AP10 [get_ports "DDR4_A8"] ;# Bank 64 VCCO - VCC1V2 - IO_L4N_T0U_N7_DBC_AD7N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A8"] ;# Bank 64 VCCO - VCC1V2 - IO_L4N_T0U_N7_DBC_AD7N_64 -#set_property PACKAGE_PIN AP11 [get_ports "DDR4_A9"] ;# Bank 64 VCCO - VCC1V2 - IO_L4P_T0U_N6_DBC_AD7P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A9"] ;# Bank 64 VCCO - VCC1V2 - IO_L4P_T0U_N6_DBC_AD7P_64 -#set_property PACKAGE_PIN AM10 [get_ports "DDR4_A10"] ;# Bank 64 VCCO - VCC1V2 - IO_L3N_T0L_N5_AD15N_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A10"] ;# Bank 64 VCCO - VCC1V2 - IO_L3N_T0L_N5_AD15N_64 -#set_property PACKAGE_PIN AL10 [get_ports "DDR4_A11"] ;# Bank 64 VCCO - VCC1V2 - IO_L3P_T0L_N4_AD15P_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A11"] ;# Bank 64 VCCO - VCC1V2 - IO_L3P_T0L_N4_AD15P_64 -#set_property PACKAGE_PIN AM11 [get_ports "DDR4_A12"] ;# Bank 64 VCCO - VCC1V2 - IO_L2N_T0L_N3_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A12"] ;# Bank 64 VCCO - VCC1V2 - IO_L2N_T0L_N3_64 -#set_property PACKAGE_PIN AL11 [get_ports "DDR4_A13"] ;# Bank 64 VCCO - VCC1V2 - IO_L2P_T0L_N2_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A13"] ;# Bank 64 VCCO - VCC1V2 - IO_L2P_T0L_N2_64 -#set_property PACKAGE_PIN AK12 [get_ports "DDR4_BA0"] ;# Bank 64 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BA0"] ;# Bank 64 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_64 -#set_property PACKAGE_PIN AJ12 [get_ports "DDR4_BA1"] ;# Bank 64 VCCO - VCC1V2 - IO_L1P_T0L_N0_DBC_64 -#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BA1"] ;# Bank 64 VCCO - VCC1V2 - IO_L1P_T0L_N0_DBC_64 -#Other net PACKAGE_PIN AJ11 - 6N6772 Bank 64 - VREF_64 -#set_property PACKAGE_PIN T34 [get_ports "HDMI_RX0_C_N"] ;# Bank 128 - MGTHRXN0_128 -#set_property PACKAGE_PIN P34 [get_ports "HDMI_RX1_C_N"] ;# Bank 128 - MGTHRXN1_128 -#set_property PACKAGE_PIN N32 [get_ports "HDMI_RX2_C_N"] ;# Bank 128 - MGTHRXN2_128 -#set_property PACKAGE_PIN M34 [get_ports "SMA_MGT_RX_C_N"] ;# Bank 128 - MGTHRXN3_128 -#set_property PACKAGE_PIN T33 [get_ports "HDMI_RX0_C_P"] ;# Bank 128 - MGTHRXP0_128 -#set_property PACKAGE_PIN P33 [get_ports "HDMI_RX1_C_P"] ;# Bank 128 - MGTHRXP1_128 -#set_property PACKAGE_PIN N31 [get_ports "HDMI_RX2_C_P"] ;# Bank 128 - MGTHRXP2_128 -#set_property PACKAGE_PIN M33 [get_ports "SMA_MGT_RX_C_P"] ;# Bank 128 - MGTHRXP3_128 -#set_property PACKAGE_PIN T30 [get_ports "HDMI_TX0_N"] ;# Bank 128 - MGTHTXN0_128 -#set_property PACKAGE_PIN R32 [get_ports "HDMI_TX1_N"] ;# Bank 128 - MGTHTXN1_128 -#set_property PACKAGE_PIN P30 [get_ports "HDMI_TX2_N"] ;# Bank 128 - MGTHTXN2_128 -#set_property PACKAGE_PIN M30 [get_ports "SMA_MGT_TX_N"] ;# Bank 128 - MGTHTXN3_128 -#set_property PACKAGE_PIN T29 [get_ports "HDMI_TX0_P"] ;# Bank 128 - MGTHTXP0_128 -#set_property PACKAGE_PIN R31 [get_ports "HDMI_TX1_P"] ;# Bank 128 - MGTHTXP1_128 -#set_property PACKAGE_PIN P29 [get_ports "HDMI_TX2_P"] ;# Bank 128 - MGTHTXP2_128 -#set_property PACKAGE_PIN M29 [get_ports "SMA_MGT_TX_P"] ;# Bank 128 - MGTHTXP3_128 -#set_property PACKAGE_PIN N28 [get_ports "HDMI_RX_CLK_C_N"] ;# Bank 128 - MGTREFCLK1N_128 -#set_property PACKAGE_PIN N27 [get_ports "HDMI_RX_CLK_C_P"] ;# Bank 128 - MGTREFCLK1P_128 -#set_property PACKAGE_PIN R28 [get_ports "HDMI_SI5324_OUT_C_N"] ;# Bank 128 - MGTREFCLK0N_128 -#set_property PACKAGE_PIN R27 [get_ports "HDMI_SI5324_OUT_C_P"] ;# Bank 128 - MGTREFCLK0P_128 -#set_property PACKAGE_PIN A29 [get_ports "MGTRREF_128"] ;# Bank 128 - MGTRREF_L -#Other net PACKAGE_PIN A30 - MGTAVTT Bank 128 - MGTAVTTRCAL_L -#set_property PACKAGE_PIN L32 [get_ports "FMC_HPC1_DP4_M2C_N"] ;# Bank 129 - MGTHRXN0_129 -#set_property PACKAGE_PIN K34 [get_ports "FMC_HPC1_DP5_M2C_N"] ;# Bank 129 - MGTHRXN1_129 -#set_property PACKAGE_PIN H34 [get_ports "FMC_HPC1_DP6_M2C_N"] ;# Bank 129 - MGTHRXN2_129 -#set_property PACKAGE_PIN F34 [get_ports "FMC_HPC1_DP7_M2C_N"] ;# Bank 129 - MGTHRXN3_129 -#set_property PACKAGE_PIN L31 [get_ports "FMC_HPC1_DP4_M2C_P"] ;# Bank 129 - MGTHRXP0_129 -#set_property PACKAGE_PIN K33 [get_ports "FMC_HPC1_DP5_M2C_P"] ;# Bank 129 - MGTHRXP1_129 -#set_property PACKAGE_PIN H33 [get_ports "FMC_HPC1_DP6_M2C_P"] ;# Bank 129 - MGTHRXP2_129 -#set_property PACKAGE_PIN F33 [get_ports "FMC_HPC1_DP7_M2C_P"] ;# Bank 129 - MGTHRXP3_129 -#set_property PACKAGE_PIN K30 [get_ports "FMC_HPC1_DP4_C2M_N"] ;# Bank 129 - MGTHTXN0_129 -#set_property PACKAGE_PIN J32 [get_ports "FMC_HPC1_DP5_C2M_N"] ;# Bank 129 - MGTHTXN1_129 -#set_property PACKAGE_PIN H30 [get_ports "FMC_HPC1_DP6_C2M_N"] ;# Bank 129 - MGTHTXN2_129 -#set_property PACKAGE_PIN G32 [get_ports "FMC_HPC1_DP7_C2M_N"] ;# Bank 129 - MGTHTXN3_129 -#set_property PACKAGE_PIN K29 [get_ports "FMC_HPC1_DP4_C2M_P"] ;# Bank 129 - MGTHTXP0_129 -#set_property PACKAGE_PIN J31 [get_ports "FMC_HPC1_DP5_C2M_P"] ;# Bank 129 - MGTHTXP1_129 -#set_property PACKAGE_PIN H29 [get_ports "FMC_HPC1_DP6_C2M_P"] ;# Bank 129 - MGTHTXP2_129 -#set_property PACKAGE_PIN G31 [get_ports "FMC_HPC1_DP7_C2M_P"] ;# Bank 129 - MGTHTXP3_129 -#set_property PACKAGE_PIN J28 [get_ports "USER_SMA_MGT_CLOCK_C_N"] ;# Bank 129 - MGTREFCLK1N_129 -#set_property PACKAGE_PIN J27 [get_ports "USER_SMA_MGT_CLOCK_C_P"] ;# Bank 129 - MGTREFCLK1P_129 -#set_property PACKAGE_PIN L28 [get_ports "USER_MGT_SI570_CLOCK1_C_N"] ;# Bank 129 - MGTREFCLK0N_129 -#set_property PACKAGE_PIN L27 [get_ports "USER_MGT_SI570_CLOCK1_C_P"] ;# Bank 129 - MGTREFCLK0P_129 -#set_property PACKAGE_PIN E32 [get_ports "FMC_HPC1_DP0_M2C_N"] ;# Bank 130 - MGTHRXN0_130 -#set_property PACKAGE_PIN D34 [get_ports "FMC_HPC1_DP1_M2C_N"] ;# Bank 130 - MGTHRXN1_130 -#set_property PACKAGE_PIN C32 [get_ports "FMC_HPC1_DP2_M2C_N"] ;# Bank 130 - MGTHRXN2_130 -#set_property PACKAGE_PIN B34 [get_ports "FMC_HPC1_DP3_M2C_N"] ;# Bank 130 - MGTHRXN3_130 -#set_property PACKAGE_PIN E31 [get_ports "FMC_HPC1_DP0_M2C_P"] ;# Bank 130 - MGTHRXP0_130 -#set_property PACKAGE_PIN D33 [get_ports "FMC_HPC1_DP1_M2C_P"] ;# Bank 130 - MGTHRXP1_130 -#set_property PACKAGE_PIN C31 [get_ports "FMC_HPC1_DP2_M2C_P"] ;# Bank 130 - MGTHRXP2_130 -#set_property PACKAGE_PIN B33 [get_ports "FMC_HPC1_DP3_M2C_P"] ;# Bank 130 - MGTHRXP3_130 -#set_property PACKAGE_PIN F30 [get_ports "FMC_HPC1_DP0_C2M_N"] ;# Bank 130 - MGTHTXN0_130 -#set_property PACKAGE_PIN D30 [get_ports "FMC_HPC1_DP1_C2M_N"] ;# Bank 130 - MGTHTXN1_130 -#set_property PACKAGE_PIN B30 [get_ports "FMC_HPC1_DP2_C2M_N"] ;# Bank 130 - MGTHTXN2_130 -#set_property PACKAGE_PIN A32 [get_ports "FMC_HPC1_DP3_C2M_N"] ;# Bank 130 - MGTHTXN3_130 -#set_property PACKAGE_PIN F29 [get_ports "FMC_HPC1_DP0_C2M_P"] ;# Bank 130 - MGTHTXP0_130 -#set_property PACKAGE_PIN D29 [get_ports "FMC_HPC1_DP1_C2M_P"] ;# Bank 130 - MGTHTXP1_130 -#set_property PACKAGE_PIN B29 [get_ports "FMC_HPC1_DP2_C2M_P"] ;# Bank 130 - MGTHTXP2_130 -#set_property PACKAGE_PIN A31 [get_ports "FMC_HPC1_DP3_C2M_P"] ;# Bank 130 - MGTHTXP3_130 -#set_property PACKAGE_PIN G28 [get_ports "FMC_HPC1_GBTCLK0_M2C_C_N"] ;# Bank 130 - MGTREFCLK0N_130 -#set_property PACKAGE_PIN G27 [get_ports "FMC_HPC1_GBTCLK0_M2C_C_P"] ;# Bank 130 - MGTREFCLK0P_130 -#set_property PACKAGE_PIN E28 [get_ports "FMC_HPC1_GBTCLK1_M2C_C_N"] ;# Bank 130 - MGTREFCLK1N_130 -#set_property PACKAGE_PIN E27 [get_ports "FMC_HPC1_GBTCLK1_M2C_C_P"] ;# Bank 130 - MGTREFCLK1P_130 -#set_property PACKAGE_PIN T1 [get_ports "FMC_HPC0_DP6_M2C_N"] ;# Bank 228 - MGTHRXN0_228 -#set_property PACKAGE_PIN P1 [get_ports "FMC_HPC0_DP5_M2C_N"] ;# Bank 228 - MGTHRXN1_228 -#set_property PACKAGE_PIN M1 [get_ports "FMC_HPC0_DP7_M2C_N"] ;# Bank 228 - MGTHRXN2_228 -#set_property PACKAGE_PIN L3 [get_ports "FMC_HPC0_DP4_M2C_N"] ;# Bank 228 - MGTHRXN3_228 -#set_property PACKAGE_PIN T2 [get_ports "FMC_HPC0_DP6_M2C_P"] ;# Bank 228 - MGTHRXP0_228 -#set_property PACKAGE_PIN P2 [get_ports "FMC_HPC0_DP5_M2C_P"] ;# Bank 228 - MGTHRXP1_228 -#set_property PACKAGE_PIN M2 [get_ports "FMC_HPC0_DP7_M2C_P"] ;# Bank 228 - MGTHRXP2_228 -#set_property PACKAGE_PIN L4 [get_ports "FMC_HPC0_DP4_M2C_P"] ;# Bank 228 - MGTHRXP3_228 -#set_property PACKAGE_PIN R3 [get_ports "FMC_HPC0_DP6_C2M_N"] ;# Bank 228 - MGTHTXN0_228 -#set_property PACKAGE_PIN P5 [get_ports "FMC_HPC0_DP5_C2M_N"] ;# Bank 228 - MGTHTXN1_228 -#set_property PACKAGE_PIN N3 [get_ports "FMC_HPC0_DP7_C2M_N"] ;# Bank 228 - MGTHTXN2_228 -#set_property PACKAGE_PIN M5 [get_ports "FMC_HPC0_DP4_C2M_N"] ;# Bank 228 - MGTHTXN3_228 -#set_property PACKAGE_PIN R4 [get_ports "FMC_HPC0_DP6_C2M_P"] ;# Bank 228 - MGTHTXP0_228 -#set_property PACKAGE_PIN P6 [get_ports "FMC_HPC0_DP5_C2M_P"] ;# Bank 228 - MGTHTXP1_228 -#set_property PACKAGE_PIN N4 [get_ports "FMC_HPC0_DP7_C2M_P"] ;# Bank 228 - MGTHTXP2_228 -#set_property PACKAGE_PIN M6 [get_ports "FMC_HPC0_DP4_C2M_P"] ;# Bank 228 - MGTHTXP3_228 -#set_property PACKAGE_PIN J7 [get_ports "38N7145"] ;# Bank 228 - MGTREFCLK1N_228 -#set_property PACKAGE_PIN J8 [get_ports "38N7142"] ;# Bank 228 - MGTREFCLK1P_228 -#set_property PACKAGE_PIN L7 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_N"] ;# Bank 228 - MGTREFCLK0N_228 -#set_property PACKAGE_PIN L8 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_P"] ;# Bank 228 - MGTREFCLK0P_228 -#set_property PACKAGE_PIN A6 [get_ports "38N2099"] ;# Bank 228 - MGTRREF_R -#Other net PACKAGE_PIN A5 - MGTAVTT Bank 228 - MGTAVTTRCAL_R -#set_property PACKAGE_PIN K1 [get_ports "FMC_HPC0_DP3_M2C_N"] ;# Bank 229 - MGTHRXN0_229 -#set_property PACKAGE_PIN J3 [get_ports "FMC_HPC0_DP1_M2C_N"] ;# Bank 229 - MGTHRXN1_229 -#set_property PACKAGE_PIN H1 [get_ports "FMC_HPC0_DP0_M2C_N"] ;# Bank 229 - MGTHRXN2_229 -#set_property PACKAGE_PIN F1 [get_ports "FMC_HPC0_DP2_M2C_N"] ;# Bank 229 - MGTHRXN3_229 -#set_property PACKAGE_PIN K2 [get_ports "FMC_HPC0_DP3_M2C_P"] ;# Bank 229 - MGTHRXP0_229 -#set_property PACKAGE_PIN J4 [get_ports "FMC_HPC0_DP1_M2C_P"] ;# Bank 229 - MGTHRXP1_229 -#set_property PACKAGE_PIN H2 [get_ports "FMC_HPC0_DP0_M2C_P"] ;# Bank 229 - MGTHRXP2_229 -#set_property PACKAGE_PIN F2 [get_ports "FMC_HPC0_DP2_M2C_P"] ;# Bank 229 - MGTHRXP3_229 -#set_property PACKAGE_PIN K5 [get_ports "FMC_HPC0_DP3_C2M_N"] ;# Bank 229 - MGTHTXN0_229 -#set_property PACKAGE_PIN H5 [get_ports "FMC_HPC0_DP1_C2M_N"] ;# Bank 229 - MGTHTXN1_229 -#set_property PACKAGE_PIN G3 [get_ports "FMC_HPC0_DP0_C2M_N"] ;# Bank 229 - MGTHTXN2_229 -#set_property PACKAGE_PIN F5 [get_ports "FMC_HPC0_DP2_C2M_N"] ;# Bank 229 - MGTHTXN3_229 -#set_property PACKAGE_PIN K6 [get_ports "FMC_HPC0_DP3_C2M_P"] ;# Bank 229 - MGTHTXP0_229 -#set_property PACKAGE_PIN H6 [get_ports "FMC_HPC0_DP1_C2M_P"] ;# Bank 229 - MGTHTXP1_229 -#set_property PACKAGE_PIN G4 [get_ports "FMC_HPC0_DP0_C2M_P"] ;# Bank 229 - MGTHTXP2_229 -#set_property PACKAGE_PIN F6 [get_ports "FMC_HPC0_DP2_C2M_P"] ;# Bank 229 - MGTHTXP3_229 -#set_property PACKAGE_PIN E7 [get_ports "38N7165"] ;# Bank 229 - MGTREFCLK1N_229 -#set_property PACKAGE_PIN E8 [get_ports "38N7162"] ;# Bank 229 - MGTREFCLK1P_229 -#set_property PACKAGE_PIN G7 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_N"] ;# Bank 229 - MGTREFCLK0N_229 -#set_property PACKAGE_PIN G8 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_P"] ;# Bank 229 - MGTREFCLK0P_229 -#set_property PACKAGE_PIN D1 [get_ports "SFP0_RX_N"] ;# Bank 230 - MGTHRXN0_230 -#set_property PACKAGE_PIN C3 [get_ports "SFP1_RX_N"] ;# Bank 230 - MGTHRXN1_230 -#set_property PACKAGE_PIN B1 [get_ports "SFP2_RX_N"] ;# Bank 230 - MGTHRXN2_230 -#set_property PACKAGE_PIN A3 [get_ports "SFP3_RX_N"] ;# Bank 230 - MGTHRXN3_230 -#set_property PACKAGE_PIN D2 [get_ports "SFP0_RX_P"] ;# Bank 230 - MGTHRXP0_230 -#set_property PACKAGE_PIN C4 [get_ports "SFP1_RX_P"] ;# Bank 230 - MGTHRXP1_230 -#set_property PACKAGE_PIN B2 [get_ports "SFP2_RX_P"] ;# Bank 230 - MGTHRXP2_230 -#set_property PACKAGE_PIN A4 [get_ports "SFP3_RX_P"] ;# Bank 230 - MGTHRXP3_230 -#set_property PACKAGE_PIN E3 [get_ports "SFP0_TX_N"] ;# Bank 230 - MGTHTXN0_230 -#set_property PACKAGE_PIN D5 [get_ports "SFP1_TX_N"] ;# Bank 230 - MGTHTXN1_230 -#set_property PACKAGE_PIN B5 [get_ports "SFP2_TX_N"] ;# Bank 230 - MGTHTXN2_230 -#set_property PACKAGE_PIN A7 [get_ports "SFP3_TX_N"] ;# Bank 230 - MGTHTXN3_230 -#set_property PACKAGE_PIN E4 [get_ports "SFP0_TX_P"] ;# Bank 230 - MGTHTXP0_230 -#set_property PACKAGE_PIN D6 [get_ports "SFP1_TX_P"] ;# Bank 230 - MGTHTXP1_230 -#set_property PACKAGE_PIN B6 [get_ports "SFP2_TX_P"] ;# Bank 230 - MGTHTXP2_230 -#set_property PACKAGE_PIN A8 [get_ports "SFP3_TX_P"] ;# Bank 230 - MGTHTXP3_230 -#set_property PACKAGE_PIN C7 [get_ports "USER_MGT_SI570_CLOCK2_C_N"] ;# Bank 230 - MGTREFCLK0N_230 -#set_property PACKAGE_PIN C8 [get_ports "USER_MGT_SI570_CLOCK2_C_P"] ;# Bank 230 - MGTREFCLK0P_230 -#set_property PACKAGE_PIN B9 [get_ports "SFP_SI5328_OUT_C_N"] ;# Bank 230 - MGTREFCLK1N_230 -#set_property PACKAGE_PIN B10 [get_ports "SFP_SI5328_OUT_C_P"] ;# Bank 230 - MGTREFCLK1P_230 -################################################################################ -### PS Side -################################################################################ -#Other net PACKAGE_PIN AF16 - MIO0_QSPI_LWR_CLK Bank 500 - PS_MIO0 -#Other net PACKAGE_PIN AJ16 - MIO1_QSPI_LWR_DQ1 Bank 500 - PS_MIO1 -#Other net PACKAGE_PIN AD16 - MIO2_QSPI_LWR_DQ2 Bank 500 - PS_MIO2 -#Other net PACKAGE_PIN AG16 - MIO3_QSPI_LWR_DQ3 Bank 500 - PS_MIO3 -#Other net PACKAGE_PIN AH16 - MIO4_QSPI_LWR_DQ0 Bank 500 - PS_MIO4 -#Other net PACKAGE_PIN AM15 - MIO5_QSPI_LWR_CS_B Bank 500 - PS_MIO5 -#Other net PACKAGE_PIN AL15 - 53N6816 Bank 500 - PS_MIO6 -#Other net PACKAGE_PIN AD17 - MIO7_QSPI_UPR_CS_B Bank 500 - PS_MIO7 -#Other net PACKAGE_PIN AE17 - MIO8_QSPI_UPR_DQ0 Bank 500 - PS_MIO8 -#Other net PACKAGE_PIN AP15 - MIO9_QSPI_UPR_DQ1 Bank 500 - PS_MIO9 -#Other net PACKAGE_PIN AH17 - MIO10_QSPI_UPR_DQ2 Bank 500 - PS_MIO10 -#Other net PACKAGE_PIN AF17 - MIO11_QSPI_UPR_DQ3 Bank 500 - PS_MIO11 -#Other net PACKAGE_PIN AJ17 - MIO12_QSPI_UPR_CLK Bank 500 - PS_MIO12 -#Other net PACKAGE_PIN AK17 - MIO13PS_GPIO2 Bank 500 - PS_MIO13 -#Other net PACKAGE_PIN AL16 - MIO14_I2C0_SCL Bank 500 - PS_MIO14 -#Other net PACKAGE_PIN AN16 - MIO15_I2C0_SDA Bank 500 - PS_MIO15 -#Other net PACKAGE_PIN AM16 - MIO16_I2C1_SCL Bank 500 - PS_MIO16 -#Other net PACKAGE_PIN AP16 - MIO17_I2C1_SDA Bank 500 - PS_MIO17 -#Other net PACKAGE_PIN AE18 - MIO18_UART0_RXD Bank 500 - PS_MIO18 -#Other net PACKAGE_PIN AL17 - MIO19_UART0_TXD Bank 500 - PS_MIO19 -#Other net PACKAGE_PIN AD18 - MIO20_UART1_TXD Bank 500 - PS_MIO20 -#Other net PACKAGE_PIN AF18 - MIO21_UART1_RXD Bank 500 - PS_MIO21 -#Other net PACKAGE_PIN AD20 - MIO22_BUTTON Bank 500 - PS_MIO22 -#Other net PACKAGE_PIN AD19 - MIO23_LED Bank 500 - PS_MIO23 -#Other net PACKAGE_PIN AE20 - MIO24_CAN_TX Bank 500 - PS_MIO24 -#Other net PACKAGE_PIN AE19 - MIO25_CAN_RX Bank 500 - PS_MIO25 -#Other net PACKAGE_PIN P21 - MIO26_PMU_INPUT Bank 501 - PS_MIO26 -#Other net PACKAGE_PIN M21 - MIO27_DP_AUX_OUT Bank 501 - PS_MIO27 -#Other net PACKAGE_PIN N21 - MIO28_DP_HPD Bank 501 - PS_MIO28 -#Other net PACKAGE_PIN K22 - MIO29_DP_OE Bank 501 - PS_MIO29 -#Other net PACKAGE_PIN L21 - MIO30_DP_AUX_IN Bank 501 - PS_MIO30 -#Other net PACKAGE_PIN J22 - MIO31_PCIE_RESET_N Bank 501 - PS_MIO31 -#Other net PACKAGE_PIN H22 - MIO32_PMU_GPO0 Bank 501 - PS_MIO32 -#Other net PACKAGE_PIN H23 - MIO33_PMU_GPO1 Bank 501 - PS_MIO33 -#Other net PACKAGE_PIN L22 - MIO34_PMU_GPO2 Bank 501 - PS_MIO34 -#Other net PACKAGE_PIN P22 - MIO35_PMU_GPO3 Bank 501 - PS_MIO35 -#Other net PACKAGE_PIN K23 - MIO36_PMU_GPO4 Bank 501 - PS_MIO36 -#Other net PACKAGE_PIN N22 - MIO37_PMU_GPO5 Bank 501 - PS_MIO37 -#Other net PACKAGE_PIN L23 - MIO38_PS_GPIO1 Bank 501 - PS_MIO38 -#Other net PACKAGE_PIN N23 - MIO39_SDIO_SEL Bank 501 - PS_MIO39 -#Other net PACKAGE_PIN M23 - MIO40_SDIO_DIR_CMD Bank 501 - PS_MIO40 -#Other net PACKAGE_PIN J24 - MIO41_SDIO_DIR_DAT0 Bank 501 - PS_MIO41 -#Other net PACKAGE_PIN M24 - MIO42_SDIO_DIR_DAT1_3 Bank 501 - PS_MIO42 -#Other net PACKAGE_PIN K24 - 53N6798 Bank 501 - PS_MIO43 -#Other net PACKAGE_PIN N24 - MIO44_SDIO_PROTECT Bank 501 - PS_MIO44 -#Other net PACKAGE_PIN P24 - MIO45_SDIO_DETECT Bank 501 - PS_MIO45 -#Other net PACKAGE_PIN J25 - MIO46_SDIO_DAT0 Bank 501 - PS_MIO46 -#Other net PACKAGE_PIN L25 - MIO47_SDIO_DAT1 Bank 501 - PS_MIO47 -#Other net PACKAGE_PIN M25 - MIO48_SDIO_DAT2 Bank 501 - PS_MIO48 -#Other net PACKAGE_PIN K25 - MIO49_SDIO_DAT3 Bank 501 - PS_MIO49 -#Other net PACKAGE_PIN P25 - MIO50_SDIO_CMD Bank 501 - PS_MIO50 -#Other net PACKAGE_PIN N25 - MIO51_SDIO_CLK Bank 501 - PS_MIO51 -#Other net PACKAGE_PIN F22 - MIO52_USB_CLK Bank 502 - PS_MIO52 -#Other net PACKAGE_PIN E23 - MIO53_USB_DIR Bank 502 - PS_MIO53 -#Other net PACKAGE_PIN F23 - MIO54_USB_DATA2 Bank 502 - PS_MIO54 -#Other net PACKAGE_PIN B23 - MIO55_USB_NXT Bank 502 - PS_MIO55 -#Other net PACKAGE_PIN C23 - MIO56_USB_DATA0 Bank 502 - PS_MIO56 -#Other net PACKAGE_PIN A23 - MIO57_USB_DATA1 Bank 502 - PS_MIO57 -#Other net PACKAGE_PIN G23 - MIO58_USB_STP Bank 502 - PS_MIO58 -#Other net PACKAGE_PIN B24 - MIO59_USB_DATA3 Bank 502 - PS_MIO59 -#Other net PACKAGE_PIN E24 - MIO60_USB_DATA4 Bank 502 - PS_MIO60 -#Other net PACKAGE_PIN C24 - MIO61_USB_DATA5 Bank 502 - PS_MIO61 -#Other net PACKAGE_PIN G24 - MIO62_USB_DATA6 Bank 502 - PS_MIO62 -#Other net PACKAGE_PIN D24 - MIO63_USB_DATA7 Bank 502 - PS_MIO63 -#Other net PACKAGE_PIN A25 - MIO64_ENET_TX_CLK Bank 502 - PS_MIO64 -#Other net PACKAGE_PIN A26 - MIO65_ENET_TX_D0 Bank 502 - PS_MIO65 -#Other net PACKAGE_PIN A27 - MIO66_ENET_TX_D1 Bank 502 - PS_MIO66 -#Other net PACKAGE_PIN B25 - MIO67_ENET_TX_D2 Bank 502 - PS_MIO67 -#Other net PACKAGE_PIN B26 - MIO68_ENET_TX_D3 Bank 502 - PS_MIO68 -#Other net PACKAGE_PIN B27 - MIO69_ENET_TX_CTRL Bank 502 - PS_MIO69 -#Other net PACKAGE_PIN C26 - MIO70_ENET_RX_CLK Bank 502 - PS_MIO70 -#Other net PACKAGE_PIN C27 - MIO71_ENET_RX_D0 Bank 502 - PS_MIO71 -#Other net PACKAGE_PIN E25 - MIO72_ENET_RX_D1 Bank 502 - PS_MIO72 -#Other net PACKAGE_PIN H24 - MIO73_ENET_RX_D2 Bank 502 - PS_MIO73 -#Other net PACKAGE_PIN G25 - MIO74_ENET_RX_D3 Bank 502 - PS_MIO74 -#Other net PACKAGE_PIN D25 - MIO75_ENET_RX_CTRL Bank 502 - PS_MIO75 -#Other net PACKAGE_PIN H25 - MIO76_ENET_MDC Bank 502 - PS_MIO76 -#Other net PACKAGE_PIN F25 - MIO77_ENET_MDIO Bank 502 - PS_MIO77 -#Other net PACKAGE_PIN W21 - PS_DONE Bank 503 - PS_DONE -#Other net PACKAGE_PIN T21 - PS_ERR_OUT Bank 503 - PS_ERROR_OUT -#Other net PACKAGE_PIN R21 - PS_ERR_STATUS Bank 503 - PS_ERROR_STATUS -#Other net PACKAGE_PIN V24 - PS_INIT_B Bank 503 - PS_INIT_B -#Other net PACKAGE_PIN R25 - JTAG_TCK Bank 503 - PS_JTAG_TCK -#Other net PACKAGE_PIN U25 - JTAG_TDI Bank 503 - PS_JTAG_TDI -#Other net PACKAGE_PIN T25 - FPGA_TDO_FMC_TDI Bank 503 - PS_JTAG_TDO -#Other net PACKAGE_PIN R24 - JTAG_TMS Bank 503 - PS_JTAG_TMS -#Other net PACKAGE_PIN T22 - PS_MODE0 Bank 503 - PS_MODE0 -#Other net PACKAGE_PIN R22 - PS_MODE1 Bank 503 - PS_MODE1 -#Other net PACKAGE_PIN T23 - PS_MODE2 Bank 503 - PS_MODE2 -#Other net PACKAGE_PIN R23 - PS_MODE3 Bank 503 - PS_MODE3 -#Other net PACKAGE_PIN V21 - PS_PADI Bank 503 - PS_PADI -#Other net PACKAGE_PIN V22 - PS_PADO Bank 503 - PS_PADO -#Other net PACKAGE_PIN V23 - PS_POR_B Bank 503 - PS_POR_B -#Other net PACKAGE_PIN U21 - PS_PROG_B Bank 503 - PS_PROG_B -#Other net PACKAGE_PIN U24 - PS_REF_CLK Bank 503 - PS_REF_CLK -#Other net PACKAGE_PIN U23 - PS_SRST_B Bank 503 - PS_SRST_B -#Other net PACKAGE_PIN AP29 - DDR4_SODIMM_A0 Bank 504 - PS_DDR_A0 -#Other net PACKAGE_PIN AP30 - DDR4_SODIMM_A1 Bank 504 - PS_DDR_A1 -#Other net PACKAGE_PIN AL28 - DDR4_SODIMM_A10 Bank 504 - PS_DDR_A10 -#Other net PACKAGE_PIN AK27 - DDR4_SODIMM_A11 Bank 504 - PS_DDR_A11 -#Other net PACKAGE_PIN AJ25 - DDR4_SODIMM_A12 Bank 504 - PS_DDR_A12 -#Other net PACKAGE_PIN AL25 - DDR4_SODIMM_A13 Bank 504 - PS_DDR_A13 -#Other net PACKAGE_PIN AK25 - DDR4_SODIMM_WE_B Bank 504 - PS_DDR_A14 -#Other net PACKAGE_PIN AK24 - DDR4_SODIMM_CAS_B Bank 504 - PS_DDR_A15 -#Other net PACKAGE_PIN AM24 - DDR4_SODIMM_RAS_B Bank 504 - PS_DDR_A16 -#Other net PACKAGE_PIN AF25 - 68N6692 Bank 504 - PS_DDR_A17 -#Other net PACKAGE_PIN AP26 - DDR4_SODIMM_A2 Bank 504 - PS_DDR_A2 -#Other net PACKAGE_PIN AP27 - DDR4_SODIMM_A3 Bank 504 - PS_DDR_A3 -#Other net PACKAGE_PIN AP25 - DDR4_SODIMM_A4 Bank 504 - PS_DDR_A4 -#Other net PACKAGE_PIN AN24 - DDR4_SODIMM_A5 Bank 504 - PS_DDR_A5 -#Other net PACKAGE_PIN AM29 - DDR4_SODIMM_A6 Bank 504 - PS_DDR_A6 -#Other net PACKAGE_PIN AM28 - DDR4_SODIMM_A7 Bank 504 - PS_DDR_A7 -#Other net PACKAGE_PIN AM26 - DDR4_SODIMM_A8 Bank 504 - PS_DDR_A8 -#Other net PACKAGE_PIN AM25 - DDR4_SODIMM_A9 Bank 504 - PS_DDR_A9 -#Other net PACKAGE_PIN AG25 - DDR4_SODIMM_ACT_B Bank 504 - PS_DDR_ACT_N -#Other net PACKAGE_PIN AF22 - DDR4_SODIMM_ALERT_B Bank 504 - PS_DDR_ALERT_N -#Other net PACKAGE_PIN AH26 - DDR4_SODIMM_BA0 Bank 504 - PS_DDR_BA0 -#Other net PACKAGE_PIN AG26 - DDR4_SODIMM_BA1 Bank 504 - PS_DDR_BA1 -#Other net PACKAGE_PIN AK28 - DDR4_SODIMM_BG0 Bank 504 - PS_DDR_BG0 -#Other net PACKAGE_PIN AH27 - DDR4_SODIMM_BG1 Bank 504 - PS_DDR_BG1 -#Other net PACKAGE_PIN AN27 - DDR4_SODIMM_CK0_C Bank 504 - PS_DDR_CK_N0 -#Other net PACKAGE_PIN AL27 - DDR4_SODIMM_CK1_C Bank 504 - PS_DDR_CK_N1 -#Other net PACKAGE_PIN AN26 - DDR4_SODIMM_CK0_T Bank 504 - PS_DDR_CK0 -#Other net PACKAGE_PIN AL26 - DDR4_SODIMM_CK1_T Bank 504 - PS_DDR_CK1 -#Other net PACKAGE_PIN AN29 - DDR4_SODIMM_CKE0 Bank 504 - PS_DDR_CKE0 -#Other net PACKAGE_PIN AJ27 - DDR4_SODIMM_CKE1 Bank 504 - PS_DDR_CKE1 -#Other net PACKAGE_PIN AN28 - DDR4_SODIMM_CS0_B Bank 504 - PS_DDR_CS_N0 -#Other net PACKAGE_PIN AL30 - DDR4_SODIMM_CS1_B Bank 504 - PS_DDR_CS_N1 -#Other net PACKAGE_PIN AN17 - DDR4_SODIMM_DM0_B Bank 504 - PS_DDR_DM0 -#Other net PACKAGE_PIN AM21 - DDR4_SODIMM_DM1_B Bank 504 - PS_DDR_DM1 -#Other net PACKAGE_PIN AK19 - DDR4_SODIMM_DM2_B Bank 504 - PS_DDR_DM2 -#Other net PACKAGE_PIN AH24 - DDR4_SODIMM_DM3_B Bank 504 - PS_DDR_DM3 -#Other net PACKAGE_PIN AH31 - DDR4_SODIMM_DM4_B Bank 504 - PS_DDR_DM4 -#Other net PACKAGE_PIN AE30 - DDR4_SODIMM_DM5_B Bank 504 - PS_DDR_DM5 -#Other net PACKAGE_PIN AJ31 - DDR4_SODIMM_DM6_B Bank 504 - PS_DDR_DM6 -#Other net PACKAGE_PIN AE34 - DDR4_SODIMM_DM7_B Bank 504 - PS_DDR_DM7 -#Other net PACKAGE_PIN AN34 - DDR4_SODIMM_DM8_B Bank 504 - PS_DDR_DM8 -#Other net PACKAGE_PIN AP20 - DDR4_SODIMM_DQ0 Bank 504 - PS_DDR_DQ0 -#Other net PACKAGE_PIN AP18 - DDR4_SODIMM_DQ1 Bank 504 - PS_DDR_DQ1 -#Other net PACKAGE_PIN AP19 - DDR4_SODIMM_DQ2 Bank 504 - PS_DDR_DQ2 -#Other net PACKAGE_PIN AP17 - DDR4_SODIMM_DQ3 Bank 504 - PS_DDR_DQ3 -#Other net PACKAGE_PIN AM20 - DDR4_SODIMM_DQ4 Bank 504 - PS_DDR_DQ4 -#Other net PACKAGE_PIN AM19 - DDR4_SODIMM_DQ5 Bank 504 - PS_DDR_DQ5 -#Other net PACKAGE_PIN AM18 - DDR4_SODIMM_DQ6 Bank 504 - PS_DDR_DQ6 -#Other net PACKAGE_PIN AL18 - DDR4_SODIMM_DQ7 Bank 504 - PS_DDR_DQ7 -#Other net PACKAGE_PIN AP22 - DDR4_SODIMM_DQ8 Bank 504 - PS_DDR_DQ8 -#Other net PACKAGE_PIN AP21 - DDR4_SODIMM_DQ9 Bank 504 - PS_DDR_DQ9 -#Other net PACKAGE_PIN AP24 - DDR4_SODIMM_DQ10 Bank 504 - PS_DDR_DQ10 -#Other net PACKAGE_PIN AN23 - DDR4_SODIMM_DQ11 Bank 504 - PS_DDR_DQ11 -#Other net PACKAGE_PIN AL21 - DDR4_SODIMM_DQ12 Bank 504 - PS_DDR_DQ12 -#Other net PACKAGE_PIN AL22 - DDR4_SODIMM_DQ13 Bank 504 - PS_DDR_DQ13 -#Other net PACKAGE_PIN AM23 - DDR4_SODIMM_DQ14 Bank 504 - PS_DDR_DQ14 -#Other net PACKAGE_PIN AL23 - DDR4_SODIMM_DQ15 Bank 504 - PS_DDR_DQ15 -#Other net PACKAGE_PIN AL20 - DDR4_SODIMM_DQ16 Bank 504 - PS_DDR_DQ16 -#Other net PACKAGE_PIN AK20 - DDR4_SODIMM_DQ17 Bank 504 - PS_DDR_DQ17 -#Other net PACKAGE_PIN AJ20 - DDR4_SODIMM_DQ18 Bank 504 - PS_DDR_DQ18 -#Other net PACKAGE_PIN AK18 - DDR4_SODIMM_DQ19 Bank 504 - PS_DDR_DQ19 -#Other net PACKAGE_PIN AG20 - DDR4_SODIMM_DQ20 Bank 504 - PS_DDR_DQ20 -#Other net PACKAGE_PIN AH18 - DDR4_SODIMM_DQ21 Bank 504 - PS_DDR_DQ21 -#Other net PACKAGE_PIN AG19 - DDR4_SODIMM_DQ22 Bank 504 - PS_DDR_DQ22 -#Other net PACKAGE_PIN AG18 - DDR4_SODIMM_DQ23 Bank 504 - PS_DDR_DQ23 -#Other net PACKAGE_PIN AG21 - DDR4_SODIMM_DQ24 Bank 504 - PS_DDR_DQ24 -#Other net PACKAGE_PIN AH21 - DDR4_SODIMM_DQ25 Bank 504 - PS_DDR_DQ25 -#Other net PACKAGE_PIN AG24 - DDR4_SODIMM_DQ26 Bank 504 - PS_DDR_DQ26 -#Other net PACKAGE_PIN AG23 - DDR4_SODIMM_DQ27 Bank 504 - PS_DDR_DQ27 -#Other net PACKAGE_PIN AK22 - DDR4_SODIMM_DQ28 Bank 504 - PS_DDR_DQ28 -#Other net PACKAGE_PIN AJ21 - DDR4_SODIMM_DQ29 Bank 504 - PS_DDR_DQ29 -#Other net PACKAGE_PIN AJ22 - DDR4_SODIMM_DQ30 Bank 504 - PS_DDR_DQ30 -#Other net PACKAGE_PIN AK23 - DDR4_SODIMM_DQ31 Bank 504 - PS_DDR_DQ31 -#Other net PACKAGE_PIN AG31 - DDR4_SODIMM_DQ32 Bank 504 - PS_DDR_DQ32 -#Other net PACKAGE_PIN AG30 - DDR4_SODIMM_DQ33 Bank 504 - PS_DDR_DQ33 -#Other net PACKAGE_PIN AG29 - DDR4_SODIMM_DQ34 Bank 504 - PS_DDR_DQ34 -#Other net PACKAGE_PIN AG28 - DDR4_SODIMM_DQ35 Bank 504 - PS_DDR_DQ35 -#Other net PACKAGE_PIN AJ30 - DDR4_SODIMM_DQ36 Bank 504 - PS_DDR_DQ36 -#Other net PACKAGE_PIN AK29 - DDR4_SODIMM_DQ37 Bank 504 - PS_DDR_DQ37 -#Other net PACKAGE_PIN AK30 - DDR4_SODIMM_DQ38 Bank 504 - PS_DDR_DQ38 -#Other net PACKAGE_PIN AJ29 - DDR4_SODIMM_DQ39 Bank 504 - PS_DDR_DQ39 -#Other net PACKAGE_PIN AE27 - DDR4_SODIMM_DQ40 Bank 504 - PS_DDR_DQ40 -#Other net PACKAGE_PIN AF28 - DDR4_SODIMM_DQ41 Bank 504 - PS_DDR_DQ41 -#Other net PACKAGE_PIN AF30 - DDR4_SODIMM_DQ42 Bank 504 - PS_DDR_DQ42 -#Other net PACKAGE_PIN AF31 - DDR4_SODIMM_DQ43 Bank 504 - PS_DDR_DQ43 -#Other net PACKAGE_PIN AD28 - DDR4_SODIMM_DQ44 Bank 504 - PS_DDR_DQ44 -#Other net PACKAGE_PIN AD27 - DDR4_SODIMM_DQ45 Bank 504 - PS_DDR_DQ45 -#Other net PACKAGE_PIN AD29 - DDR4_SODIMM_DQ46 Bank 504 - PS_DDR_DQ46 -#Other net PACKAGE_PIN AD30 - DDR4_SODIMM_DQ47 Bank 504 - PS_DDR_DQ47 -#Other net PACKAGE_PIN AH33 - DDR4_SODIMM_DQ48 Bank 504 - PS_DDR_DQ48 -#Other net PACKAGE_PIN AJ34 - DDR4_SODIMM_DQ49 Bank 504 - PS_DDR_DQ49 -#Other net PACKAGE_PIN AH34 - DDR4_SODIMM_DQ50 Bank 504 - PS_DDR_DQ50 -#Other net PACKAGE_PIN AH32 - DDR4_SODIMM_DQ51 Bank 504 - PS_DDR_DQ51 -#Other net PACKAGE_PIN AK34 - DDR4_SODIMM_DQ52 Bank 504 - PS_DDR_DQ52 -#Other net PACKAGE_PIN AK33 - DDR4_SODIMM_DQ53 Bank 504 - PS_DDR_DQ53 -#Other net PACKAGE_PIN AL32 - DDR4_SODIMM_DQ54 Bank 504 - PS_DDR_DQ54 -#Other net PACKAGE_PIN AL31 - DDR4_SODIMM_DQ55 Bank 504 - PS_DDR_DQ55 -#Other net PACKAGE_PIN AG33 - DDR4_SODIMM_DQ56 Bank 504 - PS_DDR_DQ56 -#Other net PACKAGE_PIN AG34 - DDR4_SODIMM_DQ57 Bank 504 - PS_DDR_DQ57 -#Other net PACKAGE_PIN AF32 - DDR4_SODIMM_DQ58 Bank 504 - PS_DDR_DQ58 -#Other net PACKAGE_PIN AF33 - DDR4_SODIMM_DQ59 Bank 504 - PS_DDR_DQ59 -#Other net PACKAGE_PIN AD31 - DDR4_SODIMM_DQ60 Bank 504 - PS_DDR_DQ60 -#Other net PACKAGE_PIN AD32 - DDR4_SODIMM_DQ61 Bank 504 - PS_DDR_DQ61 -#Other net PACKAGE_PIN AD34 - DDR4_SODIMM_DQ62 Bank 504 - PS_DDR_DQ62 -#Other net PACKAGE_PIN AD33 - DDR4_SODIMM_DQ63 Bank 504 - PS_DDR_DQ63 -#Other net PACKAGE_PIN AN31 - DDR4_SODIMM_CB0 Bank 504 - PS_DDR_DQ64 -#Other net PACKAGE_PIN AP31 - DDR4_SODIMM_CB1 Bank 504 - PS_DDR_DQ65 -#Other net PACKAGE_PIN AP32 - DDR4_SODIMM_CB2 Bank 504 - PS_DDR_DQ66 -#Other net PACKAGE_PIN AP33 - DDR4_SODIMM_CB3 Bank 504 - PS_DDR_DQ67 -#Other net PACKAGE_PIN AM31 - DDR4_SODIMM_CB4 Bank 504 - PS_DDR_DQ68 -#Other net PACKAGE_PIN AM33 - DDR4_SODIMM_CB5 Bank 504 - PS_DDR_DQ69 -#Other net PACKAGE_PIN AM34 - DDR4_SODIMM_CB6 Bank 504 - PS_DDR_DQ70 -#Other net PACKAGE_PIN AL33 - DDR4_SODIMM_CB7 Bank 504 - PS_DDR_DQ71 -#Other net PACKAGE_PIN AN19 - DDR4_SODIMM_DQS0_C Bank 504 - PS_DDR_DQS_N0 -#Other net PACKAGE_PIN AN22 - DDR4_SODIMM_DQS1_C Bank 504 - PS_DDR_DQS_N1 -#Other net PACKAGE_PIN AJ19 - DDR4_SODIMM_DQS2_C Bank 504 - PS_DDR_DQS_N2 -#Other net PACKAGE_PIN AH23 - DDR4_SODIMM_DQS3_C Bank 504 - PS_DDR_DQS_N3 -#Other net PACKAGE_PIN AH29 - DDR4_SODIMM_DQS4_C Bank 504 - PS_DDR_DQS_N4 -#Other net PACKAGE_PIN AE29 - DDR4_SODIMM_DQS5_C Bank 504 - PS_DDR_DQS_N5 -#Other net PACKAGE_PIN AK32 - DDR4_SODIMM_DQS6_C Bank 504 - PS_DDR_DQS_N6 -#Other net PACKAGE_PIN AE33 - DDR4_SODIMM_DQS7_C Bank 504 - PS_DDR_DQS_N7 -#Other net PACKAGE_PIN AN33 - DDR4_SODIMM_DQS8_C Bank 504 - PS_DDR_DQS_N8 -#Other net PACKAGE_PIN AN18 - DDR4_SODIMM_DQS0_T Bank 504 - PS_DDR_DQS_P0 -#Other net PACKAGE_PIN AN21 - DDR4_SODIMM_DQS1_T Bank 504 - PS_DDR_DQS_P1 -#Other net PACKAGE_PIN AH19 - DDR4_SODIMM_DQS2_T Bank 504 - PS_DDR_DQS_P2 -#Other net PACKAGE_PIN AH22 - DDR4_SODIMM_DQS3_T Bank 504 - PS_DDR_DQS_P3 -#Other net PACKAGE_PIN AH28 - DDR4_SODIMM_DQS4_T Bank 504 - PS_DDR_DQS_P4 -#Other net PACKAGE_PIN AE28 - DDR4_SODIMM_DQS5_T Bank 504 - PS_DDR_DQS_P5 -#Other net PACKAGE_PIN AJ32 - DDR4_SODIMM_DQS6_T Bank 504 - PS_DDR_DQS_P6 -#Other net PACKAGE_PIN AE32 - DDR4_SODIMM_DQS7_T Bank 504 - PS_DDR_DQS_P7 -#Other net PACKAGE_PIN AN32 - DDR4_SODIMM_DQS8_T Bank 504 - PS_DDR_DQS_P8 -#Other net PACKAGE_PIN AM30 - DDR4_SODIMM_ODT0 Bank 504 - PS_DDR_ODT0 -#Other net PACKAGE_PIN AJ26 - DDR4_SODIMM_ODT1 Bank 504 - PS_DDR_ODT1 -#Other net PACKAGE_PIN AF20 - DDR4_SODIMM_PARITY Bank 504 - PS_DDR_PARITY -#Other net PACKAGE_PIN AF21 - ZYNQ_DDR4_SODIMM_RESET_B Bank 504 - PS_DDR_RAM_RST_N -#Other net PACKAGE_PIN AF23 - UDIMM_PS_ZQ Bank 504 - PS_DDR_ZQ -#Other net PACKAGE_PIN AF27 - 68N6670 Bank 504 - PS_SENSE_DDRPHY_VREF_N -#Other net PACKAGE_PIN AF26 - 68N6673 Bank 504 - PS_SENSE_DDRPHY_VREF_P -#Other net PACKAGE_PIN AB34 - GTR_LANE0_RX_N Bank 505 - PS_MGTRRXN0_505 -#Other net PACKAGE_PIN AA32 - GTR_LANE1_RX_N Bank 505 - PS_MGTRRXN1_505 -#Other net PACKAGE_PIN Y34 - GTR_LANE2_RX_N Bank 505 - PS_MGTRRXN2_505 -#Other net PACKAGE_PIN V34 - GTR_LANE3_RX_N Bank 505 - PS_MGTRRXN3_505 -#Other net PACKAGE_PIN AB33 - GTR_LANE0_RX_P Bank 505 - PS_MGTRRXP0_505 -#Other net PACKAGE_PIN AA31 - GTR_LANE1_RX_P Bank 505 - PS_MGTRRXP1_505 -#Other net PACKAGE_PIN Y33 - GTR_LANE2_RX_P Bank 505 - PS_MGTRRXP2_505 -#Other net PACKAGE_PIN V33 - GTR_LANE3_RX_P Bank 505 - PS_MGTRRXP3_505 -#Other net PACKAGE_PIN AB30 - GTR_LANE0_TX_N Bank 505 - PS_MGTRTXN0_505 -#Other net PACKAGE_PIN Y30 - GTR_LANE1_TX_N Bank 505 - PS_MGTRTXN1_505 -#Other net PACKAGE_PIN W32 - GTR_LANE2_TX_N Bank 505 - PS_MGTRTXN2_505 -#Other net PACKAGE_PIN V30 - GTR_LANE3_TX_N Bank 505 - PS_MGTRTXN3_505 -#Other net PACKAGE_PIN AB29 - GTR_LANE0_TX_P Bank 505 - PS_MGTRTXP0_505 -#Other net PACKAGE_PIN Y29 - GTR_LANE1_TX_P Bank 505 - PS_MGTRTXP1_505 -#Other net PACKAGE_PIN W31 - GTR_LANE2_TX_P Bank 505 - PS_MGTRTXP2_505 -#Other net PACKAGE_PIN V29 - GTR_LANE3_TX_P Bank 505 - PS_MGTRTXP3_505 -#Other net PACKAGE_PIN AA28 - GTR_REF_CLK_PCIE_C_N Bank 505 - PS_MGTREFCLK0N_505 -#Other net PACKAGE_PIN AA27 - GTR_REF_CLK_PCIE_C_P Bank 505 - PS_MGTREFCLK0P_505 -#Other net PACKAGE_PIN W28 - GTR_REF_CLK_SATA_C_N Bank 505 - PS_MGTREFCLK1N_505 -#Other net PACKAGE_PIN W27 - GTR_REF_CLK_SATA_C_P Bank 505 - PS_MGTREFCLK1P_505 -#Other net PACKAGE_PIN U28 - GTR_REF_CLK_USB3_C_N Bank 505 - PS_MGTREFCLK2N_505 -#Other net PACKAGE_PIN U27 - GTR_REF_CLK_USB3_C_P Bank 505 - PS_MGTREFCLK2P_505 -#Other net PACKAGE_PIN U32 - GTR_REF_CLK_DP_C_N Bank 505 - PS_MGTREFCLK3N_505 -#Other net PACKAGE_PIN U31 - GTR_REF_CLK_DP_C_P Bank 505 - PS_MGTREFCLK3P_505 -#Other net PACKAGE_PIN AB28 - 69N5804 Bank 505 - PS_MGTRREF_505 diff --git a/target/xilinx/flavor_vanilla/flavor_vanilla.mk b/target/xilinx/flavor_vanilla/flavor_vanilla.mk index 4302e951..aeac1c33 100644 --- a/target/xilinx/flavor_vanilla/flavor_vanilla.mk +++ b/target/xilinx/flavor_vanilla/flavor_vanilla.mk @@ -9,6 +9,7 @@ xilinx_bit_vanilla := $(CAR_XIL_DIR)/flavor_vanilla/out/carfield_top_xilinx.bit # This flavor requires pre-compiled Xilinx IPs (which may depend on the board) xilinx_ips_names_vanilla_vcu128 := xlnx_mig_ddr4 xlnx_clk_wiz xlnx_vio +xilinx_ips_names_vanilla_vcu118 := xlnx_mig_ddr4 xlnx_clk_wiz xlnx_vio xilinx_ips_names_vanilla := $(xilinx_ips_names_vanilla_${XILINX_BOARD}) # Path to compiled ips xilinx_ips_paths_vanilla = $(foreach ip-name,$(xilinx_ips_names_vanilla),$(xilinx_ip_dir)/$(ip-name)/$(ip-name).srcs/sources_1/ip/$(ip-name)/$(ip-name).xci) @@ -55,3 +56,5 @@ car-xil-clean-vanilla: cd $(CAR_XIL_DIR)/flavor_vanilla && rm -rf scripts/add_sources.tcl* *.log *.jou *.str *.mif carfield.* .Xil/ .PHONY: car-xil-clean-vanilla + +include $(CAR_XIL_DIR)/flavor_vanilla/sim/sim.mk diff --git a/target/xilinx/flavor_vanilla/scripts/run.tcl b/target/xilinx/flavor_vanilla/scripts/run.tcl index c14efe8e..6980be8a 100644 --- a/target/xilinx/flavor_vanilla/scripts/run.tcl +++ b/target/xilinx/flavor_vanilla/scripts/run.tcl @@ -14,7 +14,7 @@ set_param general.maxThreads 8 # Contraints files selection switch $::env(XILINX_BOARD) { - "vcu128" { + "vcu128" - "vcu118" { import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD).xdc import_files -fileset constrs_1 -norecurse constraints/carfield_top_xilinx.xdc # General constraints diff --git a/target/xilinx/flavor_vanilla/sim/run_simulation.tcl b/target/xilinx/flavor_vanilla/sim/run_simulation.tcl new file mode 100644 index 00000000..8adc4629 --- /dev/null +++ b/target/xilinx/flavor_vanilla/sim/run_simulation.tcl @@ -0,0 +1,42 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +source add_sources.tcl + +if {[string first "xlnx_clk_wiz" $::env(IPS)] != -1} { + source ips/xlnx_clk_wiz/questa/compile.do + +if {[string first "xlnx_vio" $::env(IPS)] != -1} { + source ips/xlnx_vio/questa/compile.do +}} + +if {[string first "xlnx_mig_ddr4" $::env(IPS)] != -1} { + source ips/xlnx_mig_ddr4_ex/questa/compile.do + source ips/xlnx_mig_ddr4/questa/compile.do + vlog -work work ips/xlnx_mig_ddr4_ex/imports/sim_tb_top.sv -L xil_defaultlib +} + +## Note : this testbench does not implenent the ddr4 memory model +set TESTBENCH "work.sim_tb_top xil_defaultlib.glbl" + +set XLIB_ARGS "-L secureip -L xpm -L unisims_ver -L unimacro_ver -L work -L xil_defaultlib" + +if {![info exists VOPTARGS]} { + set VOPTARGS "+acc" +} + +set flags "-permissive -suppress 3009 -suppress 8386 -error 7" + +set pargs "" +if {[info exists BOOTMODE]} { append pargs "+BOOTMODE=${BOOTMODE} " } +if {[info exists PRELMODE]} { append pargs "+PRELMODE=${PRELMODE} " } +if {[info exists BINARY]} { append pargs "+BINARY=${BINARY} " } +if {[info exists IMAGE]} { append pargs "+IMAGE=${IMAGE} " } + +eval "vsim ${TESTBENCH} -t 1ps -vopt -voptargs=\"${VOPTARGS}\"" ${XLIB_ARGS} ${pargs} ${flags} + +set StdArithNoWarnings 1 +set NumericStdNoWarnings 1 diff --git a/target/xilinx/flavor_vanilla/sim/setup_simulation.tcl b/target/xilinx/flavor_vanilla/sim/setup_simulation.tcl new file mode 100644 index 00000000..7e3c10c3 --- /dev/null +++ b/target/xilinx/flavor_vanilla/sim/setup_simulation.tcl @@ -0,0 +1,44 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set command "" +set script_path [ file dirname [ file normalize [ info script ] ] ] + +if { $argc == 1 } { + set command [lindex $argv 0] +} + +puts "Running with SIMULATOR_PATH=$::env(SIMULATOR_PATH) ; GCC_PATH=$::env(GCC_PATH) ; XILINX_SIMLIB_PATH=$::env(XILINX_SIMLIB_PATH)" + +# Compile the vivado simlib to XILINX_SIMLIB_PATH +if { $command == "compile_simlib" } { + set command "compile_simlib -simulator questa -simulator_exec_path {$::env(SIMULATOR_PATH)} \ + -gcc_exec_path {$::env(GCC_PATH)} -family all -language verilog -library all -dir {$::env(XILINX_SIMLIB_PATH)} -force" + # For some reason this command does not work well when not eval from the string + eval $command + +# Export simulation scripts for each ip +} elseif { $command == "export_simulation" } { + open_project $::env(VIVADO_PROJECT) + export_simulation -simulator questa -directory "./ips" -lib_map_path "$::env(XILINX_SIMLIB_PATH)" \ + -absolute_path -force -of_objects [get_ips *] + +# Export simulation scripts for each ip +} elseif { $command == "export_example" } { + open_project $::env(VIVADO_PROJECT) + open_example_project -dir "./ips" -force [get_ips xlnx_mig_ddr4] + +# Export simulation scripts for each ip +} elseif { $command == "export_example_simulation" } { + open_project $::env(VIVADO_PROJECT) + export_simulation -lib_map_path "$::env(XILINX_SIMLIB_PATH)" -directory "." -simulator questa \ + -ip_user_files_dir "./ips/xlnx_mig_ddr4_ex/xlnx_mig_ddr4_ex.ip_user_files" \ + -ipstatic_source_dir "./ips/xlnx_mig_ddr4_ex/xlnx_mig_ddr4_ex.ip_user_files/ipstatic" -use_ip_compiled_libs -directory "./ips/xlnx_mig_ddr4_ex/" -absolute_path + +# Unknown command +} else { + puts "[$argv0] Unknown command: $command" +} diff --git a/target/xilinx/flavor_vanilla/sim/sim.mk b/target/xilinx/flavor_vanilla/sim/sim.mk new file mode 100644 index 00000000..25b902f4 --- /dev/null +++ b/target/xilinx/flavor_vanilla/sim/sim.mk @@ -0,0 +1,67 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Cyril Koenig + +CAR_XIL_SIM_DIR ?= $(CAR_XIL_DIR)/flavor_vanilla/sim + +CAR_XIL_SIM_SIMLIB_PATH ?= /home/$(USER)/xlib_questa-2022.3_vivado-2022.1 +CAR_XIL_SIM_SIMULATOR_PATH ?= /usr/pack/questa-2022.3-bt/questasim/bin +CAR_XIL_SIM_GCC_PATH ?= /usr/pack/questa-2022.3-bt/questasim/gcc-7.4.0-linux_x86_64/bin + +car-xil-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CAR_XIL_SIM_DIR)/ips/, $(xilinx_ips_names_vanilla))) + +# Pre-generated/modified example projects (contain the simulation top level) +ifneq ($(filter xlnx_mig_ddr4,$(xilinx_ips_names_vanilla)),) + car-xil-sim-example-projects := xlnx_mig_ddr4_ex +endif +ifneq ($(filter xlnx_mig_7_ddr3,$(xilinx_ips_names_vanilla)),) + car-xil-sim-example-projects := xlnx_mig_7_ddr3_ex +endif + +car-xil-sim-example-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CAR_XIL_SIM_DIR)/ips/, $(car-xil-sim-example-projects))) + +vivado_env_sim := $(vivado_env_vanilla) \ + XILINX_SIMLIB_PATH=$(CAR_XIL_SIM_SIMLIB_PATH) \ + SIMULATOR_PATH=$(CAR_XIL_SIM_SIMULATOR_PATH) \ + GCC_PATH=$(CAR_XIL_SIM_GCC_PATH) \ + VIVADO_PROJECT=$(CAR_XIL_DIR)/flavor_vanilla/carfield.xpr + +car-xil-vlog-args := -suppress 2583 -suppress 13314 + +# Fetch example projects at IIS (containing SRAM behavioral models) +$(CAR_XIL_SIM_DIR)/ips/%_ex/questa/compile.do: + mkdir -p $(CAR_XIL_SIM_DIR)/ips + # First the example project + cd $(CAR_XIL_SIM_DIR) && $(vivado_env_sim) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_example" + # Then the example simulation + cd $(CAR_XIL_SIM_DIR) && $(vivado_env_sim) VIVADO_PROJECT=$(CAR_XIL_DIR)/flavor_vanilla/sim/ips/xlnx_mig_ddr4_ex/xlnx_mig_ddr4_ex.xpr $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_example_simulation" + # Replace the DUT with carfield top + patch $(CAR_XIL_SIM_DIR)/ips/xlnx_mig_ddr4_ex/imports/sim_tb_top.sv $(CAR_XIL_SIM_DIR)/sim_tb_top.diff + +# Generate generic Xilinx simulation libraries +$(CAR_XIL_SIM_SIMLIB_PATH)/modelsim.ini: + cd $(CAR_XIL_SIM_DIR) && $(vivado_env_sim) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib" + +# Export IPs simulation models +$(CAR_XIL_SIM_DIR)/ips/%/questa/compile.do: + mkdir -p $(CAR_XIL_SIM_DIR)/ips + cd $(CAR_XIL_SIM_DIR) && $(vivado_env_sim) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation" + +# Generate bender script +$(CAR_XIL_SIM_DIR)/add_sources.tcl: + $(BENDER) script vsim -t sim -t test $(common_targs) $(xilinx_targs_vanilla) $(common_defs) $(xilinx_defs_vanilla) --vlog-arg="$(car-xil-vlog-args)" > $@ + +# Start questa +car-xil-sim: $(CAR_XIL_DIR)/flavor_vanilla/carfield.xpr $(CAR_XIL_SIM_SIMLIB_PATH)/modelsim.ini $(car-xil-sim-example-scripts) $(car-xil-sim-scripts) $(CAR_XIL_SIM_DIR)/add_sources.tcl + mkdir -p $(CAR_XIL_SIM_DIR)/questa_lib + cp $(CAR_XIL_SIM_SIMLIB_PATH)/modelsim.ini $(CAR_XIL_SIM_DIR) + chmod +w $(CAR_XIL_SIM_DIR)/modelsim.ini + cd $(CAR_XIL_SIM_DIR) && BOARD="$(XILINX_BOARD)" IPS="$(xilinx_ips_names_vanilla)" questa-2022.3 vsim -work work -do "run_simulation.tcl" + +# Clean +car-xil-sim-clean: + cd $(CAR_XIL_SIM_DIR) && rm -rf *.log questa_lib work transcript vsim.wlf add_sources.tcl .Xil modelsim.ini ips + +.PHONY: clean-sim sim diff --git a/target/xilinx/flavor_vanilla/sim/sim_tb_top.diff b/target/xilinx/flavor_vanilla/sim/sim_tb_top.diff new file mode 100644 index 00000000..beb310d0 --- /dev/null +++ b/target/xilinx/flavor_vanilla/sim/sim_tb_top.diff @@ -0,0 +1,61 @@ +217,220c217,244 +< example_top +< u_example_top +< ( +< .sys_rst (sys_rst), +--- +> logic cpu_reset; +> logic cpu_resetn; +> logic sys_clk_p; +> logic sys_clk_n; +> logic testmode_i; +> logic [1:0] boot_mode_i; +> logic jtag_tck_i; +> logic jtag_tms_i; +> logic jtag_tdi_i; +> logic jtag_tdo_o; +> logic jtag_trst_ni; +> logic jtag_vdd_o; +> logic jtag_gnd_o; +> logic uart_tx_o; +> logic uart_rx_i; +> +> assign cpu_reset = sys_rst; +> assign cpu_resetn = ~cpu_reset; +> assign boot_mode_i = '0; +> assign testmode_i = '0; +> assign jtag_tck_i = '0; +> assign jtag_tms_i = '0; +> assign jtag_tdi_i = '0; +> assign jtag_trst_ni = '0; +> assign uart_rx_i = '0; +> +> assign sys_clk_p = c0_sys_clk_p; +> assign sys_clk_n = c0_sys_clk_n; +222,241c248,252 +< .c0_data_compare_error (c0_data_compare_error), +< .c0_init_calib_complete (c0_init_calib_complete), +< .c0_sys_clk_p (c0_sys_clk_p), +< .c0_sys_clk_n (c0_sys_clk_n), +< +< .c0_ddr4_act_n (c0_ddr4_act_n), +< .c0_ddr4_adr (c0_ddr4_adr), +< .c0_ddr4_ba (c0_ddr4_ba), +< .c0_ddr4_bg (c0_ddr4_bg), +< .c0_ddr4_cke (c0_ddr4_cke), +< .c0_ddr4_odt (c0_ddr4_odt), +< .c0_ddr4_cs_n (c0_ddr4_cs_n), +< .c0_ddr4_ck_t (c0_ddr4_ck_t_int), +< .c0_ddr4_ck_c (c0_ddr4_ck_c_int), +< .c0_ddr4_reset_n (c0_ddr4_reset_n), +< .c0_ddr4_dm_dbi_n (c0_ddr4_dm_dbi_n), +< .c0_ddr4_dq (c0_ddr4_dq), +< .c0_ddr4_dqs_c (c0_ddr4_dqs_c), +< .c0_ddr4_dqs_t (c0_ddr4_dqs_t) +< ); +--- +> carfield_top_xilinx +> u_carfield_top_xilinx +> ( +> .* +> ); \ No newline at end of file diff --git a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv index 33d96e1d..7d4cd381 100644 --- a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv +++ b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv @@ -208,12 +208,13 @@ module carfield_top_xilinx logic vio_reset; logic [1:0] vio_boot_mode, vio_boot_mode_safety; - xlnx_vio ( + xlnx_vio i_xlnx_vio ( .clk(soc_clk), .probe_out0(vio_reset), .probe_out1(vio_boot_mode), .probe_out2(vio_boot_mode_safety) ); + assign sys_rst = cpu_reset | vio_reset; assign boot_mode = boot_mode_i | vio_boot_mode; assign boot_mode_safety = boot_mode_safety_i | vio_boot_mode_safety; diff --git a/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv b/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv index cf4ec8f2..b33fdda9 100644 --- a/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv +++ b/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv @@ -60,13 +60,13 @@ module dram_wrapper_xilinx #( }; `endif -`ifdef TARGET_ZCU102 +`ifdef TARGET_VCU118 localparam dram_cfg_t cfg = '{ - EnCDC : 1, // ??? MHz axi (attention CDC logdepth) + EnCDC : 1, // 300 MHz axi (attention CDC logdepth) IdWidth : 4, - AddrWidth : 29, - DataWidth : 128, - StrobeWidth : 16 + AddrWidth : 32, // TODO: in the original patch this was 31, why? + DataWidth : 512, + StrobeWidth : 64 }; `endif @@ -270,26 +270,6 @@ module dram_wrapper_xilinx #( .c0_ddr4_s_axi_rresp (cdc_dram_rsp.r.resp), .c0_ddr4_s_axi_rlast (cdc_dram_rsp.r.last), .c0_ddr4_s_axi_rvalid (cdc_dram_rsp.r_valid), -`ifdef TARGET_VCU128 - // Axi ctrl - .c0_ddr4_s_axi_ctrl_awvalid('0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr ('0), - .c0_ddr4_s_axi_ctrl_wvalid ('0), - .c0_ddr4_s_axi_ctrl_wready (), - .c0_ddr4_s_axi_ctrl_wdata ('0), - .c0_ddr4_s_axi_ctrl_bvalid (), - .c0_ddr4_s_axi_ctrl_bready ('0), - .c0_ddr4_s_axi_ctrl_bresp (), - .c0_ddr4_s_axi_ctrl_arvalid('0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr ('0), - .c0_ddr4_s_axi_ctrl_rvalid (), - .c0_ddr4_s_axi_ctrl_rready ('0), - .c0_ddr4_s_axi_ctrl_rdata (), - .c0_ddr4_s_axi_ctrl_rresp (), - .c0_ddr4_interrupt (), -`endif // Others .c0_init_calib_complete (), // keep open .addn_ui_clkout1 (dram_clk_o), @@ -366,4 +346,4 @@ module dram_wrapper_xilinx #( ); `endif // USE_DDR3 -endmodule \ No newline at end of file +endmodule diff --git a/target/xilinx/flavor_vanilla/src/phy_definitions.svh b/target/xilinx/flavor_vanilla/src/phy_definitions.svh index 98ad955a..05925167 100644 --- a/target/xilinx/flavor_vanilla/src/phy_definitions.svh +++ b/target/xilinx/flavor_vanilla/src/phy_definitions.svh @@ -4,10 +4,10 @@ // // Cyril Koenig -`ifdef TARGET_VCU128 +`ifdef TARGET_VCU118 `define USE_RESET `define USE_JTAG - `define USE_JTAG_VDDGND + // Hardwired VDD GND on the PMOD `define USE_QSPI `define USE_STARTUPE3 `define USE_VIO @@ -18,14 +18,18 @@ `endif `endif -`ifdef TARGET_ZCU102 +`ifdef TARGET_VCU128 `define USE_RESET `define USE_JTAG + `define USE_JTAG_VDDGND + `define USE_QSPI + `define USE_STARTUPE3 + `define USE_VIO `define HypNumChips 1 `define HypNumPhys 1 `ifdef GEN_NO_HYPERBUS `define USE_DDR4 - `endif `define USE_VIO + `endif `endif ///////////////////// @@ -39,31 +43,30 @@ `define USE_DDR `endif +/* DDR4 intf */ `define DDR4_INTF \ - /* DDR4 intf */ \ +`ifdef TARGET_VCU128 \ + inout [71:0] c0_ddr4_dq, \ + inout [8:0] c0_ddr4_dqs_c, \ + inout [8:0] c0_ddr4_dqs_t, \ + inout [8:0] c0_ddr4_dm_dbi_n, \ + output [1:0] c0_ddr4_cs_n, \ +`elsif TARGET_VCU118 \ + inout [63:0] c0_ddr4_dq, \ + inout [7:0] c0_ddr4_dqs_c, \ + inout [7:0] c0_ddr4_dqs_t, \ + inout [7:0] c0_ddr4_dm_dbi_n, \ + output c0_ddr4_cs_n, \ +`endif \ output c0_ddr4_reset_n, \ - output [0:0] c0_ddr4_ck_t, \ output [0:0] c0_ddr4_ck_c, \ + output [0:0] c0_ddr4_ck_t, \ output c0_ddr4_act_n, \ output [16:0] c0_ddr4_adr, \ output [1:0] c0_ddr4_ba, \ output [0:0] c0_ddr4_bg, \ output [0:0] c0_ddr4_cke, \ - output [0:0] c0_ddr4_odt, \ -`ifdef TARGET_VCU128 \ - output [1:0] c0_ddr4_cs_n, \ - inout [8:0] c0_ddr4_dm_dbi_n, \ - inout [71:0] c0_ddr4_dq, \ - inout [8:0] c0_ddr4_dqs_c, \ - inout [8:0] c0_ddr4_dqs_t, \ -`endif \ -`ifdef TARGET_ZCU102 \ - output [0:0] c0_ddr4_cs_n, \ - inout [1:0] c0_ddr4_dm_dbi_n, \ - inout [15:0] c0_ddr4_dq, \ - inout [1:0] c0_ddr4_dqs_c, \ - inout [1:0] c0_ddr4_dqs_t, \ -`endif + output [0:0] c0_ddr4_odt, `define DDR3_INTF \ output ddr3_ck_p, \ diff --git a/target/xilinx/scripts/bin2jtag.py b/target/xilinx/scripts/bin2jtag.py new file mode 100644 index 00000000..3379e174 --- /dev/null +++ b/target/xilinx/scripts/bin2jtag.py @@ -0,0 +1,100 @@ +#!/usr/bin/env python3 + +# Copyright 2020 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Generate a tcl script for writing a binary to a memory location in the FPGA from Vivado. +# This requires the JTAG2AXIMaster Xilinx IP to be present inside the design +# +# Usage: +# bin2jtag.py -d hw_axi_1 -b 1000 bootrom.bin > mem.tcl +# +# In vivado then `source mem.tcl` to execute +# +# Requires bin2coe +# - https://github.com/anishathalye/bin2coe/blob/master/src/bin2coe + +from argparse import ArgumentParser +from io import BytesIO +from signal import signal, SIGPIPE, SIG_DFL +import sys + +import bin2coe.convert + +signal(SIGPIPE, SIG_DFL) + + +def main(): + parser = ArgumentParser() + parser.add_argument('-d', '--device', type=str, default='hw_axi_1', help='what HW axi to use') + parser.add_argument('-b', '--base', type=str, default='0', help='memory base address in hex') + parser.add_argument('-c', '--chunk-size', type=int, default=32, help='number of words per burst transaction') + parser.add_argument('binary', metavar='BIN', type=str, nargs=1, help='bin input') + options = parser.parse_args() + + width = 32 + radix = 16 + fd_o = sys.stdout + + with open(options.binary[0], 'rb') as f: + data = f.read() + + # Writes jtag commands to fd_o + convert(fd_o, data, width, radix, int(options.base, 16), options.device, True, options.chunk_size) + + +def convert(output, data, width, radix, address, dev, rb, chunk_size): + # License + output.write("# Copyright 2020 ETH Zurich and University of Bologna.\n") + output.write("# Solderpad Hardware License, Version 0.51, see LICENSE for details.\n") + output.write("# SPDX-License-Identifier: SHL-0.51\n") + + # Pre tcl script + output.write("set errs 0\n") + + # Templates for one data write + t = f"[get_hw_axis {dev}]" + tpl = "create_hw_axi_txn -cache 0 -force {n} {t} -address {a} -len {l} -type write -data {d}" + tpl_rb = "create_hw_axi_txn -cache 0 -force {n} {t} -address {a} -len {l} -type read" + tpl_run = "run_hw_axi {txn}" + tx_name = "txn" + + # Get coe format from bin2coe + temp = BytesIO() + bin2coe.convert.convert(output=temp, data=data, width=width, depth=0, fill=0, + radix=radix, little_endian=True, mem=True) + + # Split the coe format into string words + word_list = [w for w in temp.getvalue().decode("utf-8").split("\n") if w != ""] + + # Loop over the string words + i = 0 + while i < len(word_list): + # Take care at for the end of the list + k = min(len(word_list)-i, chunk_size) + # Reorganize words + words = word_list[i:i+k][::-1] + # Write axi write + out = tpl.format(n=tx_name, t=t, a=f"{address:08x}", d="_".join(words), l=len(words)) + '\n' + output.write(out) + output.write(tpl_run.format(txn=tx_name) + '\n') + # Write axi readback + if rb: + out = tpl_rb.format(n="wb", t=t, a=f"{address:08x}", l=len(words)) + '\n' + output.write(out) + output.write(f"run_hw_axi {'wb'}\n") + output.write("set resp [get_property DATA [get_hw_axi_txns wb]]\n") + s = f"set exp {''.join(words)}\n" + s += "if {$exp ne $resp} { puts Error; incr errs }\n" + output.write(s) + # Get to next chunk + address += k * 4 + i += k + + if rb: + output.write("puts \"Errors: $errs\"\n") + + +if __name__ == "__main__": + main() diff --git a/target/xilinx/scripts/flash_spi.tcl b/target/xilinx/scripts/flash_spi.tcl index e6d6c360..a45c230a 100644 --- a/target/xilinx/scripts/flash_spi.tcl +++ b/target/xilinx/scripts/flash_spi.tcl @@ -17,20 +17,36 @@ set mcs_file image.mcs if {$::env(XILINX_BOARD) eq "vcu128"} { set hw_device [get_hw_devices xcvu37p_0] set hw_mem_device [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0] +} elseif {$::env(XILINX_BOARD) eq "vcu118"} { + set mcs_primary_file image_primary.mcs + set mcs_secondary_file image_secondary.mcs + set hw_device [get_hw_devices xcvu9p_0] + set hw_mem_device [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4_x8}] 0] } # Create flash configuration file -write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ +if {$::env(XILINX_BOARD) eq "vcu118"} { + write_cfgmem -force -format mcs -size 256 -interface SPIx8 \ -loaddata "up $offset $file" \ -checksum \ -file $mcs_file +} else { + write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ + -loaddata "up $offset $file" \ + -checksum \ + -file $mcs_file +} set_property PARAM.FREQUENCY 15000000 [get_hw_targets *] create_hw_cfgmem -hw_device $hw_device $hw_mem_device set hw_cfgmem [get_property PROGRAM.HW_CFGMEM $hw_device] set_property PROGRAM.ADDRESS_RANGE {use_file} $hw_cfgmem -set_property PROGRAM.FILES [list $mcs_file ] $hw_cfgmem +if {$::env(XILINX_BOARD) eq "vcu118"} { + set_property PROGRAM.FILES [list $mcs_primary_file $mcs_secondary_file] $hw_cfgmem +} else { + set_property PROGRAM.FILES [list $mcs_file ] $hw_cfgmem +} set_property PROGRAM.PRM_FILE {} $hw_cfgmem set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $hw_cfgmem set_property PROGRAM.BLANK_CHECK 0 $hw_cfgmem diff --git a/target/xilinx/scripts/overrides.sh b/target/xilinx/scripts/overrides.sh index c1db7201..7bd4a71e 100755 --- a/target/xilinx/scripts/overrides.sh +++ b/target/xilinx/scripts/overrides.sh @@ -12,13 +12,13 @@ SCRIPT_DIR="$(dirname "$(readlink -f "$0")")" for f in `find $SCRIPT_DIR/../src/overrides -not -type d -printf "%f\n"`; do echo "Removing $f $1.tmp" grep -v -P "(? $1.tmp - mv $1.tmp $1 + diff $1.tmp $@ | grep ">\|<" + cp $1.tmp $1 done - -#for f in `find $SCRIPT_DIR/../src/overrides -not -type d -printf "%f\n"`; do -# echo "Removing $f $1.tmp" -# grep -v -P "(? $1.tmp -# diff $1.tmp $@ | grep ">\|<" -# mv $1.tmp $1 -#done +for f in `find $SCRIPT_DIR/../src/overrides -not -type d -printf "%f\n"`; do + echo "Removing $f $1.tmp" + grep -v -P "(? $1.tmp + diff $1.tmp $@ | grep ">\|<" + cp $1.tmp $1 +done diff --git a/target/xilinx/scripts/program.tcl b/target/xilinx/scripts/program.tcl index bf442c04..f7ecb87f 100644 --- a/target/xilinx/scripts/program.tcl +++ b/target/xilinx/scripts/program.tcl @@ -17,7 +17,9 @@ if {$::env(XILINX_BOARD) eq "genesys2"} { if {$::env(XILINX_BOARD) eq "vcu128"} { set hw_device [get_hw_devices xcvu37p_0] } - +if {$::env(XILINX_BOARD) eq "vcu118"} { + set hw_device [get_hw_devices xcvu9p_0] +} set_property PARAM.FREQUENCY 15000000 [get_hw_targets *] current_hw_device $hw_device diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk index 14424794..9562a929 100644 --- a/target/xilinx/xilinx.mk +++ b/target/xilinx/xilinx.mk @@ -15,7 +15,7 @@ VIVADO ?= vitis-2020.2 vivado XILINX_PROJECT ?= carfield # XILINX_FLAVOR in {vanilla,bd} see carfield_bd.mk XILINX_FLAVOR ?= bd -# Board in {vcu128} +# XILINX_BOARD in {vcu128, vcu118} XILINX_BOARD ?= vcu128 ifeq ($(XILINX_BOARD),vcu128) @@ -26,6 +26,14 @@ ifeq ($(XILINX_BOARD),vcu128) XILINX_HOST ?= bordcomputer endif +ifeq ($(XILINX_BOARD),vcu118) + xilinx_part := xcvu9p-flga2104-2L-e + xilinx_board_long := xilinx.com:vcu118:part0:2.4 + XILINX_PORT ?= 3249 + XILINX_FPGA_PATH ?= xilinx_tcf/Digilent/210308A3B1D8 + XILINX_HOST ?= bordcomputer +endif + XILINX_USE_ARTIFACTS ?= 0 XILINX_ARTIFACTS_ROOT ?= XILINX_ELABORATION_ONLY ?= 0 @@ -95,7 +103,11 @@ car-xil-program: car-xil-flash: $(CAR_SW_DIR)/boot/linux_carfield_$(XILINX_FLAVOR)_$(XILINX_BOARD).gpt.bin $(vivado_env) FILE=$< OFFSET=0 $(VIVADO) $(VIVADO_FLAGS) -source $(CAR_XIL_DIR)/scripts/flash_spi.tcl +# Flash uboot image +car-xil-flash-uboot: $(CAR_SW_DIR)/boot/uboot_carfield_$(XILINX_FLAVOR)_$(XILINX_BOARD).gpt.bin + $(vivado_env) FILE=$< OFFSET=0 $(VIVADO) $(VIVADO_FLAGS) -source $(CAR_XIL_DIR)/scripts/flash_spi.tcl + ## Clean Xilinx artifacts for all implementations car-xil-clean: car-xil-clean-vanilla car-xil-clean-bd xilinx-ip-clean-all -.PHONY: car-xil-program car-xil-flash car-xil-clean car-xil-all +.PHONY: car-xil-program car-xil-clean car-xil-all diff --git a/target/xilinx/xilinx_ips/carfield_ip/constraints/carfield_xilinx_ip.xdc b/target/xilinx/xilinx_ips/carfield_ip/constraints/carfield_xilinx_ip.xdc index 1a23e1aa..628d6c4e 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/constraints/carfield_xilinx_ip.xdc +++ b/target/xilinx/xilinx_ips/carfield_ip/constraints/carfield_xilinx_ip.xdc @@ -12,7 +12,6 @@ set UART_IO_SPEED 200.0 # Global Settings # ################### -# The output of the reset synchronizer set_false_path -from [get_ports cpu_reset*] ########## diff --git a/target/xilinx/xilinx_ips/carfield_ip/constraints/ooc_carfield_ip.xdc b/target/xilinx/xilinx_ips/carfield_ip/constraints/ooc_carfield_ip.xdc index c8529797..6eaabbcd 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/constraints/ooc_carfield_ip.xdc +++ b/target/xilinx/xilinx_ips/carfield_ip/constraints/ooc_carfield_ip.xdc @@ -1,7 +1,7 @@ -create_clock -name carfield_ooc_synth_clk_100 -period 100 [get_ports clk_100] -create_clock -name carfield_ooc_synth_clk_50 -period 50 [get_ports clk_50] -create_clock -name carfield_ooc_synth_clk_20 -period 20 [get_ports clk_20] -create_clock -name carfield_ooc_synth_clk_10 -period 10 [get_ports clk_10] +create_clock -name carfield_ooc_synth_clk_10 -period 100 [get_ports clk_100] +create_clock -name carfield_ooc_synth_clk_20 -period 50 [get_ports clk_50] +create_clock -name carfield_ooc_synth_clk_50 -period 20 [get_ports clk_20] +create_clock -name carfield_ooc_synth_clk_100 -period 10 [get_ports clk_10] set_case_analysis 0 [get_ports testmode_i] set_clock_groups -name async_clks -asynchronous \ diff --git a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv index 37344c4a..d2160f99 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv +++ b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv @@ -569,7 +569,7 @@ module carfield_xilinx assign qspi_cs_b_ts = ~spi_cs_en; assign qspi_dqo_ts = ~spi_sd_en; - // On VCU128/ZCU102, SPI ports are not directly available + // On VCU128/VCU118, SPI ports are not directly available STARTUPE3 #( .PROG_USR("FALSE"), .SIM_CCLK_FREQ(0.0) diff --git a/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl b/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl index 70467762..9bb06d8c 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl +++ b/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl @@ -30,7 +30,7 @@ set_property top carfield_xilinx_ip [current_fileset] # Attention SFCU is only used because of Carfield's structure update_compile_order -fileset sources_1 -synth_design -rtl -name rtl_1 -sfcu +# synth_design -rtl -name rtl_1 -sfcu ipx::package_project -root_dir . -vendor ethz.ch -library user -taxonomy /UserIP -set_current false diff --git a/target/xilinx/xilinx_ips/xlnx_clk_wiz/tcl/run.tcl b/target/xilinx/xilinx_ips/xlnx_clk_wiz/tcl/run.tcl index 5ae7ddb6..14960b79 100644 --- a/target/xilinx/xilinx_ips/xlnx_clk_wiz/tcl/run.tcl +++ b/target/xilinx/xilinx_ips/xlnx_clk_wiz/tcl/run.tcl @@ -42,6 +42,41 @@ if {$::env(XILINX_BOARD) eq "vcu128"} { ] [get_ips $ipName] } +if {$::env(XILINX_BOARD) eq "vcu118"} { + set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {250.000} \ + CONFIG.CLKOUT1_USED {true} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_100} \ + CONFIG.CLK_OUT2_PORT {clk_50} \ + CONFIG.CLK_OUT3_PORT {clk_20} \ + CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100.000} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.CLKIN1_JITTER_PS {33.330000000000005} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {4.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {4.0} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {12} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {24} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {60} \ + CONFIG.MMCM_CLKOUT4_DIVIDE {120} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT1_JITTER {134.506} \ + CONFIG.CLKOUT1_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT2_JITTER {153.164} \ + CONFIG.CLKOUT2_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT3_JITTER {184.746} \ + CONFIG.CLKOUT3_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT4_JITTER {213.887} \ + CONFIG.CLKOUT4_PHASE_ERROR {154.678} \ + ] [get_ips $ipName] +} + if {$::env(XILINX_BOARD) eq "zcu102"} { set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer} \ CONFIG.PRIM_IN_FREQ {300.000} \ diff --git a/target/xilinx/xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl b/target/xilinx/xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl index 04af1667..64434eb3 100644 --- a/target/xilinx/xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl +++ b/target/xilinx/xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl @@ -52,6 +52,25 @@ if {$::env(XILINX_BOARD) eq "vcu128"} { CONFIG.C0.BANK_GROUP_WIDTH {1} \ CONFIG.C0.DDR4_AxiSelection {true} \ ] [get_ips $ipName] +} elseif {$::env(XILINX_BOARD) eq "vcu118"} { + set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c1_062} \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.Reference_Clock {No_Buffer} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {4000} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + CONFIG.C0.DDR4_DataWidth {64} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiAddressWidth {31} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.Reference_Clock {No_Buffer} \ + CONFIG.C0.BANK_GROUP_WIDTH {1} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + ] [get_ips $ipName] } From 47e7b9419587cf68417ae3601b2c9a6440a33122 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 30 Jun 2024 19:28:13 +0200 Subject: [PATCH 2/6] Remove references to carfield.xdc in various run.tcl. --- target/xilinx/flavor_bd/scripts/run.tcl | 10 ++-------- target/xilinx/flavor_vanilla/scripts/run.tcl | 12 ++++-------- target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl | 6 +++--- 3 files changed, 9 insertions(+), 19 deletions(-) diff --git a/target/xilinx/flavor_bd/scripts/run.tcl b/target/xilinx/flavor_bd/scripts/run.tcl index 749de4c4..47034a87 100644 --- a/target/xilinx/flavor_bd/scripts/run.tcl +++ b/target/xilinx/flavor_bd/scripts/run.tcl @@ -18,9 +18,8 @@ set_param general.maxThreads 8 set_property ip_repo_paths ../xilinx_ips/carfield_ip [current_project] update_ip_catalog -# Add params to runs +# Define sources import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD).xdc -import_files -fileset constrs_1 -norecurse ../constraints/carfield_islands.tcl source scripts/add_includes.tcl # Build block design @@ -28,7 +27,7 @@ source scripts/carfield_bd_$::env(XILINX_BOARD).tcl # Add the ext_jtag pins to block design if {[info exists ::env(GEN_EXT_JTAG)] && ($::env(GEN_EXT_JTAG)==1)} { - source scripts/carfield_bd_$::env(XILINX_BOARD)_ext_jtag.tcl + source scripts/carfield_bd_$::env(XILINX_BOARD)_ext_jtag.tcl import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_ext_jtag.xdc } @@ -47,12 +46,8 @@ generate_target all [get_files *design_1.bd] export_ip_user_files -of_objects [get_files *design_1.bd] -no_script create_ip_run [get_files *design_1.bd] -# Make sure carfield.xdc (imported from IP) executes after carfield_islands.tcl (that generates the clocks) -set_property processing_order LATE [get_files carfield.xdc] - # Bet list of synthesis and OOO synthesis to do set synth_runs [get_runs *synth*] -# Exclude the whole design (synth_1) and the carfield IP (bug) if { $rdi::mode == "gui" } { # Exclude the whole design the carfield IP from GUI (todo: inspect GUI bug when only carfield ooc has changed) set all_ooc_synth [lsearch -regexp -all -inline -not $synth_runs {^synth_1$|carfield}] @@ -133,7 +128,6 @@ if ($DEBUG) { } # Need to save save constraints before implementing the core set_property target_constrs_file [get_files $::env(XILINX_BOARD).xdc] [current_fileset -constrset] - save_constraints -force implement_debug_core write_debug_probes -force probes.ltx diff --git a/target/xilinx/flavor_vanilla/scripts/run.tcl b/target/xilinx/flavor_vanilla/scripts/run.tcl index 6980be8a..3466d20e 100644 --- a/target/xilinx/flavor_vanilla/scripts/run.tcl +++ b/target/xilinx/flavor_vanilla/scripts/run.tcl @@ -14,15 +14,9 @@ set_param general.maxThreads 8 # Contraints files selection switch $::env(XILINX_BOARD) { - "vcu128" - "vcu118" { + "genesys2" - "vcu128" - "vcu118" { import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD).xdc - import_files -fileset constrs_1 -norecurse constraints/carfield_top_xilinx.xdc - # General constraints - import_files -fileset constrs_1 -norecurse ../constraints/carfield_islands.tcl - # Make sure carfield.xdc executes after carfield_islands.tcl (that generates the clocks) - import_files -fileset constrs_1 -norecurse ../constraints/carfield.xdc - set_property SCOPED_TO_REF carfield [get_files carfield.xdc] - set_property processing_order LATE [get_files carfield.xdc] + import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_PROJECT).xdc } default { exit 1 @@ -52,6 +46,8 @@ if {[info exists ::env(XILINX_ELABORATION_ONLY)] && $::env(XILINX_ELABORATION_ON set_property XPM_LIBRARIES XPM_MEMORY [current_project] + synth_design -rtl -name rtl_1 -sfcu + set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] # Enable sfcu due to package conflicts set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-sfcu} -objects [get_runs synth_1] diff --git a/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl b/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl index 9bb06d8c..b61bbc5b 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl +++ b/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl @@ -21,9 +21,9 @@ add_files -fileset constrs_1 constraints/ooc_carfield_ip.xdc set_property USED_IN {synthesis out_of_context} [get_files ooc_carfield_ip.xdc] import_files -fileset constrs_1 -norecurse constraints/carfield_xilinx_ip.xdc # General constraints -import_files -fileset constrs_1 -norecurse ../../constraints/carfield.xdc -set_property SCOPED_TO_REF carfield [get_files carfield.xdc] -set_property processing_order LATE [get_files carfield.xdc] +# import_files -fileset constrs_1 -norecurse ../../constraints/carfield.xdc +# set_property SCOPED_TO_REF carfield [get_files carfield.xdc] +# set_property processing_order LATE [get_files carfield.xdc] # Package IP set_property top carfield_xilinx_ip [current_fileset] From bd0daffd553d03f7bd0b2841bb84122bf32c60bf Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 1 Jul 2024 12:13:32 +0200 Subject: [PATCH 3/6] Remove jtag_trst_ni connection in external jtag tcl script. --- target/xilinx/flavor_bd/scripts/carfield_bd_vcu118_ext_jtag.tcl | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118_ext_jtag.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118_ext_jtag.tcl index a5570104..217c694f 100644 --- a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118_ext_jtag.tcl +++ b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118_ext_jtag.tcl @@ -10,9 +10,7 @@ set jtag_tck_i [ create_bd_port -dir I jtag_tck_i ] set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ] set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ] set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ] -set jtag_trst_ni [ create_bd_port -dir I jtag_trst_ni ] connect_bd_net -net carfield_xilinx_ip_0_jtag_tdo_o [get_bd_ports jtag_tdo_o] [get_bd_pins carfield_xilinx_ip_0/jtag_tdo_o] connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tck_i] connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tdi_i] connect_bd_net -net jtag_tms_i_1 [get_bd_ports jtag_tms_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tms_i] -connect_bd_net -net jtag_trst_ni_1 [get_bd_ports jtag_trst_ni] [get_bd_pins carfield_xilinx_ip_0/jtag_trst_ni] From 544f3cc40c82044aaf94536d7ad213acb21633f1 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 3 Oct 2024 18:28:46 +0200 Subject: [PATCH 4/6] Bump L2 and RISC-V Atomics. --- Bender.local | 2 +- Bender.lock | 4 ++-- Bender.yml | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Bender.local b/Bender.local index 010531c4..4e532cb1 100644 --- a/Bender.local +++ b/Bender.local @@ -4,7 +4,7 @@ overrides: axi: { git: https://github.com/pulp-platform/axi.git , version: 0.39.3 } - axi_riscv_atomics: { git: https://github.com/pulp-platform/axi_riscv_atomics.git , rev: 46d567cad5a614a82778702d48b3a789aed7711b } # branch: astral + axi_riscv_atomics: { git: https://github.com/pulp-platform/axi_riscv_atomics.git , rev: 062bc36cbcca25629384e7f12efa6693273b3e07 } # branch: astral apb: { git: "https://github.com/pulp-platform/apb.git" , version: 0.2.3 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git" , rev: "c37bdb47339bf70e8323de8df14ea8bbeafb6583" } # branch: astral-rebase hci: { git: "https://github.com/pulp-platform/hci.git" , rev: d31af36ebcaf2196fb51676b40782aa8cbd9cc69 } # branch: remove-automatic-parameter-prop diff --git a/Bender.lock b/Bender.lock index 9289ac0b..f687d31e 100644 --- a/Bender.lock +++ b/Bender.lock @@ -66,7 +66,7 @@ packages: - common_cells - obi axi_riscv_atomics: - revision: 46d567cad5a614a82778702d48b3a789aed7711b + revision: 062bc36cbcca25629384e7f12efa6693273b3e07 version: null source: Git: https://github.com/pulp-platform/axi_riscv_atomics.git @@ -202,7 +202,7 @@ packages: - fpnew - tech_cells_generic dyn_mem: - revision: 480590062742230dc9bd4050358a15b4747bdf34 + revision: 6753d2046da6dfc8efbef5e6f22053a621f111d9 version: null source: Git: https://github.com/pulp-platform/dyn_spm.git diff --git a/Bender.yml b/Bender.yml index 7a75d788..a2b97f09 100644 --- a/Bender.yml +++ b/Bender.yml @@ -15,7 +15,7 @@ dependencies: axi: { git: https://github.com/pulp-platform/axi.git, version: 0.39.1 } cheshire: { git: https://github.com/pulp-platform/cheshire.git, rev: d6274a52dab68d12765b64d670d528774eb36c2c } # branch: idma-rebase hyperbus: { git: https://github.com/pulp-platform/hyperbus.git, rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh - dyn_mem: { git: https://github.com/pulp-platform/dyn_spm.git, rev: 480590062742230dc9bd4050358a15b4747bdf34 } # branch: main + dyn_mem: { git: https://github.com/pulp-platform/dyn_spm.git, rev: 6753d2046da6dfc8efbef5e6f22053a621f111d9 } # branch: astral safety_island: { git: https://github.com/pulp-platform/safety_island.git, rev: aaef55c798ab53560faaf451a86668fa1e6d0f3b } # branch: carfield pulp_cluster: { git: https://github.com/pulp-platform/pulp_cluster.git, rev: 1a167ec4ec46fa4a0c3d054b1213c0e6bc15d075 } # branch: astral opentitan: { git: https://github.com/pulp-platform/opentitan.git, rev: faca6f28e20195e9b56eb822c58bec4a3a19dd4f } # branch: mc/astral From ac12bceb5ca81ddf8beccd3620db7341631f170c Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 18 Oct 2024 15:38:36 +0200 Subject: [PATCH 5/6] Fix JTAG connections. --- .../xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv index d2160f99..d0c37982 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv +++ b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv @@ -32,6 +32,7 @@ module carfield_xilinx input logic jtag_tms_i, input logic jtag_tdi_i, output logic jtag_tdo_o, + output logic jtag_ot_tdo_o, input logic jtag_trst_ni, output logic jtag_vdd_o, output logic jtag_gnd_o, @@ -716,20 +717,20 @@ module carfield_xilinx .jtag_trst_ni (jtag_trst_ni), .jtag_tms_i (jtag_tms_i), .jtag_tdi_i (jtag_tdi_i), - .jtag_tdo_o (jtag_host_to_safety), + .jtag_tdo_o (jtag_tdo_o), .jtag_tdo_oe_o (), // Secure Subsystem JTAG Interface .jtag_ot_tck_i (jtag_tck_i), .jtag_ot_trst_ni (jtag_trst_ni), .jtag_ot_tms_i (jtag_tms_i), - .jtag_ot_tdi_i (jtag_safety_to_ot), - .jtag_ot_tdo_o (jtag_tdo_o), // Take in account when they are unactivated + .jtag_ot_tdi_i (jtag_tdi_i), + .jtag_ot_tdo_o (jtag_ot_tdo_o), // Take in account when they are unactivated .jtag_ot_tdo_oe_o (), // Safety Island JTAG Interface .jtag_safety_island_tck_i (jtag_tck_i), .jtag_safety_island_trst_ni(jtag_trst_ni), .jtag_safety_island_tms_i (jtag_tms_i), - .jtag_safety_island_tdi_i (jtag_host_to_safety), + .jtag_safety_island_tdi_i (jtag_tdi_i), .jtag_safety_island_tdo_o (jtag_safety_to_ot), .bootmode_safe_isln_i (boot_mode_safety), // UART Interface From dee83b40d5e6bda246f4bcf492d23c26cf1b0183 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 31 Oct 2024 15:28:04 +0100 Subject: [PATCH 6/6] Adjust constraints. --- target/xilinx/constraints/carfield.xdc | 11 +++++++++++ target/xilinx/flavor_bd/constraints/vcu118.xdc | 14 +++++++------- .../xilinx_ips/carfield_ip/src/carfield_xilinx.sv | 2 +- target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl | 6 +++--- 4 files changed, 22 insertions(+), 11 deletions(-) diff --git a/target/xilinx/constraints/carfield.xdc b/target/xilinx/constraints/carfield.xdc index 6b05a217..66061f98 100644 --- a/target/xilinx/constraints/carfield.xdc +++ b/target/xilinx/constraints/carfield.xdc @@ -16,6 +16,8 @@ set_property DONT_TOUCH TRUE [get_cells gen_domain_clock_mux[*].i_clk_mux] # TODO Check this set_false_path -from [get_pins gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].clock_has_been_disabled_q_reg[*]/C] -to [get_pins gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].clock_has_been_disabled_q_reg[*]/D] set_false_path -from [get_pins gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].clock_has_been_disabled_q_reg[*]/C] -to [get_pins gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].glitch_filter_q_reg[*][*]/D] +set_false_path -from [get_pins gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].gate_en_q_reg/C] +set_false_path -from [get_pins gen_domain_clock_mux[*].i_clk_div/gate_en_q_reg/C] # Enable all clocks (clk_en register) set_property DONT_TOUCH TRUE [get_cells i_carfield_reg_top/u_*_clk_sel] @@ -38,6 +40,8 @@ set_property CLOCK_BUFFER_TYPE NONE $all_in_mux # No max delay on sw reset since clock can be gated anyways set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {ORIG_REF_NAME=="rstgen" || REF_NAME=="rstgen"}] set_false_path -through [get_pins -of_objects [get_cells -hier i_carfield_rstgen] -filter {DIRECTION==OUT}] +set_false_path -from [get_pins i_carfield_rstgen/gen_rstgen_for_domains[*].i_rstgen/i_rstgen_bypass/synch_regs_q_reg*/C] +set_false_path -through [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[*]/*] set_false_path -hold -through [get_pins -filter {DIRECTION==OUT} -of_objects [get_cells -hier -filter {REF_NAME == rstgen || ORIG_REF_NAME == rstgen}]] set_false_path -setup -hold -from [get_pins -of_objects [get_cells -hier -filter {NAME=~*i_carfield_reg_top/u_*_rst/*}] -filter {IS_CLOCK}] -to [get_clocks *domain_clk] @@ -59,6 +63,13 @@ set_max_delay -datapath -from [get_pins i_host_rstgen/i_rstgen_bypass/synch_regs # Hold and max delay on 2 phases and 2 phases clearable set_max_delay -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME =~ cdc_2phase_src* || ORIG_REF_NAME =~ cdc_2phase_src*}]] $SOC_TCK set_false_path -hold -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME =~ cdc_2phase_src* || ORIG_REF_NAME =~ cdc_2phase_src*}]] +set_false_path -from [get_pins i_cheshire_wrap/gen_ext_slv_src_cdc[*].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_src_ar/*/C] +set_false_path -from [get_pins i_cheshire_wrap/gen_ext_slv_src_cdc[*].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_src_aw/*/C] +set_false_path -from [get_pins i_cheshire_wrap/gen_ext_slv_src_cdc[*].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_src_w/*/C] +set_false_path -from [get_pins gen_periph.i_cdc_dst_peripherals/i_cdc_fifo_gray_dst_ar/*/C] +set_false_path -from [get_pins gen_periph.i_cdc_dst_peripherals/i_cdc_fifo_gray_dst_w/*/C] +set_false_path -from [get_pins gen_l2.i_reconfigurable_l2/gen_cdc_fifos[*].i_dst_cdc/i_cdc_fifo_gray_dst_w/*/C] +set_false_path -from [get_pins gen_l2.i_reconfigurable_l2/i_reg_cdc_dst/*/C] # Hold and max delay on 4 phases set_max_delay -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME == cdc_4phase_src || ORIG_REF_NAME == cdc_4phase_src}]] $SOC_TCK diff --git a/target/xilinx/flavor_bd/constraints/vcu118.xdc b/target/xilinx/flavor_bd/constraints/vcu118.xdc index 76f65cbb..f9001c66 100644 --- a/target/xilinx/flavor_bd/constraints/vcu118.xdc +++ b/target/xilinx/flavor_bd/constraints/vcu118.xdc @@ -2,16 +2,16 @@ set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}] # Create system clocks -#create_clock -period 4 -name sys_clk [get_pins design_1_i/util_ds_buf_0/IBUF_OUT] +create_clock -period 4 -name sys_clk [get_pins design_1_i/util_ds_buf_0/IBUF_OUT] set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins design_1_i/util_ds_buf_0/IBUF_OUT] -#create_clock -period 4 -name pcie_clk [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]] -#create_clock -period 4 -name pcie_clk_div [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]] -#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]] -#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]] +create_clock -period 4 -name pcie_clk [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]] +create_clock -period 4 -name pcie_clk_div [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]] # PCIe clock LOC -#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0P]] [get_ports pcie_refclk_clk_p[0]] -#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0N]] [get_ports pcie_refclk_clk_n[0]] +set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0P]] [get_ports pcie_refclk_clk_p[0]] +set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0N]] [get_ports pcie_refclk_clk_n[0]] # VCU128 Rev1.0 XDC # Date: 01/24/2018 diff --git a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv index d0c37982..42fabfe7 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv +++ b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv @@ -222,7 +222,7 @@ module carfield_xilinx assign soc_clk = clk_50; assign alt_clk = clk_20; assign host_clk = soc_clk; - assign periph_clk = soc_clk; + assign periph_clk = clk_10; ///////////////////// // Reset Generator // diff --git a/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl b/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl index b61bbc5b..9bb06d8c 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl +++ b/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl @@ -21,9 +21,9 @@ add_files -fileset constrs_1 constraints/ooc_carfield_ip.xdc set_property USED_IN {synthesis out_of_context} [get_files ooc_carfield_ip.xdc] import_files -fileset constrs_1 -norecurse constraints/carfield_xilinx_ip.xdc # General constraints -# import_files -fileset constrs_1 -norecurse ../../constraints/carfield.xdc -# set_property SCOPED_TO_REF carfield [get_files carfield.xdc] -# set_property processing_order LATE [get_files carfield.xdc] +import_files -fileset constrs_1 -norecurse ../../constraints/carfield.xdc +set_property SCOPED_TO_REF carfield [get_files carfield.xdc] +set_property processing_order LATE [get_files carfield.xdc] # Package IP set_property top carfield_xilinx_ip [current_fileset]