The code to handle breakpoints in target-mips/translate.c does not appear to account for 16-bit microMIPS instructions (or 16-bit MIPS16 instructions). The offending code is the pc += 4 in the following fragment. While this looks like a bug it does not seem to affect the ability to debug code for some reason i.e. GDB successfully single steps through 16-bit instructions and can breakpoint 16-bit instructions. The comment suggests this code is only present to ensure the 'tb' is flushed and perhaps flushing more than necessary is not a problem. Presumably the PC to resume from is stashed as part of raising the exception.
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == ctx.pc) {
save_cpu_state(&ctx, 1);
ctx.bstate = BS_BRANCH;
gen_helper_0e0i(raise_exception, EXCP_DEBUG);
/* Include the breakpoint location or the tb won't
* be flushed when it must be. */
ctx.pc += 4;
goto done_generating;
}
}
}
The code to handle breakpoints in target-mips/translate.c does not appear to account for 16-bit microMIPS instructions (or 16-bit MIPS16 instructions). The offending code is the pc += 4 in the following fragment. While this looks like a bug it does not seem to affect the ability to debug code for some reason i.e. GDB successfully single steps through 16-bit instructions and can breakpoint 16-bit instructions. The comment suggests this code is only present to ensure the 'tb' is flushed and perhaps flushing more than necessary is not a problem. Presumably the PC to resume from is stashed as part of raising the exception.