Slave signals are multiply driven issue

[Nadeem-Ahmed-S]

When no of slaves is greater than 1 then the slave signals i.e., pready, prdata, pslverr are multiply driven to the interface.
The issue is different based on simulators.

1. Questa-sim :
   a. Resulted in warnings when slave signals i.e., pready, prdata, pslverr are declared as logic type in the interface.
   b. If the same signals are declared as wire, then it is entering into the infinite loop.
2. Cadence :
   a. Resulted in compilation errors when slave signals i.e., pready, prdata, pslverr are declared as logic type in the interface.
   b. If the same signals are declared as wire, then it is completely working fine.