Greetings,
In the main README.md of the repo, a strategy of breaking down VHDL packages is mentioned and then a one-by-one convertion to Verilog equivalents.
Would you mind providing a minimum working example with a script at a language of your choice? I just want to understand the process better. Assuming a package that has records, components, consts etc. how would one proceed with this?
Thank you in advance
Greetings,
In the main README.md of the repo, a strategy of breaking down VHDL packages is mentioned and then a one-by-one convertion to Verilog equivalents.
Would you mind providing a minimum working example with a script at a language of your choice? I just want to understand the process better. Assuming a package that has records, components, consts etc. how would one proceed with this?
Thank you in advance