Generated Verilog fails to compile with iverilog v13.x due to parameter declaration order

[ApexGP]

After updating to iverilog v13.0-1 (on Arch Linux), I noticed that the Verilog code generated by vhd2vl no longer compiles if a VHDL generic is used to define a port width.

Modern versions of iverilog have tightened "declaration before use" rules. Currently, vhd2vl translates generics into parameters inside the module body, which is too late for parameters used in the port list when using Non-ANSI style declarations.

For example, in concat.vhd:

entity repeat_concat is
    generic (
        W : integer := 8
    );
    port (
        expY : in  std_logic_vector(26 downto 0);
        y    : out std_logic_vector(W + 24 downto 0)
    );
end entity;

Now we get

module repeat_concat(
    input  wire [26:0] expY,
    output wire [W + 24:0] y  
);

parameter [31:0] W = 8; 

// ...
endmodule

And error message from iverilog

error: Unable to bind parameter `W' in `repeat_concat'
error: Dimensions must be constant.
error: This MSB expression violates the rule: (W)+('sd24)
Check for declaration after use.

Under the new standards, the expected output should be

module repeat_concat #(
    parameter [31:0] W = 8
)(
    input  wire [26:0] expY,
    output wire [W + 24:0] y
);
// ...
endmodule

The generator should be updated to support ANSI-style module headers where parameters are declared before the port list, or ensure that parameters are defined in a way that satisfies modern compiler binding rules.