From c1f9acf916c6749eb24c94604284e88f08d60213 Mon Sep 17 00:00:00 2001
From: Ivan Pechenezhskiy <pechenezhski@wisc.edu>
Date: Tue, 26 Jan 2016 22:53:45 -0600
Subject: [PATCH 1/6] Fix bug #309

---
 fpgalib/adc.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpgalib/adc.py b/fpgalib/adc.py
index d97812bb..4635c027 100644
--- a/fpgalib/adc.py
+++ b/fpgalib/adc.py
@@ -955,7 +955,7 @@ def registerReadback(self):
         @inlineCallbacks
         def func():
             # build registry packet
-            regs = self.regRun(self.RUN_MODE_REGISTER_READBACK, 0) # 0 reps?
+            regs = self.regRun(self.RUN_MODE_REGISTER_READBACK, {}, 0)
             
             p = self.makePacket("registerReadback")
             p.write(regs.tostring())

From ea9a2ca23bf04609f961bd7252d540690aacd7da Mon Sep 17 00:00:00 2001
From: Ivan Pechenezhskiy <pechenezhski@wisc.edu>
Date: Tue, 26 Jan 2016 22:55:03 -0600
Subject: [PATCH 2/6] Allow access to AD clock bits, improve readability

---
 fpgalib/adc.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fpgalib/adc.py b/fpgalib/adc.py
index 4635c027..1e1c47a4 100644
--- a/fpgalib/adc.py
+++ b/fpgalib/adc.py
@@ -1052,7 +1052,8 @@ def processReadback(resp):
         a = np.fromstring(resp, dtype='<u1')
         return {
             'build': a[0],
-            'noPllLatch': a[1]&1 == 1,
+            'noPllLatch': bool(a[1] & 1),
+            'dClkBits': a[1] >> 1 & 0b1111,
             'executionCounter': int(a[2]) + int(a[3] << 8),
             'nPackets': a[4],
             'badPackets': a[5]

From 4ba6826f163c62684ee198639299f6a0cfe2fd75 Mon Sep 17 00:00:00 2001
From: Ivan Pechenezhskiy <pechenezhski@wisc.edu>
Date: Thu, 28 Jan 2016 00:29:02 -0600
Subject: [PATCH 3/6] Make the bitwise operation priorities explicit

---
 fpgalib/adc.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpgalib/adc.py b/fpgalib/adc.py
index 1e1c47a4..94b258e7 100644
--- a/fpgalib/adc.py
+++ b/fpgalib/adc.py
@@ -1053,7 +1053,7 @@ def processReadback(resp):
         return {
             'build': a[0],
             'noPllLatch': bool(a[1] & 1),
-            'dClkBits': a[1] >> 1 & 0b1111,
+            'dClkBits': (a[1] >> 1) & 0b1111,
             'executionCounter': int(a[2]) + int(a[3] << 8),
             'nPackets': a[4],
             'badPackets': a[5]

From 3b7d395ace3908b4f3047d7f277570ae89fa7db5 Mon Sep 17 00:00:00 2001
From: Ivan Pechenezhskiy <pechenezhski@wisc.edu>
Date: Thu, 28 Jan 2016 01:09:28 -0600
Subject: [PATCH 4/6] Use named arguments in regRun calls

Where applicable, swap the position of filterStretchLen and
filterStretchAt to be consistent with the regRun method definition.
---
 fpgalib/adc.py | 46 ++++++++++++++++++++++++----------------------
 1 file changed, 24 insertions(+), 22 deletions(-)

diff --git a/fpgalib/adc.py b/fpgalib/adc.py
index 94b258e7..906dc213 100644
--- a/fpgalib/adc.py
+++ b/fpgalib/adc.py
@@ -227,13 +227,10 @@ def runCalibrate(self):
         @inlineCallbacks
         def func():
             # build register packet
-            filterFunc=np.zeros(self.FILTER_LEN, dtype='<u1')
-            filterStretchLen=0
-            filterStretchAt=0
-            demods={}
-            regs = self.regRun(RUN_MODE_CALIBRATE, 1, filterFunc,
-                filterStretchLen, filterStretchAt, demods)
-    
+            filterFunc = np.zeros(self.FILTER_LEN, dtype='<u1')
+            regs = self.regRun(mode=RUN_MODE_CALIBRATE, reps=1, 
+                    filterFunc=filterFunc, filterStretchAt=0,
+                    filterStretchLen=0, demods={})
             # create packet for the ethernet server
             p = self.makePacket()
             p.write(regs.tostring()) # send registry packet
@@ -305,9 +302,10 @@ def runPacket(self, page, slave, delay, sync):
         
         filterFunc, filterStretchLen, filterStretchAt = self.filter
         startDelay = self.startDelay + delay
-        regs = self.dev.regRun(self.mode, self.reps, filterFunc,
-                               filterStretchLen, filterStretchAt,
-                               self.channels, startDelay)
+        regs = self.dev.regRun(mode=self.mode, reps=self.reps,
+                filterFunc=filterFunc, filterStretchAt=filterStretchAt,
+                filterStretchLen=filterStretchLen, demods=self.channels,
+                startDelay=startDelay)
         return regs
     
     def collectPacket(self, seqTime, ctx):
@@ -441,9 +439,10 @@ def runAverage(self, filterFunc, filterStretchLen, filterStretchAt,
         @inlineCallbacks
         def func():
             # build registry packet
-            regs = self.regRun(self, self.RUN_MODE_AVERAGE_AUTO, 1, filterFunc,
-                filterStretchLen, filterStretchAt, demods)
-            
+            regs = self.regRun(self, mode=self.RUN_MODE_AVERAGE_AUTO, 
+                    reps=1, filterFunc=filterFunc,
+                    filterStretchAt=filterStretchAt,
+                    filterStretchLen=filterStretchLen, demods=demods)
             p = self.makePacket()
             p.write(regs.tostring())
             p.timeout(T.Value(10, 's'))
@@ -460,9 +459,10 @@ def runDemod(self, filterFunc, filterStretchLen, filterStretchAt, demods):
         @inlineCallbacks
         def func():
             # build register packet
-            regs = self.regRun(self.RUN_MODE_DEMOD_AUTO, 1, filterFunc,
-                filterStretchLen, filterStretchAt, demods)
-    
+            regs = self.regRun(mode=self.RUN_MODE_DEMOD_AUTO, reps=1,
+                    filterFunc=filterFunc, 
+                    filterStretchAt=filterStretchAt,
+                    filterStretchLen=filterStretchLen, demods=demods)
             # create packet for the ethernet server
             p = self.makePacket()
             self.makeFilter(filterFunc, p) # upload filter function
@@ -650,7 +650,8 @@ def runPacket(self, page, slave, delay, sync):
         This is cheesey and ought to be fixed.
         """
         startDelay = self.startDelay + delay
-        regs = self.dev.regRun(self.mode, self.info, self.reps, startDelay=startDelay)
+        regs = self.dev.regRun(mode=self.mode, info=self.info,
+                reps=self.reps, startDelay=startDelay)
         # print("ADC run packet: %s" % (regs,))
         return regs    
     
@@ -955,8 +956,8 @@ def registerReadback(self):
         @inlineCallbacks
         def func():
             # build registry packet
-            regs = self.regRun(self.RUN_MODE_REGISTER_READBACK, {}, 0)
-            
+            regs = self.regRun(mode=self.RUN_MODE_REGISTER_READBACK,
+                    info={}, reps=0)
             p = self.makePacket("registerReadback")
             p.write(regs.tostring())
             p.timeout(T.Value(10, 's'))
@@ -973,7 +974,8 @@ def runAverage(self):
         @inlineCallbacks
         def func():
             # build registry packet
-            regs = self.regRun(self.RUN_MODE_AVERAGE_AUTO, {}, 1)
+            regs = self.regRun(mode=self.RUN_MODE_AVERAGE_AUTO, info={},
+                    reps=1)
             p = self.makePacket("runAverage")
             p.write(regs.tostring())
             p.timeout(T.Value(10, 's'))
@@ -1000,8 +1002,8 @@ def runDemod(self, info):
         @inlineCallbacks
         def func():
             # build register packet
-            regs = self.regRun(self.RUN_MODE_DEMOD_AUTO, info, 1)
-    
+            regs = self.regRun(mode=self.RUN_MODE_DEMOD_AUTO, info=info,
+                    reps=1)
             # create packet for the ethernet server
             p = self.makePacket("runDemod packet")
             self.makeTriggerTable(triggerTable,p)

From c2320b2d32a07f01cf3391cb11477dc58b7f5e94 Mon Sep 17 00:00:00 2001
From: Ivan Pechenezhskiy <pechenezhski@wisc.edu>
Date: Sat, 6 Feb 2016 20:26:01 -0600
Subject: [PATCH 5/6] Remove an unnecessary self reference when calling a
 method

This has been added to the brunch per @maffoo suggestion.
---
 fpgalib/adc.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpgalib/adc.py b/fpgalib/adc.py
index 906dc213..4d40b8fc 100644
--- a/fpgalib/adc.py
+++ b/fpgalib/adc.py
@@ -439,7 +439,7 @@ def runAverage(self, filterFunc, filterStretchLen, filterStretchAt,
         @inlineCallbacks
         def func():
             # build registry packet
-            regs = self.regRun(self, mode=self.RUN_MODE_AVERAGE_AUTO, 
+            regs = self.regRun(mode=self.RUN_MODE_AVERAGE_AUTO, 
                     reps=1, filterFunc=filterFunc,
                     filterStretchAt=filterStretchAt,
                     filterStretchLen=filterStretchLen, demods=demods)

From 6c665de5ca0305d35a49d1a9ce67ca0fb860860b Mon Sep 17 00:00:00 2001
From: Ivan Pechenezhskiy <pechenezhski@wisc.edu>
Date: Tue, 16 Feb 2016 19:24:22 -0600
Subject: [PATCH 6/6] Bug fix version bump

This server heavily relays upon  fpgalib.adc. This warrants a bug fix
version number bump.
---
 ghz_fpga_server.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ghz_fpga_server.py b/ghz_fpga_server.py
index c6dd9a94..16174da8 100644
--- a/ghz_fpga_server.py
+++ b/ghz_fpga_server.py
@@ -177,7 +177,7 @@
 ### BEGIN NODE INFO
 [info]
 name = GHz FPGAs
-version = 5.2.0
+version = 5.2.1
 description = Talks to DAC and ADC boards
 
 [startup]