From f23096de26f57b15fc4d79358ffffb042099dfa3 Mon Sep 17 00:00:00 2001 From: Lucas Kramer Date: Fri, 9 Jan 2026 09:34:28 -0800 Subject: [PATCH 1/5] Support port spltting methods with multiple output ports --- src/Libraries/Base1/Prelude.bs | 240 +++++++++++------- src/comp/AAddScheduleDefs.hs | 12 +- src/comp/ACheck.hs | 3 +- src/comp/AConv.hs | 204 +++++++++------ src/comp/ADropUndet.hs | 2 + src/comp/ADumpSchedule.hs | 2 +- src/comp/AExpand.hs | 6 + src/comp/AExpr2STP.hs | 29 ++- src/comp/AExpr2Util.hs | 14 +- src/comp/AExpr2Yices.hs | 30 ++- src/comp/ANoInline.hs | 2 +- src/comp/APaths.hs | 134 ++++++---- src/comp/ARankMethCalls.hs | 3 +- src/comp/ARenameIO.hs | 4 +- src/comp/ASchedule.hs | 12 +- src/comp/AState.hs | 99 +++++--- src/comp/ASyntax.hs | 156 +++++++----- src/comp/ASyntaxUtil.hs | 41 +++ src/comp/ATaskSplice.hs | 7 +- src/comp/AUses.hs | 2 + src/comp/AVeriQuirks.hs | 7 + src/comp/AVerilog.hs | 8 +- src/comp/AVerilogUtil.hs | 12 +- src/comp/BackendNamingConventions.hs | 54 ++-- src/comp/BinData.hs | 8 + src/comp/CSyntax.hs | 6 +- src/comp/CType.hs | 10 +- src/comp/CVPrint.hs | 7 +- src/comp/DisjointTest.hs | 30 ++- src/comp/GenWrap.hs | 34 ++- src/comp/IExpand.hs | 93 ++++--- src/comp/IExpandUtils.hs | 15 +- src/comp/IInlineFmt.hs | 22 +- src/comp/ISplitIf.hs | 6 +- src/comp/ISyntax.hs | 10 +- src/comp/ISyntaxUtil.hs | 48 ++-- src/comp/ITransform.hs | 4 +- src/comp/IfcBetterInfo.hs | 8 +- src/comp/LambdaCalc.hs | 12 +- src/comp/LambdaCalcUtil.hs | 13 +- src/comp/Parser/BSV/CVParser.lhs | 8 +- src/comp/Parser/BSV/CVParserImperative.lhs | 16 +- src/comp/Parser/Classic/CParser.hs | 2 +- src/comp/PreStrings.hs | 2 + src/comp/SAL.hs | 13 +- src/comp/SignalNaming.hs | 7 + src/comp/SimCCBlock.hs | 29 ++- src/comp/SimCOpt.hs | 1 + src/comp/SimExpand.hs | 11 +- src/comp/SimMakeCBlocks.hs | 47 +++- src/comp/SimPackage.hs | 12 +- src/comp/SimPackageOpt.hs | 13 +- src/comp/SystemCWrapper.hs | 8 +- src/comp/TCheck.hs | 51 ++-- src/comp/TopUtils.hs | 4 +- src/comp/Type.hs | 23 +- src/comp/VIOProps.hs | 17 +- src/comp/VModInfo.hs | 22 +- src/comp/bluetcl.hs | 167 ++++++------ src/comp/showrules.hs | 2 +- .../module.tcl.bluetcl-bh-out.expected | 6 +- .../commands/module.tcl.bluetcl-out.expected | 6 +- .../submodule.tcl.bluetcl-bh-out.expected | 68 +++-- .../submodule.tcl.bluetcl-out.expected | 68 +++-- .../inhigh.tcl.bluetcl-bh-out.expected | 4 +- .../inhigh.tcl.bluetcl-out.expected | 4 +- .../prims.tcl.bluetcl-bh-out.expected | 46 ++-- .../port_types/prims.tcl.bluetcl-out.expected | 46 ++-- .../zero_size.tcl.bluetcl-bh-out.expected | 4 +- .../zero_size.tcl.bluetcl-out.expected | 4 +- .../bluespec_inc/b1354/mkMulti.v.expected | 96 +++---- .../bsc.bugs/bluespec_inc/b1490/b1490.exp | 2 +- .../bsc.bugs/bluespec_inc/b1610/Test2.bs | 2 +- .../bsc.bugs/bluespec_inc/b1758/b1758.exp | 12 +- .../bluespec_inc/b262/sysBug262Opt.v.expected | 6 +- .../bluespec_inc/b292/mkDesign.v.expected | 22 +- .../bluespec_inc/b293/mkDesign1.v.expected | 16 +- .../bluespec_inc/b302/mkDesign.v.expected | 113 ++++----- .../bsc.codegen/foreign/BDPIActionValue_.bsv | 2 +- testsuite/bsc.doc/UserGuide_mkGCD.v.expected | 8 +- .../bsc.evaluator/mkTest.atsexpand.expected | 8 +- .../mkTest.atsexpand.nolift.expandif.expected | 8 +- ...ormConstantAcrossEquals.atsexpand.expected | 8 +- .../bsc.evaluator/sysShiftMult.ats.expected | 30 +-- .../EResources.bs.bsc-vcomp-out.expected | 4 +- .../lc-sysMultiArityConcat.out.expected | 8 +- .../lc-sysStructs.out.expected | 18 +- .../lambda_calculus/lc-sysTb.out.expected | 50 ++-- .../sal/CTX_sysMultiArityConcat.sal.expected | 10 +- .../bsc.misc/sal/CTX_sysStructs.sal.expected | 18 +- testsuite/bsc.misc/sal/CTX_sysTb.sal.expected | 50 ++-- ...alNum_ENotation.bsv.bsc-vcomp-out.expected | 2 +- .../Method.bsv.bsc-vcomp-out.expected | 6 +- ...thodActionValue.bsv.bsc-vcomp-out.expected | 12 +- .../MethodRead.bsv.bsc-vcomp-out.expected | 12 +- .../NoInline.bsv.bsc-vcomp-out.expected | 8 +- .../SplitIf.bsv.bsc-sched-out.expected | 4 +- .../SplitIf2.bsv.bsc-sched-out.expected | 8 +- .../AVArgUse_C.bsv.bsc-sched-out.expected | 2 +- .../AVArgUse_SBR.bsv.bsc-sched-out.expected | 2 +- .../sysStateNameTest.atsexpand.expected | 2 +- .../sysStateNameTest2.atsexpand.expected | 2 +- .../statename/sysUseMod2.atsexpand.expected | 2 +- .../sysUseMod2Arrow.atsexpand.expected | 2 +- .../DummyInRuleQual.bs.bsc-vcomp-out.expected | 2 +- testsuite/bsc.verilog/astate/astate.exp | 6 +- testsuite/bsc.verilog/inline/inline.exp | 4 +- ...ne_ResNotInBits.bsv.bsc-vcomp-out.expected | 6 - testsuite/bsc.verilog/splitports/DeepSplit.bs | 26 +- .../bsc.verilog/splitports/InstanceSplit.bs | 23 +- .../bsc.verilog/splitports/ShallowSplit.bs | 23 +- .../bsc.verilog/splitports/splitports.exp | 42 +++ .../splitports/sysDeepSplit.out.expected | 5 + .../splitports/sysInstanceSplit.out.expected | 4 + .../splitports/sysShallowSplit.out.expected | 4 + 115 files changed, 1729 insertions(+), 1091 deletions(-) diff --git a/src/Libraries/Base1/Prelude.bs b/src/Libraries/Base1/Prelude.bs index 7d6472321..04aba7f0d 100644 --- a/src/Libraries/Base1/Prelude.bs +++ b/src/Libraries/Base1/Prelude.bs @@ -259,8 +259,8 @@ package Prelude( NumConArg(..), StarConArg(..), OtherConArg(..), MetaConsNamed(..), MetaConsAnon(..), MetaField(..), - WrapField(..), WrapMethod(..), WrapPorts(..), - Port(..), unPort, SplitPorts(..) + WrapField(..), WrapMethod(..), WrapPorts(..), NonEmptyBits(..), + Port(..), unPort, SplitPorts(..), PrimSeqTupleBits(..) ) where infixr 0 $ @@ -920,9 +920,9 @@ fromPrimAction a = ActionValue (\aw -> AVStruct { avValue = _; avAction = a; avW type Action = ActionValue () --X@ \begin{verbatim} ---X@ typedef ActionValue_#(0) Action_; +--X@ typedef ActionValue_#(void) Action_; --X@ \end{verbatim} -type Action_ = ActionValue_ 0 +type Action_ = ActionValue_ () --@ An empty \te{Action}. --@ \index{noAction@\te{noAction} (empty action)} @@ -939,23 +939,36 @@ noAction = fromPrimAction primNoActions (:<-) :: Reg a -> ActionValue a -> Action (:<-) r av = av `bind` r._write ---X@ A primitive \te{ActionValue} of bits +--X@ A primitive \te{ActionValue} of bits. +--X@ The type parameter should be either (), Bit n, or a tuple of Bit n. --X@ \begin{verbatim} ---X@ struct ActionValue_ #(type n); +--X@ struct ActionValue_ #(type a; --X@ \end{verbatim} -struct ActionValue_ n +struct ActionValue_ a = - avValue_ :: Bit n + avValue_ :: a avAction_ :: PrimAction -toActionValue_ :: (Bits a n) => ActionValue a -> ActionValue_ n -toActionValue_ (ActionValue av) = +toActionValue_ :: (Bits a n) => ActionValue a -> ActionValue_ (Bit n) +toActionValue_ = bitsToActionValue_ ∘ fmap pack + +fromActionValue_ :: (Bits a n) => ActionValue_ (Bit n) -> ActionValue a +fromActionValue_ = fmap unpack ∘ bitsFromActionValue_ + +toAction_ :: Action -> Action_ +toAction_ = bitsToActionValue_ + +fromAction_ :: Action_ -> Action +fromAction_ = bitsFromActionValue_ + +bitsToActionValue_ :: ActionValue a -> ActionValue_ a +bitsToActionValue_ (ActionValue av) = letseq av' = av ActionWorld - in ActionValue_ { avValue_ = pack av'.avValue; avAction_ = av'.avAction} + in ActionValue_ { avValue_ = av'.avValue; avAction_ = av'.avAction} -fromActionValue_ :: (Bits a n) => ActionValue_ n -> ActionValue a -fromActionValue_ av_ = ActionValue (\aw -> - AVStruct { avValue = unpack av_.avValue_; avAction = av_.avAction_; avWorld = aw}) +bitsFromActionValue_ :: ActionValue_ a -> ActionValue a +bitsFromActionValue_ av_ = ActionValue (\ aw -> + AVStruct { avValue = av_.avValue_; avAction = av_.avAction_; avWorld = aw}) -- ---------------------------------------------------------------- @@ -2586,7 +2599,7 @@ messageM s = do --@ endfunction: id --@ \end{libverbatim} id :: a -> a -id x = x +id _x = _x --@ Make a function curried --@ \index{curry@\te{curry} (Prelude function)} @@ -3223,9 +3236,9 @@ $time = fromActionValue_ (__time__) $stime :: ActionValue (Bit 32) $stime = fromActionValue_ (__stime__) -foreign __time__ :: ActionValue_ 64 = "$time" +foreign __time__ :: ActionValue_ (Bit 64) = "$time" -foreign __stime__ :: ActionValue_ 32 = "$stime" +foreign __stime__ :: ActionValue_ (Bit 32) = "$stime" -- File type and system tasks which use it data File = InvalidFile | @@ -3279,7 +3292,7 @@ foreign $fflush :: PrimAction = "$fflush" -- Type checking is done by bsc -- $fopen :: String -> ActionValue#(File) -- $fopen :: String -> String -> ActionValue#(File) -foreign $fopen :: ActionValue_ 32 = "$fopen" +foreign $fopen :: ActionValue_ (Bit 32) = "$fopen" -- The arguments for these are handled internally @@ -3288,16 +3301,16 @@ foreign $fwriteb :: PrimAction = "$fwriteb" foreign $fwriteo :: PrimAction = "$fwriteo" foreign $fwriteh :: PrimAction = "$fwriteh" -foreign $swriteAV :: ActionValue_ n = "$swriteAV" +foreign $swriteAV :: ActionValue_ (Bit n) = "$swriteAV" foreign $swrite :: PrimAction = "$swrite" -foreign $swritebAV :: ActionValue_ n = "$swritebAV" +foreign $swritebAV :: ActionValue_ (Bit n) = "$swritebAV" foreign $swriteb :: PrimAction = "$swriteb" -foreign $swriteoAV :: ActionValue_ n = "$swriteoAV" +foreign $swriteoAV :: ActionValue_ (Bit n) = "$swriteoAV" foreign $swriteo :: PrimAction = "$swriteo" -foreign $swritehAV :: ActionValue_ n = "$swritehAV" +foreign $swritehAV :: ActionValue_ (Bit n) = "$swritehAV" foreign $swriteh :: PrimAction = "$swriteh" -foreign $sformatAV :: ActionValue_ n = "$sformatAV" +foreign $sformatAV :: ActionValue_ (Bit n) = "$sformatAV" foreign $sformat :: PrimAction = "$sformat" foreign $fdisplay :: PrimAction = "$fdisplay" @@ -3305,20 +3318,19 @@ foreign $fdisplayb :: PrimAction = "$fdisplayb" foreign $fdisplayo :: PrimAction = "$fdisplayo" foreign $fdisplayh :: PrimAction = "$fdisplayh" -foreign $random :: ActionValue_ 32 = "$random" +foreign $random :: ActionValue_ (Bit 32) = "$random" $fgetc :: File -> ActionValue (Int 32) -- to allow space for -1 $fgetc f = fromActionValue_ (__fgetc__ (pack f)) -foreign __fgetc__ :: Bit 32 -> ActionValue_ 32 = "$fgetc" +foreign __fgetc__ :: Bit 32 -> ActionValue_ (Bit 32) = "$fgetc" $fclose :: File -> Action -$fclose f = fromActionValue_ (__fclose__ (pack f)) +$fclose f = fromAction_ (__fclose__ (pack f)) foreign __fclose__ :: Bit 32 -> Action_ = "$fclose" $ungetc :: Bit 8 -> File -> ActionValue (Int 32) $ungetc c f = fromActionValue_ ( __fungetc__ c (pack f)) -foreign __fungetc__ :: Bit 8 -> Bit 32 -> ActionValue_ 32 = "$ungetc" - +foreign __fungetc__ :: Bit 8 -> Bit 32 -> ActionValue_ (Bit 32) = "$ungetc" -- "standard" file descriptors stdin :: File @@ -3333,7 +3345,7 @@ stdout_mcd = MCD 1 $test$plusargs :: String -> ActionValue Bool $test$plusargs x = fromActionValue_ (__testplusargs__ x) -foreign __testplusargs__ :: String -> ActionValue_ 1 = "$test$plusargs" +foreign __testplusargs__ :: String -> ActionValue_ (Bit 1) = "$test$plusargs" ------------------ @@ -3419,8 +3431,8 @@ class AppendTuple a b c | a b -> c where splitTuple :: c -> (a, b) instance AppendTuple a () a where - appendTuple x _ = x - splitTuple x = (x, ()) + appendTuple _x _ = _x + splitTuple _x = (_x, ()) -- The above instance should take precedence over the other cases that assume -- b is non-unit. To avoid overlapping instances, the below are factored out as @@ -3435,7 +3447,7 @@ class AppendTuple' a b c | a b -> c where instance AppendTuple' () a a where appendTuple' _ = id - splitTuple' x = ((), x) + splitTuple' _x = ((), _x) instance (AppendTuple'' a b c) => AppendTuple' a b c where appendTuple' = appendTuple'' @@ -3446,13 +3458,13 @@ class AppendTuple'' a b c | a b -> c where splitTuple'' :: c -> (a, b) instance AppendTuple'' a b (a, b) where - appendTuple'' a b = (a, b) + appendTuple'' _x _y = (_x, _y) splitTuple'' = id instance (AppendTuple'' a b c) => AppendTuple'' (h, a) b (h, c) where - appendTuple'' (x, y) z = (x, appendTuple'' y z) - splitTuple'' (x, y) = case splitTuple'' y of - (w, z) -> ((x, w), z) + appendTuple'' (_x, _y) _z = (_x, appendTuple'' _y _z) + splitTuple'' (_x, _y) = case splitTuple'' _y of + (_w, _z) -> ((_x, _w), _z) class TupleSize a n | a -> n where {} instance TupleSize () 0 where {} @@ -4466,18 +4478,16 @@ data (MetaField :: $ -> # -> *) name idx = MetaField deriving (FShow) --- Tag a method with metadata. --- Currently just the list of input port names. --- Should eventually include the output port names, when we support multiple output ports. -primitive primMethod :: List String -> a -> a +-- Tag a method with metadata: the input and output port names. +primitive primMethod :: List String -> List String -> a -> a -- Convert bewtween a field in an interface that is being synthesized, -- and a field in the corresponding field in the generated wrapper interface. -- Also takes the name of the field for error reporting purposes. class (WrapField :: $ -> * -> * -> *) name f w | name f -> w where - -- Given a proxy value for the field name, and the values of the prefix and arg_names pragmas, + -- Given a proxy value for the field name, and the values of the prefix, arg_names and result pragmas, -- converts a synthesized interface field value to its wrapper interface field. - toWrapField :: StrArg name -> String -> List String -> f -> w + toWrapField :: StrArg name -> String -> List String -> String -> f -> w -- Given a proxy value for the field name, converts a wrapper interface field value -- to its synthesized interface field. @@ -4488,35 +4498,39 @@ class (WrapField :: $ -> * -> * -> *) name f w | name f -> w where saveFieldPortTypes :: StrArg name -> f -> Maybe Name__ -> String -> List String -> String -> Module () instance (WrapMethod m w) => (WrapField name m w) where - toWrapField _ prefix names = - let baseNames = methodArgBaseNames (_ :: m) prefix names 1 - in primMethod (inputPortNames (_ :: m) baseNames) ∘ toWrapMethod + toWrapField _ prefix argNames resultName = + let argBaseNames = methodArgBaseNames (_ :: m) prefix argNames 1 + in primMethod + (inputPortNames (_ :: m) argBaseNames) + (outputPortNames (_ :: m) resultName) + ∘ toWrapMethod fromWrapField _ = fromWrapMethod - saveFieldPortTypes _ _ modName prefix names = - let baseNames = methodArgBaseNames (_ :: m) prefix names 1 - in saveMethodPortTypes (_ :: m) modName baseNames + saveFieldPortTypes _ _ modName prefix argNames resultName = + let baseNames = methodArgBaseNames (_ :: m) prefix argNames 1 + in saveMethodPortTypes (_ :: m) modName baseNames resultName -- TODO: It doesn't seem possible to have a PrimAction field in a synthesized interface, -- but this case was being handled in GenWrap. instance WrapField name PrimAction PrimAction where - toWrapField _ _ _ = id + toWrapField _ _ _ _ = id fromWrapField _ = id saveFieldPortTypes _ _ _ _ _ _ = return () instance WrapField name Clock Clock where - toWrapField _ _ _ = id + toWrapField _ _ _ _ = id fromWrapField _ = id saveFieldPortTypes _ _ _ _ _ _ = return () instance WrapField name Reset Reset where - toWrapField _ _ _ = id + toWrapField _ _ _ _ = id fromWrapField _ = id saveFieldPortTypes _ _ _ _ _ _ = return () instance (Bits a n) => WrapField name (Inout a) (Inout_ n) where - toWrapField _ _ _ = primInoutCast0 + toWrapField _ _ _ _ = primInoutCast0 fromWrapField _ = primInoutUncast0 - saveFieldPortTypes _ _ modName _ _ result = primSavePortType modName result $ typeOf (_ :: (Inout a)) + saveFieldPortTypes _ _ modName _ _ result = + primSavePortType modName result $ typeOf (_ :: (Inout a)) class WrapMethod m w | m -> w where -- Convert a synthesized interface method to its wrapper interface method. @@ -4531,6 +4545,9 @@ class WrapMethod m w | m -> w where -- Compute the list of input port names for a method, from the argument base names. inputPortNames :: m -> List String -> List String + -- Compute the list of input port names for a method, from the result base name. + outputPortNames :: m -> String -> List String + -- Save the port types for a method, given the module name, argument base names and result name. saveMethodPortTypes :: m -> Maybe Name__ -> List String -> String -> Module () @@ -4549,83 +4566,122 @@ instance (SplitPorts a p, TupleSize p n, WrapPorts p pb, WrapMethod b v, Curry ( (prefix +++ "_" +++ integerToString i) (methodArgBaseNames (_ :: b) prefix Nil $ i + 1) - inputPortNames _ (Cons h t) = checkPortNames (_ :: a) h `listPrimAppend` inputPortNames (_ :: b) t + inputPortNames _ (Cons h t) = + filterZeroWidthPorts (_ :: p) (checkPortNames (_ :: a) h) + `listPrimAppend` inputPortNames (_ :: b) t inputPortNames _ Nil = error "inputPortNames: empty arg names list" + outputPortNames _ = outputPortNames (_ :: b) + saveMethodPortTypes _ modName (Cons h t) result = do savePortTypes (_ :: p) modName $ checkPortNames (_ :: a) h saveMethodPortTypes (_ :: b) modName t result saveMethodPortTypes _ _ Nil _ = error "saveMethodPortTypes: empty arg names list" -instance (Bits a n) => WrapMethod (ActionValue a) (ActionValue_ n) where - toWrapMethod = toActionValue_ - fromWrapMethod = fromActionValue_ +instance (SplitPorts a p, TupleSize p n, WrapPorts p pb, PrimSeqTupleBits pb) => + WrapMethod (ActionValue a) (ActionValue_ pb) where + toWrapMethod = bitsToActionValue_ ∘ fmap (primDeepSeqTupleBits ∘ packPorts ∘ splitPorts) + fromWrapMethod = fmap (unsplitPorts ∘ unpackPorts) ∘ bitsFromActionValue_ methodArgBaseNames _ _ Nil _ = Nil methodArgBaseNames prx prefix argNames _ = primError (getEvalPosition prx) $ integerToString (listLength argNames) +++ " excess arg_names provided for method " +++ prefix inputPortNames _ Nil = Nil inputPortNames _ (Cons _ _) = error "inputPortNames: uncaught excess arg names" - saveMethodPortTypes _ modName _ result = primSavePortType modName result $ typeOf (_ :: a) + outputPortNames _ base = filterZeroWidthPorts (_ :: p) $ checkPortNames (_ :: a) base + saveMethodPortTypes _ modName _ result = + savePortTypes (_ :: p) modName $ checkPortNames (_ :: a) result -instance (Bits a n) => WrapMethod a (Bit n) where - toWrapMethod = pack - fromWrapMethod = unpack +instance (SplitPorts a p, TupleSize p n, WrapPorts p pb, PrimSeqTupleBits pb) => + WrapMethod a pb where + toWrapMethod = primDeepSeqTupleBits ∘ packPorts ∘ splitPorts + fromWrapMethod = unsplitPorts ∘ unpackPorts methodArgBaseNames _ _ Nil _ = Nil methodArgBaseNames prx prefix argNames _ = primError (getEvalPosition prx) $ integerToString (listLength argNames) +++ " excess arg_names provided for method " +++ prefix inputPortNames _ Nil = Nil inputPortNames _ (Cons _ _) = error "inputPortNames: uncaught excess arg names" - saveMethodPortTypes _ modName _ result = primSavePortType modName result $ typeOf (_ :: a) - -{- -Eventually, we should support splitting multiple output ports. -instance (SplitPorts a p, TupleSize p n, WrapPorts p pb) => WrapMethod (ActionValue a) (ActionValue pb) where - toWrapMethod = fmap packPorts - fromWrapMethod = fmap unpackPorts - outputPortNames _ base = checkPortNames (_ :: a) base - saveMethodPortTypes _ modName _ result = - savePortTypes (_ :: p) modName $ checkPortNames (_ :: a) result - -instance (SplitPorts a p, TupleSize p n, WrapPorts p pb) => WrapMethod a pb where - toWrapMethod a = packPorts a - fromWrapMethod a = unpackPorts a - outputPortNames _ base = checkPortNames (_ :: a) base + outputPortNames _ base = filterZeroWidthPorts (_ :: p) $ checkPortNames (_ :: a) base saveMethodPortTypes _ modName _ result = savePortTypes (_ :: p) modName $ checkPortNames (_ :: a) result --} class WrapPorts p pb | p -> pb where - -- Convert from a tuple of values to a tuple of bits. + -- Convert from a tuple of Port values to a tuple of bits. packPorts :: p -> pb - -- Convert from a tuple of bits to a tuple of values. + -- Convert from a tuple of bits to a tuple of Port values. unpackPorts :: pb -> p -- Save the port types, given their names. savePortTypes :: p -> Maybe Name__ -> List String -> Module () - -instance (Bits a n, WrapPorts b bb) => WrapPorts (Port a, b) (Bit n, bb) where - packPorts (Port a, b) = (pack a, packPorts b) - unpackPorts (a, b) = (Port $ unpack a, unpackPorts b) + -- Filter the port names to only those that have non-zero width. + filterZeroWidthPorts :: p -> List String -> List String + +instance (Bits a n, NonEmptyBits n ab, WrapPorts b bb, AppendTuple ab bb pb) => + WrapPorts (Port a, b) pb where + packPorts (Port a, b) = toNonEmptyBits (pack a) `appendTuple` packPorts b + unpackPorts p = case splitTuple p of + (ab, bb) -> (Port (unpack (fromNonEmptyBits ab)), unpackPorts bb) savePortTypes _ modName (Cons h t) = do - primSavePortType modName h $ typeOf (_ :: a) + if valueOf n > 0 + then primSavePortType modName h $ typeOf (_ :: a) + else return () savePortTypes (_ :: b) modName t savePortTypes _ _ Nil = error "savePortTypes: empty port names list" - -instance (Bits a n) => WrapPorts (Port a) (Bit n) where - packPorts (Port a) = pack a - unpackPorts = Port ∘ unpack - savePortTypes _ modName (Cons h _) = primSavePortType modName h $ typeOf (_ :: a) - savePortTypes _ _ Nil = error "savePortTypes: empty port names list" + filterZeroWidthPorts _ (Cons h t) = + if valueOf n > 0 + then Cons h (filterZeroWidthPorts (_ :: b) t) + else filterZeroWidthPorts (_ :: b) t + filterZeroWidthPorts _ Nil = error "filterZeroWidthPorts: empty port names list" + +instance (Bits a n, NonEmptyBits n pb) => WrapPorts (Port a) pb where + packPorts (Port a) = toNonEmptyBits (pack a) + unpackPorts = Port ∘ unpack ∘ fromNonEmptyBits + savePortTypes _ modName (Cons h Nil) = primSavePortType modName h $ typeOf (_ :: a) + savePortTypes _ _ _ = error "savePortTypes: expected one port name" + filterZeroWidthPorts _ (Cons h Nil) = + if valueOf n > 0 then Cons h Nil else Nil + filterZeroWidthPorts _ _ = error "filterZeroWidthPorts: expected one port name" instance WrapPorts () () where packPorts _ = () unpackPorts _ = () - savePortTypes _ _ _ = return () + savePortTypes _ _ Nil = return () + savePortTypes _ _ _ = error "savePortTypes: non-empty port names list" + filterZeroWidthPorts _ Nil = Nil + filterZeroWidthPorts _ _ = error "filterZeroWidthPorts: non-empty port names list" + +-- Helper class to conditionally convert Bit 0 to () +class NonEmptyBits n pb | n -> pb where + toNonEmptyBits :: Bit n -> pb + fromNonEmptyBits :: pb -> Bit n + +instance NonEmptyBits 0 () where + toNonEmptyBits _ = () + fromNonEmptyBits _ = 0 + +instance NonEmptyBits n (Bit n) where + toNonEmptyBits = id + fromNonEmptyBits = id + +-- Force a tuple of bit values to be fully expanded by the evaluator. +primDeepSeqTupleBits :: (PrimSeqTupleBits a) => a -> a +primDeepSeqTupleBits a = primSeqTupleBits a a + +class PrimSeqTupleBits a where + primSeqTupleBits :: a -> b -> b + +instance (PrimSeqTupleBits b) => PrimSeqTupleBits (Bit n, b) where + primSeqTupleBits (a, b) c = primSeq a (primSeqTupleBits b c) + +instance PrimSeqTupleBits (Bit n) where + primSeqTupleBits = primSeq + +instance PrimSeqTupleBits () where + primSeqTupleBits () = id -- Compute the list port names for type 'a' given a base name. -- Check that the number of port names matches the number of ports. --- This error should only occur if there is an error in a WrapPorts instance. +-- This error should only occur if there is an error in a SplitPorts instance. checkPortNames :: (SplitPorts a p, TupleSize p n) => a -> String -> List String checkPortNames proxy base = let pn = portNames proxy base diff --git a/src/comp/AAddScheduleDefs.hs b/src/comp/AAddScheduleDefs.hs index 44449a2ed..d90ae6e8a 100644 --- a/src/comp/AAddScheduleDefs.hs +++ b/src/comp/AAddScheduleDefs.hs @@ -105,12 +105,12 @@ aAddScheduleDefs flags pps pkg aschedinfo = -- The ExprMaps map from a method name (not RDY) to the expression -- for that method's ready or enable condition. let pre_rdy_map = M.fromList $ - [ (dropReadyPrefixId (aIfaceName m), adef_expr (aif_value m)) + [ (dropReadyPrefixId (aif_name m), adef_expr $ aif_value m) | m <- ifc0 - , isRdyId (aIfaceName m) + , isRdyId (aif_name m) ] pre_en_map = M.fromList $ - [ (aIfaceName m, e) + [ (aif_name m, e) | m <- ifc0 , (Just e) <- [getMethodEnExpr m] ] @@ -280,11 +280,11 @@ mkIfcWFs _ _ _ = [] -- ignore RDY methods, clocks, resets, inouts -- Get the map from a method to its rule names (or def name, for value method) buildRuleMap :: AIFace -> Maybe (Id, [Id]) buildRuleMap m@(AIAction {}) = - Just (aIfaceName m, map aRuleName (aIfaceRules m)) + Just (aif_name m, map aRuleName (aIfaceRules m)) buildRuleMap m@(AIActionValue {}) = - Just (aIfaceName m, map aRuleName (aIfaceRules m)) + Just (aif_name m, map aRuleName (aIfaceRules m)) buildRuleMap m@(AIDef { aif_name = mid }) | not (isRdyId mid) = - Just (mid, [aIfaceName m]) + Just (mid, [aif_name m]) buildRuleMap _ = Nothing -- Replace the value in a RDY method diff --git a/src/comp/ACheck.hs b/src/comp/ACheck.hs index f42553812..602d8227e 100644 --- a/src/comp/ACheck.hs +++ b/src/comp/ACheck.hs @@ -98,7 +98,6 @@ chkAIface aa@(AIAction { aif_body = rs }) = chkAIface aa@(AIActionValue { aif_value = d, aif_body = rs }) = tracePP "chkAIface AIActionValue" aa $ (all chkARule rs) && (chkADef d) - chkAIface aa@(AIClock { aif_clock = c }) = tracePP "chkAIface AIClock" aa $ chkAClock c @@ -422,6 +421,8 @@ checkUse :: S.Set AId -> S.Set AId -> S.Set AId -> AExpr -> [AId] checkUse ds is ps (APrim _ _ _ es) = checkUses ds is ps es checkUse ds is ps (AMethCall _ i m es) = checkUses ds is ps es -- XXX check i and m ? checkUse ds is ps (AMethValue _ i m) = [] -- XXX check i and m ? +checkUse ds is ps (ATuple _ es) = checkUses ds is ps es +checkUse ds is ps (ATupleSel _ e _) = checkUse ds is ps e checkUse ds is ps (ANoInlineFunCall _ _ _ es) = checkUses ds is ps es checkUse ds is ps (AFunCall { ae_args = es }) = checkUses ds is ps es -- because all of the expressions used are used by the ATaskAction diff --git a/src/comp/AConv.hs b/src/comp/AConv.hs index 2ea42a585..b939ba1a0 100644 --- a/src/comp/AConv.hs +++ b/src/comp/AConv.hs @@ -13,8 +13,8 @@ import Id import FStringCompat import Flags(Flags) import PreStrings(sSigned) -import PreIds(idBit, idAVAction_, idAVValue_, idClockOsc, idClockGate, - idInout_, idPrimArray) +import PreIds(idBit, idActionValue_, idAVAction_, idAVValue_, idClockOsc, idClockGate, + idInout_, idPrimArray, idPrimPair, idPrimFst, idPrimSnd, idPrimUnit) import Pragma import Error(internalError, EMsg, WMsg, ErrMsg(..), ErrorHandle, bsError, bsWarning) @@ -28,7 +28,6 @@ import GenWrapUtils(isGenId, dropGenSuffixId) import Prim import Data.List(genericLength, nub) import Data.Maybe(fromMaybe) -import CType(TISort(..), StructSubType(..)) import VModInfo(lookupOutputClockWires, lookupOutputResetWire, lookupIfcInoutWire, vArgs, VArgInfo(..)) import SignalNaming @@ -187,18 +186,18 @@ aDo imod@(IModule mi fmod be wi ps iks its clks rsts itvs pts idefs rs ifc ffcal flags <- getFlags -- AVInst keeps the types of method ports - let tsConv :: Id -> [IType] -> ([AType], Maybe AType, Maybe AType) + let tsConv :: Id -> [IType] -> ([AType], Maybe AType, [AType]) tsConv i ts = let inputs = initOrErr "tsConv" ts res = lastOrErr "tsConv" ts in_types = map (aTypeConv i) inputs (en_type, val_type) - | isitActionValue_ res && getAV_Size res > 0 - = (Just (ATBit 1), Just (ATBit (getAV_Size res))) + | isitActionValue_ res + = (Just (ATBit 1), aTypesConv i (getAV_Type res)) | isActionType res - = (Just (ATBit 1), Nothing) + = (Just (ATBit 1), []) | otherwise - = (Nothing, Just (aTypeConv i res)) + = (Nothing, aTypesConv i res) in (in_types, en_type, val_type) let (IRules sps irule_list) = rs @@ -366,9 +365,7 @@ aIface flags iface@(IEFace i its maybe_e maybe_rs wp fi) = do ++ ppReadable iface) | otherwise -> do - -- internal error if type actionvalue XXX ae <- aExpr e - --trace ("exit v " ++ ppReadable i) $ return () return (AIDef i its' wp g (ADef i (aTypeConv i t) ae []) fi []) (Nothing, Just rs) -> do @@ -382,7 +379,7 @@ aIface flags iface@(IEFace i its maybe_e maybe_rs wp fi) = do ae <- aExpr val_ --trace ("exit av " ++ ppReadable i) $ return () return (AIActionValue its' wp g i arule_list - (ADef i (aTypeConv i t) ae []) fi ) + (ADef i (aTypeConv i t) ae []) fi ) -- should internalError if size(val_)==0 XXX aRule :: IRule a -> M ARule @@ -507,69 +504,17 @@ aExpr (IAps (ICon i (ICSel { })) ts (e:es)) = internalError ("aExpr: too many arguments to avValue_: " ++ ppReadable es) --- value part of ActionValue task without arguments -aExpr e@(IAps (ICon m (ICSel { })) _ - [(ICon i (ICForeign {fName = name, - isC = isC, - foports = Nothing, - fcallNo = mn}))]) - | m == idAVValue_ = - let n = case (mn) of - Nothing -> internalError - ("aExpr: avValue_ on ICForeign without fcallNo") - Just val -> val - t = aTypeConvE e (iGetType e) - in - return (ATaskValue t i name isC n) - --- value part of ActionValue task with arguments -aExpr e@(IAps (ICon m (ICSel { })) _ - [(IAps (ICon i (ICForeign {fName = name, - isC = isC, - foports = Nothing, - fcallNo = mn})) fts fes)]) - | m == idAVValue_ = - let n = case (mn) of - Nothing -> internalError - ("aExpr: avValue_ on ICForeign without fcallNo") - Just val -> val - t = aTypeConvE e (iGetType e) - in - -- the value side carries no arguments - -- the cookie "n" will connect it back up to the action side - return (ATaskValue t i name isC n) - --- value part of ActionValue method -aExpr e@(IAps (ICon sel_id (ICSel { })) ts - [(IAps (ICon m (ICSel { })) _ (ICon i (ICStateVar { }) : es))]) - | (sel_id == idAVValue_) = do - i' <- transId i - let atype = aTypeConvE e (iGetType e) - -- arguments should have been dropped in IExpand - when (not (null es)) $ - internalError ("AConv.aExpr actionvalue value with args " ++ - ppReadable e) - -- IExpand is failing to optimize away bit-zero results from methods - -- and foreign functions, so catch that here for ActionValue methods - return $ if (atype == aTZero) - then ASInt i (ATBit 0) (ilDec 0) - else AMethValue atype i' m +aExpr e@(IAps (ICon _ (ICSel {})) _ _) = aSelExpr sels selExpr + where + (sels, selExpr) = unfoldICSel e --- value method -aExpr e@(IAps (ICon m (ICSel { })) _ (ICon i (ICStateVar { }) : es)) = do - i' <- transId i - let atype = aTypeConvE e (iGetType e) - es' <- mapM aSExpr es - return $ AMethCall atype i' m es' + unfoldICSel :: IExpr a -> ([(Id, AType)], [IExpr a]) + unfoldICSel e@(IAps (ICon i (ICSel {})) _ [e']) = + let (sels, a) = unfoldICSel e' + in ((i, aTypeConvE e $ iGetType e) : sels, a) + unfoldICSel e@(IAps (ICon i (ICSel {})) _ a) = ([(i, aTypeConvE e $ iGetType e)], a) + unfoldICSel e = ([], [e]) -aExpr e@(IAps (ICon m (ICSel { })) _ [(ICon i (ICClock { iClock = c }))]) | m == idClockGate = do - ac <- aClock c - return (aclock_gate ac) --- XXX This is here because aClock calls aSExpr on the oscillator. However, --- XXX that should be the only place where an osc ever appears in an expr. -aExpr e@(IAps (ICon m (ICSel { })) _ [(ICon i (ICClock { iClock = c }))]) | m == idClockOsc = do - ac <- aClock c - return (aclock_osc ac) aExpr (IAps (ICon _ (ICCon { iConType = ITAp _ t, conTagInfo = cti })) _ _) | t == itBit1 = return $ aSBool (conNo cti /= 0) aExpr e@(IAps (ICon i (ICForeign { fName = name, isC = isC, foports = Nothing})) ts es) = do @@ -593,6 +538,11 @@ aExpr e@(IAps (ICon i (ICForeign { fName = name, isC = False, foports = (Just op return $ ANoInlineFunCall t i' (ANoInlineFun name ns ops Nothing) es' +aExpr e@(IAps (ICon i _) _ _) | i == idPrimPair = do + let at = aTypeConvE e (iGetType e) + aes <- aTupleExpr e + return (ATuple at aes) + aExpr e@(ICon v (ICModPort { iConType = t })) = return (ASPort (aTypeConvE e t) v) aExpr e@(ICon v (ICModParam { iConType = t })) = return (ASParam (aTypeConvE e t) v) aExpr e@(ICon v (ICMethArg { iConType = t })) = return (ASPort (aTypeConvE e t) v) @@ -638,11 +588,105 @@ aExpr e@(ICon _ (ICInout { iConType = it, iInout = i})) | (isitInout_ it) = do ai <- aInout i return (ASInout at ai) +aExpr (ICon i _) | i == idPrimUnit = return $ ASInt i (ATBit 0) (ilDec 0) + aExpr e = internalError ("AConv.aExpr at " ++ ppString p ++ ":" ++ ppReadable e ++ "\n" ++ (show p) ++ ":" ++ (showTypeless e)) where p = getIExprPosition e +aTupleExpr :: IExpr a -> M [AExpr] +aTupleExpr (IAps (ICon i _) [t1, t2] [e1, e2]) | i == idPrimPair = do + ae1 <- aSExpr e1 + ae2 <- aTupleExpr e2 + return (ae1:ae2) +aTupleExpr e = fmap (:[]) (aSExpr e) + +aSelExpr :: [(Id, AType)] -> [IExpr a] -> M AExpr + +-- value part of ActionValue task without arguments +aSelExpr [(m, t)] [(ICon i (ICForeign {fName = name, + isC = isC, + foports = Nothing, + fcallNo = mn}))] + | m == idAVValue_ = + let n = case (mn) of + Nothing -> internalError + ("aExpr: avValue_ on ICForeign without fcallNo") + Just val -> val + in + return (ATaskValue t i name isC n) + +-- value part of ActionValue task with arguments +aSelExpr [(m, t)] [(IAps (ICon i (ICForeign {fName = name, + isC = isC, + foports = Nothing, + fcallNo = mn})) fts fes)] + | m == idAVValue_ = + let n = case (mn) of + Nothing -> internalError + ("aExpr: avValue_ on ICForeign without fcallNo") + Just val -> val + in + -- the value side carries no arguments + -- the cookie "n" will connect it back up to the action side + return (ATaskValue t i name isC n) + +-- port selected from value part of ActionValue method +aSelExpr ((sel, atype) : sels) base@(ICon i (ICStateVar { }) : es) + | (sel == idPrimFst || sel == idPrimSnd) + , [(iav, atypeTup), (m, _)] <- dropWhile ((== idPrimSnd) . fst) sels = do + i' <- transId i + -- arguments should have been dropped in IExpand + when (not (null es)) $ + internalError ("AConv.aExpr actionvalue value with args " ++ + ppReadable sels ++ "\n" ++ ppReadable base) + let idx = toInteger $ (if sel == idPrimSnd then 1 else 0) + length sels - 2 + return $ ATupleSel atype (AMethValue atypeTup i' m) $ idx + 1 + +-- port selected from value method +aSelExpr ((sel, atype) : sels) (ICon i (ICStateVar { }) : es) + | (sel == idPrimFst || sel == idPrimSnd) + , [(m, atypeTup)] <- dropWhile ((== idPrimSnd) . fst) sels = do + i' <- transId i + es' <- mapM aSExpr es + let idx = toInteger $ (if sel == idPrimSnd then 1 else 0) + length sels - 1 + return $ ATupleSel atype (AMethCall atypeTup i' m es') $ idx + 1 + +-- value part of ActionValue method +aSelExpr sels@[(iav, atype), (m, _)] base@(ICon i (ICStateVar { }) : es) + | (iav == idAVValue_) = do + i' <- transId i + -- arguments should have been dropped in IExpand + when (not (null es)) $ + internalError ("AConv.aExpr actionvalue value with args " ++ + ppReadable sels ++ "\n" ++ ppReadable base) + -- IExpand is failing to optimize away bit-zero results from methods + -- and foreign functions, so catch that here for ActionValue methods + return $ if (atype == aTZero) + then ASInt i (ATBit 0) (ilDec 0) + else AMethValue atype i' m + +-- value method +aSelExpr [(m, atype)] (ICon i (ICStateVar { }) : es) = do + i' <- transId i + es' <- mapM aSExpr es + return $ AMethCall atype i' m es' + +aSelExpr [(m, _)] [ICon i (ICClock { iClock = c })] | m == idClockGate = do + ac <- aClock c + return (aclock_gate ac) +-- XXX This is here because aClock calls aSExpr on the oscillator. However, +-- XXX that should be the only place where an osc ever appears in an expr. +aSelExpr [(m, _)] [ICon i (ICClock { iClock = c })] | m == idClockOsc = do + ac <- aClock c + return (aclock_osc ac) + +aSelExpr sels base = internalError + ("AConv.aSelExpr:" ++ + ppReadable sels ++ "\n" ++ ppReadable base) + + aEDef :: Id -> IExpr a -> [DefProp] -> M AExpr aEDef i e ps = do da <- getDA @@ -662,12 +706,14 @@ aTypeConv _ (ITAp (ITCon i _ _) (ITNum n)) | i == idInout_ = ATAbstract idInout_ aTypeConv a (ITAp (ITCon r _ _) elem_ty) | r == idPrimArray = -- no way to get the size internalError("aTypeConv: array: " ++ ppReadable a) +aTypeConv a t@(ITAp (ITAp (ITCon p _ _) _) _) | p == idPrimPair = + ATTuple (aTypesConv a t) aTypeConv _ t | t == itReal = ATReal aTypeConv _ t | t == itString = ATString Nothing -- Deal with AVs -aTypeConv _ (ITAp (ITCon i t (TIstruct SStruct fs@(val:_))) (ITNum n)) = - ATBit n - -- internalError ("Yes\n\n" ++ (show a) ++"\n\n" ++ (show n)) +aTypeConv a (ITAp (ITCon i _ _) t) | i == idActionValue_ = + aTypeConv a t +aTypeConv a (ITCon i _ _) | i == idPrimUnit = ATBit 0 aTypeConv _ t = abs t [] where abs (ITCon i _ _) ns = ATAbstract i (reverse ns) abs (ITAp t _) ns = abs t ns @@ -684,17 +730,25 @@ aTypeConvE a (ITAp (ITCon r _ _) elem_ty) | r == idPrimArray = -- XXX we could examine the expression and find the type -- XXX but this func isn't used to get the type of PrimBuildArray internalError ("aTypeConv: array: " ++ ppReadable a) +aTypeConvE _ t@(ITAp (ITAp (ITCon p _ _) _) _) | p == idPrimPair = + ATTuple (aTypesConv p t) aTypeConvE a t | t == itReal = ATReal aTypeConvE a t | t == itString = case a of (ICon _ (ICString _ s)) -> ATString (Just (genericLength s)) otherwise -> ATString Nothing +aTypeConvE a (ITCon i _ _) | i == idPrimUnit = ATBit 0 aTypeConvE a t = abs t [] where abs (ITCon i _ _) ns = ATAbstract i (reverse ns) abs (ITAp t _) ns = abs t ns abs _ _ = -- ATAbstract idBit [] -- XXX what's this internalError ("aTypeConvE|" ++ show t) +aTypesConv :: Id -> IType -> [AType] +aTypesConv a (ITAp (ITAp (ITCon p _ _) t1) t2) | p == idPrimPair = + aTypeConv a t1 : aTypesConv a t2 +aTypesConv a t = [aTypeConv a t] + realPrim :: PrimOp -> Bool realPrim p = p `elem` [ diff --git a/src/comp/ADropUndet.hs b/src/comp/ADropUndet.hs index 2e9a0fb9f..fd764c4e1 100644 --- a/src/comp/ADropUndet.hs +++ b/src/comp/ADropUndet.hs @@ -100,6 +100,8 @@ hasNoActionValue :: M.Map AId Bool -> AExpr -> Bool hasNoActionValue avm (APrim { ae_args = es }) = all (hasNoActionValue avm) es hasNoActionValue avm (AMethCall { ae_args = es }) = all (hasNoActionValue avm) es hasNoActionValue avm (AMethValue {}) = False +hasNoActionValue avm (ATuple _ es) = all (hasNoActionValue avm) es +hasNoActionValue avm (ATupleSel { ae_exp = e }) = hasNoActionValue avm e hasNoActionValue avm (ANoInlineFunCall { ae_args = es }) = all (hasNoActionValue avm) es hasNoActionValue avm (AFunCall { ae_args = es }) = all (hasNoActionValue avm) es hasNoActionValue avm (ATaskValue {}) = False diff --git a/src/comp/ADumpSchedule.hs b/src/comp/ADumpSchedule.hs index ab6ecd630..5f0c59dda 100644 --- a/src/comp/ADumpSchedule.hs +++ b/src/comp/ADumpSchedule.hs @@ -322,7 +322,7 @@ genMethodDumpMap vSchedInfo ifc = methodDumpMap -- don't include output clocks and resets -- don't include ready Ids methodList = filter (not . isRdyId) $ - map aIfaceName (aIfaceMethods ifc) + map aif_name (aIfaceMethods ifc) methodRdys = [(mn, p) | (AIDef { aif_name = mn, aif_value = (ADef _ _ p _) }) <- ifc, isRdyId mn] methodDumpMap = [ (mid, p, clist) diff --git a/src/comp/AExpand.hs b/src/comp/AExpand.hs index 7f3227c5d..bf8f32eb5 100644 --- a/src/comp/AExpand.hs +++ b/src/comp/AExpand.hs @@ -458,6 +458,8 @@ isSimple c (APrim i t PrimConcat es) = c && all (is isSimple c e@(APrim _ _ p es) = c && isSmall e && cheap p es -- && all (isSimple c) es isSimple c (AMethCall _ _ _ es) = null es isSimple c (AMethValue _ _ _) = True +isSimple c (ATupleSel _ e _) = isSimple c e +isSimple c (ATuple _ es) = all (isSimple c) es -- foreign function calls cannot be inlined -- (except for $signed and $unsigned - handled by mustInline) isSimple c e@(AFunCall { }) = False @@ -537,6 +539,10 @@ getExprSize (APrim _ _ _ es) = (nub $ concat vars, sum terms, 1 + maximum depths getExprSize (AMethCall t i mid args) = ([mid],1,1) getExprSize (AMethValue t i mid) = ([mid],1,1) +getExprSize (ATupleSel t e i) = (vars, terms + 1, depth + 1) + where (vars,terms,depth) = getExprSize e +getExprSize (ATuple t es) = (nub $ concat vars, sum terms + 1, maximum depths + 1) + where (vars,terms,depths) = unzip3 $ map getExprSize es getExprSize (ATaskValue { }) = ([], 1,1) getExprSize (ASPort t i) = ([i], 1,1) getExprSize (ASParam t i) = ([i], 1,1) diff --git a/src/comp/AExpr2STP.hs b/src/comp/AExpr2STP.hs index ce45f26cd..49acffe8e 100644 --- a/src/comp/AExpr2STP.hs +++ b/src/comp/AExpr2STP.hs @@ -19,6 +19,7 @@ import qualified Data.Map as M import qualified STP as S import Data.Maybe(fromMaybe) +import Data.List (genericIndex) import ErrorUtil(internalError) import Flags @@ -32,7 +33,7 @@ import PFPrint import Util(itos, map_insertMany, makePairs) import TopUtils(withElapsed) -import AExpr2Util(getMethodOutputPort) +import AExpr2Util(getMethodOutputPorts) import Debug.Trace(traceM) import IOUtil(progArgs) @@ -583,15 +584,35 @@ convAExpr2SExpr mty (AMethCall ty@(ATBit width) modId methId args) = do -- get the actual port name, so that methods which share the same output port -- will appear logically equivalent smap <- gets stateMap - let portId = getMethodOutputPort smap modId methId - e = (AMethCall ty modId portId args) + let e = case getMethodOutputPorts smap modId methId of + [portId] -> AMethCall ty modId portId args + ports -> internalError ("convAExpr2SExpr: unexpected output ports: " ++ + ppReadable (modId, methId, ports)) -- XXX This could be an unevaluated function, applied to converted arguments addUnknownExpr mty e width convAExpr2SExpr mty (AMethValue ty@(ATBit width) modId methId) = do -- get the actual port name, so that methods which share the same output port -- will appear logically equivalent smap <- gets stateMap - let portId = getMethodOutputPort smap modId methId + let e = case getMethodOutputPorts smap modId methId of + [portId] -> AMethValue ty modId portId + ports -> internalError ("convAExpr2SExpr: unexpected output ports: " ++ + ppReadable (modId, methId, ports)) + -- XXX This could be an unevaluated function, applied to converted arguments + addUnknownExpr mty e width +convAExpr2SExpr mty (ATupleSel ty@(ATBit width) (AMethCall _ modId methId args) selIdx) = do + -- get the actual port name, so that methods which share the same output port + -- will appear logically equivalent + smap <- gets stateMap + let portId = getMethodOutputPorts smap modId methId `genericIndex` selIdx + e = (AMethCall ty modId portId args) + -- XXX This could be an unevaluated function, applied to converted arguments + addUnknownExpr mty e width +convAExpr2SExpr mty (ATupleSel ty@(ATBit width) (AMethValue _ modId methId) selIdx) = do + -- get the actual port name, so that methods which share the same output port + -- will appear logically equivalent + smap <- gets stateMap + let portId = getMethodOutputPorts smap modId methId `genericIndex` selIdx e = (AMethValue ty modId portId) -- XXX This could be an unevaluated function, applied to converted arguments addUnknownExpr mty e width diff --git a/src/comp/AExpr2Util.hs b/src/comp/AExpr2Util.hs index 104a25735..37db3c5fb 100644 --- a/src/comp/AExpr2Util.hs +++ b/src/comp/AExpr2Util.hs @@ -1,7 +1,7 @@ -- Common code used by various converters module AExpr2Util( - getMethodOutputPort + getMethodOutputPorts ) where import qualified Data.Map as M @@ -32,8 +32,8 @@ import VModInfo(VModInfo(..), VFieldInfo(..), vName_to_id) -- XXX we can replace them with an unevaluated function applied to its arguments! -- XXX That way, the SMT solver will handle any equivalence of the arguments. -getMethodOutputPort :: (M.Map AId VModInfo) -> AId -> AId -> AId -getMethodOutputPort stateMap modId methId = +getMethodOutputPorts :: (M.Map AId VModInfo) -> AId -> AId -> [AId] +getMethodOutputPorts stateMap modId methId = let mod_err = internalError("canonMethCalls: module not found: " ++ ppReadable modId) fields = vFields $ M.findWithDefault mod_err modId stateMap @@ -41,14 +41,12 @@ getMethodOutputPort stateMap modId methId = ppReadable (modId, methId)) findFn (Method { vf_name = i }) = qualEq i methId findFn _ = False - mport = case (find findFn fields) of - Just (Method { vf_output = mo }) -> mo + ports = case (find findFn fields) of + Just (Method { vf_outputs = os }) -> os _ -> meth_err out_err = internalError("canonMethCalls: method has no output: " ++ ppReadable (modId, methId)) - in case mport of - Just (vn,_) -> vName_to_id vn - _ -> out_err + in if null ports then out_err else map (vName_to_id . fst) ports -- ------------------------- diff --git a/src/comp/AExpr2Yices.hs b/src/comp/AExpr2Yices.hs index b621930e0..6e96878c4 100644 --- a/src/comp/AExpr2Yices.hs +++ b/src/comp/AExpr2Yices.hs @@ -18,6 +18,7 @@ import Control.Monad.State(StateT, runStateT, liftIO, import qualified Data.Map as M import qualified Yices as Y import Data.Word(Word32) +import Data.List (genericIndex) import ErrorUtil(internalError) import Flags @@ -30,7 +31,7 @@ import VModInfo(VModInfo) import PFPrint import Util(itos, map_insertMany, makePairs) import TopUtils(withElapsed) -import AExpr2Util(getMethodOutputPort) +import AExpr2Util(getMethodOutputPorts) import Debug.Trace(traceM) import IOUtil(progArgs) @@ -587,16 +588,37 @@ convAExpr2YExpr mty (AMethCall ty@(ATBit width) modId methId args) = do -- get the actual port name, so that methods which share the same output port -- will appear logically equivalent smap <- gets stateMap - let portId = getMethodOutputPort smap modId methId - e = (AMethCall ty modId portId args) + let e = case getMethodOutputPorts smap modId methId of + [portId] -> AMethCall ty modId portId args + ports -> internalError ("convAExpr2YExpr: unexpected output ports: " + ++ ppReadable (modId, methId, ports)) -- XXX This could be an unevaluated function, applied to converted arguments addUnknownExpr mty e width convAExpr2YExpr mty (AMethValue ty@(ATBit width) modId methId) = do -- get the actual port name, so that methods which share the same output port -- will appear logically equivalent smap <- gets stateMap - let portId = getMethodOutputPort smap modId methId + let e = case getMethodOutputPorts smap modId methId of + [portId] -> AMethValue ty modId portId + ports -> internalError ("convAExpr2YExpr: unexpected output ports: " + ++ ppReadable (modId, methId, ports)) + -- XXX This could be an unevaluated function, applied to converted arguments + addUnknownExpr mty e width +convAExpr2YExpr mty (ATupleSel ty@(ATBit width) (AMethCall _ modId methId args) selIdx) = do + -- get the actual port name, so that methods which share the same output port + -- will appear logically equivalent + smap <- gets stateMap + let portId = getMethodOutputPorts smap modId methId `genericIndex` selIdx + e = (AMethCall ty modId portId args) + -- XXX This could be an unevaluated function, applied to converted arguments + addUnknownExpr mty e width +convAExpr2YExpr mty (ATupleSel ty@(ATBit width) (AMethValue _ modId methId) selIdx) = do + -- get the actual port name, so that methods which share the same output port + -- will appear logically equivalent + smap <- gets stateMap + let portId = getMethodOutputPorts smap modId methId `genericIndex` selIdx e = (AMethValue ty modId portId) + -- XXX This could be an unevaluated function, applied to converted arguments addUnknownExpr mty e width convAExpr2YExpr mty e@(AMGate (ATBit 1) _ _) = diff --git a/src/comp/ANoInline.hs b/src/comp/ANoInline.hs index 4cee039c9..8b5449fed 100644 --- a/src/comp/ANoInline.hs +++ b/src/comp/ANoInline.hs @@ -157,7 +157,7 @@ liftAExpr True (ANoInlineFunCall t i f es) = do liftAExpr _ (APrim aid ty op es) = do es' <- mapM (liftAExpr False) es return $ APrim aid ty op es' -liftAExpr _ (AMethCall ty aid mid es) = do +liftAExpr _ (AMethCall ty aid mid es) = do es' <- mapM (liftAExpr False) es return $ AMethCall ty aid mid es' liftAExpr _ (AFunCall ty aid fun isC es) = do diff --git a/src/comp/APaths.hs b/src/comp/APaths.hs index 4b6e9bc64..5b761890e 100644 --- a/src/comp/APaths.hs +++ b/src/comp/APaths.hs @@ -116,7 +116,7 @@ import VModInfo(vPath, vFields, vArgs, import Pragma import Control.Monad(when) import Data.Maybe(isJust, isNothing, fromJust) -import Data.List(partition) +import Data.List(partition, genericIndex) import Id(unQualId, getIdBaseString) import Eval import Position(getPosition) @@ -170,8 +170,8 @@ data PathNode = PNDef AId | -- arguments to methods of submodules (Ids: instance, method, arg #) PNStateMethodArg AId AId Integer | - -- return values of methods of submodules (Ids: instance, method) - PNStateMethodRes AId AId | + -- return values of methods of submodules (Ids: instance, method, result #) + PNStateMethodRes AId AId Integer | -- enable signal of action methods of submodules (Ids: instance, method) PNStateMethodEnable AId AId | -- imported state has no ready signal @@ -190,8 +190,8 @@ data PathNode = PNWillFire AId | -- arguments to methods of current module (Ids: method, argument) PNTopMethodArg AId AId | - -- return values of methods of current module (Id: method) - PNTopMethodRes AId | + -- return values of methods of current module (Ids: method, result #) + PNTopMethodRes AId Integer | -- this is an internal graph node for the method's ready signal, -- the real output port is handled by a separate read method -- (Id: method) @@ -228,8 +228,8 @@ printPathNode use_pvprint d p node = fsep [text "Argument", pp port_id, s2par "of method", quotes (pp meth_id), s2par "of submodule", quotes (pp inst_id)] - (PNStateMethodRes inst_id meth_id) -> - fsep [s2par "Return value", + (PNStateMethodRes inst_id meth_id port_id) -> + fsep [s2par "Return value", pp port_id, s2par "of method", quotes (pp meth_id), s2par "of submodule", quotes (pp inst_id)] (PNStateMethodEnable inst_id meth_id) -> @@ -255,8 +255,8 @@ printPathNode use_pvprint d p node = (PNTopMethodArg meth_id arg_id) -> fsep [text "Argument", pp arg_id, s2par "of top-level method", quotes (pp meth_id)] - (PNTopMethodRes meth_id) -> - fsep [text "Output", + (PNTopMethodRes meth_id res_num) -> + fsep [text "Output", pp res_num, s2par "of top-level method", quotes (pp meth_id)] (PNTopMethodReady meth_id) -> fsep [s2par "Ready condition", @@ -290,14 +290,14 @@ instance PVPrint PathNode where instance NFData PathNode where rnf (PNDef aid) = rnf aid rnf (PNStateMethodArg a1 a2 n) = rnf3 a1 a2 n - rnf (PNStateMethodRes a1 a2) = rnf2 a1 a2 + rnf (PNStateMethodRes a1 a2 n) = rnf3 a1 a2 n rnf (PNStateMethodEnable a1 a2) = rnf2 a1 a2 rnf (PNStateArgument aid vn n) = rnf3 aid vn n rnf (PNStateMethodArgMux a1 a2) = rnf2 a1 a2 rnf (PNCanFire aid) = rnf aid rnf (PNWillFire aid) = rnf aid rnf (PNTopMethodArg a1 a2) = rnf2 a1 a2 - rnf (PNTopMethodRes aid) = rnf aid + rnf (PNTopMethodRes aid n) = rnf2 aid n rnf (PNTopMethodReady aid) = rnf aid rnf (PNTopMethodEnable aid) = rnf aid rnf (PNTopArgument aid n) = rnf2 aid n @@ -314,7 +314,7 @@ filterPNDefs pns = filter (not . isPNDef) pns isPNDef _ = False alwaysRdyNode :: [PProp] -> PathNode -> Bool -alwaysRdyNode pps (PNTopMethodRes m) = isAlwaysRdy pps m +alwaysRdyNode pps (PNTopMethodRes m _) = isAlwaysRdy pps m alwaysRdyNode pps _ = False enWhenRdyNode :: [PProp] -> PathNode -> Bool @@ -475,13 +475,13 @@ aPathsPreSched errh flags apkg = do -- 1) method name -- 2) input argument list zipped with [1..] -- 3) (Maybe VName) if method has an enable signal (action method) - -- 4) (Maybe VName) if method has a result (now only value methods) + -- 4) result list zipped with [1..] (value methods only) -- 5) (Maybe Id) if method has an associated clock -- Note: the VPort's are stripped of VeriPortProp to be just VName -- XXX is the VeriPortProp info worth keeping? state_instances :: [ ( AId, [(VName, VName)], [(VName, Integer, AExpr)], - [(AId, [(VName,Integer)], Maybe VName, Maybe VName, Maybe AId)] ) ] + [(AId, [(VName,Integer)], Maybe VName, [(VName, Integer)], Maybe AId)] ) ] state_instances = [(inst_id, nns, args, meth_info) | avi <- vs, @@ -498,12 +498,13 @@ aPathsPreSched errh flags apkg = do -- method info let meth_info = - [(meth_id, numbered_args, maybe_EN, maybe_res, maybe_clk) | + [(meth_id, numbered_args, maybe_EN, numbered_res, maybe_clk) | vfieldinfo@(Method { vf_name = meth_id }) <- vFields vmi, let args = map fst (vf_inputs vfieldinfo), let numbered_args = zip args [1..], let maybe_EN = (vf_enable vfieldinfo) >>= return . fst, - let maybe_res = (vf_output vfieldinfo) >>= return . fst, + let res = (vf_outputs vfieldinfo) >>= return . fst, + let numbered_res = zip res [1..], let maybe_clk = vf_clock vfieldinfo ] ] @@ -511,13 +512,14 @@ aPathsPreSched errh flags apkg = do state_input_nodes = [ PNStateMethodArg inst_id meth_id arg_num | (inst_id, _, _, methods) <- state_instances, - (meth_id, numbered_args, maybe_EN, maybe_res, _) <- methods, + (meth_id, numbered_args, maybe_EN, _, _) <- methods, arg_num <- map snd numbered_args ] state_output_nodes = - [ PNStateMethodRes inst_id meth_id | + [ PNStateMethodRes inst_id meth_id res_num | (inst_id, _, _, methods) <- state_instances, - (meth_id, _, _, Just res_name, _) <- methods + (meth_id, _, _, numbered_res, _) <- methods, + res_num <- map snd numbered_res ] state_enable_nodes = [ PNStateMethodEnable inst_id meth_id | @@ -558,7 +560,7 @@ aPathsPreSched errh flags apkg = do let method_inputs = [(arg, PNTopMethodArg m arg) | (AIDef { aif_inputs = args, - aif_value = (ADef m _ _ _) }) <- ifc, + aif_name = m }) <- ifc, (arg,_) <- args] ++ [(arg, PNTopMethodArg m arg) | (AIAction { aif_inputs = args, aif_name = m }) <- ifc, @@ -567,9 +569,14 @@ aPathsPreSched errh flags apkg = do aif_name = m }) <- ifc, (arg,_) <- args] + num_outputs (ADef {adef_type = ATTuple ts}) = fromIntegral (length ts) + num_outputs _ = 1 + method_outputs = - [(m, PNTopMethodRes m) | (AIDef { aif_value = (ADef m _ _ _) }) <- ifc] ++ - [(m, PNTopMethodRes m) | (AIActionValue { aif_name = m, aif_value = (ADef m' _ _ _) }) <- ifc] + [(m, PNTopMethodRes m res) | (AIDef { aif_name = m, aif_value = v }) <- ifc, + res <- [1..(num_outputs v)] ] ++ + [(m, PNTopMethodRes m res) | (AIActionValue { aif_name = m, aif_value = v }) <- ifc, + res <- [1..(num_outputs v)] ] method_enables = -- Name creation is safe, since it is based on VFieldInfo @@ -620,7 +627,7 @@ aPathsPreSched errh flags apkg = do -- These are internal graph nodes, not part of the interface. -- There are separate read methods which become the Verilog ports. - method_ready_nodes = map (PNTopMethodReady . aIfaceName) ifc + method_ready_nodes = map (PNTopMethodReady . aif_name) ifc -- ---------- @@ -683,17 +690,24 @@ aPathsPreSched errh flags apkg = do -- methods (ifc) let mkMethodEdges :: AIFace -> [(PathNode,PathNode)] - mkMethodEdges (AIDef mid inputs wp rdy (ADef m _ e _) _ _) = + mkMethodEdges (AIDef mid inputs wp rdy def@(ADef _ t e _) _ _) = -- connect the rdy expression (likely just an ASDef reference) -- to the internal graph node for the method ready - (mkEdges (PNTopMethodReady m) rdy env) ++ + (mkEdges (PNTopMethodReady mid) rdy env) ++ -- make faux connections from the rdy to the arguments, so that -- dependencies in the other direction are caught as loops - [(PNTopMethodReady m, PNTopMethodArg m arg) | (arg,_) <- inputs] ++ + [(PNTopMethodReady mid, PNTopMethodArg mid arg) | (arg,_) <- inputs] ++ + if length result_types /= length results + then internalError + ("APaths.aPathsPreSched: unexpected method results: " ++ ppReadable def) -- connect the definition to the method result -- (this method has no enable, so it cannot contribute to any -- methcall argument muxes, so just use "mkEdges") - (mkEdges (PNTopMethodRes m) e env) + else [edge | (res, e') <- zip [1..] results, edge <- mkEdges (PNTopMethodRes mid res) e' env] + where result_types | ATTuple ts <- t = ts + | otherwise = [t] + results | ATuple { ae_elems = elems } <- e = elems + | otherwise = [e] mkMethodEdges (AIAction inputs wp rdy m rs fi) = let rdy_node = PNTopMethodReady m en_node = PNTopMethodEnable m @@ -726,7 +740,7 @@ aPathsPreSched errh flags apkg = do -- connect the rules concatMap mkMRuleEdges rs - mkMethodEdges (AIActionValue inputs wp rdy m rs (ADef m' _ e _) fi) = + mkMethodEdges (AIActionValue inputs wp rdy m rs def@(ADef _ t e _) fi) = let rdy_node = PNTopMethodReady m en_node = PNTopMethodEnable m mkMRuleEdges (ARule ri _ _ _ rpred actions _ _) = @@ -748,6 +762,10 @@ aPathsPreSched errh flags apkg = do [(en_node, wf_node)] ++ -- add edges from rule WillFire to ENs in each action (concatMap (mkActionEdges env wf_node) actions) + result_types | ATTuple ts <- t = ts + | otherwise = [t] + results | ATuple { ae_elems = elems } <- e = elems + | otherwise = [e] in -- make faux connections from the rdy to the arguments and the -- enable, so that dependencies in the other direction are caught @@ -755,10 +773,14 @@ aPathsPreSched errh flags apkg = do [(rdy_node, en_node)] ++ [(rdy_node, PNTopMethodArg m arg) | (arg,_) <- inputs] ++ - -- connect the definition to the method result + (if length result_types /= length results + then internalError + ("APaths.aPathsPreSched: unexpected method results: " ++ ppReadable def) + -- connect the definitions to the method results -- (this method's Enable could contribute to methcall argument -- muxes, so use "mkEdgesWithMux") - (mkEdgesWithMux en_node (PNTopMethodRes m) e env) ++ + else [edge | (res, e') <- zip [1..] results, + edge <- (mkEdgesWithMux en_node (PNTopMethodRes m res) e' env)]) ++ -- connect the rules concatMap mkMRuleEdges rs @@ -788,9 +810,10 @@ aPathsPreSched errh flags apkg = do -- (but there are paths for instantiation arguments which become ports) let findOutputPathNodes inst_id vname methods = - [ (clk, PNStateMethodRes inst_id meth_id) | - (meth_id, _, _, Just res, clk) <- methods, - res == vname + [ (clk, PNStateMethodRes inst_id meth_id res_num) | + (meth_id, _, _, numbered_res, clk) <- methods, + (res_name, res_num) <- numbered_res, + res_name == vname ] findInputPathNodes inst_id vname methods argpairs = [ (Nothing, PNStateArgument inst_id arg_id arg_num) | @@ -885,7 +908,7 @@ aPathsPreSched errh flags apkg = do n <- filter (\x -> not (S.member x pathnodeset)) [n1,n2] ] when (not (null unknown_nodes)) $ internalError ("APath.aPaths': nodes not in graph: " ++ - show unknown_nodes) + ppReadable unknown_nodes ++ "\npathnodes = " ++ ppReadable pathnodes) -- ==================== -- Construct the graph @@ -905,10 +928,10 @@ aPathsPreSched errh flags apkg = do -- For urgency to be computed by paths, we must assume a path from -- a method's ready signal to its enable signal. - let rdy_to_en_edges = [(PNTopMethodRes rdy_id, PNTopMethodEnable m_id) | + let rdy_to_en_edges = [(PNTopMethodRes rdy_id 1, PNTopMethodEnable m_id) | (AIAction { aif_pred = (ASDef _ rdy_id), aif_name = m_id, aif_fieldinfo = m_fi }) <- ifc ] ++ - [(PNTopMethodRes rdy_id, PNTopMethodEnable m_id) | + [(PNTopMethodRes rdy_id 1, PNTopMethodEnable m_id) | (AIActionValue { aif_pred = (ASDef _ rdy_id), aif_name = m_id, aif_fieldinfo = m_fi }) <- ifc ] @@ -928,7 +951,7 @@ aPathsPreSched errh flags apkg = do -- edges from WF to RDY of value method [ (wf_rule_id, meth_id, filtered_path) | (PNWillFire wf_rule_id, rs) <- zip will_fire_nodes reachables, - (AIDef { aif_value = (ADef meth_id _ _ _) }) <- ifc, + (AIDef { aif_name = meth_id }) <- ifc, let meth_node = (PNTopMethodReady meth_id), let mpath = lookup meth_node rs, isJust mpath, @@ -1066,14 +1089,14 @@ aPathsPostSched flags pps apkg pathGraphInfo (ASchedule scheds _) = do -- We don't currently need the argument conversion info, because -- the node already contains the converted name (and not the number) let meth_info_map = M.fromList $ - [ (meth_id, ({-numbered_args,-} maybe_EN, maybe_res)) | + [ (meth_id, ({-numbered_args,-} maybe_EN, res)) | meth <- apkg_interface apkg, let vfieldinfo = aif_fieldinfo meth, let meth_id = vf_name vfieldinfo, --let args = map fst (vf_inputs vfieldinfo), --let numbered_args = zip args [1..], let maybe_EN = (vf_enable vfieldinfo) >>= return . fst, - let maybe_res = (vf_output vfieldinfo) >>= return . fst + let res = (vf_outputs vfieldinfo) >>= return . fst ] let findMethod m = @@ -1084,10 +1107,9 @@ aPathsPostSched flags pps apkg pathGraphInfo (ASchedule scheds _) = do -- the "arg" is already the VName and not a number let convertArg m arg = aidToVName arg - let convertRes m = + let convertRes m res_num = case (findMethod m) of - (_, Just res) -> res - _ -> internalError ("APaths convertRes: " ++ ppReadable m) + (_, res) -> res `genericIndex` (res_num - 1) let convertEnable m = case (findMethod m) of @@ -1096,7 +1118,7 @@ aPathsPostSched flags pps apkg pathGraphInfo (ASchedule scheds _) = do -- convert PathNode back to VName let pnToVName (PNTopMethodArg m arg) = convertArg m arg - pnToVName (PNTopMethodRes m) = convertRes m + pnToVName (PNTopMethodRes m res) = convertRes m res pnToVName (PNTopMethodEnable m) = convertEnable m pnToVName (PNTopArgument a _) = aidToVName a pnToVName (PNTopClkGate a) = aidToVName a @@ -1219,9 +1241,31 @@ findEdges env (AMethCall t i qmi exprs) = (edges, ms) = concatUnzip (map f (zip [1..] exprs)) meth_arg_mux = PNStateMethodArgMux i mi muxes = if null exprs then ms else meth_arg_mux:ms - in ([PNStateMethodRes i mi], edges, muxes) + in ([PNStateMethodRes i mi 1], edges, muxes) findEdges env (AMethValue t i qmi) = - ([PNStateMethodRes i (unQualId qmi)], [], []) + ([PNStateMethodRes i (unQualId qmi) 1], [], []) +findEdges env (ATupleSel _ (AMethCall t i qmi exprs) oi) = + -- make edges between exprs and meth input + -- return the output connection + let mi = unQualId qmi + -- like mkEdgesWithMux, but want to return the muxes, not connect them + f (n,exp) = let (is, edges, muxes) = findEdges env exp + pn = PNStateMethodArg i mi n + es = edges ++ (connectEdge pn is) + in (es, muxes) + (edges, ms) = concatUnzip (map f (zip [1..] exprs)) + meth_arg_mux = PNStateMethodArgMux i mi + muxes = if null exprs then ms else meth_arg_mux:ms + in ([PNStateMethodRes i mi oi], edges, muxes) +findEdges env (ATupleSel _ (AMethValue t i qmi) oi) = + ([PNStateMethodRes i (unQualId qmi) oi], [], []) +findEdges env (ATupleSel _ e _) = + internalError + ("APaths.findEdges: unexpected ATupleSel expression: " ++ ppReadable e) + +findEdges env (ATuple _ es) = + -- return any connections found in the element expressions + concatUnzip3 (map (findEdges env) es) findEdges env (ANoInlineFunCall { ae_args = es }) = -- return the function call inputs -- and return any connections found in the argument expressions diff --git a/src/comp/ARankMethCalls.hs b/src/comp/ARankMethCalls.hs index 9826b41b9..9b6a946f6 100644 --- a/src/comp/ARankMethCalls.hs +++ b/src/comp/ARankMethCalls.hs @@ -42,7 +42,7 @@ aRankMethCalls errh pprops orig_pkg = aRankMethCallsInternal :: ErrorHandle -> [[Id]] -> APackage -> IO APackage aRankMethCallsInternal _ [] orig_pkg = return orig_pkg aRankMethCallsInternal errh orig_ranks orig_pkg = - do let method_map = [(aIfaceName m, m) | m <- apkg_interface orig_pkg] + do let method_map = [(aif_name m, m) | m <- apkg_interface orig_pkg] rule_map = [(dropRulePrefixId (arule_id r), r) | r <- apkg_rules orig_pkg] def_map = [(adef_objid d, d) | d <- apkg_local_defs orig_pkg] -- add method ready signals foreach method in (* perf_spec *) @@ -121,6 +121,7 @@ class RankMethCalls ats_t where rankMethCalls :: Int -> ats_t -> (ats_t, [Id] {- local defs to rank -}) instance RankMethCalls AExpr where + -- TODO handle ATupleSel here? rankMethCalls ver expr@(AMethCall { ameth_id = name, ae_args = args }) = let (ranked_args, defs_to_rewrite) = rankMethCalls ver args in (expr { ameth_id = rankId ver name, ae_args = ranked_args }, diff --git a/src/comp/ARenameIO.hs b/src/comp/ARenameIO.hs index deb852f21..9403b7b44 100644 --- a/src/comp/ARenameIO.hs +++ b/src/comp/ARenameIO.hs @@ -134,11 +134,11 @@ trSI mp si = trM (Nothing) = Nothing trM (Just x) = Just (tr mp x) - trMeth ami@(ASPMethodInfo i ty mr me mv args rs) = + trMeth ami@(ASPMethodInfo i ty mr me vs args rs) = ami { aspm_name = tr mp i, aspm_mrdyid = trM mr, aspm_menableid = trM me, - aspm_mresultid = trM mv, + aspm_resultids = map (tr mp) vs, aspm_inputs = map (tr mp) args } in ASPSignalInfo { diff --git a/src/comp/ASchedule.hs b/src/comp/ASchedule.hs index 5b152464e..6a5d2127b 100644 --- a/src/comp/ASchedule.hs +++ b/src/comp/ASchedule.hs @@ -4146,13 +4146,13 @@ cvtIfc (AIActionValue _ _ ifPred ifId ifRs (ADef dId t _ _) _) = -- call will be in the same Rule structure as the action part) -- (note that, if the method body is not split into multiple -- rule, dId and rId will be the same) - [(Rule rId rOrig [ifPred, rPred] [ifPred, rPred, dExpr] rActs) + [(Rule rId rOrig [ifPred, rPred] ([ifPred, rPred, dExpr]) rActs) | (ARule rId rps rDesc rWireProps rPred rActs _ rOrig) <- ifRs] - where dExpr = ASDef t dId -cvtIfc (AIDef _ _ _ ifPred (ADef dId t _ _) _ _) - | isRdyId dId = [] - | otherwise = [(Rule dId Nothing [ifPred] [ifPred,dExpr] [])] - where dExpr = ASDef t dId + where dExpr = ASDef t dId +cvtIfc (AIDef mId _ _ _ _ _ _) | isRdyId mId = [] +cvtIfc (AIDef mId _ _ ifPred (ADef dId t _ _) _ _) = + [(Rule mId Nothing [ifPred] [ifPred, dExpr] [])] + where dExpr = ASDef t dId cvtIfc (AIClock {}) = [] cvtIfc (AIReset {}) = [] cvtIfc (AIInout {}) = [] diff --git a/src/comp/AState.hs b/src/comp/AState.hs index dda4ded85..d4ab80910 100644 --- a/src/comp/AState.hs +++ b/src/comp/AState.hs @@ -37,6 +37,7 @@ import AUses(useDropCond) import AVerilogUtil(vNameToTask) import RSchedule(RAT, ratToNestedLists) import Wires(WireProps(..)) +import Data.Maybe (listToMaybe) --import Debug.Trace --import Util(traces) @@ -209,12 +210,12 @@ aState' flags pps schedule_info apkg = do -- We separate out the RDY defs for always_ready methods from others, -- because we want the defs (they feed into enables) but do want the -- RDY ports. - isAlwaysReadyMethod m = (isRdyId (aIfaceName m)) && (isAlwaysRdy pps (aIfaceName m)) + isAlwaysReadyMethod m = (isRdyId (aif_name m)) && (isAlwaysRdy pps (aif_name m)) (always_rdy_ifc,other_ifc) = partition isAlwaysReadyMethod ifc outs :: [ADef] - outs = concatMap (outputDefToADef fmod pps) other_ifc + outs = concatMap (outputDefToADefs fmod pps) other_ifc always_ready_defs :: [ADef] - always_ready_defs = concatMap (outputDefToADef fmod pps) always_rdy_ifc + always_ready_defs = concatMap (outputDefToADefs fmod pps) always_rdy_ifc --traceM( "ifc are: " ++ ppReadable ifc ) ; --traceM( "outs are: " ++ ppReadable outs ) ; @@ -413,7 +414,7 @@ aState' flags pps schedule_info apkg = do -- mkEmuxxs needs to know which are the value methods, because -- selectors for muxes are RDY for value methods (instead of WILLFIRE) - value_method_ids = [ i | (AIDef { aif_value = (ADef i _ _ _) }) <- ifc ] + value_method_ids = [ i | (AIDef { aif_name = i }) <- ifc ] -- muxes for values (definitions) (emux_selss, emux_valss, emux_outss, esss) = @@ -444,7 +445,9 @@ aState' flags pps schedule_info apkg = do -- actionvalue method value references can be unconditionally converted subst :: AExpr -> Maybe AExpr subst (AMethValue vt modId methId) = - Just (ASPort vt (mkMethId modId methId Nothing MethodResult)) + Just (ASPort vt (mkMethId modId methId Nothing (MethodResult 1))) + subst (ATupleSel vt (AMethValue _ modId methId) idx) = + Just (ASPort vt (mkMethId modId methId Nothing (MethodResult idx))) -- substitute AMOsc, AMGate, AMReset references with their port subst (AMGate gt modId clkId) = Just (mkOutputGatePort vmi_map modId clkId) @@ -455,7 +458,15 @@ aState' flags pps schedule_info apkg = do let ino = do mult <- M.lookup (modId, methId) omMultMap -- send unused calls of multi-ported methods to port 0 toMaybe (mult > 1) 0 - in Just (ASPort vt (mkMethId modId methId ino MethodResult)) + in Just (ASPort vt (mkMethId modId methId ino (MethodResult 1))) + me' -> me' + subst e@(ATupleSel vt (AMethCall _ modId methId es) idx) = + case (M.lookup e substs) of + Nothing -> + let ino = do mult <- M.lookup (modId, methId) omMultMap + -- send unused calls of multi-ported methods to port 0 + toMaybe (mult > 1) 0 + in Just (ASPort vt (mkMethId modId methId ino (MethodResult idx))) me' -> me' -- AMethValue, AMGate and AMethCall should cover it subst e = Nothing @@ -658,7 +669,7 @@ genModVars vs omMultMap = allmvars -- and whether it's an action method) -- ( m@(Method { vf_name = methId, vf_inputs = argIds, vf_mult = mult }), - (argTypes, en_type, val_type) ) + (argTypes, en_type, val_types) ) <- zip (vFields vmodinfo) methType, -- -- for each part of the method, produce a triple of @@ -674,9 +685,8 @@ genModVars vs omMultMap = allmvars Nothing -> [] (Just t) -> [(MethodEnable, t, True)]) ++ -- value triple - (case (val_type) of - Nothing -> [] - (Just t) -> [(MethodResult, t, False)]), + [(MethodResult n, t, False) + | (n, t) <- zip [1..] val_types ], -- uniquifiers for multiple ports -- (if only one copy, then the list just contains 0) ino <- map (toMaybe (mult > 1)) [ 0 .. (getMultUse (modId, methId) - 1) `max` 0 ], @@ -709,25 +719,38 @@ isForeign (ATaskAction { }) = True isForeign _ = False --- Create an output ADef from the Interface method +-- Create output ADefs from the Interface method -- consider only value method returns and outputs of ActionValue methods -- note that expressions are named according to the information on -- the VFieldInfo -outputDefToADef :: Bool -> [PProp] -> AIFace -> [ADef] -outputDefToADef fmod pps ai@(AIDef{}) = if convert then [newdef] else [] - where def = aif_value ai - resName = mkNamedOutput (aif_fieldinfo ai) - newdef = def{ adef_objid = resName } - convert = not (fmod && isRdyId (aif_name ai)) -outputDefToADef _ pps ai@(AIActionValue{}) = [newdef] - where def = aif_value ai - resName = mkNamedOutput (aif_fieldinfo ai) - newdef = def{ adef_objid = resName } -outputDefToADef _ _ a@(AIAction{}) = [] -outputDefToADef _ _ a@(AIClock{}) = [] -outputDefToADef _ _ a@(AIReset{}) = [] -outputDefToADef _ _ a@(AIInout{}) = [] - +outputDefToADefs :: Bool -> [PProp] -> AIFace -> [ADef] +outputDefToADefs fmod pps (AIDef{aif_name=name, aif_value=def, aif_fieldinfo=fi}) = if convert then newdefs else [] + where resNames= mkNamedOutputs fi + newdefs = outputADefToADefs def resNames + convert = not (fmod && isRdyId name) +outputDefToADefs _ pps (AIActionValue{aif_name=name, aif_value=def, aif_fieldinfo=fi}) = newdefs + where resNames= mkNamedOutputs fi + newdefs = outputADefToADefs def resNames +outputDefToADefs _ _ a@(AIAction{}) = [] +outputDefToADefs _ _ a@(AIClock{}) = [] +outputDefToADefs _ _ a@(AIReset{}) = [] +outputDefToADefs _ _ a@(AIInout{}) = [] + +outputADefToADefs :: ADef -> [Id] -> [ADef] +outputADefToADefs (ADef { adef_type = ATTuple ts, adef_expr = ATuple _ es }) resNames = + zipWith3 (\t e resName -> ADef { adef_objid = resName, + adef_type = t, + adef_expr = e, + adef_props = [] }) + ts es resNames +outputADefToADefs (ADef { adef_type = t, adef_expr = e }) [resName] = + [ADef { adef_objid = resName, + adef_type = t, + adef_expr = e, + adef_props = [] }] +outputADefToADefs (ADef { adef_type = ATBit 0}) [] = [] +outputADefToADefs def resNames = + internalError $ "outputADefToADefs: unexpected ADef resNames: " ++ ppReadable (def, resNames) getVInst :: AId -> [AVInst] -> AVInst getVInst i as = head ( [ a | a <- as, i == (avi_vname a) ] ++ @@ -756,7 +779,7 @@ mkSIMethodTuple (AIDef name args _ pred _ vfi _) = aspm_type = "value", aspm_mrdyid = Just rdy, aspm_menableid = Nothing, - aspm_mresultid = Just res, + aspm_resultids = res, aspm_inputs = map fst args, aspm_assocrules = [] } ] @@ -767,7 +790,7 @@ mkSIMethodTuple (AIAction args _ pred name rs vfi) = aspm_type = "action", aspm_mrdyid = Just rdy, aspm_menableid = Just ena, - aspm_mresultid = Nothing, + aspm_resultids = [], aspm_inputs = map fst args, aspm_assocrules = map aRuleName rs } ] @@ -778,7 +801,7 @@ mkSIMethodTuple (AIActionValue args _ pred name rs _ vfi) = aspm_type = "actionvalue", aspm_mrdyid = Just rdy, aspm_menableid = Just ena, - aspm_mresultid = Just res, + aspm_resultids = res, aspm_inputs = map fst args, aspm_assocrules = map aRuleName rs } ] @@ -808,8 +831,8 @@ mkSignalInfoMethod aifaces = merged mergePorts [a] = [a] mergePorts [a, b] = [res] where res = case (isRdyId (aspm_name a), isRdyId (aspm_name b)) of - (True, False) -> b { aspm_mrdyid = (aspm_mresultid a) } - (False, True) -> a { aspm_mrdyid = (aspm_mresultid b) } + (True, False) -> b { aspm_mrdyid = listToMaybe (aspm_resultids a) } + (False, True) -> a { aspm_mrdyid = listToMaybe (aspm_resultids b) } _ -> internalError( "mergePorts" ++ ppReadable (a,b) ) mergePorts x = internalError( "mergePorts2:" ++ ppReadable x ) @@ -830,6 +853,7 @@ ratToBlobs mMap omMultMap rat = let -- True if there are 2 or more uses of the method, -- which means we need to do some sort of muxing + nonTrivial :: MethBlob -> Bool nonTrivial (_, (((AMethCall _ _ _ _, _) : _) : _)) = True nonTrivial _ = False @@ -1014,8 +1038,7 @@ mkEmuxs :: ([AExpr] -> [AExpr]) -> ([AExpr] -> AExpr) -> AId -> AId -> Maybe Integer -> MethPortBlob -> ([ADef], [ADef], [ADef], AExprSubst) mkEmuxs tl cnd rdb value_method_ids om o m ino emrs = - let meth_id = mkMethId o m ino MethodResult - + let -- Break each MethPortBlob into a list of the expressions for -- each argument, and then transpose the entire structure to -- make a list of, for each argument, a list of the different @@ -1031,8 +1054,16 @@ mkEmuxs tl cnd rdb value_method_ids om o m ino emrs = [1..] arg_blobs (sel_defs, val_defs, out_defs) = concatUnzip3 def_tuples + mkPortSubsts (e, _) = + case aType e of + ATTuple ats -> + [ (ATupleSel at e idx, + ASPort at $ mkMethId o m ino $ MethodResult idx) + | (idx, at) <- zip [1..] ats ] + at -> [ (e, ASPort at $ mkMethId o m ino $ MethodResult 1) ] + -- Replace the method call with the output port of the method - subst = [(e, ASPort (aType e) meth_id) | (e, _) <- emrs] + subst = concatMap mkPortSubsts emrs in -- traces ("mkEmuxs " ++ ppReadable emrs ++ ppReadable xs) $ (sel_defs, val_defs, out_defs, subst) diff --git a/src/comp/ASyntax.hs b/src/comp/ASyntax.hs index c60a6c0a0..c08febd54 100644 --- a/src/comp/ASyntax.hs +++ b/src/comp/ASyntax.hs @@ -61,14 +61,12 @@ module ASyntax( isUnsizedString, dropSize, unifyStringTypes, + isTupleType, getArrayElemType, getArraySize, - aIfaceName, - aIfaceNameString, aIfaceProps, - aIfaceResSize, - aIfaceResType, - aIfaceResId, + aIfaceResTypes, + aIfaceResIds, aIfaceArgs, aIfaceArgSize, aIfaceRules, @@ -97,6 +95,8 @@ module ASyntax( ppeAPackage, mkMethId, mkMethStr, + mkMethArgStr, + mkMethResStr, isMethId, MethodPart(..), getParams, @@ -127,12 +127,12 @@ import Prim import ErrorUtil(internalError) import Backend import Pragma -import PreStrings(fsDollar, fsUnderscore, fsEnable) +import PreStrings(fsDollar, fsUnderscore, fsEnable, fs_arg, fs_res) import FStringCompat -- import Position(noPosition) import Position import Data.Maybe -import Util(itos, fromJustOrErr) +import Util(itos) import VModInfo import Wires import ProofObligation(ProofObligation, MsgFn) @@ -340,7 +340,7 @@ data ASPMethodInfo = ASPMethodInfo { aspm_type :: String, aspm_mrdyid :: Maybe AId, aspm_menableid :: Maybe AId, - aspm_mresultid :: Maybe AId, + aspm_resultids :: [AId], aspm_inputs :: [AId], aspm_assocrules :: [AId] } @@ -351,7 +351,7 @@ instance PPrint ASPMethodInfo where <+> text (aspm_type aspmi) <> equals <> braces ( pPrint d 0 (aspm_mrdyid aspmi) <+> pPrint d 0 (aspm_menableid aspmi) <+> - pPrint d 0 (aspm_mresultid aspmi) <+> + pPrint d 0 (aspm_resultids aspmi) $+$ pPrint d 0 (aspm_inputs aspmi) $+$ pPrint d 0 (aspm_assocrules aspmi) ) @@ -446,6 +446,10 @@ data AType = atr_length :: ASize, atr_elem_type :: AType } + -- Tuple type, for methods with multiple return values + | ATTuple { + att_elem_types :: [AType] + } -- abstract type, PrimAction, Interface, Clock, .. -- (can take size parameters as arguments) | ATAbstract { @@ -459,6 +463,7 @@ instance NFData AType where rnf (ATString msz) = rnf msz rnf ATReal = () rnf (ATArray len typ) = rnf2 len typ + rnf (ATTuple typs) = rnf typs rnf (ATAbstract aid args) = rnf2 aid args instance HasPosition AType where @@ -505,6 +510,10 @@ unifyStringTypes (t:ts) | isUnsizedString t = t helper t (t1:ts) | t /= t1 = dropSize t | otherwise = helper t ts +isTupleType :: AType -> Bool +isTupleType (ATTuple _) = True +isTupleType _ = False + type ASize = Integer getArrayElemType :: AType -> AType @@ -571,10 +580,10 @@ data AVInst = AVInst { -- XXX This list corresponds to vFields in the VModInfo, but cannot be -- XXX stored there, because VModInfo is created before types are known. -- There is a triple for each method in vFields of VModInfo. - -- The triple contains the types of each argument (in order) and maybe - -- the types of the EN and return value. + -- The triple contains the types of each argument (in order), maybe + -- the type of the EN, and the return values. -- NOTE: These are the output language types (i.e. ATBit n) - avi_meth_types :: [([AType], Maybe AType, Maybe AType)], + avi_meth_types :: [([AType], Maybe AType, [AType])], -- This field maps source-language types to their corresponding ports avi_port_types :: M.Map VName IType, avi_vmi :: VModInfo, -- Verilog names, conflict info, etc. @@ -672,11 +681,12 @@ getIfcInoutPorts :: AVInst -> [(AId, (AId, AType, VPort))] getIfcInoutPorts avi = let vmi = avi_vmi avi - res_types = map (\ (_,_,mr) -> mr) (avi_meth_types avi) + res_types = map (\ (_,_,rs) -> rs) (avi_meth_types avi) ifc_inouts = [(id,vn,ty) - | (Inout id vn _ _, mr) <- zip (vFields vmi) res_types, - let ty = fromJustOrErr ("ASyntax.unknown inout " ++ - ppReadable id) mr] + | (Inout id vn _ _, rs) <- zip (vFields vmi) res_types, + let ty = case rs of + [r] -> r + _ -> error ("ASyntax.unknown inout " ++ ppReadable id)] mkInoutPort ty vname = (mkOutputWireId (avi_vname avi) vname, @@ -817,17 +827,6 @@ instance NFData AIFace where rnf (AIReset name rst finfo) = rnf3 name rst finfo rnf (AIInout name inout finfo) = rnf3 name inout finfo -aIfaceName :: AIFace -> AId -aIfaceName (AIDef { aif_value = (ADef i _ _ _)}) = i -- XXX use aif_name -aIfaceName (AIAction { aif_name = i}) = i -aIfaceName (AIActionValue { aif_name = i}) = i -aIfaceName (AIClock { aif_name = i}) = i -aIfaceName (AIReset { aif_name = i}) = i -aIfaceName (AIInout { aif_name = i}) = i - -aIfaceNameString :: AIFace -> String -aIfaceNameString i = getIdString (aIfaceName i) - aiface_vname :: AIFace -> String aiface_vname i = getIdString (vf_name (aif_fieldinfo i)) @@ -838,25 +837,18 @@ aIfaceProps (AIAction { aif_props = p }) = p aIfaceProps (AIActionValue { aif_props = p }) = p aIfaceProps _ = emptyWireProps --- result size -aIfaceResSize :: AIFace -> Integer -aIfaceResSize (AIAction { }) = 0 -aIfaceResSize (AIDef {aif_value = (ADef _ (ATBit n) _ _) }) = n -aIfaceResSize (AIActionValue {aif_value = (ADef _ (ATBit n) _ _) }) = n -aIfaceResSize x = internalError ("aIfaceResSize: " ++ show x) - -aIfaceResType :: AIFace -> AType +aIfaceResTypes :: AIFace -> [AType] -- XXX should be ATAction? -aIfaceResType (AIAction { }) = ATBit 0 -aIfaceResType (AIDef { aif_value = (ADef _ t _ _)}) = t -aIfaceResType (AIActionValue { aif_value = (ADef _ t _ _)}) = t +aIfaceResTypes (AIAction { }) = [ATBit 0] +aIfaceResTypes (AIDef { aif_value = (ADef _ t _ _) }) = [t] +aIfaceResTypes (AIActionValue { aif_value = (ADef _ t _ _) }) = [t] -- should not need type of clock or reset -aIfaceResType x = internalError ("aIfaceResType: " ++ show x) +aIfaceResTypes x = internalError ("aIfaceResTypes: " ++ show x) -aIfaceResId :: AIFace -> [AId] -aIfaceResId (AIDef {aif_value = (ADef i _ _ _) }) = [i] -aIfaceResId (AIActionValue {aif_value = (ADef i _ _ _) }) = [i] -aIfaceResId _ = [] +aIfaceResIds :: AIFace -> [AId] +aIfaceResIds (AIDef {aif_name=id}) = [id] +aIfaceResIds (AIActionValue {aif_name=id}) = [id] +aIfaceResIds _ = [] aIfaceArgs :: AIFace -> [AInput] aIfaceArgs (AIClock {}) = [] @@ -904,7 +896,7 @@ addRdyToARule rdyId r0@(ARule { arule_id = ri, arule_pred = e }) = (d, r) aIfaceSchedNames :: AIFace -> [ARuleId] aIfaceSchedNames (AIAction { aif_body = rs}) = map arule_id rs aIfaceSchedNames (AIActionValue { aif_body = rs}) = map arule_id rs -aIfaceSchedNames (AIDef { aif_value = d }) = [adef_objid d] +aIfaceSchedNames (AIDef { aif_name = i }) = [i] aIfaceSchedNames _ = [] aIfacePred :: AIFace -> APred @@ -1054,6 +1046,16 @@ data AExpr ae_objid :: AId, ameth_id :: AMethodId } + | ATuple { + ae_type :: AType, + ae_elems :: [AExpr] + } + -- selection from an ATTuple + | ATupleSel { + ae_type :: AType, + ae_exp :: AExpr, + ae_index :: Integer + } -- calls a combinatorial function expressed via module instantiation -- XXX this can be created not only via "noinline" in BSV, -- XXX but also "foreign" in Classic syntax; consider renaming? @@ -1152,6 +1154,8 @@ instance NFData AExpr where rnf (APrim oid typ prim args) = rnf4 oid typ prim args rnf (AMethCall typ oid mid args) = rnf4 typ oid mid args rnf (AMethValue typ oid mid) = rnf3 typ oid mid + rnf (ATuple typ elems) = rnf2 typ elems + rnf (ATupleSel typ expr index) = rnf3 typ expr index rnf (ANoInlineFunCall typ oid fun args) = rnf4 typ oid fun args rnf (AFunCall typ oid fname isC args) = rnf5 typ oid fname isC args rnf (ATaskValue typ oid fname isC cookie) = rnf5 typ oid fname isC cookie @@ -1177,6 +1181,12 @@ instance Eq AExpr where AMethValue t aid mid == AMethValue t' aid' mid' = (t == t') && (mid == mid') && (aid == aid') + ATuple t aexprs == ATuple t' aexprs' = + (t == t') && (aexprs == aexprs') + + ATupleSel t aexpr index == ATupleSel t' aexpr' index' = + (t == t') && (index == index') && (aexpr == aexpr') + ANoInlineFunCall t aid af aexprs == ANoInlineFunCall t' aid' af' aexprs' = (t == t') && (af == af') && (aexprs == aexprs') && (aid == aid') @@ -1222,6 +1232,9 @@ instance HasPosition AExpr where getPosition APrim{ ae_objid = p } = getPosition p getPosition AMethCall{ ae_objid = p } = getPosition p getPosition AMethValue{ ae_objid = p } = getPosition p + getPosition ATuple{ ae_elems = e : _ } = getPosition e + getPosition ATuple{ ae_elems = [] } = noPosition -- Is there something better? + getPosition ATupleSel{ ae_exp = e } = getPosition e getPosition ANoInlineFunCall{ ae_objid = p } = getPosition p getPosition AFunCall{ ae_objid = p } = getPosition p getPosition ATaskValue{ ae_objid = p } = getPosition p @@ -1434,7 +1447,7 @@ instance PPrint AIFace where pPrint d p ai@(AIDef {} ) = (text "--AIDef" <+> pPrint d p (aif_name ai)) $+$ foldr (($+$) . ppV d) empty (aif_inputs ai) $+$ - pPrint d 0 (aif_value ai) $+$ + pPrint d p (aif_value ai) $+$ pPred d p (aif_pred ai) $+$ pPrint d 0 (aif_props ai) $+$ pPrint d 0 (aif_fieldinfo ai) $+$ @@ -1560,9 +1573,14 @@ instance PPrint AExpr where pPrint d p (ATaskValue _ i _ _ n) = pparen (p>0) $ pPrint d 1 i <> text ("#" ++ itos(n)) pPrint d p (AMethCall _ i m es) = pparen (p>0 && not (null es)) $ - pPrint d 1 i <> sep (text "." <> ppMethId d m : map (pPrint d 1) es) + pPrint d 1 i <> + sep (text "." <> ppMethId d m : map (pPrint d 1) es) pPrint d p (AMethValue _ i m) = pparen (p>0) $ pPrint d 1 i <> text "." <> ppMethId d m + pPrint d p (ATuple _ es) = + pparen (p>0) $ parens (commaSep (map (pPrint d 0) es)) + pPrint d p (ATupleSel _ e idx) = + pparen (p>0) $ pPrint d 0 e <> text "[" <> pPrint d 0 idx <> text "]" pPrint d p (ASPort _ i) = pPrint d p i pPrint d p (ASParam _ i) = pPrint d p i pPrint d p (ASDef _ i) = pPrint d p i @@ -1592,6 +1610,8 @@ instance PPrint AType where pPrint d p (ATString (Just n)) = text ("String (" ++ (itos n) ++ " chars)") pPrint d p (ATArray sz ty) = text "Array" <+> text (itos sz) <+> pPrint d 0 ty + pPrint d p (ATTuple ts) = + text "Tuple" <+> parens (commaSep (map (pPrint d 0) ts)) pPrint d p (ATAbstract i ns) = sep (text "ABSTRACT: " : pPrint d 0 i : map (pPrint d 0) ns) binOp :: PrimOp -> Bool @@ -1854,7 +1874,12 @@ instance PPrintExpand AExpr where <> if (null es) then empty else (parens (hsep ( punctuate comma docArgs )) ) where docArgs = map (pPrintExpand m d defContext) es - pPrintExpand m d ec (AMethValue _ i meth) = pPrint d 1 i <> text "." <> ppMethId d meth + pPrintExpand m d ec (AMethValue _ i meth) = + pPrint d 1 i <> text "." <> ppMethId d meth + pPrintExpand m d ec (ATuple _ es) = + pparen (useParen ec) $ parens (commaSep (map (pPrintExpand m d defContext) es)) + pPrintExpand m d ec (ATupleSel _ e idx) = + pparen (useParen ec) $ pPrintExpand m d defContext e <> text ("[" ++ itos idx ++ "]") pPrintExpand m d ec (ASPort _ i) = pPrint d (getP ec) i pPrintExpand m d ec (ASParam _ i) = pPrint d (getP ec) i pPrintExpand m d ec (ASDef _ i) | isIdWillFire i && (lookupLevel m) > 0 || @@ -1885,19 +1910,21 @@ defLookup d ped = M.findWithDefault err d (defmap ped) -- # Some standardized methods for making (default) method strings -- ############################################################################# data MethodPart = - MethodArg Integer | -- argument 1, 2, ... input - MethodResult | -- return value output - MethodEnable -- enable signal input + MethodArg Integer | -- argument 1, 2, ... input + MethodResult Integer | -- return value 1, 2, ... output + MethodEnable -- enable signal input deriving (Eq) -- The method syntax is as follows: --- Arguments are $_ starting from 1 --- (e.g. the_fifo$enq_1) --- Return values are $ (e.g. the_fifo$first) +-- Arguments are $_ARG_ starting from 1 +-- (e.g. the_fifo$enq_ARG_1) +-- Return values are $_RES_ (e.g. the_fifo$first_RES_1) -- Enable signals are $EN_ (e.g. the_fifo$EN_enq) --- Multi-ported methods are $__ +-- Multi-ported methods are $__ARG_ +-- or $__RES_ -- The portnum is only omitted if the method has one or -- and infinite number of ports (like a register) +-- XXX these should probably just be a data type rather than Ids mkMethId :: Id -> Id -> Maybe Integer -> MethodPart -> Id mkMethId o m ino mp = -- trace ("POS O: " ++ (show (getIdPosition o)) ++ " " ++ @@ -1922,13 +1949,8 @@ mkMethStr obj m m_port mp = fsUnderscore, mkNumFString port] base = case mp of - MethodArg n -> - if (n == 0) - then internalError "mkMethStr" - else concatFString [meth_port, - fsUnderscore, - mkNumFString n] - MethodResult -> meth_port + MethodArg n -> mkMethArgStr meth_port n + MethodResult n -> mkMethResStr meth_port n MethodEnable -> -- XXX are we overloading fsEnable? concatFString [fsEnable, meth_port] @@ -1937,6 +1959,18 @@ mkMethStr obj m m_port mp = fsDollar, base] +mkMethArgStr :: FString -> Integer -> FString +mkMethArgStr meth_port n = + if (n == 0) + then internalError "mkMethArgStr" + else concatFString [meth_port, fsUnderscore, fs_arg, mkNumFString n] + +mkMethResStr :: FString -> Integer -> FString +mkMethResStr meth_port n = + if (n == 0) + then internalError "mkMethResStr" + else concatFString [meth_port, fsUnderscore, fs_res, mkNumFString n] + -- ############################################################################# -- # -- ############################################################################# diff --git a/src/comp/ASyntaxUtil.hs b/src/comp/ASyntaxUtil.hs index 561672e45..a12b6580d 100644 --- a/src/comp/ASyntaxUtil.hs +++ b/src/comp/ASyntaxUtil.hs @@ -72,6 +72,8 @@ instance AVars AExpr where aVars (ANoInlineFunCall _ _ _ es) = concatMap aVars es aVars (AFunCall _ _ _ _ es) = concatMap aVars es aVars (AMethCall _ _ _ es) = concatMap aVars es + aVars (ATuple _ es) = concatMap aVars es + aVars (ATupleSel _ e _) = aVars e -- aVars (ATaskValue ...) = [] -- because the variables are really "used" -- by the action which sets it -- same for AMethValue @@ -117,6 +119,8 @@ aMethValues :: AExpr -> [(AId, AId, AType)] aMethValues e@(APrim {}) = concatMap aMethValues (ae_args e) aMethValues e@(AMethCall {}) = concatMap aMethValues (ae_args e) aMethValues (AMethValue ty obj meth) = [(obj,meth,ty)] +aMethValues (ATuple _ es) = concatMap aMethValues es +aMethValues (ATupleSel _ e _) = aMethValues e aMethValues e@(ANoInlineFunCall {}) = concatMap aMethValues (ae_args e) aMethValues e@(AFunCall {}) = concatMap aMethValues (ae_args e) aMethValues (ATaskValue {}) = [] @@ -137,6 +141,8 @@ aMethCalls :: AExpr -> [(AId, AId)] aMethCalls e@(APrim {}) = concatMap aMethCalls (ae_args e) aMethCalls (AMethCall _ obj meth es) = ((obj,meth) : concatMap aMethCalls es) aMethCalls (AMethValue _ obj meth) = [] +aMethCalls (ATuple _ es) = concatMap aMethCalls es +aMethCalls (ATupleSel _ e _) = aMethCalls e aMethCalls e@(ANoInlineFunCall {}) = concatMap aMethCalls (ae_args e) aMethCalls e@(AFunCall {}) = concatMap aMethCalls (ae_args e) aMethCalls (ATaskValue {}) = [] @@ -157,6 +163,8 @@ aTaskValues :: AExpr -> [(AId, Integer, AType)] aTaskValues e@(APrim {}) = concatMap aTaskValues (ae_args e) aTaskValues e@(AMethCall {}) = concatMap aTaskValues (ae_args e) aTaskValues (AMethValue {}) = [] +aTaskValues (ATuple _ es) = concatMap aTaskValues es +aTaskValues (ATupleSel _ e _) = aTaskValues e aTaskValues e@(ANoInlineFunCall {}) = concatMap aTaskValues (ae_args e) aTaskValues e@(AFunCall {}) = concatMap aTaskValues (ae_args e) aTaskValues (ATaskValue ty f_id fun isC cookie) = [(f_id, cookie, ty)] @@ -180,6 +188,8 @@ exprForeignCalls e@(AFunCall {}) = else (concatMap exprForeignCalls (ae_args e)) exprForeignCalls e@(APrim {}) = concatMap exprForeignCalls (ae_args e) exprForeignCalls e@(AMethCall {}) = concatMap exprForeignCalls (ae_args e) +exprForeignCalls (ATuple _ es) = concatMap exprForeignCalls es +exprForeignCalls (ATupleSel _ e _) = exprForeignCalls e exprForeignCalls e@(ANoInlineFunCall {}) = concatMap exprForeignCalls (ae_args e) exprForeignCalls _ = [] @@ -227,6 +237,7 @@ instance ATypeC AType where aSize e = case aType e of ATBit s -> s + ATTuple ts -> sum (map aSize ts) ATString (Just s) -> 8*s -- 8 bits per character ATAbstract i [n] | i==idInout_ -> n ATArray sz t -> sz * (aSize t) @@ -455,6 +466,8 @@ aSubst m = mapAExprs xsub xsub x@(ASDef _ i) = M.findWithDefault x i m xsub (APrim aid t p es) = APrim aid t p (aSubst m es) xsub (AMethCall t i meth es) = AMethCall t i meth (aSubst m es) + xsub (ATuple t es) = ATuple t (aSubst m es) + xsub (ATupleSel t e n) = ATupleSel t (aSubst m e) n xsub (ANoInlineFunCall t i f es) = ANoInlineFunCall t i f (aSubst m es) xsub (AFunCall t i f isC es) = AFunCall t i f isC (aSubst m es) xsub (ASAny t me) = ASAny t (fmap (aSubst m) me) @@ -474,6 +487,12 @@ exprMap f e@(APrim i t o args) = exprMap f e@(AMethCall t i m args) = let e' = AMethCall t i m (map (exprMap f) args) in fromMaybe e' (f e) +exprMap f e@(ATuple t args) = + let e' = ATuple t (map (exprMap f) args) + in fromMaybe e' (f e) +exprMap f e@(ATupleSel t expr n) = + let e' = ATupleSel t (exprMap f expr) n + in fromMaybe e' (f e) exprMap f e@(ANoInlineFunCall t i fun args) = let e' = ANoInlineFunCall t i fun (map (exprMap f) args) in fromMaybe e' (f e) @@ -501,6 +520,18 @@ exprMapM f e@(AMethCall t i m args) = do Just e' -> return e' Nothing -> do args' <- mapM (exprMapM f) args return $ AMethCall t i m args' +exprMapM f e@(ATuple t elems) = do + me <- f e + case me of + Just e' -> return e' + Nothing -> do elems' <- mapM (exprMapM f) elems + return $ ATuple t elems' +exprMapM f e@(ATupleSel t expr n) = do + me <- f e + case me of + Just e' -> return e' + Nothing -> do expr' <- exprMapM f expr + return $ ATupleSel t expr' n exprMapM f e@(ANoInlineFunCall t i fun args) = do me <- f e case me of @@ -527,6 +558,12 @@ exprFold f v e@(APrim i t o args) = exprFold f v e@(AMethCall t i m args) = let v' = foldr (flip (exprFold f)) v args in f e v' +exprFold f v e@(ATuple t elems) = + let v' = foldr (flip (exprFold f)) v elems + in f e v' +exprFold f v e@(ATupleSel t expr n) = + let v' = exprFold f v expr + in f e v' exprFold f v e@(ANoInlineFunCall t i fun args) = let v' = foldr (flip (exprFold f)) v args in f e v' @@ -612,6 +649,10 @@ aIdFnToAExprFn fn (AMethCall ty aid mid args) = AMethCall ty (fn aid) mid (mapAExprs (aIdFnToAExprFn fn) args) aIdFnToAExprFn fn (AMethValue ty aid mid) = AMethValue ty (fn aid) mid +aIdFnToAExprFn fn (ATuple ty exprs) = + ATuple ty (mapAExprs (aIdFnToAExprFn fn) exprs) +aIdFnToAExprFn fn (ATupleSel ty expr n) = + ATupleSel ty (aIdFnToAExprFn fn expr) n aIdFnToAExprFn fn (ANoInlineFunCall ty aid fun args) = ANoInlineFunCall ty (fn aid) fun (mapAExprs (aIdFnToAExprFn fn) args) aIdFnToAExprFn fn (AFunCall ty aid fun isC args) = diff --git a/src/comp/ATaskSplice.hs b/src/comp/ATaskSplice.hs index 42d131c4d..8b821fcd0 100644 --- a/src/comp/ATaskSplice.hs +++ b/src/comp/ATaskSplice.hs @@ -1,7 +1,6 @@ module ATaskSplice(aTaskSplice) where import ASyntax import ASyntaxUtil -import Data.Maybe import Id import qualified Data.Map as M import ErrorUtil(internalError) @@ -14,9 +13,9 @@ aTaskSplice :: APackage -> APackage aTaskSplice apkg = mapAActions (spliceAction spliceMap) apkg where spliceMap = M.fromList [ (n, (id, t)) | ADef id t (ATaskValue { ae_cookie = n }) _ <- defs ] defs = (apkg_local_defs apkg) ++ - (mapMaybe av_ret_def (apkg_interface apkg)) - av_ret_def act@(AIActionValue {}) = Just (aif_value act) - av_ret_def _ = Nothing + (concatMap av_ret_def (apkg_interface apkg)) + av_ret_def act@(AIActionValue {}) = [aif_value act] + av_ret_def _ = [] spliceAction :: SpliceMap -> AAction -> AAction spliceAction spliceMap a@(ATaskAction { ataskact_temp = Nothing }) = diff --git a/src/comp/AUses.hs b/src/comp/AUses.hs index 557271206..cfe6961ba 100644 --- a/src/comp/AUses.hs +++ b/src/comp/AUses.hs @@ -846,6 +846,8 @@ eDomain e@(AMethCall _ i mi es) = do let this_use = singleMethodExprUse i (unQualId mi) e ucTrue es_uses <- mapM eDomain es mergeExprUsesM (this_use : es_uses) +eDomain (ATuple _ es) = mapM eDomain es >>= mergeExprUsesM +eDomain (ATupleSel _ e _) = eDomain e eDomain e@(AFunCall { ae_objid = i, ae_args = es }) = do let this_use = singleFFuncExprUse i e ucTrue es_uses <- mapM eDomain es diff --git a/src/comp/AVeriQuirks.hs b/src/comp/AVeriQuirks.hs index c09ab72bb..86cf40b1b 100644 --- a/src/comp/AVeriQuirks.hs +++ b/src/comp/AVeriQuirks.hs @@ -308,6 +308,12 @@ aQExp top (APrim aid t p es) = mapM (aQExp False) es >>= return . APrim ai aQExp top (AMethCall t i m es) = mapM (aQExp False) es >>= return . AMethCall t i m aQExp top (ANoInlineFunCall t i f es) = mapM (aQExp False) es >>= return . ANoInlineFunCall t i f aQExp top (AFunCall t i f isC es) = mapM (aQExp False) es >>= return . AFunCall t i f isC +aQExp top (ATuple t es) = do + es' <- mapM (aQExp False) es + return (ATuple t es') +aQExp top (ATupleSel t e n) = do + e' <- aQExp False e + return (ATupleSel t e' n) aQExp top e@(AMethValue {}) = return e aQExp top e@(ASInt _ _ _) = return e aQExp top e@(ASReal _ _ _) = return e @@ -396,6 +402,7 @@ aSInt t i = ASInt defaultAId t (ilHex i) mkDefS :: AExpr -> QQState AExpr mkDefS e@(AMethCall _ o m []) = return e -- XXX shouldn't exist mkDefS e@(AMethValue _ o m) = return e -- XXX shouldn't exist +mkDefS e@(ATupleSel _ _ _) = return e -- XXX shouldn't exist mkDefS e@(ASDef {}) = return e mkDefS e@(ASPort {}) = return e mkDefS e@(ASParam {}) = return e diff --git a/src/comp/AVerilog.hs b/src/comp/AVerilog.hs index 155495c48..438d735a8 100644 --- a/src/comp/AVerilog.hs +++ b/src/comp/AVerilog.hs @@ -474,8 +474,8 @@ groupPorts si as = -- (function to be folded over the method port info) findMethod :: ASPMethodInfo -> ([(AId,String,[VArg])],[(Id,VArg)]) -> ([(AId,String,[VArg])],[(Id,VArg)]) - findMethod (ASPMethodInfo i ty mr me mv args _) (ms, ports) = - let is = (catMaybes [mr, me, mv]) ++ args + findMethod (ASPMethodInfo i ty mr me vs args _) (ms, ports) = + let is = (catMaybes [mr, me]) ++ vs ++ args (ps, remaining) = findIds is ports in ((i,ty,ps):ms, remaining) @@ -574,10 +574,10 @@ groupMethodDefs vDef si ds = mkForMethod :: ASPMethodInfo -> ([VMItem], [VMItem], [VMItem], M.Map AId ADef) -> ([VMItem], [VMItem], [VMItem], M.Map AId ADef) - mkForMethod (ASPMethodInfo i ty mr _ mv _ rs) (odecls, idecls, gs, defs) = + mkForMethod (ASPMethodInfo i ty mr _ vs _ rs) (odecls, idecls, gs, defs) = let -- get the output defs - output_ids = catMaybes [mv, mr] + output_ids = vs ++ maybeToList mr (output_defs, other_defs) = findADefs output_ids defs -- get the rule defs rule_sched_ids = concatMap getRuleSignals rs diff --git a/src/comp/AVerilogUtil.hs b/src/comp/AVerilogUtil.hs index 36b06f395..0034e13c6 100644 --- a/src/comp/AVerilogUtil.hs +++ b/src/comp/AVerilogUtil.hs @@ -862,7 +862,7 @@ vState flags rewire_map avinst = mkEnId m m_port = vMethId v_inst_name m m_port MethodEnable port_rename_table - mkResId m m_port = vMethId v_inst_name m m_port MethodResult port_rename_table + mkResId m k m_port = vMethId v_inst_name m m_port (MethodResult k) port_rename_table -- add the multiplicity to Verilog port names -- (if there are not multiple ports, no uniquifier is added) @@ -886,9 +886,10 @@ vState flags rewire_map avinst = inps = [ (mkVId (portid s ino), mkArgId m k ino, vSize argType) - | (meth@(Method m _ _ mult ps mo me), + | (meth@(Method m _ _ mult ps outs me), (argTypes,_,_)) <- zip (vFields vi) mts, + -- (VName s, vps) -- let multu = getMethodMultUse m, ino <- if mult > 1 then map Just [0..mult-1] else [Nothing], (VName s, argType, k) <- zip3 (map fst ps) argTypes [1..], @@ -908,7 +909,7 @@ vState flags rewire_map avinst = mkVId (portid s ino), mkEnId m ino, inhigh ) - | (Method m _ _ mult ss mo me@(Just (VName s,vps))) + | (Method m _ _ mult ss outs me@(Just (VName s,vps))) <- vFields vi, let inhigh = VPinhigh `elem` vps, -- let multu = getMethodMultUse m, @@ -922,9 +923,10 @@ vState flags rewire_map avinst = meth_return_vals = nub [ (mkVId (portid s ino), - mkResId m ino) - | ((Method m _ _ mult ss mo@(Just (VName s, vps)) me), (_,_,Just retType)) + mkResId m k ino) + | ((Method m _ _ mult ss outs me), (_,_,retTypes)) <- zip (vFields vi) mts, + ((VName s, vps), retType, k) <- zip3 outs retTypes [1..], isNotZeroSized retType, -- let multu = getMethodMultUse m, ino <- if mult > 1 then map Just [0..mult-1] else [Nothing] diff --git a/src/comp/BackendNamingConventions.hs b/src/comp/BackendNamingConventions.hs index 7aec08133..bf3e4bdf7 100644 --- a/src/comp/BackendNamingConventions.hs +++ b/src/comp/BackendNamingConventions.hs @@ -96,8 +96,8 @@ rwireHasId = mkId noPosition (mkFString rwireHasStr) rwireSetEnId, rwireSetArgId, rwireGetResId, rwireHasResId :: Id -> Id rwireSetEnId i = mkMethId i rwireSetId Nothing MethodEnable rwireSetArgId i = mkMethId i rwireSetId Nothing (MethodArg 1) -rwireGetResId i = mkMethId i rwireGetId Nothing MethodResult -rwireHasResId i = mkMethId i rwireHasId Nothing MethodResult +rwireGetResId i = mkMethId i rwireGetId Nothing (MethodResult 1) +rwireHasResId i = mkMethId i rwireHasId Nothing (MethodResult 1) -- ============================== -- Primitive CReg @@ -134,7 +134,7 @@ cregReadId n = mkId noPosition (mkFString (cregReadStr n)) cregWriteId n = mkId noPosition (mkFString (cregWriteStr n)) cregReadResId, cregWriteEnId, cregWriteArgId :: Id -> Int -> Id -cregReadResId i n = mkMethId i (cregReadId n) Nothing MethodResult +cregReadResId i n = mkMethId i (cregReadId n) Nothing (MethodResult 1) cregWriteEnId i n = mkMethId i (cregWriteId n) Nothing MethodEnable cregWriteArgId i n = mkMethId i (cregWriteId n) Nothing (MethodArg 1) @@ -351,7 +351,7 @@ regWriteId pos = mkId pos (mkFString regWriteStr) -- XXX no position? regReadResId, regWriteEnId, regWriteArgId :: Id -> Id -regReadResId i = mkMethId i (regReadId noPosition) Nothing MethodResult +regReadResId i = mkMethId i (regReadId noPosition) Nothing (MethodResult 1) regWriteEnId i = mkMethId i (regWriteId noPosition) Nothing MethodEnable regWriteArgId i = mkMethId i (regWriteId noPosition) Nothing (MethodArg 1) @@ -378,17 +378,17 @@ cregToReg old_avi = updVPort new_vn (_, ps) = (new_vn, ps) (new_vFields, new_meth_types) = - let convField (Method nm c r m [] (Just res) Nothing, ts) + let convField (Method nm c r m [] [res] Nothing, ts) | (nm == cregReadId 0) = let nm' = regReadId (getPosition nm) res' = updVPort qoutPortName res - in Just (Method nm' c r m [] (Just res') Nothing, ts) - convField (Method nm c r m [arg] Nothing (Just en), ts) + in Just (Method nm' c r m [] [res'] Nothing, ts) + convField (Method nm c r m [arg] [] (Just en), ts) | (nm == cregWriteId 0) = let nm' = regWriteId (getPosition nm) arg' = updVPort dinPortName arg en' = updVPort enPortName en - in Just (Method nm' c r m [arg'] Nothing (Just en'), ts) + in Just (Method nm' c r m [arg'] [] (Just en'), ts) convField _ = Nothing in unzip $ mapMaybe convField $ @@ -530,11 +530,11 @@ createMapForVMod :: AId -> VFieldInfo -> [(FString,FString)] createMapForVMod _ (Clock _) = [] createMapForVMod _ (Reset _) = [] createMapForVMod _ (Inout {}) = [] -createMapForVMod inst_id (Method meth_id _ _ mult ins mo me) = -- trace (ppReadable result) $ +createMapForVMod inst_id (Method meth_id _ _ mult ins outs me) = -- trace (ppReadable result) $ result where result = zip meths_fstr ports_fstr - (fmeths,fports) = createMapForOneMeth meth_id mult ins me mo + (fmeths,fports) = createMapForOneMeth meth_id mult ins outs me inst_fstr = getIdFString inst_id addInstId fs = concatFString [inst_fstr, fsDollar, fs] meths_fstr = map addInstId fmeths @@ -545,8 +545,8 @@ createMapForVMod inst_id (Method meth_id _ _ mult ins mo me) = -- trace (ppReada -- For a single method, create two lists: -- * The Bluespec names for the arguments and RDY/EN -- (for example, ["set_1","set"] or ["get"]) --- The first items in the list are the arguments, and the last is --- the return value or the enable (depending on the type of method). +-- The first items in the list are the arguments, followed by +-- the return value(s) and/or the enable (depending on the type of method). -- * The Verilog port names corresponding to the Bluespec names -- (for example, ["D_IN","EN"] or ["Q_OUT"]) -- If the method has multiplicity > 1, then the first list @@ -559,37 +559,35 @@ createMapForVMod inst_id (Method meth_id _ _ mult ins mo me) = -- trace (ppReada -- mkMethId in ASyntax -- the two lists should be the same length (this is checked) createMapForOneMeth :: Id -> Integer -> - [VPort] -> Maybe VPort -> Maybe VPort -> + [VPort] -> [VPort] -> Maybe VPort -> ([FString],[FString]) -createMapForOneMeth meth_id mult ins me mo = if check then +createMapForOneMeth meth_id mult ins outs me = if check then -- trace (ppReadable (method_names, verilog_names)) $ (method_names, verilog_names) else err where check = length method_names == length verilog_names err = internalError ("createMapForOneMeth " ++ - ppReadable (meth_id, mult, ins, me, mo)) + ppReadable (meth_id, mult, ins, me, outs)) meth_fstr = getIdFString meth_id meth_mult = if mult <= 1 then [meth_fstr] else [ concatFString [meth_fstr, fsUnderscore, mkNumFString n] | n <- [0 .. mult-1] ] - -- for method "x", make the names "x_1, x_2, .." for the ports - -- make the names x__n for multi-ported methods - method_input_names = [ addNum meth_n arg_n | + -- for method "x", make the names "x_ARG_1, x_ARG_2, .." for the ports + -- make the names x__ARG_n for multi-ported methods + method_input_names = [ mkMethArgStr meth_n (toInteger arg_n) | meth_n <- meth_mult, arg_n <- [1 .. length ins]] - addNum fs n = - concatFString [fs, fsUnderscore, (mkNumFString (toInteger n))] - -- the Verilog port names for the above verilog_input_names = map getFStringForVerilogPair ins - -- names for the output port - (method_output_names, verilog_output_name) = - case (mo) of - Nothing -> ([], []) - Just p -> (meth_mult, [getFStringForVerilogPair p]) + -- names for the output ports + method_output_names = [ mkMethResStr meth_n (toInteger out_n) | + meth_n <- meth_mult, out_n <- [1 .. length outs]] + + -- the Verilog port names for the above + verilog_output_names = map getFStringForVerilogPair outs -- names for the enable (method_enable_names, verilog_enable_name) = @@ -608,14 +606,14 @@ createMapForOneMeth meth_id mult ins me mo = if check then verilog_names_pre_mult = verilog_input_names ++ verilog_enable_name ++ - verilog_output_name + verilog_output_names -- handle the multiplicity for verilog names here -- note how we go from 1..mult instead of 0..mult-1 -- as the method side does verilog_names = if (mult <= 1) then verilog_names_pre_mult - else [addNum fs n | -- PORT_N + else [concatFString [fs, fsUnderscore, (mkNumFString (toInteger n))] | -- PORT_N fs <- verilog_names_pre_mult, n <- [1..mult]] diff --git a/src/comp/BinData.hs b/src/comp/BinData.hs index 96dbac24a..8999c37f4 100644 --- a/src/comp/BinData.hs +++ b/src/comp/BinData.hs @@ -997,6 +997,7 @@ instance Bin AType where writeBytes (ATReal) = do putI 2; writeBytes (ATArray sz t) = do putI 3; toBin sz; toBin t writeBytes (ATAbstract i szs) = do putI 4; toBin i; toBin szs + writeBytes (ATTuple ts) = do putI 5; toBin ts readBytes = do i <- getI case i of @@ -1005,6 +1006,7 @@ instance Bin AType where 2 -> do return ATReal 3 -> do sz <- fromBin; t <- fromBin; return (ATArray sz t) 4 -> do i <- fromBin; szs <- fromBin; return (ATAbstract i szs) + 5 -> do ts <- fromBin; return (ATTuple ts) n -> internalError $ "GenABin.Bin(AType).readBytes: " ++ show n -- ---------- @@ -1034,6 +1036,8 @@ instance Bin AExpr where writeBytes (AMGate t obj clk) = section "AExpr" $ do putI 14; toBin t; toBin obj; toBin clk writeBytes (ASInout t iot) = section "AExpr" $ do putI 15; toBin t; toBin iot writeBytes (ASReal i t val) = section "AExpr" $ do putI 16; toBin i; toBin t; toBin val + writeBytes (ATupleSel t e idx) = section "AExpr" $ do putI 17; toBin t; toBin e; toBin idx + writeBytes (ATuple t es) = section "AExpr" $ do putI 18; toBin t; toBin es readBytes = do i <- getI case i of @@ -1067,6 +1071,10 @@ instance Bin AExpr where 15 -> do t <- fromBin; iot <- fromBin; return (ASInout t iot) 16 -> do { i <- fromBin; t <- fromBin; val <- fromBin; return (ASReal i t val) } + 17 -> do { t <- fromBin; e <- fromBin; idx <- fromBin; + return (ATupleSel t e idx) } + 18 -> do { t <- fromBin; es <- fromBin; + return (ATuple t es) } n -> internalError $ "GenABin.Bin(IExpr).readBytes: " ++ show n -- toBin e = Out [AExp e] () -- fromBin = readShared diff --git a/src/comp/CSyntax.hs b/src/comp/CSyntax.hs index c8d40355e..9b3c7c04e 100644 --- a/src/comp/CSyntax.hs +++ b/src/comp/CSyntax.hs @@ -1272,9 +1272,11 @@ instance PPrint CExpr where f (Inout i (VName p) mc mr) = t "inout_field " <> ppVarId d i <+> t p <+> mfi "clocked_by" mc <+> mfi "reset_by" mr - f (Method i mc mr n ps mo me) = + f (Method i mc mr n ps os me) = ppVarId d i <> g n <+> t "=" <+> t (unwords (map h ps)) <+> - mfi "clocked_by" mc <+> mfi "reset_by" mr <+> mfp "output" mo <+> mfp "enable" me + mfi "clocked_by" mc <+> mfi "reset_by" mr <+> + (if null os then empty else t"output" <+> t (unwords (map h os))) <+> + mfp "enable" me g 1 = t"" g n = t("[" ++ itos n ++ "]") h (s,[]) = show s diff --git a/src/comp/CType.hs b/src/comp/CType.hs index 5978c408e..5f33c015e 100644 --- a/src/comp/CType.hs +++ b/src/comp/CType.hs @@ -449,14 +449,20 @@ getActionValueArg t = internalError ("getActionValueArg: " ++ ppReadable t) -- These are used during foreign function processing to determine if arguments -- and return values are polymorphic or of a known size. isTypePolyBit :: Type -> Bool +isTypePolyBit (TAp (TCon (TyCon i _ _)) (TAp (TCon (TyCon i' _ _)) arg)) + | (i == idActionValue) || (i == idActionValue_), (i' == idBit) = isTVar arg isTypePolyBit (TAp (TCon (TyCon i _ _)) arg) | (i == idBit) || (i == idActionValue) || (i == idActionValue_) = isTVar arg isTypePolyBit _ = False +-- Note that this is only used for foreign functions, so it does not currently handle tuples of Bits bitWidth :: Type -> Integer +bitWidth (TAp (TCon (TyCon i _ _)) (TAp (TCon (TyCon i' _ _)) arg)) + | ((i == idActionValue) || (i == idActionValue_)) && + (i' == idBit) && + (isTNum arg) = getTNum arg bitWidth (TAp (TCon (TyCon i _ _)) arg) - | ((i == idBit) || (i == idActionValue) || (i == idActionValue_)) && - (isTNum arg) = getTNum arg + | (i == idBit) && (isTNum arg) = getTNum arg bitWidth t = internalError $ "bitWidth: not a Bit type of known width -- " ++ (show t) diff --git a/src/comp/CVPrint.hs b/src/comp/CVPrint.hs index f2c8c95d6..e75f79ddc 100644 --- a/src/comp/CVPrint.hs +++ b/src/comp/CVPrint.hs @@ -842,7 +842,7 @@ ppVeriMethod d _ (Inout i (VName s) mclk mrst) = (case mrst of Nothing -> empty Just i -> t"reset_by (" <> pvpId d i <> t")") -ppVeriMethod d mr (Method i mc mreset n pts mo me) = +ppVeriMethod d mr (Method i mc mreset n pts os me) = let f _ _ Nothing = empty f before after (Just (VName vn, prs)) = (case prs of @@ -851,7 +851,10 @@ ppVeriMethod d mr (Method i mc mreset n pts mo me) = (t (before ++ vn ++ after)) in t"method " <> - (f "" " " mo) <> + (case os of + [] -> empty + [o] -> f "" " " (Just o) + _ -> t"(" <> sepList (map (f "" " " . Just) os) (t",") <> t")") <> (pvpId d i <> (if n == 1 then empty else (t"[" <> (pp d n) <> t"]")) <> (t"(" <> sepList (map (f "" "" . Just) pts) (t",") <> t")") <> diff --git a/src/comp/DisjointTest.hs b/src/comp/DisjointTest.hs index 88d177c79..1de2481ce 100644 --- a/src/comp/DisjointTest.hs +++ b/src/comp/DisjointTest.hs @@ -11,12 +11,13 @@ module DisjointTest( import qualified Data.Set as S import qualified Data.Map as M import Control.Monad(foldM {- , when -}) +import Data.List (genericIndex) import Util(ordPair,uniquePairs) -import Error(ErrorHandle) +import Error(ErrorHandle, internalError) import Pretty -import PPrint(PPrint(..)) +import PPrint(PPrint(..), ppReadable) import Flags import ASyntax @@ -24,7 +25,7 @@ import ASyntaxUtil(AExprs(..), aAnd) import Pragma import VModInfo(VModInfo) -import AExpr2Util(getMethodOutputPort) +import AExpr2Util(getMethodOutputPorts) --import Debug.Trace(trace) import qualified AExpr2STP as STP @@ -270,9 +271,26 @@ buildSupportMap adefs avis rs = --trace ("XXX support map:" ++ ppReadable res) $ findSupport e@(ASDef _ i) = [DDef def i] where def = M.findWithDefault (err i) i idToDef findSupport e@(APrim { ae_args = es}) = findAExprs findSupport es - findSupport e@(AMethCall {ae_args = es}) = findAExprs findSupport es ++ [DMethod (ae_objid e) vlogport] - where vlogport = getMethodOutputPort portMap (ae_objid e) (ameth_id e) - findSupport e@(AMethValue {}) = [DMethod (ae_objid e) (ameth_id e)] + findSupport e@(AMethCall {ae_args = es}) = + case getMethodOutputPorts portMap (ae_objid e) (ameth_id e) of + [vlogport] -> findAExprs findSupport es ++ [DMethod (ae_objid e) vlogport] + ports -> internalError ("buildSupportMap: unexpected output ports: " + ++ ppReadable (ae_objid e, ameth_id e, ports)) + findSupport e@(AMethValue {}) = + case getMethodOutputPorts portMap (ae_objid e) (ameth_id e) of + [vlogport] -> [DMethod (ae_objid e) vlogport] + ports -> internalError ("buildSupportMap: unexpected output ports: " + ++ ppReadable (ae_objid e, ameth_id e, ports)) + findSupport e@(ATupleSel _ (AMethCall {ae_args = es}) idx) = + findAExprs findSupport es ++ [DMethod (ae_objid e) vlogport] + where + ports = getMethodOutputPorts portMap (ae_objid e) (ameth_id e) + vlogport = genericIndex ports (idx - 1) + findSupport e@(ATupleSel _ (AMethValue {}) idx) = + [DMethod (ae_objid e) vlogport] + where + ports = getMethodOutputPorts portMap (ae_objid e) (ameth_id e) + vlogport = genericIndex ports (idx - 1) findSupport e@(ANoInlineFunCall{ ae_args = es}) = findAExprs findSupport es findSupport e@(ATaskValue {ae_objid=id}) = [DTask id] findSupport e@(ASPort {ae_objid = id}) = [DLeaf id] diff --git a/src/comp/GenWrap.hs b/src/comp/GenWrap.hs index 03fa7dc11..c297e5da8 100644 --- a/src/comp/GenWrap.hs +++ b/src/comp/GenWrap.hs @@ -684,11 +684,11 @@ fixCModuleVerilog n (ss,ts,ps) in [mStmtSPTO vp e] saveArgTypes _ = [] let saveFieldTypes finf (Method { vf_inputs = inps, - vf_output = mo }) = do + vf_outputs = outs }) = do let rt = ret_type finf isAV <- isActionValue rt output_type <- if isAV then getAVType "fixCModVer" rt else return rt - let output_stmt = maybeToList (fmap ((flip mStmtSPT) rt) mo) + let output_stmt = map ((flip mStmtSPT) rt) outs -- we let the type-checker error on mismatches return (output_stmt ++ (zipWith mStmtSPT inps (arg_types finf))) saveFieldTypes finf (Inout { vf_inout = vn }) = do @@ -796,7 +796,7 @@ procType (n, ns, as, ts, ctx) ty = do if isAV then do av_t <- getAVType "procType" ty return (n+1, newId:ns, newSVar:as, - (ty, (TAp tActionValue_ (cTVarNum newId))):ts, + (ty, (TAp tActionValue_ (TAp tBit (cTVarNum newId)))):ts, (bitsCtx av_t newSVar):ctx) else do isInout <- isInoutType ty @@ -1112,10 +1112,13 @@ genTo pps ty mk = localPrefix = joinStrings_ currentPre localPrefix1 prefix = stringLiteralAt noPosition localPrefix arg_names = mkList (getPosition f) [stringLiteralAt (getPosition i) (getIdString i) | i <- aIds] - fnp = mkTypeProxyExpr $ TAp (cTCon idStrArg) $ cTStr (fieldPathName prefixes f)(getIdPosition f) + localResult1 = fromMaybe (getIdBaseString f) (lookupResultIfcPragma ciPrags) + localResult = joinStrings_ currentPre localResult1 + result = stringLiteralAt noPosition localResult + fnp = mkTypeProxyExpr $ TAp (cTCon idStrArg) $ cTStr (fieldPathName prefixes f) (getIdPosition f) -- XXX idEmpty is a horrible way to know no more selection is required let ec = if f == idEmpty then sel else CSelect sel (setInternal f) - let e = CApply (CVar idToWrapField) [fnp, prefix, arg_names, ec] + let e = CApply (CVar idToWrapField) [fnp, prefix, arg_names, result, ec] return [CLValue (binId prefixes f) [CClause [] [] e] []] -- -------------------- @@ -1637,10 +1640,10 @@ fixupVeriField _ _ f@(Reset { }) = f fixupVeriField _ _ f@(Inout { }) = f fixupVeriField pps vportprops m@(Method { }) = m { vf_inputs = inputs', - vf_output = output', + vf_outputs = outputs', vf_enable = enable'' } where inputs' = map fixup (vf_inputs m) - output' = fmap fixup (vf_output m) + outputs' = map fixup (vf_outputs m) enable' = fmap fixup (vf_enable m) fixup = fixupPort vportprops alwaysEnabled = isAlwaysEn pps (vf_name m) @@ -2044,10 +2047,8 @@ genNewMethodIfcPragmas ifcp pragmas fieldId newFieldId = ar = if (isAlwaysReadyIfc joinedPrags) then [PIAlwaysRdy ] else [] ae = if (isAlwaysEnabledIfc joinedPrags) then [PIAlwaysEnabled ] else [] -- The result names used the prefix plus the given of generated name - mResName = lookupResultIfcPragma pragmas - resultName = case mResName of - Just str -> joinStrings_ currentPre str - Nothing -> joinStrings_ currentPre methodStr + localResult1 = fromMaybe (getIdString fieldId) (lookupResultIfcPragma pragmas) + resultName = joinStrings_ currentPre localResult1 -- resName = (PIResultName resultName) -- The ready name @@ -2203,14 +2204,11 @@ mkFieldSavePortTypeStmts v ifcId = concatMapM $ meth noPrefixes ifcId _ -> do -- Compute the local prefix and result name for this field in the flattened interface -- from the current prefixes and pragmas from the field definition. - let methodStr = getIdBaseString f - currentPre = ifcp_renamePrefixes prefixes -- the current rename prefix + let currentPre = ifcp_renamePrefixes prefixes -- the current rename prefix localPrefix1 = fromMaybe (getIdBaseString f) (lookupPrefixIfcPragma ciPrags) localPrefix = joinStrings_ currentPre localPrefix1 - mResName = lookupResultIfcPragma ciPrags - resultName = case mResName of - Just str -> joinStrings_ currentPre str - Nothing -> joinStrings_ currentPre methodStr + localResult1 = fromMaybe (getIdBaseString f) (lookupResultIfcPragma ciPrags) + localResult = joinStrings_ currentPre localResult1 -- Arguments to saveFieldPortTypes: proxies for the field name as a type level string and the field type, -- and the values for the prefix, arg_names, and result pragmas. @@ -2218,7 +2216,7 @@ mkFieldSavePortTypeStmts v ifcId = concatMapM $ meth noPrefixes ifcId proxy = mkTypeProxyExpr $ foldr arrow r as prefix = stringLiteralAt noPosition localPrefix arg_names = mkList (getPosition f) [stringLiteralAt (getPosition i) (getIdString i) | i <- aIds] - result = stringLiteralAt noPosition resultName + result = stringLiteralAt noPosition localResult return [ CSExpr Nothing $ cVApply idLiftModule $ diff --git a/src/comp/IExpand.hs b/src/comp/IExpand.hs index 25c9875a1..5406dc632 100644 --- a/src/comp/IExpand.hs +++ b/src/comp/IExpand.hs @@ -295,7 +295,10 @@ iExpand errh flags symt alldefs is_noinlined_func pps def@(IDef mi _ _ _) = do t = iGetType e -- the name for the new IDef being created i = case expr_name of - Just name -> + -- Heuristic: treat names starting with _ as bad names, + -- as these may come from the arguments of functions like + -- id _x = _x + Just name | not (isEmptyId name) && head (getIdBaseString name) /= '_' -> setKeepId $ mkIdPost name (mkFString (iExpandPref ++ show p)) _ -> @@ -311,8 +314,9 @@ iExpand errh flags symt alldefs is_noinlined_func pps def@(IDef mi _ _ _) = do in -- return the expression that should replace the heap pointer, -- and maybe a Def, if the expression is a def reference - if simple e || isActionType t then + if simple e || isActionType t || isPairType t then -- inline the expression, no def is created for this heap ptr + --trace ("not inlining " ++ show i ++ " " ++ ppReadable t) $ (e', Nothing) else -- assign the expr to a def, and replace the ptr reference @@ -1035,11 +1039,11 @@ iExpandField modId implicitCond clkRst (i, bi, e, t) = do showTopProgress ("Elaborating method " ++ quote (pfpString i)) setIfcSchedNameScopeProgress (Just (IEP_Method i False)) (_, P p e') <- evalUH e - let (ins, eb) = case e' of - ICon _ (ICMethod _ ins eb) -> (ins, eb) + let (ins, outs, eb) = case e' of + ICon _ (ICMethod _ ins outs eb) -> (ins, outs, eb) _ -> internalError ("iExpandField: expected ICMethod: " ++ ppReadable e') (its, ((IDef i1 t1 e1 _), ws1, fi1), ((IDef wi wt we _), ws2, fi2)) - <- iExpandMethod modId 1 [] (pConj implicitCond p) clkRst (i, bi, ins, eb) + <- iExpandMethod modId 1 [] (pConj implicitCond p) clkRst (i, bi, ins, outs, eb) let wp1 = wsToProps ws1 -- default clock domain forced in by iExpandField let wp2 = wsToProps ws2 setIfcSchedNameScopeProgress Nothing @@ -1048,10 +1052,10 @@ iExpandField modId implicitCond clkRst (i, bi, e, t) = do -- expand a method iExpandMethod :: Id -> Integer -> [Id] -> HPred -> - (HClock, HReset) -> (Id, BetterInfo.BetterInfo, [String], HExpr) -> + (HClock, HReset) -> (Id, BetterInfo.BetterInfo, [String], [String], HExpr) -> G ([(Id, IType)], (HDef, HWireSet, VFieldInfo), (HDef, HWireSet, VFieldInfo)) -iExpandMethod modId n args implicitCond clkRst@(curClk, _) (i, bi, ins, e) = do +iExpandMethod modId n args implicitCond clkRst@(curClk, _) (i, bi, ins, outs, e) = do when doDebug $ traceM ("iExpandMethod " ++ ppString i ++ " " ++ ppReadable e) (_, P p e') <- evalUH e case e' of @@ -1061,23 +1065,24 @@ iExpandMethod modId n args implicitCond clkRst@(curClk, _) (i, bi, ins, e) = do -- a GenWrap-added context that wasn't satisfied, and GenWrap -- should only be adding Bits) errG (reportNonSynthTypeInMethod modId i e') - ILam li ty eb -> iExpandMethodLam modId n args implicitCond clkRst (i, bi, ins, eb) li ty p - _ -> iExpandMethod' implicitCond curClk (i, bi, e') p + ILam li ty eb -> iExpandMethodLam modId n args implicitCond clkRst (i, bi, ins, outs, eb) li ty p + _ -> iExpandMethod' implicitCond curClk (i, bi, outs, e') p iExpandMethodLam :: Id -> Integer -> [Id] -> HPred -> - (HClock, HReset) -> (Id, BetterInfo.BetterInfo, [String], HExpr) -> + (HClock, HReset) -> (Id, BetterInfo.BetterInfo, [String], [String], HExpr) -> Id -> IType -> Pred HeapData -> G ([(Id, IType)], (HDef, HWireSet, VFieldInfo), (HDef, HWireSet, VFieldInfo)) -iExpandMethodLam modId n args implicitCond clkRst (i, bi, ins, eb) li ty p = do - -- traceM ("iExpandMethodLam " ++ ppString i ++ " " ++ show ins) +iExpandMethodLam modId n args implicitCond clkRst (i, bi, ins, outs, eb) li ty p = do + --traceM ("iExpandMethodLam " ++ ppString i ++ " " ++ show (ins, outs)) + if null ins then internalError "iExpandMethodLam: no inputs" else return () let i' :: Id i' = mkId (getPosition i) $ mkFString $ head ins -- substitute argument with a modvar and replace with body eb' :: HExpr eb' = eSubst li (ICon i' (ICMethArg ty)) eb (its, (d, ws1, wf1), (wd, ws2, wf2)) <- - iExpandMethod modId (n+1) (i':args) (pConj implicitCond p) clkRst (i, bi, tail ins, eb') + iExpandMethod modId (n+1) (i':args) (pConj implicitCond p) clkRst (i, bi, tail ins, outs, eb') let inps :: [VPort] inps = vf_inputs wf1 let wf1' :: VFieldInfo @@ -1086,11 +1091,11 @@ iExpandMethodLam modId n args implicitCond clkRst (i, bi, ins, eb) li ty p = do _ -> internalError "iExpandMethodLam: unexpected wf1" return ((i', ty) : its, (d, ws1, wf1'), (wd, ws2, wf2)) -iExpandMethod' :: HPred -> HClock -> (Id, BetterInfo.BetterInfo, HExpr) -> +iExpandMethod' :: HPred -> HClock -> (Id, BetterInfo.BetterInfo, [String], HExpr) -> Pred HeapData -> G ([(Id, IType)], (HDef, HWireSet, VFieldInfo), (HDef, HWireSet, VFieldInfo)) -iExpandMethod' implicitCond curClk (i, bi, e0) p0 = do +iExpandMethod' implicitCond curClk (i, bi, outs, e0) p0 = do -- want the result type, not a type including arguments let methType :: IType methType = iGetType e0 @@ -1133,7 +1138,7 @@ iExpandMethod' implicitCond curClk (i, bi, e0) p0 = do IAps f@(ICon _ (ICTuple {})) ts [e1, e2] | isActionType methType -> let pos = getIdPosition i - vt = actionValue_BitN methType + vt = getAV_Type methType v = icUndetAt pos vt UNotUsed in (IAps f ts [v, icNoActions], ws) _ -> internalError "iExpandMethod: fixupActionWireSet" @@ -1149,8 +1154,8 @@ iExpandMethod' implicitCond curClk (i, bi, e0) p0 = do rdyId = mkRdyId i let enablePort :: Maybe VPort enablePort = toMaybe (isActionType methType) (BetterInfo.mi_enable bi) - let outputPort :: Maybe VPort - outputPort = toMaybe (isValueType methType) (BetterInfo.mi_result bi) + let outputPorts :: [VPort] + outputPorts = map (id_to_vPort . mkId (getPosition i) . mkFString) outs let rdyPort :: VPort rdyPort = BetterInfo.mi_ready bi @@ -1160,12 +1165,12 @@ iExpandMethod' implicitCond curClk (i, bi, e0) p0 = do Method { vf_name = i, vf_clock = methClock, vf_reset = methReset, vf_mult = 1, vf_inputs = [], - vf_output = outputPort, vf_enable = enablePort }), + vf_outputs = outputPorts, vf_enable = enablePort }), ((IDef rdyId itBit1 readySignal []), final_ws, Method { vf_name = rdyId, vf_clock = methClock, vf_reset = methReset, vf_mult = 1, vf_inputs = [], - vf_output = Just rdyPort, vf_enable = Nothing })) + vf_outputs = [rdyPort], vf_enable = Nothing })) -- deduce clock name for VFieldInfo -- type required to control ancestry-checking with action methods @@ -2519,20 +2524,16 @@ walkNF e = -- XXX is adding the clock to the wire set redundant? clk@(ICon i (ICClock { iClock = c })) : _ -> upd (pConj p0 p) (IAps f ts es') (wsAddClock c ws) - -- if the outer selector is avValue_ or avAction_ - -- and the inner is a method call - [(IAps sel@(ICon i_sel2 (ICSel { })) ts_2 es_2)] - | (i_sel == idAVValue_ || i_sel == idAVAction_) -> do - case es_2 of - st@(ICon i (ICStateVar { iVar = v })) : _ -> - handleMethod i_sel2 v - _ -> internalError ("walkNF: selector should be a method call") - - -- the inner selector can wind up on the heap - -- because of "move" in evalHeap - [e_ref@(IRefT t ptr ref)] | (isitActionValue_ t) || (isitAction t) - -> do (P p' e', ws) <- walkNF e_ref - upd (pConj p0 p') (IAps f ts [e']) ws + -- We can be selecting the avValue or avAction from an ActionValue method, + -- or a tuple member out of the result of calling a method with multiple outputs, + -- and need to recurse. + [e] | (i_sel == idAVValue_ || + i_sel == idAVAction_ || + i_sel == idPrimFst || + i_sel == idPrimSnd) -> do + do (P p' e', ws) <- walkNF e + upd (pConj p0 p') (IAps f ts [e']) ws + _ -> do when doDebug $ traceM "not stvar or foreign\n" when doDebug $ traceM (show u ++ "\n") when doDebug $ traceM (show es' ++ "\n") @@ -2547,6 +2548,11 @@ walkNF e = (P p' e', ws) <- walkNF e upd (pConjs [p0, p, p']) e' ws + IAps f@(ICon _ (ICTuple {})) ts [e1, e2] -> do + (P pe1 e1', ws1) <- walkNF e1 + (P pe2 e2', ws2) <- walkNF e2 + upd (pConj pe1 pe2) (IAps f ts [e1', e2']) (wsJoin ws1 ws2) + -- Any other application is not in NF (which is unexpected?) IAps f ts es -> do _ <- internalError ("walkNF fall-through: " ++ ppReadable (f,ts,es)) @@ -3126,10 +3132,16 @@ conAp' i (ICPrim _ PrimIsRawUndefined) _ (T t : E e : as) = do _ -> -- do traceM ("IsRawUndefined: False") return (P p iFalse) -conAp' i (ICPrim _ PrimMethod) _ [T t, E eInNames, E meth] = do +conAp' i (ICPrim _ PrimMethod) _ [T t, E eInNames, E eOutNames, E meth] = do (inNames, _) <- evalStringList eInNames + (outNames, _) <- evalStringList eOutNames P p meth' <- eval1 meth - return $ P p $ ICon (dummyId noPosition) $ ICMethod {iConType = t, iInputNames = inNames, iMethod = meth'} + return $ P p $ ICon (dummyId noPosition) $ ICMethod { + iConType = t, + iInputNames = inNames, + iOutputNames = outNames, + iMethod = meth' + } -- XXX is this still needed? conAp' i (ICUndet { iConType = t }) e as | t == itClock = @@ -3849,7 +3861,7 @@ conAp' _ (ICPrim _ op) fe@(ICon prim_id _) as | strictPrim op = do when doTrans $ traceM ("conAp: iTransform fallthrough: " ++ ppReadable (op, mkAp fe as')) errh <- getErrHandle case (iTransExpr errh (mkAp fe as')) of - (e', True) -> do + (e', True) | isBitType (iGetType e') -> do -- we used to evaluate further here, but that shouldn't -- be necessary (and probably indicates a bug elsewhere) when (doDebug || doTrans) $ traceM ("conAp: iTransform result: " ++ ppReadable e') @@ -4829,6 +4841,11 @@ doSel sel s tys ty n as ee (p, e) = -- canonical applications are strict (e.g. method call applications) _ | isCanon e -> bldApUH' "Sel" sel (map T tys ++ (E ee : as)) + -- tuple section from a multi-output method result + _ | s == idPrimFst || s == idPrimSnd -> do + (_, P p e') <- evalUH e + addPredG p $ bldApUH' "Sel PrimFst/Snd" sel (map T tys ++ (E e' : as)) + -- otherwise fail _ -> internalError ("doSel: " ++ ppReadable (sel, e, as)) @@ -4842,7 +4859,7 @@ isCanon (ICon _ (ICModParam { })) = True isCanon (ICon _ (ICClock { })) = True --isCanon (IAps (ICon _ (ICPrim _ PrimBlock)) _ _) = True -- XXX is this the best way? isCanon (IAps (ICon _ (ICSel { })) _ [_]) = True -isCanon (IAps (ICon _ (ICOut { })) _ [_]) = True +--isCanon (IAps (ICon _ (ICOut { })) _ [_]) = True -- AV of foreign function application is canon --isCanon (IAps (ICon _ (ICForeign { })) _ _) = True isCanon (IRefT _ _ _) = True diff --git a/src/comp/IExpandUtils.hs b/src/comp/IExpandUtils.hs index f6e3f7ec1..c781effd3 100644 --- a/src/comp/IExpandUtils.hs +++ b/src/comp/IExpandUtils.hs @@ -357,18 +357,23 @@ isPrimType (ITCon i _ _) = i == idPrimAction || -- i == idInteger i == idFmt || -- also not really a primitive i == idClock || - i == idReset + i == idReset || + i == idPrimUnit +-- ActionValue_ must be applied to (a tuple of) Bit +isPrimType (ITAp (ITCon i _ _) t) + | i == idActionValue_ = t == itPrimUnit || isBitTupleType t -- Primitive constructor applied to numeric type(s) isPrimType (ITAp a t) | iGetKind t == Just IKNum = isPrimTAp a -- Primitive arrays isPrimType (ITAp (ITCon i _ _) elem_ty) | i == idPrimArray = isPrimType elem_ty +-- Tuples of bits +isPrimType t | isBitTupleType t = True isPrimType _ = False -- Primitive type applications isPrimTAp :: IType -> Bool isPrimTAp (ITCon _ _ (TIstruct SInterface{} _)) = True -isPrimTAp (ITCon i _ _) = i == idActionValue_ || - i == idBit || +isPrimTAp (ITCon i _ _) = i == idBit || i == idInout_ isPrimTAp (ITAp a t) | iGetKind t == Just IKNum = isPrimTAp a isPrimTAp _ = False @@ -2058,8 +2063,8 @@ chkIfcPortNames errh args ifcs (ClockInfo ci co _ _) (ResetInfo ri ro) = ifc_port_names = [ (n, i) - | IEFace {ief_fieldinfo = Method i _ _ _ ins out en} <- ifcs, - (VName n, _) <- ins ++ maybeToList out ++ maybeToList en ] + | IEFace {ief_fieldinfo = Method i _ _ _ ins outs en} <- ifcs, + (VName n, _) <- ins ++ outs ++ maybeToList en ] ifc_inout_names = [ (n, i) | IEFace {ief_fieldinfo = Inout i (VName n) _ _} <- ifcs ] ifc_clock_names = diff --git a/src/comp/IInlineFmt.hs b/src/comp/IInlineFmt.hs index 54c117277..347e07a50 100644 --- a/src/comp/IInlineFmt.hs +++ b/src/comp/IInlineFmt.hs @@ -354,12 +354,13 @@ createValueExprs x = [createValueExpr x] -- ############################################################################# createValueExpr :: IExpr a -> IExpr a -createValueExpr (IAps (ICon c (ICSel {})) [ITNum s] [e@(IAps (ICon _ (ICForeign {})) _ _)]) | c == idAVAction_ +createValueExpr (IAps (ICon c (ICSel {})) [ITAp b (ITNum s)] [e@(IAps (ICon _ (ICForeign {})) _ _)]) + | c == idAVAction_, b == itBit = x - where x = (IAps (ICon idAVValue_ (ICSel {iConType = tt , selNo = 0, numSel = 2 })) [ITNum s] [e]) + where x = (IAps (ICon idAVValue_ (ICSel {iConType = tt , selNo = 0, numSel = 2 })) [ITAp itBit $ ITNum s] [e]) v0 = head tmpVarIds - tt = ITForAll v0 IKNum (ITAp (ITAp (ITCon (idArrow noPosition) (IKFun IKStar (IKFun IKStar IKStar)) TIabstract) (ITAp (ITCon idActionValue_ (IKFun IKNum IKStar) (TIstruct SStruct [idAVValue_,idAVAction_])) (ITVar v0))) - (ITAp itBit (ITVar v0)) ) + tt = ITForAll v0 IKStar (ITAp (ITAp (ITCon (idArrow noPosition) (IKFun IKStar (IKFun IKStar IKStar)) TIabstract) (ITAp (ITCon idActionValue_ (IKFun IKStar IKStar) (TIstruct SStruct [idAVValue_,idAVAction_])) (ITVar v0))) + (ITVar v0) ) createValueExpr (IAps cc@(ICon i (ICPrim _ PrimIf)) ts [cond, e0, e1]) = x where x = (IAps cc [rt] [cond, e0', e1']) @@ -370,11 +371,12 @@ createValueExpr x = internalError ("createValueExpr: " ++ ppReadable x) createActionExpr :: IExpr a -> IExpr a -createActionExpr (IAps (ICon c (ICSel {})) [ITNum s] [e@(IAps (ICon _ (ICForeign {})) _ _)]) | c == idAVValue_ +createActionExpr (IAps (ICon c (ICSel {})) [ITAp b (ITNum s)] [e@(IAps (ICon _ (ICForeign {})) _ _)]) + | c == idAVValue_, b == itBit = x - where x = (IAps (ICon idAVAction_ (ICSel {iConType = tt , selNo = 1, numSel = 2 })) [ITNum s] [e]) + where x = (IAps (ICon idAVAction_ (ICSel {iConType = tt , selNo = 1, numSel = 2 })) [ITAp itBit $ ITNum s] [e]) v0 = head tmpVarIds - tt = ITForAll v0 IKNum (ITAp (ITAp (ITCon (idArrow noPosition) (IKFun IKStar (IKFun IKStar IKStar)) TIabstract) (ITAp (ITCon idActionValue_ (IKFun IKNum IKStar) (TIstruct SStruct [idAVValue_,idAVAction_])) (ITVar v0))) + tt = ITForAll v0 IKStar (ITAp (ITAp (ITCon (idArrow noPosition) (IKFun IKStar (IKFun IKStar IKStar)) TIabstract) (ITAp (ITCon idActionValue_ (IKFun IKStar IKStar) (TIstruct SStruct [idAVValue_,idAVAction_])) (ITVar v0))) itAction ) createActionExpr (IAps cc@(ICon i (ICPrim _ PrimIf)) ts [cond, e0, e1]) = x @@ -386,14 +388,16 @@ createActionExpr x = joinActions [] allStrings :: IExpr a -> Bool -allStrings (IAps (ICon c (ICSel {})) [ITNum s] [(IAps (ICon _ (ICForeign {})) _ [e])]) | c == idAVAction_ && iGetType e == itString +allStrings (IAps (ICon c (ICSel {})) [ITAp b (ITNum s)] [(IAps (ICon _ (ICForeign {})) _ [e])]) + | c == idAVAction_ && b == itBit && iGetType e == itString = True allStrings (IAps (ICon i (ICPrim _ PrimIf)) _ [_, e0, e1]) = allStrings e0 && allStrings e1 allStrings _ = False createStringExpr :: IExpr a -> IExpr a -createStringExpr (IAps (ICon c (ICSel {})) [ITNum s] [(IAps (ICon _ (ICForeign {})) _ [e])]) | c == idAVAction_ +createStringExpr (IAps (ICon c (ICSel {})) [ITAp b (ITNum s)] [(IAps (ICon _ (ICForeign {})) _ [e])]) + | c == idAVAction_, b == itBit = e createStringExpr (IAps cc@(ICon i (ICPrim _ PrimIf)) ts [cond, e0, e1]) = x diff --git a/src/comp/ISplitIf.hs b/src/comp/ISplitIf.hs index 93fd3c942..07ef8351e 100644 --- a/src/comp/ISplitIf.hs +++ b/src/comp/ISplitIf.hs @@ -445,7 +445,7 @@ iSplitIface flags ieface@(IEFace i xargs (Just (e,t)) Nothing wp fi) in (smap, IEFace i xargs Nothing (Just irules_opt) wp fi) else case e of (IAps (ICon av (ICTuple {fieldIds = [_val_id,_act_id]})) - [ITNum _] [val_,act_]) + [_] [val_,act_]) | (av == idActionValue_) -> let irule = IRule i [] (getIdString i) wp iTrue act_ Nothing [] irules = IRules [] [irule] -- no sps @@ -457,9 +457,9 @@ iSplitIface flags ieface@(IEFace i xargs (Just (e,t)) Nothing wp fi) iSplitIface _ _ = internalError ("iSplitIface: no expression or unexpected rule") mkExpression :: IExpr a -> IType -> Maybe (IExpr a, IType) -mkExpression val_ ty = if (0==(getAV_Size ty)) +mkExpression val_ ty = if (isEmptyType (getAV_Type ty)) then Nothing - else (Just (val_,(actionValue_BitN ty))) + else (Just (val_,(getAV_Type ty))) check_meth_rules :: (PrimOp -> Bool) -> IEFace a -> Maybe (IExpr a) diff --git a/src/comp/ISyntax.hs b/src/comp/ISyntax.hs index 4bb08b7f5..d8635c2a0 100644 --- a/src/comp/ISyntax.hs +++ b/src/comp/ISyntax.hs @@ -822,7 +822,7 @@ data IConInfo a = -- only exists before expansion | ICSchedPragmas { iConType :: IType, iPragmas :: [CSchedulePragma] } - | ICMethod { iConType :: IType, iInputNames :: [String], iMethod :: IExpr a } + | ICMethod { iConType :: IType, iInputNames :: [String], iOutputNames :: [String], iMethod :: IExpr a } | ICClock { iConType :: IType, iClock :: IClock a } | ICReset { iConType :: IType, iReset :: IReset a } -- iReset has effective type itBit1 | ICInout { iConType :: IType, iInout :: IInout a } @@ -917,8 +917,8 @@ cmpC c1 c2 = ICIFace { ifcTyId = ti1, ifcIds = is1 } -> compare (ti1, is1) (ifcTyId c2, ifcIds c2) ICRuleAssert { iAsserts = asserts } -> compare asserts (iAsserts c2) ICSchedPragmas { iPragmas = pragmas } -> compare pragmas (iPragmas c2) - ICMethod { iInputNames = inames1, iMethod = meth1 } -> - compare (inames1, meth1) (iInputNames c2, iMethod c2) + ICMethod { iInputNames = inames1, iOutputNames = outnames1, iMethod = meth1 } -> + compare (inames1, outnames1, meth1) (iInputNames c2, iOutputNames c2, iMethod c2) -- the ICon Id is not sufficient for equality comparison for Clk/Rst ICClock { iClock = clock1 } -> compare clock1 (iClock c2) ICReset { iReset = reset1 } -> compare reset1 (iReset c2) @@ -1243,7 +1243,7 @@ instance NFData (IConInfo a) where rnf (ICIFace x1 x2 x3) = rnf3 x1 x2 x3 rnf (ICRuleAssert x1 x2) = rnf2 x1 x2 rnf (ICSchedPragmas x1 x2) = rnf2 x1 x2 - rnf (ICMethod x1 x2 x3) = rnf3 x1 x2 x3 + rnf (ICMethod x1 x2 x3 x4) = rnf4 x1 x2 x3 x4 rnf (ICClock x1 x2) = rnf2 x1 x2 rnf (ICReset x1 x2) = rnf2 x1 x2 rnf (ICInout x1 x2) = rnf2 x1 x2 @@ -1465,7 +1465,7 @@ showTypelessCI (ICValue {iConType = t, iValDef = e}) = "(ICValue)" showTypelessCI (ICIFace {iConType = t, ifcTyId = i, ifcIds = ids}) = "(ICIFace _ " ++ (show i) ++ " " ++ (show ids) ++ ")" showTypelessCI (ICRuleAssert {iConType = t, iAsserts = rps}) = "(ICRuleAssert _ " ++ (show rps) ++ ")" showTypelessCI (ICSchedPragmas {iConType = t, iPragmas = sps}) = "(ICSchedPragmas _ " ++ (show sps) ++ ")" -showTypelessCI (ICMethod {iConType = t, iInputNames = ins, iMethod = m }) = "(ICMethod " ++ (show ins) ++ " " ++ (ppReadable m) ++ ")" +showTypelessCI (ICMethod {iConType = t, iInputNames = ins, iOutputNames = outs, iMethod = m }) = "(ICMethod " ++ (show ins) ++ " " ++ (show outs) ++ " " ++ (ppReadable m) ++ ")" showTypelessCI (ICClock {iConType = t, iClock = clock}) = "(ICClock)" showTypelessCI (ICReset {iConType = t, iReset = reset}) = "(ICReset)" showTypelessCI (ICInout {iConType = t, iInout = inout}) = "(ICInout)" diff --git a/src/comp/ISyntaxUtil.hs b/src/comp/ISyntaxUtil.hs index abeb7ee8f..f5842f7cb 100644 --- a/src/comp/ISyntaxUtil.hs +++ b/src/comp/ISyntaxUtil.hs @@ -120,18 +120,16 @@ isSimpleType t = t == itInteger || t == itChar isitAction :: IType -> Bool -isitAction (ITAp (ITCon i (IKFun IKNum IKStar) - (TIstruct SStruct [_,_] ) ) (ITNum x)) - | (i == idActionValue_) = (x == 0) -isitAction (ITAp (ITCon i (IKFun IKStar IKStar) _) t) - | (i == idActionValue) = t == itPrimUnit +isitAction (ITAp (ITCon i (IKFun IKStar IKStar) _ ) t) + | (i == idActionValue_) || (i == idActionValue) = isEmptyType t isitAction x = (x == itAction) --- note this returns false for x == - because ActionValue_ 0 is really an Action +-- note this returns false for x == () because ActionValue_ () is really an Action +-- Also handle ActionValue_ (Bit 0), which can be introduced by foreign functions. isitActionValue_ :: IType -> Bool -isitActionValue_ (ITAp (ITCon i (IKFun IKNum IKStar) - (TIstruct SStruct [_,_] ) ) (ITNum x)) - | x > 0 = (i == idActionValue_) +isitActionValue_ (ITAp (ITCon i (IKFun IKStar IKStar) + (TIstruct SStruct [_,_] ) ) t) = + (i == idActionValue_) && not (isEmptyType t) isitActionValue_ _ = False isitActionValue :: IType -> Bool @@ -149,11 +147,11 @@ getInout_Size t = internalError ("getInout_Size: type is not Inout_: " ++ ppReadable t) -getAV_Size :: IType -> Integer -getAV_Size (ITAp (ITCon i (IKFun IKNum IKStar) - (TIstruct SStruct [_,_] ) ) (ITNum x)) | - (i == idActionValue_) = x -getAV_Size t = internalError ("getAV_Size: type is not AV_: " ++ ppReadable t) +getAV_Type :: IType -> IType +getAV_Type (ITAp (ITCon i (IKFun IKStar IKStar) + (TIstruct SStruct [_,_] ) ) t) | + (i == idActionValue_) = t +getAV_Type t = internalError ("getAV_Type: type is not AV_: " ++ ppReadable t) getAVType :: IType -> Maybe IType getAVType (ITAp (ITCon i (IKFun IKStar IKStar) _) t) | i == idActionValue = Just t @@ -175,18 +173,34 @@ itList, itMaybe :: IType -> IType itList t = ITAp (ITCon idList (IKFun IKStar IKStar) tiList) t itMaybe t = ITAp (ITCon idMaybe (IKFun IKStar IKStar) tiMaybe) t +isPairType :: IType -> Bool +isPairType (ITAp (ITAp (ITCon i _ _) _) _) = i == idPrimPair +isPairType _ = False + +isEmptyType :: IType -> Bool +isEmptyType (ITCon i _ _) = i == idPrimUnit +isEmptyType (ITAp c (ITNum 0)) = c == itBit +isEmptyType t = False + isBitType :: IType -> Bool isBitType (ITAp c n) = c == itBit isBitType _ = False +isBitTupleType :: IType -> Bool +isBitTupleType (ITAp (ITAp (ITCon i _ _) t1) t2) | i == idPrimPair = + isBitType t1 && isBitTupleType t2 +isBitTupleType t = isBitType t + -- extension point for ActionValue methods isActionType :: IType -> Bool isActionType x = (x == itAction) || (isitActionValue_ x) || (isitAction x) -- extension point for ActionValue methods isValueType :: IType -> Bool -isValueType x | (isitActionValue_ x) && (getAV_Size x > 0) = True +isValueType x | (isitActionValue_ x) = True isValueType (ITAp t n) | t == itBit = True +isValueType (ITAp (ITAp (ITCon i _ _) t1) t2) | i == idPrimPair = + isBitType t1 && isValueType t2 isValueType _ = False -- Constructors @@ -1066,10 +1080,6 @@ joinActions [] = icNoActions joinActions as = foldr1 ja as where ja a1 a2 = IAps icJoinActions [] [a1, a2] --- perhaps the position information should be transferred over XXX -actionValue_BitN :: IType -> IType -actionValue_BitN t = itBitN (getAV_Size t) - iStrToInt :: String -> Position -> IExpr a iStrToInt s pos = iMkLitAt pos itInteger i where i = foldl sumString 0 s diff --git a/src/comp/ITransform.hs b/src/comp/ITransform.hs index 6267f2c83..98337bba0 100644 --- a/src/comp/ITransform.hs +++ b/src/comp/ITransform.hs @@ -249,8 +249,8 @@ runCSE e@(IAps _ _ _) = do -- because "runCSE" is called from iTrExpr, which already recurses on the -- arguments, so runCSE will already have been called on the arguments. let t = iGetType e - -- Only CSE applications that are not actions - if not (isActionType t) then + -- Only CSE applications that are not actions or tuple method values + if not (isActionType t || isPairType t) then newExprT t e else return e diff --git a/src/comp/IfcBetterInfo.hs b/src/comp/IfcBetterInfo.hs index 8baded88b..a519d8877 100644 --- a/src/comp/IfcBetterInfo.hs +++ b/src/comp/IfcBetterInfo.hs @@ -25,7 +25,6 @@ import VModInfo -- and for recording the types of external method ports data BetterInfo = BetterMethodInfo { mi_id :: Id, -- method Id - mi_result :: VPort, -- possible rename for method result mi_ready :: VPort, -- for ready signal mi_enable :: VPort, -- for enable signal mi_prefix :: Id -- default prefix for arguments (which are not found in classic) @@ -49,7 +48,6 @@ matchMethodName id mn = qualEq id (mi_id mn) -- creates a basic method remaing noMethodInfo :: Id -> BetterInfo noMethodInfo fieldId = BetterMethodInfo {mi_id = fieldId, - mi_result = id_to_vPort fieldId, mi_ready = id_to_vPort $ mkRdyId fieldId, mi_enable = id_to_vPort $ mkEnableId fieldId, mi_prefix = fieldId @@ -58,8 +56,7 @@ noMethodInfo fieldId = BetterMethodInfo {mi_id = fieldId, instance PPrint BetterInfo where pPrint d i info = (text "methodNames") <> ppId d (mi_id info) <> equals <> braces - ( printMaybe d i "Result:" (mi_result info) <> - printMaybe d i "Ready:" (mi_ready info) <> + ( printMaybe d i "Ready:" (mi_ready info) <> printMaybe d i "Enable:" (mi_enable info) <> text "Prefix:" <> pPrint d i (mi_prefix info) ) @@ -93,10 +90,9 @@ fieldInfoToBetterInfo :: Flags -> SymTab -> (Id,Maybe FieldInfo) -> BetterInfo fieldInfoToBetterInfo flags symTab (fieldId, Nothing) = noMethodInfo fieldId fieldInfoToBetterInfo flags symTab (fieldId, Just fi) = BetterMethodInfo {mi_id = fieldId, - mi_result = maybe (id_to_vPort fieldId) (str_to_vPort) mres, mi_ready = maybe (id_to_vPort $ mkRdyId fieldId) str_to_vPort mrdy, mi_enable = maybe (id_to_vPort $ mkEnableId fieldId) str_to_vPort men, mi_prefix = maybe fieldId (setIdBaseString fieldId) mprefix } where prags = fi_pragmas fi - (mprefix,mres,mrdy,men,_,_,_) = getMethodPragmaInfo prags + (mprefix,_,mrdy,men,_,_,_) = getMethodPragmaInfo prags diff --git a/src/comp/LambdaCalc.hs b/src/comp/LambdaCalc.hs index 8a62f0fa8..bc55c1db7 100644 --- a/src/comp/LambdaCalc.hs +++ b/src/comp/LambdaCalc.hs @@ -915,6 +915,7 @@ convAType (ATString (Just width)) = stringType -- XXX ? convAType (ATReal) = realType convAType (ATArray sz t) = arrType sz (convAType t) convAType t | (t == mkATBool) = boolType +convAType (ATTuple ts) = internalError ("convAType: multi-output methods are not yet supported") convAType t@(ATAbstract {}) = internalError ("convAType: " ++ ppReadable t) -- ----- @@ -1026,7 +1027,11 @@ convStmt modId avmap (AStmtAction cset (ACall obj meth as)) = do Nothing -> -- no name because the value is unused -- but we still need to declare the correct type case (M.lookup (unQualId meth) meth_ty_map) of - Just t -> (convAType t, Nothing) + Just [t] -> (convAType t, Nothing) + Just [] -> (voidType, Nothing) + -- TODO: support multiple return values + Just ts -> error ("convStmt: multiple return values for method " ++ + ppReadable (obj, meth, ts)) Nothing -> (voidType, Nothing) -- we'll create new defs "act#", "guard#", and "state#" with a unique number @@ -1187,6 +1192,11 @@ convAExpr e@(AMethValue t obj meth) = -- these are handled by convStmts and are not expected here internalError("convAExpr: AMethValue: " ++ ppReadable e) +convAExpr (ATupleSel _ _ _) = + internalError "convAExpr: multi-output methods are not yet supported" +convAExpr (ATuple {}) = + internalError "convAExpr: multi-output methods are not yet supported" + convAExpr (ANoInlineFunCall t i (ANoInlineFun name _ _ _) as) = do let func_id = noinlineId i a_exprs <- mapM convAExpr as diff --git a/src/comp/LambdaCalcUtil.hs b/src/comp/LambdaCalcUtil.hs index 1ed84f5a5..01876d349 100644 --- a/src/comp/LambdaCalcUtil.hs +++ b/src/comp/LambdaCalcUtil.hs @@ -159,11 +159,11 @@ lookupDef defmap i = -- Digested AVInst info for each submodule instance -- * The module name -- * The numeric type arguments for polymorphic modules --- * A map from AV method names to their return value +-- * A map from AV method names to their return values -- -type InstMap = M.Map Id (String, [Integer], M.Map Id AType) +type InstMap = M.Map Id (String, [Integer], M.Map Id [AType]) -lookupMod :: InstMap -> Id -> (String, [Integer], M.Map Id AType) +lookupMod :: InstMap -> Id -> (String, [Integer], M.Map Id [AType]) lookupMod instmap obj = case (M.lookup obj instmap) of Nothing -> internalError ("lookupMod: " ++ ppReadable obj) @@ -1037,6 +1037,9 @@ updateAExprTypes _ (AMethCall t obj meth as) = do -- method return values are Bit type updateAExprTypes _ e@(AMethValue t obj meth) = return e +updateAExprTypes _ (ATupleSel _ _ _) = error "updateAExprTypes: multi-output methods not yet supported" +updateAExprTypes _ (ATuple _ _) = error "updateAExprTypes: multi-output methods not yet supported" + -- noinline function arguments and return values are Bit type updateAExprTypes _ (ANoInlineFunCall t i f as) = do as' <- mapM updateAExprTypes_Bits as @@ -1224,13 +1227,13 @@ inlineUndet = mapAExprs g -- ------------------------- -getSubModAVMethReturnTypes :: AVInst -> M.Map Id AType +getSubModAVMethReturnTypes :: AVInst -> M.Map Id [AType] getSubModAVMethReturnTypes avi = let meth_types = avi_meth_types avi vfis = vFields (avi_vmi avi) - mkPair vfi (_, Just _, Just ret_ty) = Just (vf_name vfi, ret_ty) + mkPair vfi (_, Just _, ret_tys) = Just (vf_name vfi, ret_tys) mkPair _ _ = Nothing pairs = catMaybes $ zipWith mkPair vfis meth_types diff --git a/src/comp/Parser/BSV/CVParser.lhs b/src/comp/Parser/BSV/CVParser.lhs index 72a34959d..d22ecd528 100644 --- a/src/comp/Parser/BSV/CVParser.lhs +++ b/src/comp/Parser/BSV/CVParser.lhs @@ -1447,7 +1447,9 @@ returns a single identifier formed by joining the components with underscores. > -- Bool indicates whether there's a separate Ready method for this one > pMethodVeriProt prefix = > do pos <- getPos +> -- TODO: Add syntax for specifiying multiple output ports > (optOPort, name) <- pMethodNameOptOPort "method output port or name" +> let oPorts = maybeToList optOPort > multi <- option 1 (pInBrackets pDecimal) > args <- (option [] (pInParens (pCommaSep pMethodArgVeriPort)) > "method arguments") @@ -1492,7 +1494,7 @@ returns a single identifier formed by joining the components with underscores. > Just (VeriPt p) -> > [(mkRdyId name, > V.Method (mkRdyId fullname) -> clk rst 0 [] (Just p) Nothing, +> clk rst 0 [] [p] Nothing, > False)] > Just _ -> internalError "pMethodVeriProt(4)" > return ((name, @@ -1501,7 +1503,7 @@ returns a single identifier formed by joining the components with underscores. > rst > multi > args -> optOPort +> oPorts > en, > not(null nullOrReady)) > : nullOrReady) @@ -4584,7 +4586,7 @@ a "module verilog": > let g (s,Nothing) = [(s,[])] > g (s,Just g) = [(s,[]),(g,[])] > f (Nothing, _) = [] -> f (Just i , cmg) = [V.Method i Nothing Nothing 1 (concat(map g cmg)) Nothing Nothing] +> f (Just i , cmg) = [V.Method i Nothing Nothing 1 (concat(map g cmg)) [] Nothing] > in concat . (map f) > pImperativeForeignModuleAt :: Position -> Attributes -> ImperativeFlags diff --git a/src/comp/Parser/BSV/CVParserImperative.lhs b/src/comp/Parser/BSV/CVParserImperative.lhs index 4a8aafa9c..cccc59949 100644 --- a/src/comp/Parser/BSV/CVParserImperative.lhs +++ b/src/comp/Parser/BSV/CVParserImperative.lhs @@ -1473,9 +1473,9 @@ some of these restrictions could be lifted if we made the compiler more clever > Port (name, _) _ _ -> addInput pos name ioerrs > _ -> ioerrs > chkBVIPorts (ISBVI pos (BVI_method (_,inf@(Method {}),_))) ioerrs = ioerrs3 -> where ioerrs1 = case (vf_output inf) of -> Just (name, _) -> addOutputPort pos name ioerrs -> _ -> ioerrs +> where ioerrs1 = foldr (\(name, _) iers -> addOutputPort pos name iers) +> ioerrs +> (vf_outputs inf) > ioerrs2 = case (vf_enable inf) of > Just (name, _) -> addInput pos name ioerrs1 > _ -> ioerrs1 @@ -1704,13 +1704,13 @@ Extract each type of statement, making sure to preserve the order > CLValue si [CClause [] [] > (cVApply idPrimInoutUncast0 [(CSelect (CVar bviMname) i)])] [] > -- the following case will generate an error in chkBSVMethod below: -> mkBSVMethod (sn, Method n _ _ _ is Nothing Nothing, b) = -- ... mo me needsReady +> mkBSVMethod (sn, Method n _ _ _ is [] Nothing, b) = -- ... mo me needsReady > mkBasicDef (\ e -> e) n sn is b -> mkBSVMethod (sn, Method n _ _ _ is (Just _) Nothing, b) = -- ... mo me needsReady +> mkBSVMethod (sn, Method n _ _ _ is (_ : _) Nothing, b) = -- ... mo me needsReady > mkBasicDef (\ e -> cVApply idUnpack [e]) n sn is b -> mkBSVMethod (sn, Method n _ _ _ is Nothing (Just _), b) = -- ... mo me needsReady +> mkBSVMethod (sn, Method n _ _ _ is [] (Just _), b) = -- ... mo me needsReady > mkBasicDef (\ e -> cVApply idFromActionValue_ [e]) n sn is b -> mkBSVMethod (sn, Method n _ _ _ is (Just _) (Just _), b) = -- ... mo me needsReady +> mkBSVMethod (sn, Method n _ _ _ is (_ : _) (Just _), b) = -- ... mo me needsReady > mkBasicDef (\ e -> cVApply idFromActionValue_ [e]) n sn is b > mkBSVIfc (name,constr,ss) = @@ -1728,7 +1728,7 @@ Extract each type of statement, making sure to preserve the order > lastPos = getPosition (last stmts) > bviMname = idM lastPos -> chkBSVMethod (Method n _ _ _ _ Nothing Nothing) = -- mo me +> chkBSVMethod (Method n _ _ _ _ [] Nothing) = -- os me > cvtErr (getPosition n) (EForeignModOutputOrEnable (pvpReadable n)) > chkBSVMethod m = return () > theFamilies cs as fs = do diff --git a/src/comp/Parser/Classic/CParser.hs b/src/comp/Parser/Classic/CParser.hs index 6e37b20b6..e4e703275 100644 --- a/src/comp/Parser/Classic/CParser.hs +++ b/src/comp/Parser/Classic/CParser.hs @@ -148,7 +148,7 @@ pModule = l L_module `into` \ pos -> ||! literal (mkFString "const") .> VPconst ||! literal (mkFString "unused") .> VPunused ||! literal (mkFString "inhigh") .> VPinhigh - mkMethod i n vps mo me = Method i Nothing Nothing n vps Nothing Nothing + mkMethod i n vps mo me = Method i Nothing Nothing n vps [] Nothing pMStmt :: CParser CMStmt pMStmt = pModuleInterface diff --git a/src/comp/PreStrings.hs b/src/comp/PreStrings.hs index c4e2efbcf..e7a246220 100644 --- a/src/comp/PreStrings.hs +++ b/src/comp/PreStrings.hs @@ -206,6 +206,8 @@ fsMuxVal = mkFString "VAL" fsEnable = mkFString "EN_" fs_rdy = mkFString "RDY_" fs_rl = mkFString "RL_" +fs_arg = mkFString "ARG_" +fs_res = mkFString "RES_" fs_unnamed = mkFString "unnamed" s_unnamed = "unnamed" fs_T = mkFString "_T" diff --git a/src/comp/SAL.hs b/src/comp/SAL.hs index 52b7d8951..ad58492ac 100644 --- a/src/comp/SAL.hs +++ b/src/comp/SAL.hs @@ -503,6 +503,7 @@ boolToBitVar = SVar $ primCtx (SId "boolToBit") anyVar :: AType -> SExpr anyVar (ATBit width) = SVar $ bitCtx width (SId "undef") anyVar t | (t == mkATBool) = SVar $ primCtx (SId "undefBool") +anyVar (ATTuple ts) = internalError ("anyVar: multi-output methods are not yet supported") anyVar (ATString _) = SVar $ stringCtx (SId "undef") anyVar (ATReal) = SVar $ primCtx (SId "undefReal") anyVar (ATArray sz t) = arrBuild sz $ @@ -891,6 +892,7 @@ convARule defmap instmap mmap r@(ARule rId _ _ _ p as _ _) = convAIFace :: DefMap -> InstMap -> MethodOrderMap -> AIFace -> [SDefn] +-- TODO: support multiple method output ports convAIFace defmap instmap mmap (AIDef methId args _ p (ADef _ ret_t ret_e _) _ _) = let @@ -927,6 +929,7 @@ convAIFace defmap instmap mmap sLam (arg_infos ++ [(stateId, modType)]) $ body] +-- TODO: support multiple method output ports convAIFace defmap instmap mmap (AIActionValue args _ p methId rs (ADef _ def_t def_e _) _) = let @@ -1042,6 +1045,7 @@ convAType (ATString (Just width)) = stringType -- XXX ? convAType (ATReal) = realType convAType (ATArray sz t) = arrType sz (convAType t) convAType t | (t == mkATBool) = boolType +convAType (ATTuple ts) = internalError ("convAType: multi-output methods are not yet supported") convAType t@(ATAbstract {}) = internalError ("convAType: " ++ ppReadable t) -- ----- @@ -1156,7 +1160,11 @@ convStmt avmap (AStmtAction cset (ACall obj meth as)) = do Nothing -> -- no name because the value is unused -- but we still need to declare the correct type case (M.lookup (unQualId meth) meth_ty_map) of - Just t -> (convAType t, Nothing) + Just [t] -> (convAType t, Nothing) + Just [] -> (voidType, Nothing) + Just _ -> error ("convStmt: multiple return values for method " + ++ ppReadable meth ++ " on instance " + ++ ppReadable obj) Nothing -> (voidType, Nothing) -- we'll create new defs "act#" and "state#" with a unique number @@ -1292,6 +1300,9 @@ convAExpr e@(AMethValue t obj meth) = -- these are handled by convStmts and are not expected here internalError("convAExpr: AMethValue: " ++ ppReadable e) +convAExpr (ATupleSel _ _ _) = internalError "convAExpr: multi-output methods are not yet supported" +convAExpr (ATuple {}) = internalError "convAExpr: multi-output methods are not yet supported" + convAExpr (ANoInlineFunCall t _ (ANoInlineFun name _ _ _) as) = do let func_id = noinlineQId name a_exprs <- mapM convAExpr as diff --git a/src/comp/SignalNaming.hs b/src/comp/SignalNaming.hs index 1f2c73004..fefd26c61 100644 --- a/src/comp/SignalNaming.hs +++ b/src/comp/SignalNaming.hs @@ -10,6 +10,7 @@ import ErrorUtil(internalError) import PPrint import Id import PreIds +import Util(itos) -- remember to allow a few characters for __d3222 etc suffix signal_length_limit :: Int @@ -67,6 +68,12 @@ signalNameFromAExpr' (expr@AMethCall { }) = connectWith "_" (map signalNameFromAExpr' (ae_args expr)) signalNameFromAExpr' (expr@AMethValue { }) = ppString (ae_objid expr) ++ "_" ++ ppString (unQualId (ameth_id expr)) +signalNameFromAExpr' (expr@ATuple { }) = + "TUPLE_" ++ + connectWith "_" (map signalNameFromAExpr' (ae_elems expr)) +signalNameFromAExpr' (expr@ATupleSel { }) = + signalNameFromAExpr' (ae_exp expr) ++ + "_" ++ itos (ae_index expr) signalNameFromAExpr' (expr@ANoInlineFunCall { }) = -- use the identifier name (it is the user-known function name); -- the string in ANoInlineFun is the module name diff --git a/src/comp/SimCCBlock.hs b/src/comp/SimCCBlock.hs index 78ff83fe0..ef6418276 100644 --- a/src/comp/SimCCBlock.hs +++ b/src/comp/SimCCBlock.hs @@ -66,7 +66,7 @@ import Eval import ErrorUtil(internalError) import Data.Maybe -import Data.List(partition, intersperse, intercalate, nub, sortBy) +import Data.List(partition, intersperse, intercalate, nub, sortBy, genericDrop) import Data.List.Split(wordsBy) import Numeric(showHex) import Control.Monad(when) @@ -367,6 +367,7 @@ aTypeToCType :: AType -> (CCFragment -> CCFragment) aTypeToCType (ATBit size) = (`ofType` (bitsType size CTunsigned)) aTypeToCType (ATString _) = (`ofType` (classType "std::string")) aTypeToCType (ATReal) = (`ofType` doubleType) +aTypeToCType (ATTuple ts) = userType "WideData" aTypeToCType (ATArray _ _) = internalError "Unexpected array" aTypeToCType (ATAbstract _ _) = internalError "Unexpected abstract type" @@ -638,8 +639,7 @@ getWDataTest = do return f isWideDef :: (AType, AId) -> Bool -isWideDef x@(ATBit sz, aid) | sz > 64 = True -isWideDef x = False +isWideDef (t, _) = wideDataType t mkUndetVal :: AType -> State ConvState CCExpr mkUndetVal ty = do @@ -874,6 +874,7 @@ mkPrimCall ret sz name args = mkArg expr = if (isConst expr) || (isStringType (aType expr)) || ((aType expr) == ATReal) || + (isTupleType (aType expr)) || ((aSize expr) > 64) then aExprToCExpr noRet expr else do cexpr <- aExprToCExpr noRet expr @@ -1068,6 +1069,11 @@ aExprToCExpr _ p@(APrim _ _ _ _) = aExprToCExpr _ (AMethCall _ id mid args) = do arg_list <- mapM (aExprToCExpr noRet) args return $ (aInstMethIdToC id mid) `cCall` arg_list +aExprToCExpr ret e@(ATuple _ exprs) = + wideConcatPrim ret (aSize e) exprs +aExprToCExpr ret (ATupleSel t e idx) = + wideExtractPrim ret (aSize t) e (aSize t + sizeAfter - 1) sizeAfter + where sizeAfter = sum $ map aSize $ genericDrop idx $ att_elem_types $ ae_type e aExprToCExpr _ e@(AMGate _ id clkid) = do gmap <- gets gate_map case (M.lookup e gmap) of @@ -1145,7 +1151,7 @@ simFnStmtToCStmt (SFSDef isPort (ty,aid) Nothing) = let w = aSize ty dst = if isPort then aPortIdToCLval aid else aDefIdToCLval aid typed_id = (aTypeToCType ty) dst - in if w > 64 -- for wide data, use (bits,false) constructor to avoid initialization penalty + in if w > 64 || isTupleType ty -- for wide data, use (bits,false) constructor to avoid initialization penalty then return $ construct typed_id [mkUInt32 w, mkBool False] else return $ decl typed_id simFnStmtToCStmt (SFSDef isPort (ty@(ATString (Just sz)),aid) (Just expr)) = @@ -1422,6 +1428,11 @@ mkPortInit ((ATBit n),_,vn) | n > 32 = [ assign (aPortIdToCLval (vName_to_id vn)) (mkUInt64 0) ] mkPortInit ((ATBit n),_,vn) = [ assign (aPortIdToCLval (vName_to_id vn)) (mkUInt32 0) ] +mkPortInit (t@(ATTuple _),_,vn) = + let p = aPortIdToC (vName_to_id vn) + in [ stmt $ p `cDot` "setSize" `cCall` [ mkUInt32 $ aSize t ] + , stmt $ p `cDot` "clear" `cCall` [] + ] mkPortInit p = internalError ("SimCCBlock.mkPortInit: " ++ ppReadable p) -- Create a call to the "set_reset_fn" for submodules with output resets @@ -1708,6 +1719,8 @@ mkCtorInit task_id_set (aty@(ATBit sz),aid) = let val = ASInt defaultAId aty (ilHex (aaaa sz)) in Just (aid,[val]) | otherwise = Nothing +mkCtorInit _ (aty@(ATTuple _),aid) = + Just (aid, [ aNat (aSize aty) ]) -- system tasks shouldn't be returning other types (like String), -- so no need to consult the task_id_set mkCtorInit _ _ = Nothing @@ -2142,11 +2155,11 @@ wideLocalDef (SFSDef _ (ty, aid) _) = if wideDataType ty else [] wideLocalDef _ = [] --- return True if this type is wider than 64 bits +-- return True if this type is represented as wide data +-- (i.e. it is larger than 64 bits, or it is a tuple) wideDataType :: AType -> Bool -wideDataType (ATBit sz) - | sz > 64 = True - | otherwise = False +wideDataType (ATBit sz) = sz > 64 +wideDataType (ATTuple ts) = True wideDataType _ = False diff --git a/src/comp/SimCOpt.hs b/src/comp/SimCOpt.hs index c5d3d0afb..024c53d28 100644 --- a/src/comp/SimCOpt.hs +++ b/src/comp/SimCOpt.hs @@ -157,6 +157,7 @@ moveDefsOntoStack flags instmodmap (blocks,scheds) = let sizeOkToMove = case (M.lookup (sbid,aid) btype_map) of (Just ty) -> (ty == ATReal) || ((not (isStringType ty)) && + (not (isTupleType ty)) && ((aSize ty) <= 64)) Nothing -> False -- don't move AV task defs diff --git a/src/comp/SimExpand.hs b/src/comp/SimExpand.hs index a23885156..501fc3c25 100644 --- a/src/comp/SimExpand.hs +++ b/src/comp/SimExpand.hs @@ -1040,7 +1040,7 @@ combineCombSchedInfo use_map domain_id_map parent_abi parent_csi -- schedule graph and conflicts (even the methods not used by -- any parent rules), so we need to know which are the method Ids child_apkg = abmi_apkg child_abi - child_meth_set = S.fromList $ map aIfaceName (apkg_interface child_apkg) + child_meth_set = S.fromList $ map aif_name (apkg_interface child_apkg) -- combine each part of the CSI comb_sched_map = combineSchedMap inst parent_uses @@ -1669,7 +1669,7 @@ mkRdyMap abi = mkPair (AIClock {}) = [] mkPair (AIReset {}) = [] mkPair ifc = - let name = aIfaceName ifc + let name = aif_name ifc pred_e = aIfacePred ifc in if (isRdyId name) then [] -- Rdy methods don't have Rdy methods @@ -1974,6 +1974,8 @@ eDomain m e@(AMethCall _ i mi es) = mergeUses ([(i, unQualId mi)] : map (eDomain m) es) -- don't count the return value uses of actionvalue, only the action part eDomain m (AMethValue _ _ _) = [] +eDomain m (ATupleSel _ e _) = eDomain m e +eDomain m (ATuple _ es) = mergeUses $ map (eDomain m) es eDomain m (ANoInlineFunCall _ _ _ es) = mergeUses $ map (eDomain m) es eDomain m (AFunCall _ _ _ _ es) = mergeUses $ map (eDomain m) es eDomain _ e@(ASPort _ i) = [] @@ -2210,10 +2212,11 @@ makeMethodTemps apkg = (AIDef {}) -> (True,False) (AIActionValue {}) -> (False,True) otherwise -> (False,False) + v = aif_value aif in if is_def || is_av - then case process is_av (aif_value aif) (aif_name aif) seqNo of + then case process is_av v (aif_name aif) seqNo of (Just t@(ADef tid ty e props)) -> - let aid = adef_objid (aif_value aif) + let aid = adef_objid v -- unclear if propagating the props is correct new_def = (ADef aid ty (ASDef ty tid) props) aif' = aif { aif_value = new_def } diff --git a/src/comp/SimMakeCBlocks.hs b/src/comp/SimMakeCBlocks.hs index 9ce858b5e..fe1047ade 100644 --- a/src/comp/SimMakeCBlocks.hs +++ b/src/comp/SimMakeCBlocks.hs @@ -40,7 +40,7 @@ type ModDefMap = M.Map String DefMap -- map from method names to method port info type MethMap = M.Map AId ( Maybe VName -- enable , [(AType, AId, VName)] -- args - , Maybe (AType, VName) -- return + , [(AType, VName)] -- return , Bool -- is action , [AId] -- rule Ids ) @@ -119,7 +119,7 @@ simMakeCBlocks flags sim_system = -- methods on the top-level module top_methods = sp_interface top_pkg (top_ameths, top_vmeths) = partition aIfaceHasAction top_methods - top_vmeth_set = S.fromList $ concatMap aIfaceResId top_vmeths + top_vmeth_set = S.fromList $ concatMap aIfaceResIds top_vmeths top_ameth_set = S.fromList $ map aRuleName $ concatMap aIfaceRules top_ameths -- input clocks to the top-level module @@ -132,7 +132,7 @@ simMakeCBlocks flags sim_system = , let p_name = getModuleName p , let ms = sp_interface p , m <- ms - , let m_name = aIfaceName m + , let m_name = aif_name m , let m_rules = aIfaceRules m , let sub_actions = concatMap arule_actions m_rules , let sub_names = [ (o,m) | (ACall o m _) <- sub_actions ] @@ -208,6 +208,10 @@ getExprIds in_sched def_map known ((APrim _ _ _ args):es) = getExprIds in_sched def_map known (args ++ es) getExprIds in_sched def_map known ((AMethCall _ _ _ args):es) = getExprIds in_sched def_map known (args ++ es) +getExprIds in_sched def_map known ((ATuple _ elems):es) = + getExprIds in_sched def_map known (elems ++ es) +getExprIds in_sched def_map known ((ATupleSel _ e _):es) = + getExprIds in_sched def_map known (e:es) getExprIds in_sched def_map known ((ANoInlineFunCall _ _ _ args):es) = getExprIds in_sched def_map known (args ++ es) getExprIds in_sched def_map known ((AFunCall _ _ _ _ args):es) = @@ -290,7 +294,8 @@ onePackageToBlock flags name_map full_meth_map ss pkg = ] meth_args = concat [ ins | (_,ins,_,_,_) <- M.elems meth_map ] meth_rets = [ (rt, n, vn) - | (n, (_,_,(Just (rt,vn)),_,_)) <- M.toList meth_map + | (n, (_,_,rts,_,_)) <- M.toList meth_map + , (rt,vn) <- rts ] ports = meth_ens ++ meth_args ++ meth_rets @@ -323,7 +328,7 @@ onePackageToBlock flags name_map full_meth_map ss pkg = dms = [ M.singleton clk [(aid, fromJust m')] | m <- iface - , let aid = aIfaceName m + , let aid = aif_name m , let m' = cvtIFace modId (sp_pps pkg) def_map meth_map method_order_map reset_list m , isJust m' @@ -517,7 +522,7 @@ cvtIFace :: Id -> [PProp] -> DefMap -> MethMap -> MethodOrderMap -> [(ResetId, AReset)] -> AIFace -> Maybe SimCCFn cvtIFace modId pps def_map meth_map method_order_map reset_list m = - do let name = aIfaceName m + do let name = aif_name m inputs = aIfaceArgs m args = [ (t,i) | (i,t) <- inputs ] -- always_enabled methods need to forcibly check their ready signal @@ -527,8 +532,8 @@ cvtIFace modId pps def_map meth_map method_order_map reset_list m = if ((isAlwaysEn pps name) && (aIfaceHasAction m)) then -- we have to find the name of the port associated -- with the RDY method - let rdy_id = mkRdyId (aIfaceName m) - mport = do (_,_,Just (_,vn),_,_) <- M.lookup rdy_id meth_map + let rdy_id = mkRdyId (aif_name m) + mport = do (_,_,[(_,vn)],_,_) <- M.lookup rdy_id meth_map return $ ASPort aTBool (vName_to_id vn) in case mport of (Just prt) -> [SFSCond prt ss []] @@ -543,15 +548,21 @@ cvtIFace modId pps def_map meth_map method_order_map reset_list m = wp = aIfaceProps m rst_ids = map (ae_objid . areset_wire) (mapMaybe (\n -> lookup n reset_list) (wpResets wp)) - (men, ins, mr, _, ifcrules) <- M.lookup name meth_map + (men, ins, rs, _, ifcrules) <- M.lookup name meth_map let prt vn = vName_to_id vn - rt = do { (t,_) <- mr; return t } + rt = + case rs of + [(t,_)] -> Just t + [] -> Nothing + _ -> internalError ("cvtIFace: multiple return values " + ++ "not supported in method " + ++ ppReadable name) en_stmts = maybe [] (\vn -> [SFSAssign True (prt vn) aTrue]) men wf_stmts = map (\i -> SFSAssign False (mkIdWillFire i) aTrue) ifcrules in_stmts = map (\(t,i,vn) -> SFSAssign True (prt vn) (ASPort t i)) ins body_stmts = - case mr of - Just (t,vn) -> + case rs of + [(t,vn)] -> -- account for the possible return of an actionvalue result let -- the return def ret_def = aif_value m @@ -584,9 +595,13 @@ cvtIFace modId pps def_map meth_map method_order_map reset_list m = -- ready is off (the user lied about it being always_en'd), -- but, at that point, all bets are off anyway check_rdy ss' ++ ret_stmts - Nothing -> check_rdy $ + [] -> check_rdy $ cvtActions modId name def_map method_order_map S.empty body rst_ids + -- TODO: Support methods with multiple return values + _ -> internalError ("cvtIFace: multiple return values " + ++ "not supported in method " + ++ ppReadable name) all_stmts = concat [en_stmts, wf_stmts, in_stmts, body_stmts] return $ SimCCFn (getIdBaseString name) args rt all_stmts @@ -1443,6 +1458,8 @@ tsortActionsAndDefs modId rId mmap ds acts reset_ids = -- function to substitute ASDef for AMethValue substAV (AMethValue ty obj meth) = ASDef ty (mkAVMethTmpId obj meth) + substAV (ATuple ts es) = ATuple ts (map substAV es) + substAV (ATupleSel t e i) = ATupleSel t (substAV e) i substAV (APrim i t o es) = (APrim i t o (map substAV es)) substAV (AMethCall t o m es) = (AMethCall t o m (map substAV es)) substAV (AFunCall t o f isC es) = (AFunCall t o f isC (map substAV es)) @@ -1620,6 +1637,10 @@ substGateReferences smap stmts = e { ae_args = map substInAExpr es } substInAExpr e@(AMethCall { ae_args = es }) = e { ae_args = map substInAExpr es } + substInAExpr e@(ATuple { ae_elems = es }) = + e { ae_elems = map substInAExpr es } + substInAExpr e@(ATupleSel { ae_exp = e1 }) = + e { ae_exp = substInAExpr e1 } substInAExpr e@(ANoInlineFunCall { ae_args = es }) = e { ae_args = map substInAExpr es } substInAExpr e@(AFunCall { ae_args = es }) = diff --git a/src/comp/SimPackage.hs b/src/comp/SimPackage.hs index f17e688d8..902441aa2 100644 --- a/src/comp/SimPackage.hs +++ b/src/comp/SimPackage.hs @@ -373,9 +373,9 @@ getSimPackageInputs spkg = -- ----- getPortInfo :: [PProp] -> AIFace - -> Maybe (AId, (Maybe VName, [(AType,AId,VName)], Maybe (AType,VName), Bool, [AId])) + -> Maybe (AId, (Maybe VName, [(AType,AId,VName)], [(AType,VName)], Bool, [AId])) getPortInfo pps aif = - let name = aIfaceName aif + let name = aif_name aif vfi = aif_fieldinfo aif en = do e <- vf_enable vfi -- always enabled implies enabled when ready @@ -384,17 +384,15 @@ getPortInfo pps aif = args = aIfaceArgs aif ps = map fst (vf_inputs vfi) ins = [ (t,i,vn) | ((i,t),vn) <- zip args ps ] - rt = aIfaceResType aif - ret = case (vf_output vfi) of - (Just (vn,_)) -> Just (rt,vn) - Nothing -> Nothing + rts = aIfaceResTypes aif + rets = zip rts $ map fst $ vf_outputs vfi isAction = case aif of (AIAction {}) -> True (AIActionValue {}) -> True otherwise -> False rules = map aRuleName (aIfaceRules aif) in case vfi of - (Method {}) -> Just (name, (en, ins, ret, isAction, rules)) + (Method {}) -> Just (name, (en, ins, rets, isAction, rules)) otherwise -> Nothing -- ----- diff --git a/src/comp/SimPackageOpt.hs b/src/comp/SimPackageOpt.hs index 82f966c88..cb00c867a 100644 --- a/src/comp/SimPackageOpt.hs +++ b/src/comp/SimPackageOpt.hs @@ -138,6 +138,7 @@ inlineDefs pkg = isNotOk d | isUnsized (adef_type d) = True | (aSize d > 64) = True + | isTupleType (adef_type d) = True | isTaskOrForeignFunc d = True | isCase d = True | otherwise = False @@ -230,6 +231,10 @@ optimizeConcats pkg = -- recurse for other optConcat (APrim i t o as) = APrim i t o (map optConcat as) optConcat (AMethCall t o m as) = AMethCall t o m (map optConcat as) + -- XXX There is maybe an opportunity to optimize tuple construction here, + -- since that basically turns into a concat as well. + optConcat (ATuple t as) = ATuple t (map optConcat as) + optConcat (ATupleSel t e idx) = ATupleSel t (optConcat e) idx optConcat (AFunCall t i f isC as) = AFunCall t i f isC (map optConcat as) optConcat e = e in mapAExprs optConcat pkg @@ -316,9 +321,15 @@ convertASAny errh flags apkg = do cvtASAnyExpr (APrim aid ty op args) = do args' <- mapM cvtASAnyExpr args return $ APrim aid ty op args' - cvtASAnyExpr (AMethCall ty aid mid args) = + cvtASAnyExpr (AMethCall ty aid mid args) = do args' <- mapM cvtASAnyExpr args return $ AMethCall ty aid mid args' + cvtASAnyExpr (ATuple ty elems) = + do elems' <- mapM cvtASAnyExpr elems + return $ ATuple ty elems' + cvtASAnyExpr (ATupleSel ty exp idx) = + do exp' <- cvtASAnyExpr exp + return $ ATupleSel ty exp' idx cvtASAnyExpr (ANoInlineFunCall ty aid fun args) = do args' <- mapM cvtASAnyExpr args return $ ANoInlineFunCall ty aid fun args' diff --git a/src/comp/SystemCWrapper.hs b/src/comp/SystemCWrapper.hs index b7fd88344..860f83b42 100644 --- a/src/comp/SystemCWrapper.hs +++ b/src/comp/SystemCWrapper.hs @@ -8,7 +8,7 @@ import Pragma(isAlwaysRdy, isEnWhenRdy) import FileNameUtil(mkCxxName, mkHName) import ASyntax(AAbstractInput(..), AIFace(..), AExpr(..), AClock(..), - aIfaceArgs, aIfaceName, aIfaceProps) + aIfaceArgs, aif_name, aIfaceProps) import ASyntaxUtil import VModInfo(vName_to_id, VPathInfo(..)) import Wires @@ -38,7 +38,7 @@ checkSystemCIfc errh flags sim_system = do isBad m@(AIActionValue {}) = -- we allow ActionValue methods only -- if they have no arguments and no enable not ((null (aIfaceArgs m)) && - (isEnWhenRdy pps (aIfaceName m))) + (isEnWhenRdy pps (aif_name m))) isBad _ = False bad_methods = [ getIdBaseString (aif_name m) | m <- sp_interface top_pkg @@ -131,7 +131,7 @@ wrapSystemC flags sim_system = do mk_port_map_entry (mid, (en, ins, ri, act, _)) = let en_list = maybe [] (\vn -> [(1,vName_to_id vn,True,False)]) en in_list = [ (aSize t,i,True,False) | (t,i,_) <- ins ] - ret_list = maybe [] (\(t,vn) -> [(aSize t,vName_to_id vn,False,act)]) ri + ret_list = map (\(t,vn) -> (aSize t,vName_to_id vn,False,act)) ri ports = filter (\(n,_,_,_) -> n>0) (en_list ++ in_list ++ ret_list) always_rdy = (isRdyId mid) && (isAlwaysRdy pps mid) @@ -157,7 +157,7 @@ wrapSystemC flags sim_system = do ] -- utility functions for grouping methods by domain - meth_domains = M.fromList [ (aIfaceName aif, dom) + meth_domains = M.fromList [ (aif_name aif, dom) | aif <- (sp_interface top_pkg) , let wp = aIfaceProps aif , let dom = wpClockDomain wp diff --git a/src/comp/TCheck.hs b/src/comp/TCheck.hs index 036cfcf67..a423f9481 100644 --- a/src/comp/TCheck.hs +++ b/src/comp/TCheck.hs @@ -707,43 +707,42 @@ tiExpr as td exp@(CmoduleVerilog name ui clks rsts args fields sch ps) = do -- matches the types. let -- XXX These errors should give more info - chkResType :: [VPort] -> Maybe VPort -> Maybe VPort -> Type -> - TI ([VPort], Maybe VPort, Maybe VPort) - chkResType ps me@(Just _) mo@Nothing t = - if (isActionWithoutValue t) then return (ps, me, mo) + chkResType :: [VPort] -> Maybe VPort -> [VPort] -> Type -> + TI ([VPort], Maybe VPort, [VPort]) + chkResType ps me@(Just _) [] t = + if (isActionWithoutValue t) then return (ps, me, []) else if (isActionWithValue t) then errMissingValue "ActionValue" t - else if (isBit t) + else if (isBitTuple t) then errUnexpectedEnable "value" t else errBadResType t - chkResType ps me@Nothing mo@(Just _) t = - if (isBit t) then return (ps, me, mo) + chkResType ps me@Nothing outs@(_:_) t = + if (isBitTuple t) then return (ps, me, outs) else if (isActionWithValue t) then errMissingEnable "ActionValue" t else if (isActionWithoutValue t) then errUnexpectedValue "Action" t else errBadResType t - chkResType ps me@(Just _) mo@(Just _) t = - if (isActionWithValue t) then return (ps, me, mo) + chkResType ps me@(Just _) outs@(_:_) t = + if (isActionWithValue t) then return (ps, me, outs) else if (isActionWithoutValue t) then errUnexpectedValue "Action" t - else if (isBit t) + else if (isBitTuple t) then errUnexpectedEnable "value" t else errBadResType t - chkResType ps Nothing Nothing t = do - -- must have more than 0 ports - when (null ps) $ - err (getPosition f, - EForeignModTooFewPorts (pfpString f)) + chkResType ps Nothing [] t = do -- update the Classic fieldinfo to BSV format let inputs = initOrErr "chkResType" ps let final_port = lastOrErr "chkResType" ps -- XXX kill PrimAction once imports in Prelude are converted over if (isActionWithoutValue t) || (isPrimAction t) - then return (inputs, Just final_port, Nothing) - else if (isBit t) - then return (inputs, Nothing, Just final_port) - else errBadResType t + then return (inputs, Just final_port, []) + else if (isBitTuple t) + -- XXX should have multiple output ports for bit tuples here? + then return (inputs, Nothing, [final_port]) + else if (t == tPrimUnit) + then return (ps, Nothing, []) + else errBadResType t errBadResType t = err (getPosition f, @@ -805,9 +804,9 @@ tiExpr as td exp@(CmoduleVerilog name ui clks rsts args fields sch ps) = do else if (null argTypes) then return vfi else errInoutHasArgs - Method { vf_inputs = inputs, vf_enable = me, vf_output = mo } -> + Method { vf_inputs = inputs, vf_enable = me, vf_outputs = outputs } -> do -- updates inputs, me and mo when processing Classic format - (inputs', me', mo') <- chkResType inputs me mo resType + (inputs', me', outputs') <- chkResType inputs me outputs resType -- check if any actions are SB with themselves when (((isActionWithValue resType) || (isActionWithoutValue resType) || @@ -815,7 +814,7 @@ tiExpr as td exp@(CmoduleVerilog name ui clks rsts args fields sch ps) = do (f `elem` self_sbs)) (errActionSelfSB f) chkArgs inputs' argTypes - return (vfi { vf_inputs = inputs', vf_enable = me', vf_output = mo' }) + return (vfi { vf_inputs = inputs', vf_enable = me', vf_outputs = outputs' }) -- paramResults <- mapM tiParam es qsses <- mapM tiArg args -- let (pses, tys) = unzip paramResults @@ -899,7 +898,7 @@ tiExpr as td exp@(CForeignFuncC link_id wrap_cqt) = do when (isTypeString av_arg) $ err (getPosition pos, EForeignFuncStringRes) (ctxs, prim_sz) <- findBitSize av_arg - let prim_t = TAp tActionValue_ prim_sz + let prim_t = TAp tActionValue_ $ TAp tBit prim_sz return (ctxs, prim_t, cexpr) -- anything else must be bitifiable else do let cexpr = \e -> cVApply idUnpack [e] @@ -1521,7 +1520,7 @@ finishSWriteAV as td v f es paramResults eq_ps = let (pss, es') = unzip pses -- v <- newTVar "XXX" KNum f - let tav = TAp tActionValue_ v + let tav = TAp tActionValue_ (TAp tBit v) let taskty = foldr fn tav tys -- XXX: quantifying in IConv instead so free type vars are caught correctly @@ -1583,7 +1582,7 @@ taskCheckFOpen as td f [filen] = (vp,filentc) <- tiExpr as tString filen -- let avfile = (TAp (tActionValueAt (getPosition f)) tFile) - tav32 = TAp (tActionValue_At (getPosition f)) t32 + tav32 = TAp (tActionValue_At (getPosition f)) bit32 fty = tString `fn` tav32 applied = (CTaskApplyT f fty [filentc]) let t = cVApply (setIdPosition (getPosition f) idFromActionValue_) [applied] @@ -1599,7 +1598,7 @@ taskCheckFOpen as td f [filen,mode] = -- -- let avfile = (TAp (tActionValueAt (getPosition f)) tFile) - tav32 = TAp (tActionValue_At (getPosition f)) t32 + tav32 = TAp (tActionValue_At (getPosition f)) bit32 fty = tString `fn` tString `fn` tav32 applied = (CTaskApplyT f fty [filentc,modetc]) let t = cVApply (setIdPosition (getPosition f) idFromActionValue_) [applied] diff --git a/src/comp/TopUtils.hs b/src/comp/TopUtils.hs index 45e0f0498..7f7794af7 100644 --- a/src/comp/TopUtils.hs +++ b/src/comp/TopUtils.hs @@ -27,7 +27,7 @@ import IdPrint import ISyntax(IPackage(..), IModule(..), IStateVar(..), IRules(..)) import ASyntax(APackage(..), ASPackage(..), ARule(..), - aIfaceName) + aif_name) import SystemVerilogTokens(SV_Token(..)) import Version(bluespec, bscVersionStr) @@ -253,7 +253,7 @@ instance Stats APackage where (showLen (apkg_rules apkg) "rules" <> if v then text "" <+>pPrint PDReadable 0 [ i | ARule { arule_id = i } <- apkg_rules apkg ] else text "") $+$ (showLen (apkg_interface apkg) "interface methods" <> - if v then text "" <+> pPrint PDReadable 0 (map aIfaceName (apkg_interface apkg)) else text "") + if v then text "" <+> pPrint PDReadable 0 (map aif_name (apkg_interface apkg)) else text "") )) instance Stats ASPackage where diff --git a/src/comp/Type.hs b/src/comp/Type.hs index c8d598ce3..014a1fbce 100644 --- a/src/comp/Type.hs +++ b/src/comp/Type.hs @@ -61,13 +61,13 @@ tSizeOf = TCon (TyCon idSizeOf (Just (Kfun KStar KNum)) TIabstract) tAction, tActionValue, tActionValue_, tAction_:: Type tAction = TCon (TyCon idAction (Just KStar) (TItype 0 (TAp tActionValue tPrimUnit))) tActionValue = TCon (TyCon idActionValue (Just (Kfun KStar KStar)) (TIstruct SStruct [id__value, id__action])) -tActionValue_ = TCon (TyCon idActionValue_ (Just (Kfun KNum KStar)) (TIstruct SStruct [id__value, id__action])) -tAction_ = TAp tActionValue_ (tOfSize 0 noPosition) +tActionValue_ = TCon (TyCon idActionValue_ (Just (Kfun KStar KStar)) (TIstruct SStruct [id__value, id__action])) +tAction_ = TAp tActionValue_ tPrimUnit tActionAt, tActionValueAt, tActionValue_At :: Position -> Type tActionAt pos = TCon (TyCon (idActionAt pos) (Just KStar) (TItype 0 (TAp (tActionValueAt pos) (tPrimUnitAt pos)))) tActionValueAt pos = TCon (TyCon (idActionValueAt pos) (Just (Kfun KStar KStar)) (TIstruct SStruct [id__value_at pos, id__action_at pos])) -tActionValue_At pos = TCon (TyCon (idActionValue_At pos) (Just (Kfun KNum KStar)) (TIstruct SStruct [id__value_at pos, id__action_at pos])) +tActionValue_At pos = TCon (TyCon (idActionValue_At pos) (Just (Kfun KStar KStar)) (TIstruct SStruct [id__value_at pos, id__action_at pos])) tPrimAction, tRules :: Type tPrimAction = TCon (TyCon idPrimAction (Just KStar) TIabstract) @@ -163,13 +163,21 @@ getAVType :: Type -> Type getAVType (TAp av t) | av == tActionValue = t getAVType t = internalError("getAVType not ActionValue: " ++ ppReadable t) +-- Note that we consider ActionValue_ (Bit 0) to be an action without a value, +-- as this is still created by foreign verilog module imports. +-- XXX should rework this to just yield ActionValue_ () for empty types. isActionWithoutValue :: Type -> Bool -isActionWithoutValue (TAp av (TCon (TyNum 0 _))) = av == tActionValue_ +isActionWithoutValue (TAp av (TAp (TCon (TyCon i _ _)) (TCon (TyNum 0 _)))) = + av == tActionValue_ && i == idBit +isActionWithoutValue (TAp av (TCon (TyCon i _ _))) = + av == tActionValue_ && i == idPrimUnit isActionWithoutValue _ = False isActionWithValue :: Type -> Bool -isActionWithValue (TAp av (TCon (TyNum n _))) = (av == tActionValue_) && (n > 0) isActionWithValue (TAp av (TVar _)) = av == tActionValue_ +isActionWithValue (TAp av (TAp (TCon (TyCon i _ _)) (TCon (TyNum 0 _)))) + | av == tActionValue_ && i == idBit = False +isActionWithValue (TAp av t) = (av == tActionValue_) && isBitTuple t isActionWithValue _ = False isClock, isReset, isInout, isInout_ :: Type -> Bool @@ -199,4 +207,9 @@ isChar t = t == tChar isReal t = t == tReal isFmt t = t == tFmt +isBitTuple :: Type -> Bool +isBitTuple (TAp (TAp (TCon (TyCon i _ _)) t1) t2) | i == idPrimPair = + isBit t1 && isBitTuple t2 +isBitTuple t = isBit t + -- ------------------------- diff --git a/src/comp/VIOProps.hs b/src/comp/VIOProps.hs index f9c88fdc5..5d3302b2a 100644 --- a/src/comp/VIOProps.hs +++ b/src/comp/VIOProps.hs @@ -10,7 +10,7 @@ import Flags import PPrint import ErrorUtil(internalError) import Id -import PreIds(idPrimAction, idInout_) +import PreIds(idPrimAction, idInout_, idPrimUnit) import VModInfo(vArgs, vFields, VName(..), VeriPortProp(..), VArgInfo(..), VFieldInfo(..), VPort) import Prim @@ -151,9 +151,12 @@ getIOProps flags ppp@(ASPackage _ _ _ os is ios vs _ ds io_ds fs _ _ _) = -- create the method name map let nmap = M.fromList $ createVerilogNameMapForAVInst flags v, - -- for each method that has an output port - vfi@(Method { vf_output = Just (vname,pprops) }) - <- vFields (avi_vmi v), + -- for each method (not clocks or resets) + vfi@(Method {}) <- vFields (avi_vmi v), + -- for each method output port + (methpart, (vname, pprops)) + <- zip (map MethodResult [1..]) (vf_outputs vfi), + -- for each port copy ino <- if (vf_mult vfi > 1) then map Just [0 .. vf_mult vfi] @@ -162,7 +165,7 @@ getIOProps flags ppp@(ASPackage _ _ _ os is ios vs _ ds io_ds fs _ _ _) = let meth_id = mkMethId (avi_vname v) (vf_name vfi) ino - MethodResult, + methpart, -- convert to Verilog signal name let veri_id = xLateIdUsingFStringMap nmap meth_id ] @@ -194,7 +197,8 @@ getIOProps flags ppp@(ASPackage _ _ _ os is ios vs _ ds io_ds fs _ _ _) = -- return empty-list here; but the internal check -- is nice to have (if it's not too expensive). internalError ("getOVProp: could not find method " ++ - ppString i) + ppString i ++ " in wireMap_out:\n" ++ + ppReadable wireMap_out) -- ---------- -- construct the VeriPortProp list for an input @@ -400,5 +404,6 @@ size :: AType -> Integer size (ATBit n) = n size (ATAbstract a _) | a == idPrimAction = 1 size (ATAbstract a [n]) | a == idInout_ = n +size (ATAbstract a _) | a == idPrimUnit = 0 size (ATString _ ) = 0 size t = internalError ("getIOProps.size: " ++ show t) diff --git a/src/comp/VModInfo.hs b/src/comp/VModInfo.hs index 6964602a1..ab96eb1b9 100644 --- a/src/comp/VModInfo.hs +++ b/src/comp/VModInfo.hs @@ -23,7 +23,7 @@ module VModInfo(VModInfo, mkVModInfo, getIfcIdPosition, str_to_vPort,getVPortString, mkNamedEnable, - mkNamedOutput, + mkNamedOutputs, mkNamedReady, mkNamedInout, extractNames @@ -274,7 +274,7 @@ data VFieldInfo = Method { vf_name :: Id, -- method name -- optional because the method may be independent of a reset signal vf_mult :: Integer, -- multiplicity vf_inputs :: [VPort], - vf_output :: Maybe VPort, + vf_outputs:: [VPort], vf_enable :: Maybe VPort } | Clock { vf_name :: Id } -- output clock name -- connection information is in the ClockInfo @@ -300,11 +300,12 @@ instance NFData VFieldInfo where instance PPrint VFieldInfo where pPrint d p (Method n c r m i o e) = - text "method " <> pout o <> pPrint d p n <> pmult m <> + text "method " <> pouts o <> pPrint d p n <> pmult m <> pins i <> pena e <+> ppMClk d c <+> ppMRst d r <> text ";" - where pout Nothing = empty - pout (Just po) = pPrint d p po + where pouts [] = empty + pouts [po] = pPrint d p po + pouts o = text "(" <> sepList (map (pPrint d p) o) (text ",") <> text ")" pmult 1 = empty pmult n = text "[" <> pPrint d p n <> text "]" pins [] = empty @@ -685,17 +686,16 @@ mkNamedEnable vfi = if (newStr == "") then baseid else setIdBaseString baseid ne where baseid = mkEnableId (vf_name vfi) newStr = maybe "" getVPortString (vf_enable vfi) -mkNamedOutput :: VFieldInfo -> Id -mkNamedOutput vfi = if (newStr == "") then baseid else setIdBaseString baseid newStr +mkNamedOutputs :: VFieldInfo -> [Id] +mkNamedOutputs vfi = map (setIdBaseString baseid) newStrs where baseid = (vf_name vfi) - newStr = maybe "" getVPortString (vf_output vfi) + newStrs = map getVPortString (vf_outputs vfi) -- VFieldInfo does not have a ready field, so we just use the default construction for the ready signal. -- in aState we merge method and RDY_method to do the right thing. mkNamedReady :: VFieldInfo -> Id mkNamedReady vfi = baseid -- if (newStr == "") then baseid else setIdBaseString baseid newStr where baseid = mkRdyId (vf_name vfi) - -- newStr = maybe "" getVPortString (vf_output vfi) mkNamedInout :: VFieldInfo -> Id mkNamedInout vfi = setIdBaseString baseid newStr @@ -705,8 +705,8 @@ mkNamedInout vfi = setIdBaseString baseid newStr --------------------------- Name extraction from VFieldInfo -- extract possible port Ids from a VField Info -- return value is result, ready, enable -extractNames :: VFieldInfo -> (Id, Id, Id ) +extractNames :: VFieldInfo -> ([Id], Id, Id ) extractNames vfi = (result, ready, enable) - where result = mkNamedOutput vfi + where result = mkNamedOutputs vfi ready = mkNamedReady vfi enable = mkNamedEnable vfi diff --git a/src/comp/bluetcl.hs b/src/comp/bluetcl.hs index 3edca23b7..dccab85fb 100644 --- a/src/comp/bluetcl.hs +++ b/src/comp/bluetcl.hs @@ -1118,7 +1118,7 @@ tclModule ["methods",modname] = do let apkg = abemi_apkg abmi pps = abemi_pps abmi ifc = apkg_interface apkg - ifc_map = [ (aIfaceName aif, rawIfcFieldFromAIFace pps aif) + ifc_map = [ (aif_name aif, rawIfcFieldFromAIFace pps aif) | aif <- ifc ] let tifc = getModuleIfc abmi fs <- getIfcHierarchy Nothing ifc_map tifc @@ -1639,7 +1639,7 @@ tclRule ["full",modname,rule] = Nothing -> Nothing Just (ARule i ps _ _ rPred _ _ _) -> Just (ps, getPosition i, aAnds [ifPred, rPred]) - cvtIfc (AIDef _ _ _ ifPred (ADef dId _ _ _) _ _) = + cvtIfc (AIDef dId _ _ ifPred _ _ _) = if (dId == rId) then Just ([], getPosition dId, ifPred) else Nothing @@ -1960,7 +1960,7 @@ instance ExpandInfoHelper BModView where -- flattened ifc names let ifc_names = map pfpString $ filter (not . isRdyId) $ - map (aIfaceName) (apkg_interface apkg) + map (aif_name) (apkg_interface apkg) -- rules let rule_names = map (pfpString . arule_id) (apkg_rules apkg) -- schedule @@ -3274,7 +3274,7 @@ data RawIfcField = (Maybe Id) (Maybe Id) -- associated clk and rst [(Maybe Id, AType)] -- arguments [VPort] -- argument ports - (Maybe (VPort, AType)) -- return value + [(VPort, AType)] -- return values (Maybe VPort) -- enable signal -- Note: no ready signal at this stage | RawClock Id @@ -3292,26 +3292,32 @@ rawIfcFieldName (RawInout i _ _ _ _) = i rawIfcFieldFromAIFace :: [PProp] -> AIFace -> RawIfcField rawIfcFieldFromAIFace _ (AIDef i args _ _ def - (Method _ clk rst mult ins mo@(Just out) Nothing) _) = - let -- include the type in the "mo" - mo' = Just (out, adef_type def) - in RawMethod i mult clk rst (mapFst Just args) ins mo' Nothing + (Method _ clk rst mult ins outs Nothing) _) = + let -- include the type in the "outs" + outs' = zip outs $ + case adef_type def of + ATTuple ts -> ts + t -> [t] + in RawMethod i mult clk rst (mapFst Just args) ins outs' Nothing rawIfcFieldFromAIFace pps (AIAction args _ _ i _ - (Method _ clk rst mult ins Nothing me@(Just _))) = + (Method _ clk rst mult ins [] me@(Just _))) = let -- filter out inhigh enable ports -- XXX is there a better way to do this? me' = if (isAlwaysEn pps i) then Nothing else me - in RawMethod i mult clk rst (mapFst Just args) ins Nothing me' + in RawMethod i mult clk rst (mapFst Just args) ins [] me' rawIfcFieldFromAIFace pps (AIActionValue args _ _ i _ def - (Method _ clk rst mult ins mo@(Just out) me@(Just _))) = + (Method _ clk rst mult ins outs me@(Just _))) = let -- filter out inhigh enable ports -- XXX is there a better way to do this? me' = if (isAlwaysEn pps i) then Nothing else me - -- include the type in the "mo" - mo' = Just (out, adef_type def) - in RawMethod i mult clk rst (mapFst Just args) ins mo' me' + -- include the type in the "outs" + outs' = zip outs $ + case adef_type def of + ATTuple ts -> ts + t -> [t] + in RawMethod i mult clk rst (mapFst Just args) ins outs' me' rawIfcFieldFromAIFace _ (AIClock i _ (Clock _)) = RawClock i rawIfcFieldFromAIFace _ (AIReset i _ (Reset _)) = RawReset i rawIfcFieldFromAIFace _ (AIInout i (AInout e) (Inout _ vn mclk mrst)) = @@ -3320,23 +3326,20 @@ rawIfcFieldFromAIFace _ aif = internalError ("rawIfcFieldFromAIFace: unexpected AIFace combo: " ++ ppReadable aif) -rawIfcFieldFromAVInst :: ([AType], Maybe AType, Maybe AType) -> +rawIfcFieldFromAVInst :: ([AType], Maybe AType, [AType]) -> VFieldInfo -> RawIfcField -rawIfcFieldFromAVInst (arg_tys,_,mo_type) (Method i clk rst mult ins mo me) = +rawIfcFieldFromAVInst (arg_tys,_,out_tys) (Method i clk rst mult ins outs me) = let -- XXX AVInst doesn't record argument names args = zip (repeat Nothing) arg_tys - -- add the return bit-type to the mo - mo' = case (mo, mo_type) of - (Just o, Just o_type) -> Just (o, o_type) - (Nothing, Nothing) -> Nothing - _ -> internalError ("rawIfcFieldFromAVInst: unexpected mo: " ++ - ppReadable (mo, mo_type)) - in RawMethod i mult clk rst args ins mo' me + -- add the return bit-type to the outs + outs' = zip outs out_tys + in RawMethod i mult clk rst args ins outs' me rawIfcFieldFromAVInst _ (Clock i) = RawClock i rawIfcFieldFromAVInst _ (Reset i) = RawReset i -rawIfcFieldFromAVInst (_,_,mt) (Inout i vn mclk mrst) = - let t = fromJustOrErr ("getIfc: no type for Inout") mt - in RawInout i t vn mclk mrst +rawIfcFieldFromAVInst (_,_,[t]) (Inout i vn mclk mrst) = RawInout i t vn mclk mrst +rawIfcFieldFromAVInst _ vfi = + internalError ("rawIfcFieldFromAVInst: unexpected VFieldInfo: " ++ + ppReadable vfi) -- --------------- @@ -3486,7 +3489,7 @@ data PortIfcInfo = PIMethod Id Id (Maybe Id) (Maybe Id) -- associated clk and rst [(Maybe Id, AType, (String, IType))] -- arguments - (Maybe (String, AType, IType)) -- return value + [(String, AType, IType)] -- return values (Maybe (String, IType)) -- enable signal (Maybe (String, IType)) -- ready signal | PIClock Id Id (Maybe ((String, IType), Maybe (String, IType))) @@ -3519,7 +3522,7 @@ getModPortInfo apkg pps tifc = do -- interface hierarchy let -- map from flattened ifc name to its raw info - ifc_map = [ (aIfaceName aif, rawIfcFieldFromAIFace pps aif) + ifc_map = [ (aif_name aif, rawIfcFieldFromAIFace pps aif) | aif <- ifc ] ifc_hier <- getIfcHierarchy Nothing ifc_map tifc @@ -3633,8 +3636,8 @@ getSubmodPortInfo mtifc avi = do concatMap getIfcHier ifc_hier) adjustPrimFields :: Maybe Type -> AVInst -> - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) -> - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) + ([VFieldInfo], [([AType], Maybe AType, [AType])]) -> + ([VFieldInfo], [([AType], Maybe AType, [AType])]) adjustPrimFields Nothing _ vfts = vfts adjustPrimFields (Just tifc) avi vfts = if (leftCon tifc == Just idReg) @@ -3678,8 +3681,8 @@ adjustPrimFields (Just tifc) avi vfts = else vfts -- This is a no-op but it does add some error checking -adjustRegAlignedFields :: ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) -> - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) +adjustRegAlignedFields :: ([VFieldInfo], [([AType], Maybe AType, [AType])]) -> + ([VFieldInfo], [([AType], Maybe AType, [AType])]) adjustRegAlignedFields (vfi, fts) = let renameField vf@(Method {vf_name = i }) | (i `qualEq` id_read noPosition) = vf @@ -3689,8 +3692,8 @@ adjustRegAlignedFields (vfi, fts) = in (map renameField vfi, fts) -adjustRegFields :: ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) -> - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) +adjustRegFields :: ([VFieldInfo], [([AType], Maybe AType, [AType])]) -> + ([VFieldInfo], [([AType], Maybe AType, [AType])]) adjustRegFields (vfi, fts) = let renameField vf@(Method {vf_name = i }) | (i `qualEq` idPreludeRead) = vf { vf_name = id_read noPosition } @@ -3699,8 +3702,8 @@ adjustRegFields (vfi, fts) = ppReadable (vf_name vf)) in (map renameField vfi, fts) -adjustFIFOFields :: ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) -> - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) +adjustFIFOFields :: ([VFieldInfo], [([AType], Maybe AType, [AType])]) -> + ([VFieldInfo], [([AType], Maybe AType, [AType])]) adjustFIFOFields (vfi, fts) = let enq_rdy = mkRdyId idEnq deq_rdy = mkRdyId idDeq @@ -3712,8 +3715,8 @@ adjustFIFOFields (vfi, fts) = renameField vft = [vft] in unzip $ concatMap renameField $ zip vfi fts -adjustFIFO0Fields :: ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) -> - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) +adjustFIFO0Fields :: ([VFieldInfo], [([AType], Maybe AType, [AType])]) -> + ([VFieldInfo], [([AType], Maybe AType, [AType])]) adjustFIFO0Fields (vfi, fts) = let (clk, rst) = case vfi of @@ -3721,12 +3724,12 @@ adjustFIFO0Fields (vfi, fts) = (_:d@(Method _ c r _ _ _ _):_) -> (c, r) _ -> internalError ("adjustFIFO0Fields: vfi = " ++ ppReadable vfi) - first_vfi = Method idFirst clk rst 1 [] Nothing Nothing - first_fts = ([], Nothing, Nothing) + first_vfi = Method idFirst clk rst 1 [] [] Nothing + first_fts = ([], Nothing, []) in (first_vfi:vfi, first_fts:fts) -adjustSyncRegFields :: ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) -> - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) +adjustSyncRegFields :: ([VFieldInfo], [([AType], Maybe AType, [AType])]) -> + ([VFieldInfo], [([AType], Maybe AType, [AType])]) adjustSyncRegFields (vfi, fts) = let renameField vf@(Method {vf_name = i }) -- XXX these are qualified Clock, not Prelude @@ -3738,28 +3741,28 @@ adjustSyncRegFields (vfi, fts) = ppReadable (vf_name vf)) in (map renameField vfi, fts) -adjustRWireFields :: ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) -> - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) +adjustRWireFields :: ([VFieldInfo], [([AType], Maybe AType, [AType])]) -> + ([VFieldInfo], [([AType], Maybe AType, [AType])]) adjustRWireFields (vfi, fts) = let renameField vf@(Method {vf_name = i }) | (i `qualEq` idWHas) = vf { vf_name = unQualId $ mkRdyId idWGet } renameField vf = vf in (map renameField vfi, fts) -adjustRWire0Fields :: ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) -> - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) +adjustRWire0Fields :: ([VFieldInfo], [([AType], Maybe AType, [AType])]) -> + ([VFieldInfo], [([AType], Maybe AType, [AType])]) adjustRWire0Fields (vfi, fts) = let (clk, rst) = case vfi of ((Method _ c r _ _ _ _):_) -> (c, r) _ -> internalError ("adjustRWire0Fields: vfi = " ++ ppReadable vfi) - wget_vfi = Method (unQualId idWGet) clk rst 1 [] Nothing Nothing - wget_fts = ([], Nothing, Nothing) + wget_vfi = Method (unQualId idWGet) clk rst 1 [] [] Nothing + wget_fts = ([], Nothing, []) in (wget_vfi:vfi, wget_fts:fts) -adjustWireFields :: ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) -> - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) +adjustWireFields :: ([VFieldInfo], [([AType], Maybe AType, [AType])]) -> + ([VFieldInfo], [([AType], Maybe AType, [AType])]) adjustWireFields (vfi, fts) = let readId = id_read noPosition writeId = id_write noPosition @@ -3772,8 +3775,8 @@ adjustWireFields (vfi, fts) = in (map renameField vfi, fts) adjustPulseWireFields :: - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) -> - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) + ([VFieldInfo], [([AType], Maybe AType, [AType])]) -> + ([VFieldInfo], [([AType], Maybe AType, [AType])]) adjustPulseWireFields (vfi, fts) = let renameField vf@(Method {vf_name = i }) | (i `qualEq` idWSet) = vf { vf_name = unQualId idSend } @@ -3784,8 +3787,8 @@ adjustPulseWireFields (vfi, fts) = in (map renameField vfi, fts) adjustBypassWireFields :: - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) -> - ([VFieldInfo], [([AType], Maybe AType, Maybe AType)]) + ([VFieldInfo], [([AType], Maybe AType, [AType])]) -> + ([VFieldInfo], [([AType], Maybe AType, [AType])]) adjustBypassWireFields (vfi, fts) = let renameField vf@(Method {vf_name = i }) | (i `qualEq` idWGet) = vf { vf_name = id_read noPosition } @@ -3873,19 +3876,19 @@ getPortsIfc ptmap out_clkinfo out_rstinfo (SubIfc fId fs) = then [] else [PISubIfc fId fs'] getPortsIfc ptmap _ _ - (Field fId (RawMethod i mult mclk mrst args ins mo me) mrdy_inf) = - getPortsIfcMethod ptmap fId i mult mclk mrst args ins mo me mr + (Field fId (RawMethod i mult mclk mrst args ins outs me) mrdy_inf) = + getPortsIfcMethod ptmap fId i mult mclk mrst args ins outs me mr where mr = case (mrdy_inf) of Nothing -> Nothing - (Just (RawMethod ri m _ _ [] [] (Just (vp@(vn,_), t)) Nothing)) + (Just (RawMethod ri m _ _ [] [] [(vp@(vn,_), t)] Nothing)) | ((m == 0) || (m == 1)) -> if (t == aTBool) then Just vp else internalError ("getPortsIfc: Rdy wrong size: " ++ ppReadable (ri,t)) - (Just (RawMethod ri m _ _ as is mout men)) -> + (Just (RawMethod ri m _ _ as is os men)) -> internalError ("getPortsIfc: not Rdy: " ++ - ppReadable (ri, m, as, is, mout, men)) + ppReadable (ri, m, as, is, os, men)) (Just d) -> internalError ("getPortsIfc: not Rdy: " ++ ppReadable (rawIfcFieldName d)) getPortsIfc _ out_clkinfo _ (Field fId (RawClock i) Nothing) = @@ -3902,10 +3905,10 @@ getPortsIfc _ _ _ (Field fId rf (Just rdy_rf)) = getPortsIfcMethod :: M.Map VName IType -> Id -> Id -> Integer -> Maybe Id -> Maybe Id -> - [(Maybe Id, AType)] -> [VPort] -> Maybe (VPort, AType) -> + [(Maybe Id, AType)] -> [VPort] -> [(VPort, AType)] -> Maybe VPort -> Maybe VPort -> [PortIfcInfo] -getPortsIfcMethod ptmap fId methId mult mClk mRst args ins mOut mEn mRdy = +getPortsIfcMethod ptmap fId methId mult mClk mRst args ins outs mEn mRdy = let -- get the port-type pair for an argument getPortsArg (mi, bit_type) (vn, _) = @@ -3913,8 +3916,7 @@ getPortsIfcMethod ptmap fId methId mult mClk mRst args ins mOut mEn mRdy = then [] else [(mi, bit_type, getVNameType ptmap vn)] -- get the port-type pair for the output - getPortsOut Nothing = Nothing - getPortsOut (Just ((vn, _), bit_type)) = + getPortsOut ((vn, _), bit_type) = if (isSizeZero bit_type) then Nothing else @@ -3937,7 +3939,7 @@ getPortsIfcMethod ptmap fId methId mult mClk mRst args ins mOut mEn mRdy = -- the default result (multiplicity of 1) def_res = PIMethod fId methId mClk mRst (concat (zipWith getPortsArg args ins)) - (getPortsOut mOut) (getPortsEn mEn) (getPortsRdy mRdy) + (mapMaybe getPortsOut outs) (getPortsEn mEn) (getPortsRdy mRdy) -- the result if multiplicity > 1 mkMulRes n = @@ -3946,7 +3948,7 @@ getPortsIfcMethod ptmap fId methId mult mClk mRst args ins mOut mEn mRdy = in PIMethod (dupId s fId) -- XXX handle mults differently? (dupId s methId) mClk mRst (concat (zipWith getPortsArg args ins')) - (getPortsOut (dupMVPortType s mOut)) + (mapMaybe (getPortsOut . dupMVPortType s) outs) (getPortsEn (dupMVPort s mEn)) (getPortsRdy (dupMVPort s mRdy)) @@ -3955,9 +3957,8 @@ getPortsIfcMethod ptmap fId methId mult mClk mRst args ins mOut mEn mRdy = dupVPort suf (vn, ps) = (dupVName suf vn, ps) dupMVPort :: String -> Maybe VPort -> Maybe VPort dupMVPort suf mvp = mvp >>= Just . dupVPort suf - dupMVPortType :: String -> Maybe (VPort, AType) -> Maybe (VPort, AType) - dupMVPortType suf mvpt = - mvpt >>= (\ (vp, t) -> Just (dupVPort suf vp, t) ) + dupMVPortType :: String -> (VPort, AType) -> (VPort, AType) + dupMVPortType suf (vp, t) = (dupVPort suf vp, t) in if (mult == 1) || (mult == 0) then [def_res] @@ -4020,13 +4021,6 @@ dispMPortWithType s mport = Nothing -> [] Just (p, _) -> [tagStr s p] -dispMPortWithTypes :: String -> Maybe (String, AType, IType) -> [HTclObj] -dispMPortWithTypes s mport = - case mport of - Nothing -> [] - Just (p, _, _) -> -- XXX we have the opportunity to display the size - [tagStr s p] - -- display AType dispSize :: AType -> [HTclObj] dispSize (ATBit sz) = [tagInt "size" (fromInteger sz)] @@ -4076,16 +4070,23 @@ dispMethodArgs as = dispSize bit_type in TLst (map dispArg as) +dispMethodResults :: [(String, AType, IType)] -> HTclObj +dispMethodResults outs = + let dispOut (port, bit_type, _) = + TLst $ [tagStr "port" port] ++ + dispSize bit_type + in TLst (map dispOut outs) + dispIfc :: PortIfcInfo -> HTclObj -dispIfc (PIMethod fId i mClk mRst ins mOut mEn mRdy) = +dispIfc (PIMethod fId i mClk mRst ins outs mEn mRdy) = TLst $ [TStr "method", TStr (getIdBaseString fId), TStr (pfpString i), dispClockedBy mClk, dispResetBy mRst, - tag "args" [dispMethodArgs ins]] ++ - dispMPortWithTypes "result" mOut ++ + tag "args" [dispMethodArgs ins], + tag "results" [dispMethodResults outs]] ++ dispMPortWithType "enable" mEn ++ dispMPortWithType "ready" mRdy dispIfc (PIClock fId i Nothing) = @@ -4115,6 +4116,9 @@ dispIfc (PISubIfc fId fs) = dispPortType :: (String, IType) -> HTclObj dispPortType (p,t) = TLst [TStr p, TStr (pfpString t)] +dispPortTypes :: (String, AType, IType) -> HTclObj +dispPortTypes (p,at,t) = dispPortType (p,t) + dispMPortType :: Maybe (String, IType) -> [HTclObj] dispMPortType Nothing = [] dispMPortType (Just pt) = [dispPortType pt] @@ -4135,9 +4139,10 @@ dispPortsModArg (PAInout _ _ pt _ _) = [dispPortType pt] dispPortsIfc :: PortIfcInfo -> [HTclObj] -dispPortsIfc (PIMethod _ _ _ _ ins mOut mEn mRdy) = +dispPortsIfc (PIMethod _ _ _ _ ins outs mEn mRdy) = (map (dispPortType . thd) ins) ++ - dispMPortTypes mOut ++ dispMPortType mEn ++ dispMPortType mRdy + (map dispPortTypes outs) ++ + dispMPortType mEn ++ dispMPortType mRdy dispPortsIfc (PIClock _ _ Nothing) = [] dispPortsIfc (PIClock _ _ (Just (osc, mgate))) = [dispPortType osc] ++ dispMPortType mgate @@ -4208,7 +4213,7 @@ get_method_to_signal_map vmod = do case f of Method {} -> return () _ -> mzero -- failure, as in the guard function - port <- (vf_inputs f) ++ (maybeToList $ vf_output f) ++ (maybeToList $ vf_enable f) + port <- (vf_inputs f) ++ (vf_outputs f) ++ (maybeToList $ vf_enable f) count <- case (vf_mult f) of 1 -> return Nothing k -> map Just [1..k] diff --git a/src/comp/showrules.hs b/src/comp/showrules.hs index fbb92ebb7..531d94410 100644 --- a/src/comp/showrules.hs +++ b/src/comp/showrules.hs @@ -455,7 +455,7 @@ mkMorphState opts instmap hiermap abmis_by_name top_mod = let methmap = M.fromList [ ((inst,name),rules) | (inst,abmi) <- user_modules , aif <- apkg_interface (abmi_apkg abmi) - , let name = aIfaceName aif + , let name = aif_name aif , let rules = aIfaceRules aif , not (null rules) ] diff --git a/testsuite/bsc.bluetcl/commands/module.tcl.bluetcl-bh-out.expected b/testsuite/bsc.bluetcl/commands/module.tcl.bluetcl-bh-out.expected index b572a8ea5..784ac49b5 100644 --- a/testsuite/bsc.bluetcl/commands/module.tcl.bluetcl-bh-out.expected +++ b/testsuite/bsc.bluetcl/commands/module.tcl.bluetcl-bh-out.expected @@ -115,19 +115,19 @@ ios1_1 {Prelude.Inout Test.Bar} ---------- module ports mkT Command: module ports mkT -interface {{interface r {{method _write r__write {clock default_clock} {reset no_reset} {args {{{name r__write_1} {port r__write_1} {size 1}}}} {enable EN_r__write} {ready RDY_r__write}} {method _read r__read {clock no_clock} {reset no_reset} {args {}} {result r__read} {ready RDY_r__read}}}} {inout b b {port b} {clock default_clock} {reset default_reset}}} +interface {{interface r {{method _write r__write {clock default_clock} {reset no_reset} {args {{{name r__write_1} {port r__write_1} {size 1}}}} {results {}} {enable EN_r__write} {ready RDY_r__write}} {method _read r__read {clock no_clock} {reset no_reset} {args {}} {results {{{port r__read} {size 1}}}} {ready RDY_r__read}}}} {inout b b {port b} {clock default_clock} {reset default_reset}}} args {{inout i {port i} {clock default_clock} {reset default_reset} {size 2}} {clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}} --------- module ports mkM Command: module ports mkM -interface {{method _write _write {clock default_clock} {reset default_reset} {args {{{name _write_1} {port _write_1} {size 1}}}} {enable EN__write} {ready RDY__write}} {method _read _read {clock default_clock} {reset default_reset} {args {}} {result _read} {ready RDY__read}}} +interface {{method _write _write {clock default_clock} {reset default_reset} {args {{{name _write_1} {port _write_1} {size 1}}}} {results {}} {enable EN__write} {ready RDY__write}} {method _read _read {clock default_clock} {reset default_reset} {args {}} {results {{{port _read} {size 1}}}} {ready RDY__read}}} args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}} --------- module ports mkIfcWithVec Command: module ports mkIfcWithVec -interface {{interface vec1 {{interface 0 {{method _write vec1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec1_0__write_1} {port vec1_0__write_1} {size 1}}}} {enable EN_vec1_0__write} {ready RDY_vec1_0__write}} {method _read vec1_0__read {clock no_clock} {reset no_reset} {args {}} {result vec1_0__read} {ready RDY_vec1_0__read}}}} {interface 1 {{method _write vec1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec1_1__write_1} {port vec1_1__write_1} {size 1}}}} {enable EN_vec1_1__write} {ready RDY_vec1_1__write}} {method _read vec1_1__read {clock no_clock} {reset no_reset} {args {}} {result vec1_1__read} {ready RDY_vec1_1__read}}}}}} {interface vec2 {{interface 0 {{interface 0 {{method _write vec2_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec2_0_0__write_1} {port vec2_0_0__write_1} {size 1}}}} {enable EN_vec2_0_0__write} {ready RDY_vec2_0_0__write}} {method _read vec2_0_0__read {clock no_clock} {reset no_reset} {args {}} {result vec2_0_0__read} {ready RDY_vec2_0_0__read}}}} {interface 1 {{method _write vec2_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec2_0_1__write_1} {port vec2_0_1__write_1} {size 1}}}} {enable EN_vec2_0_1__write} {ready RDY_vec2_0_1__write}} {method _read vec2_0_1__read {clock no_clock} {reset no_reset} {args {}} {result vec2_0_1__read} {ready RDY_vec2_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec2_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec2_1_0__write_1} {port vec2_1_0__write_1} {size 1}}}} {enable EN_vec2_1_0__write} {ready RDY_vec2_1_0__write}} {method _read vec2_1_0__read {clock no_clock} {reset no_reset} {args {}} {result vec2_1_0__read} {ready RDY_vec2_1_0__read}}}} {interface 1 {{method _write vec2_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec2_1_1__write_1} {port vec2_1_1__write_1} {size 1}}}} {enable EN_vec2_1_1__write} {ready RDY_vec2_1_1__write}} {method _read vec2_1_1__read {clock no_clock} {reset no_reset} {args {}} {result vec2_1_1__read} {ready RDY_vec2_1_1__read}}}}}}}} {interface vec3 {{interface 0 {{interface 0 {{interface 0 {{method _write vec3_0_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_0_0__write_1} {port vec3_0_0_0__write_1} {size 1}}}} {enable EN_vec3_0_0_0__write} {ready RDY_vec3_0_0_0__write}} {method _read vec3_0_0_0__read {clock no_clock} {reset no_reset} {args {}} {result vec3_0_0_0__read} {ready RDY_vec3_0_0_0__read}}}} {interface 1 {{method _write vec3_0_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_0_1__write_1} {port vec3_0_0_1__write_1} {size 1}}}} {enable EN_vec3_0_0_1__write} {ready RDY_vec3_0_0_1__write}} {method _read vec3_0_0_1__read {clock no_clock} {reset no_reset} {args {}} {result vec3_0_0_1__read} {ready RDY_vec3_0_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec3_0_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_1_0__write_1} {port vec3_0_1_0__write_1} {size 1}}}} {enable EN_vec3_0_1_0__write} {ready RDY_vec3_0_1_0__write}} {method _read vec3_0_1_0__read {clock no_clock} {reset no_reset} {args {}} {result vec3_0_1_0__read} {ready RDY_vec3_0_1_0__read}}}} {interface 1 {{method _write vec3_0_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_1_1__write_1} {port vec3_0_1_1__write_1} {size 1}}}} {enable EN_vec3_0_1_1__write} {ready RDY_vec3_0_1_1__write}} {method _read vec3_0_1_1__read {clock no_clock} {reset no_reset} {args {}} {result vec3_0_1_1__read} {ready RDY_vec3_0_1_1__read}}}}}}}} {interface 1 {{interface 0 {{interface 0 {{method _write vec3_1_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_0_0__write_1} {port vec3_1_0_0__write_1} {size 1}}}} {enable EN_vec3_1_0_0__write} {ready RDY_vec3_1_0_0__write}} {method _read vec3_1_0_0__read {clock no_clock} {reset no_reset} {args {}} {result vec3_1_0_0__read} {ready RDY_vec3_1_0_0__read}}}} {interface 1 {{method _write vec3_1_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_0_1__write_1} {port vec3_1_0_1__write_1} {size 1}}}} {enable EN_vec3_1_0_1__write} {ready RDY_vec3_1_0_1__write}} {method _read vec3_1_0_1__read {clock no_clock} {reset no_reset} {args {}} {result vec3_1_0_1__read} {ready RDY_vec3_1_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec3_1_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_1_0__write_1} {port vec3_1_1_0__write_1} {size 1}}}} {enable EN_vec3_1_1_0__write} {ready RDY_vec3_1_1_0__write}} {method _read vec3_1_1_0__read {clock no_clock} {reset no_reset} {args {}} {result vec3_1_1_0__read} {ready RDY_vec3_1_1_0__read}}}} {interface 1 {{method _write vec3_1_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_1_1__write_1} {port vec3_1_1_1__write_1} {size 1}}}} {enable EN_vec3_1_1_1__write} {ready RDY_vec3_1_1_1__write}} {method _read vec3_1_1_1__read {clock no_clock} {reset no_reset} {args {}} {result vec3_1_1_1__read} {ready RDY_vec3_1_1_1__read}}}}}}}}}} {method data1 data1 {clock no_clock} {reset no_reset} {args {}} {result data1} {ready RDY_data1}} {method data2 data2 {clock no_clock} {reset no_reset} {args {}} {result data2} {ready RDY_data2}} {method data3 data3 {clock no_clock} {reset no_reset} {args {}} {result data3} {ready RDY_data3}} {interface clks1 {{interface 0 {{clock {} clks1_0 {osc CLK_clks1_0} {gate CLK_GATE_clks1_0}}}} {interface 1 {{clock {} clks1_1 {osc CLK_clks1_1} {gate CLK_GATE_clks1_1}}}}}} {interface rsts1 {{interface 0 {{reset {} rsts1_0 {port RST_N_rsts1_0} {clock default_clock}}}} {interface 1 {{reset {} rsts1_1 {port RST_N_rsts1_1} {clock default_clock}}}}}} {interface ios1 {{interface 0 {{inout {} ios1_0 {port ios1_0} {clock clks1_1} {reset rsts1_1}}}} {interface 1 {{inout {} ios1_1 {port ios1_1} {clock clks1_1} {reset rsts1_1}}}}}}} +interface {{interface vec1 {{interface 0 {{method _write vec1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec1_0__write_1} {port vec1_0__write_1} {size 1}}}} {results {}} {enable EN_vec1_0__write} {ready RDY_vec1_0__write}} {method _read vec1_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec1_0__read} {size 1}}}} {ready RDY_vec1_0__read}}}} {interface 1 {{method _write vec1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec1_1__write_1} {port vec1_1__write_1} {size 1}}}} {results {}} {enable EN_vec1_1__write} {ready RDY_vec1_1__write}} {method _read vec1_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec1_1__read} {size 1}}}} {ready RDY_vec1_1__read}}}}}} {interface vec2 {{interface 0 {{interface 0 {{method _write vec2_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec2_0_0__write_1} {port vec2_0_0__write_1} {size 1}}}} {results {}} {enable EN_vec2_0_0__write} {ready RDY_vec2_0_0__write}} {method _read vec2_0_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec2_0_0__read} {size 1}}}} {ready RDY_vec2_0_0__read}}}} {interface 1 {{method _write vec2_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec2_0_1__write_1} {port vec2_0_1__write_1} {size 1}}}} {results {}} {enable EN_vec2_0_1__write} {ready RDY_vec2_0_1__write}} {method _read vec2_0_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec2_0_1__read} {size 1}}}} {ready RDY_vec2_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec2_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec2_1_0__write_1} {port vec2_1_0__write_1} {size 1}}}} {results {}} {enable EN_vec2_1_0__write} {ready RDY_vec2_1_0__write}} {method _read vec2_1_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec2_1_0__read} {size 1}}}} {ready RDY_vec2_1_0__read}}}} {interface 1 {{method _write vec2_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec2_1_1__write_1} {port vec2_1_1__write_1} {size 1}}}} {results {}} {enable EN_vec2_1_1__write} {ready RDY_vec2_1_1__write}} {method _read vec2_1_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec2_1_1__read} {size 1}}}} {ready RDY_vec2_1_1__read}}}}}}}} {interface vec3 {{interface 0 {{interface 0 {{interface 0 {{method _write vec3_0_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_0_0__write_1} {port vec3_0_0_0__write_1} {size 1}}}} {results {}} {enable EN_vec3_0_0_0__write} {ready RDY_vec3_0_0_0__write}} {method _read vec3_0_0_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_0_0_0__read} {size 1}}}} {ready RDY_vec3_0_0_0__read}}}} {interface 1 {{method _write vec3_0_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_0_1__write_1} {port vec3_0_0_1__write_1} {size 1}}}} {results {}} {enable EN_vec3_0_0_1__write} {ready RDY_vec3_0_0_1__write}} {method _read vec3_0_0_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_0_0_1__read} {size 1}}}} {ready RDY_vec3_0_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec3_0_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_1_0__write_1} {port vec3_0_1_0__write_1} {size 1}}}} {results {}} {enable EN_vec3_0_1_0__write} {ready RDY_vec3_0_1_0__write}} {method _read vec3_0_1_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_0_1_0__read} {size 1}}}} {ready RDY_vec3_0_1_0__read}}}} {interface 1 {{method _write vec3_0_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_1_1__write_1} {port vec3_0_1_1__write_1} {size 1}}}} {results {}} {enable EN_vec3_0_1_1__write} {ready RDY_vec3_0_1_1__write}} {method _read vec3_0_1_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_0_1_1__read} {size 1}}}} {ready RDY_vec3_0_1_1__read}}}}}}}} {interface 1 {{interface 0 {{interface 0 {{method _write vec3_1_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_0_0__write_1} {port vec3_1_0_0__write_1} {size 1}}}} {results {}} {enable EN_vec3_1_0_0__write} {ready RDY_vec3_1_0_0__write}} {method _read vec3_1_0_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_1_0_0__read} {size 1}}}} {ready RDY_vec3_1_0_0__read}}}} {interface 1 {{method _write vec3_1_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_0_1__write_1} {port vec3_1_0_1__write_1} {size 1}}}} {results {}} {enable EN_vec3_1_0_1__write} {ready RDY_vec3_1_0_1__write}} {method _read vec3_1_0_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_1_0_1__read} {size 1}}}} {ready RDY_vec3_1_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec3_1_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_1_0__write_1} {port vec3_1_1_0__write_1} {size 1}}}} {results {}} {enable EN_vec3_1_1_0__write} {ready RDY_vec3_1_1_0__write}} {method _read vec3_1_1_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_1_1_0__read} {size 1}}}} {ready RDY_vec3_1_1_0__read}}}} {interface 1 {{method _write vec3_1_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_1_1__write_1} {port vec3_1_1_1__write_1} {size 1}}}} {results {}} {enable EN_vec3_1_1_1__write} {ready RDY_vec3_1_1_1__write}} {method _read vec3_1_1_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_1_1_1__read} {size 1}}}} {ready RDY_vec3_1_1_1__read}}}}}}}}}} {method data1 data1 {clock no_clock} {reset no_reset} {args {}} {results {{{port data1} {size 2}}}} {ready RDY_data1}} {method data2 data2 {clock no_clock} {reset no_reset} {args {}} {results {{{port data2} {size 4}}}} {ready RDY_data2}} {method data3 data3 {clock no_clock} {reset no_reset} {args {}} {results {{{port data3} {size 8}}}} {ready RDY_data3}} {interface clks1 {{interface 0 {{clock {} clks1_0 {osc CLK_clks1_0} {gate CLK_GATE_clks1_0}}}} {interface 1 {{clock {} clks1_1 {osc CLK_clks1_1} {gate CLK_GATE_clks1_1}}}}}} {interface rsts1 {{interface 0 {{reset {} rsts1_0 {port RST_N_rsts1_0} {clock default_clock}}}} {interface 1 {{reset {} rsts1_1 {port RST_N_rsts1_1} {clock default_clock}}}}}} {interface ios1 {{interface 0 {{inout {} ios1_0 {port ios1_0} {clock clks1_1} {reset rsts1_1}}}} {interface 1 {{inout {} ios1_1 {port ios1_1} {clock clks1_1} {reset rsts1_1}}}}}}} args {{inout io {port io} {clock default_clock} {reset default_reset} {size 2}} {clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}} --------- ---------- diff --git a/testsuite/bsc.bluetcl/commands/module.tcl.bluetcl-out.expected b/testsuite/bsc.bluetcl/commands/module.tcl.bluetcl-out.expected index d02606a21..32af9b611 100644 --- a/testsuite/bsc.bluetcl/commands/module.tcl.bluetcl-out.expected +++ b/testsuite/bsc.bluetcl/commands/module.tcl.bluetcl-out.expected @@ -115,19 +115,19 @@ ios1_1 Inout#(Test::Bar) ---------- module ports mkT Command: module ports mkT -interface {{interface r {{method _write r__write {clock default_clock} {reset no_reset} {args {{{name r__write_1} {port r__write_1} {size 1}}}} {enable EN_r__write} {ready RDY_r__write}} {method _read r__read {clock no_clock} {reset no_reset} {args {}} {result r__read} {ready RDY_r__read}}}} {inout b b {port b} {clock default_clock} {reset default_reset}}} +interface {{interface r {{method _write r__write {clock default_clock} {reset no_reset} {args {{{name r__write_1} {port r__write_1} {size 1}}}} {results {}} {enable EN_r__write} {ready RDY_r__write}} {method _read r__read {clock no_clock} {reset no_reset} {args {}} {results {{{port r__read} {size 1}}}} {ready RDY_r__read}}}} {inout b b {port b} {clock default_clock} {reset default_reset}}} args {{inout i {port i} {clock default_clock} {reset default_reset} {size 2}} {clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}} --------- module ports mkM Command: module ports mkM -interface {{method _write _write {clock default_clock} {reset default_reset} {args {{{name _write_1} {port _write_1} {size 1}}}} {enable EN__write} {ready RDY__write}} {method _read _read {clock default_clock} {reset default_reset} {args {}} {result _read} {ready RDY__read}}} +interface {{method _write _write {clock default_clock} {reset default_reset} {args {{{name _write_1} {port _write_1} {size 1}}}} {results {}} {enable EN__write} {ready RDY__write}} {method _read _read {clock default_clock} {reset default_reset} {args {}} {results {{{port _read} {size 1}}}} {ready RDY__read}}} args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}} --------- module ports mkIfcWithVec Command: module ports mkIfcWithVec -interface {{interface vec1 {{interface 0 {{method _write vec1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec1_0__write_1} {port vec1_0__write_1} {size 1}}}} {enable EN_vec1_0__write} {ready RDY_vec1_0__write}} {method _read vec1_0__read {clock no_clock} {reset no_reset} {args {}} {result vec1_0__read} {ready RDY_vec1_0__read}}}} {interface 1 {{method _write vec1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec1_1__write_1} {port vec1_1__write_1} {size 1}}}} {enable EN_vec1_1__write} {ready RDY_vec1_1__write}} {method _read vec1_1__read {clock no_clock} {reset no_reset} {args {}} {result vec1_1__read} {ready RDY_vec1_1__read}}}}}} {interface vec2 {{interface 0 {{interface 0 {{method _write vec2_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec2_0_0__write_1} {port vec2_0_0__write_1} {size 1}}}} {enable EN_vec2_0_0__write} {ready RDY_vec2_0_0__write}} {method _read vec2_0_0__read {clock no_clock} {reset no_reset} {args {}} {result vec2_0_0__read} {ready RDY_vec2_0_0__read}}}} {interface 1 {{method _write vec2_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec2_0_1__write_1} {port vec2_0_1__write_1} {size 1}}}} {enable EN_vec2_0_1__write} {ready RDY_vec2_0_1__write}} {method _read vec2_0_1__read {clock no_clock} {reset no_reset} {args {}} {result vec2_0_1__read} {ready RDY_vec2_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec2_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec2_1_0__write_1} {port vec2_1_0__write_1} {size 1}}}} {enable EN_vec2_1_0__write} {ready RDY_vec2_1_0__write}} {method _read vec2_1_0__read {clock no_clock} {reset no_reset} {args {}} {result vec2_1_0__read} {ready RDY_vec2_1_0__read}}}} {interface 1 {{method _write vec2_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec2_1_1__write_1} {port vec2_1_1__write_1} {size 1}}}} {enable EN_vec2_1_1__write} {ready RDY_vec2_1_1__write}} {method _read vec2_1_1__read {clock no_clock} {reset no_reset} {args {}} {result vec2_1_1__read} {ready RDY_vec2_1_1__read}}}}}}}} {interface vec3 {{interface 0 {{interface 0 {{interface 0 {{method _write vec3_0_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_0_0__write_1} {port vec3_0_0_0__write_1} {size 1}}}} {enable EN_vec3_0_0_0__write} {ready RDY_vec3_0_0_0__write}} {method _read vec3_0_0_0__read {clock no_clock} {reset no_reset} {args {}} {result vec3_0_0_0__read} {ready RDY_vec3_0_0_0__read}}}} {interface 1 {{method _write vec3_0_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_0_1__write_1} {port vec3_0_0_1__write_1} {size 1}}}} {enable EN_vec3_0_0_1__write} {ready RDY_vec3_0_0_1__write}} {method _read vec3_0_0_1__read {clock no_clock} {reset no_reset} {args {}} {result vec3_0_0_1__read} {ready RDY_vec3_0_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec3_0_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_1_0__write_1} {port vec3_0_1_0__write_1} {size 1}}}} {enable EN_vec3_0_1_0__write} {ready RDY_vec3_0_1_0__write}} {method _read vec3_0_1_0__read {clock no_clock} {reset no_reset} {args {}} {result vec3_0_1_0__read} {ready RDY_vec3_0_1_0__read}}}} {interface 1 {{method _write vec3_0_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_1_1__write_1} {port vec3_0_1_1__write_1} {size 1}}}} {enable EN_vec3_0_1_1__write} {ready RDY_vec3_0_1_1__write}} {method _read vec3_0_1_1__read {clock no_clock} {reset no_reset} {args {}} {result vec3_0_1_1__read} {ready RDY_vec3_0_1_1__read}}}}}}}} {interface 1 {{interface 0 {{interface 0 {{method _write vec3_1_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_0_0__write_1} {port vec3_1_0_0__write_1} {size 1}}}} {enable EN_vec3_1_0_0__write} {ready RDY_vec3_1_0_0__write}} {method _read vec3_1_0_0__read {clock no_clock} {reset no_reset} {args {}} {result vec3_1_0_0__read} {ready RDY_vec3_1_0_0__read}}}} {interface 1 {{method _write vec3_1_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_0_1__write_1} {port vec3_1_0_1__write_1} {size 1}}}} {enable EN_vec3_1_0_1__write} {ready RDY_vec3_1_0_1__write}} {method _read vec3_1_0_1__read {clock no_clock} {reset no_reset} {args {}} {result vec3_1_0_1__read} {ready RDY_vec3_1_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec3_1_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_1_0__write_1} {port vec3_1_1_0__write_1} {size 1}}}} {enable EN_vec3_1_1_0__write} {ready RDY_vec3_1_1_0__write}} {method _read vec3_1_1_0__read {clock no_clock} {reset no_reset} {args {}} {result vec3_1_1_0__read} {ready RDY_vec3_1_1_0__read}}}} {interface 1 {{method _write vec3_1_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_1_1__write_1} {port vec3_1_1_1__write_1} {size 1}}}} {enable EN_vec3_1_1_1__write} {ready RDY_vec3_1_1_1__write}} {method _read vec3_1_1_1__read {clock no_clock} {reset no_reset} {args {}} {result vec3_1_1_1__read} {ready RDY_vec3_1_1_1__read}}}}}}}}}} {method data1 data1 {clock no_clock} {reset no_reset} {args {}} {result data1} {ready RDY_data1}} {method data2 data2 {clock no_clock} {reset no_reset} {args {}} {result data2} {ready RDY_data2}} {method data3 data3 {clock no_clock} {reset no_reset} {args {}} {result data3} {ready RDY_data3}} {interface clks1 {{interface 0 {{clock {} clks1_0 {osc CLK_clks1_0} {gate CLK_GATE_clks1_0}}}} {interface 1 {{clock {} clks1_1 {osc CLK_clks1_1} {gate CLK_GATE_clks1_1}}}}}} {interface rsts1 {{interface 0 {{reset {} rsts1_0 {port RST_N_rsts1_0} {clock default_clock}}}} {interface 1 {{reset {} rsts1_1 {port RST_N_rsts1_1} {clock default_clock}}}}}} {interface ios1 {{interface 0 {{inout {} ios1_0 {port ios1_0} {clock clks1_1} {reset rsts1_1}}}} {interface 1 {{inout {} ios1_1 {port ios1_1} {clock clks1_1} {reset rsts1_1}}}}}}} +interface {{interface vec1 {{interface 0 {{method _write vec1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec1_0__write_1} {port vec1_0__write_1} {size 1}}}} {results {}} {enable EN_vec1_0__write} {ready RDY_vec1_0__write}} {method _read vec1_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec1_0__read} {size 1}}}} {ready RDY_vec1_0__read}}}} {interface 1 {{method _write vec1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec1_1__write_1} {port vec1_1__write_1} {size 1}}}} {results {}} {enable EN_vec1_1__write} {ready RDY_vec1_1__write}} {method _read vec1_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec1_1__read} {size 1}}}} {ready RDY_vec1_1__read}}}}}} {interface vec2 {{interface 0 {{interface 0 {{method _write vec2_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec2_0_0__write_1} {port vec2_0_0__write_1} {size 1}}}} {results {}} {enable EN_vec2_0_0__write} {ready RDY_vec2_0_0__write}} {method _read vec2_0_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec2_0_0__read} {size 1}}}} {ready RDY_vec2_0_0__read}}}} {interface 1 {{method _write vec2_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec2_0_1__write_1} {port vec2_0_1__write_1} {size 1}}}} {results {}} {enable EN_vec2_0_1__write} {ready RDY_vec2_0_1__write}} {method _read vec2_0_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec2_0_1__read} {size 1}}}} {ready RDY_vec2_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec2_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec2_1_0__write_1} {port vec2_1_0__write_1} {size 1}}}} {results {}} {enable EN_vec2_1_0__write} {ready RDY_vec2_1_0__write}} {method _read vec2_1_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec2_1_0__read} {size 1}}}} {ready RDY_vec2_1_0__read}}}} {interface 1 {{method _write vec2_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec2_1_1__write_1} {port vec2_1_1__write_1} {size 1}}}} {results {}} {enable EN_vec2_1_1__write} {ready RDY_vec2_1_1__write}} {method _read vec2_1_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec2_1_1__read} {size 1}}}} {ready RDY_vec2_1_1__read}}}}}}}} {interface vec3 {{interface 0 {{interface 0 {{interface 0 {{method _write vec3_0_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_0_0__write_1} {port vec3_0_0_0__write_1} {size 1}}}} {results {}} {enable EN_vec3_0_0_0__write} {ready RDY_vec3_0_0_0__write}} {method _read vec3_0_0_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_0_0_0__read} {size 1}}}} {ready RDY_vec3_0_0_0__read}}}} {interface 1 {{method _write vec3_0_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_0_1__write_1} {port vec3_0_0_1__write_1} {size 1}}}} {results {}} {enable EN_vec3_0_0_1__write} {ready RDY_vec3_0_0_1__write}} {method _read vec3_0_0_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_0_0_1__read} {size 1}}}} {ready RDY_vec3_0_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec3_0_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_1_0__write_1} {port vec3_0_1_0__write_1} {size 1}}}} {results {}} {enable EN_vec3_0_1_0__write} {ready RDY_vec3_0_1_0__write}} {method _read vec3_0_1_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_0_1_0__read} {size 1}}}} {ready RDY_vec3_0_1_0__read}}}} {interface 1 {{method _write vec3_0_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_0_1_1__write_1} {port vec3_0_1_1__write_1} {size 1}}}} {results {}} {enable EN_vec3_0_1_1__write} {ready RDY_vec3_0_1_1__write}} {method _read vec3_0_1_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_0_1_1__read} {size 1}}}} {ready RDY_vec3_0_1_1__read}}}}}}}} {interface 1 {{interface 0 {{interface 0 {{method _write vec3_1_0_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_0_0__write_1} {port vec3_1_0_0__write_1} {size 1}}}} {results {}} {enable EN_vec3_1_0_0__write} {ready RDY_vec3_1_0_0__write}} {method _read vec3_1_0_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_1_0_0__read} {size 1}}}} {ready RDY_vec3_1_0_0__read}}}} {interface 1 {{method _write vec3_1_0_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_0_1__write_1} {port vec3_1_0_1__write_1} {size 1}}}} {results {}} {enable EN_vec3_1_0_1__write} {ready RDY_vec3_1_0_1__write}} {method _read vec3_1_0_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_1_0_1__read} {size 1}}}} {ready RDY_vec3_1_0_1__read}}}}}} {interface 1 {{interface 0 {{method _write vec3_1_1_0__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_1_0__write_1} {port vec3_1_1_0__write_1} {size 1}}}} {results {}} {enable EN_vec3_1_1_0__write} {ready RDY_vec3_1_1_0__write}} {method _read vec3_1_1_0__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_1_1_0__read} {size 1}}}} {ready RDY_vec3_1_1_0__read}}}} {interface 1 {{method _write vec3_1_1_1__write {clock clks1_1} {reset no_reset} {args {{{name vec3_1_1_1__write_1} {port vec3_1_1_1__write_1} {size 1}}}} {results {}} {enable EN_vec3_1_1_1__write} {ready RDY_vec3_1_1_1__write}} {method _read vec3_1_1_1__read {clock no_clock} {reset no_reset} {args {}} {results {{{port vec3_1_1_1__read} {size 1}}}} {ready RDY_vec3_1_1_1__read}}}}}}}}}} {method data1 data1 {clock no_clock} {reset no_reset} {args {}} {results {{{port data1} {size 2}}}} {ready RDY_data1}} {method data2 data2 {clock no_clock} {reset no_reset} {args {}} {results {{{port data2} {size 4}}}} {ready RDY_data2}} {method data3 data3 {clock no_clock} {reset no_reset} {args {}} {results {{{port data3} {size 8}}}} {ready RDY_data3}} {interface clks1 {{interface 0 {{clock {} clks1_0 {osc CLK_clks1_0} {gate CLK_GATE_clks1_0}}}} {interface 1 {{clock {} clks1_1 {osc CLK_clks1_1} {gate CLK_GATE_clks1_1}}}}}} {interface rsts1 {{interface 0 {{reset {} rsts1_0 {port RST_N_rsts1_0} {clock default_clock}}}} {interface 1 {{reset {} rsts1_1 {port RST_N_rsts1_1} {clock default_clock}}}}}} {interface ios1 {{interface 0 {{inout {} ios1_0 {port ios1_0} {clock clks1_1} {reset rsts1_1}}}} {interface 1 {{inout {} ios1_1 {port ios1_1} {clock clks1_1} {reset rsts1_1}}}}}}} args {{inout io {port io} {clock default_clock} {reset default_reset} {size 2}} {clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}} --------- ---------- diff --git a/testsuite/bsc.bluetcl/commands/submodule.tcl.bluetcl-bh-out.expected b/testsuite/bsc.bluetcl/commands/submodule.tcl.bluetcl-bh-out.expected index 6f89b6109..fb719aa49 100644 --- a/testsuite/bsc.bluetcl/commands/submodule.tcl.bluetcl-bh-out.expected +++ b/testsuite/bsc.bluetcl/commands/submodule.tcl.bluetcl-bh-out.expected @@ -11,6 +11,7 @@ Command: submodule ports mkT clock default_clock reset default_reset args {{{port _write_1} {size 1}}} + results {} enable EN__write ready RDY__write method @@ -19,7 +20,7 @@ Command: submodule ports mkT clock default_clock reset default_reset args {} - result _read + results {{{port _read} {size 1}}} ready RDY__read args clock default_clock {osc CLK} @@ -36,6 +37,7 @@ Command: submodule ports mkT clock default_clock reset default_reset args {{{port _write_1} {size 1}}} + results {} enable EN__write ready RDY__write method @@ -44,7 +46,7 @@ Command: submodule ports mkT clock default_clock reset default_reset args {} - result _read + results {{{port _read} {size 1}}} ready RDY__read args clock default_clock {osc CLK} @@ -77,6 +79,7 @@ Command: submodule ports mkT clock clk reset rst args {{{port WVAL} {size 4}}} + results {} enable WSET method wget @@ -84,14 +87,14 @@ Command: submodule ports mkT clock clk reset rst args {} - result WGET + results {{{port WGET} {size 4}}} method whas whas clock clk reset rst args {} - result WHAS + results {{{port WHAS} {size 1}}} inout io_out io_out @@ -122,6 +125,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec1_0__write_1} {size 1}}} + results {} enable EN_vec1_0__write ready RDY_vec1_0__write method @@ -130,7 +134,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec1_0__read + results {{{port vec1_0__read} {size 1}}} ready RDY_vec1_0__read interface 1 @@ -140,6 +144,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec1_1__write_1} {size 1}}} + results {} enable EN_vec1_1__write ready RDY_vec1_1__write method @@ -148,7 +153,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec1_1__read + results {{{port vec1_1__read} {size 1}}} ready RDY_vec1_1__read interface vec2 @@ -162,6 +167,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec2_0_0__write_1} {size 1}}} + results {} enable EN_vec2_0_0__write ready RDY_vec2_0_0__write method @@ -170,7 +176,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec2_0_0__read + results {{{port vec2_0_0__read} {size 1}}} ready RDY_vec2_0_0__read interface 1 @@ -180,6 +186,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec2_0_1__write_1} {size 1}}} + results {} enable EN_vec2_0_1__write ready RDY_vec2_0_1__write method @@ -188,7 +195,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec2_0_1__read + results {{{port vec2_0_1__read} {size 1}}} ready RDY_vec2_0_1__read interface 1 @@ -200,6 +207,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec2_1_0__write_1} {size 1}}} + results {} enable EN_vec2_1_0__write ready RDY_vec2_1_0__write method @@ -208,7 +216,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec2_1_0__read + results {{{port vec2_1_0__read} {size 1}}} ready RDY_vec2_1_0__read interface 1 @@ -218,6 +226,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec2_1_1__write_1} {size 1}}} + results {} enable EN_vec2_1_1__write ready RDY_vec2_1_1__write method @@ -226,7 +235,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec2_1_1__read + results {{{port vec2_1_1__read} {size 1}}} ready RDY_vec2_1_1__read interface vec3 @@ -242,6 +251,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_0_0_0__write_1} {size 1}}} + results {} enable EN_vec3_0_0_0__write ready RDY_vec3_0_0_0__write method @@ -250,7 +260,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_0_0_0__read + results {{{port vec3_0_0_0__read} {size 1}}} ready RDY_vec3_0_0_0__read interface 1 @@ -260,6 +270,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_0_0_1__write_1} {size 1}}} + results {} enable EN_vec3_0_0_1__write ready RDY_vec3_0_0_1__write method @@ -268,7 +279,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_0_0_1__read + results {{{port vec3_0_0_1__read} {size 1}}} ready RDY_vec3_0_0_1__read interface 1 @@ -280,6 +291,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_0_1_0__write_1} {size 1}}} + results {} enable EN_vec3_0_1_0__write ready RDY_vec3_0_1_0__write method @@ -288,7 +300,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_0_1_0__read + results {{{port vec3_0_1_0__read} {size 1}}} ready RDY_vec3_0_1_0__read interface 1 @@ -298,6 +310,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_0_1_1__write_1} {size 1}}} + results {} enable EN_vec3_0_1_1__write ready RDY_vec3_0_1_1__write method @@ -306,7 +319,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_0_1_1__read + results {{{port vec3_0_1_1__read} {size 1}}} ready RDY_vec3_0_1_1__read interface 1 @@ -320,6 +333,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_1_0_0__write_1} {size 1}}} + results {} enable EN_vec3_1_0_0__write ready RDY_vec3_1_0_0__write method @@ -328,7 +342,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_1_0_0__read + results {{{port vec3_1_0_0__read} {size 1}}} ready RDY_vec3_1_0_0__read interface 1 @@ -338,6 +352,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_1_0_1__write_1} {size 1}}} + results {} enable EN_vec3_1_0_1__write ready RDY_vec3_1_0_1__write method @@ -346,7 +361,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_1_0_1__read + results {{{port vec3_1_0_1__read} {size 1}}} ready RDY_vec3_1_0_1__read interface 1 @@ -358,6 +373,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_1_1_0__write_1} {size 1}}} + results {} enable EN_vec3_1_1_0__write ready RDY_vec3_1_1_0__write method @@ -366,7 +382,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_1_1_0__read + results {{{port vec3_1_1_0__read} {size 1}}} ready RDY_vec3_1_1_0__read interface 1 @@ -376,6 +392,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_1_1_1__write_1} {size 1}}} + results {} enable EN_vec3_1_1_1__write ready RDY_vec3_1_1_1__write method @@ -384,7 +401,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_1_1_1__read + results {{{port vec3_1_1_1__read} {size 1}}} ready RDY_vec3_1_1_1__read method data1 @@ -392,7 +409,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result data1 + results {{{port data1} {size 2}}} ready RDY_data1 method data2 @@ -400,7 +417,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result data2 + results {{{port data2} {size 4}}} ready RDY_data2 method data3 @@ -408,7 +425,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result data3 + results {{{port data3} {size 8}}} ready RDY_data3 interface clks1 @@ -458,6 +475,7 @@ Command: submodule ports mkM clock _clk__1 reset _rst__1 args {{{port D_IN} {size 1}}} + results {} enable EN method _read @@ -465,7 +483,7 @@ Command: submodule ports mkM clock _clk__1 reset _rst__1 args {} - result Q_OUT + results {{{port Q_OUT} {size 1}}} args clock _clk__1 {osc CLK} reset _rst__1 {port RST} {clock _clk__1} @@ -480,6 +498,7 @@ Command: submodule ports mkM clock _clk__1 reset _rst__1 args {{{port D_IN} {size 1}}} + results {} enable EN method _read @@ -487,7 +506,7 @@ Command: submodule ports mkM clock _clk__1 reset _rst__1 args {} - result Q_OUT + results {{{port Q_OUT} {size 1}}} args clock _clk__1 {osc CLK} reset _rst__1 {port RST} {clock _clk__1} @@ -502,6 +521,7 @@ Command: submodule ports mkM clock _clk__1 reset _rst__1 args {{{port D_IN} {size 1}}} + results {} enable EN method _read @@ -509,7 +529,7 @@ Command: submodule ports mkM clock _clk__1 reset _rst__1 args {} - result Q_OUT + results {{{port Q_OUT} {size 1}}} args clock _clk__1 {osc CLK} reset _rst__1 {port RST} {clock _clk__1} diff --git a/testsuite/bsc.bluetcl/commands/submodule.tcl.bluetcl-out.expected b/testsuite/bsc.bluetcl/commands/submodule.tcl.bluetcl-out.expected index aaf292aaf..926e03cde 100644 --- a/testsuite/bsc.bluetcl/commands/submodule.tcl.bluetcl-out.expected +++ b/testsuite/bsc.bluetcl/commands/submodule.tcl.bluetcl-out.expected @@ -11,6 +11,7 @@ Command: submodule ports mkT clock default_clock reset default_reset args {{{port _write_1} {size 1}}} + results {} enable EN__write ready RDY__write method @@ -19,7 +20,7 @@ Command: submodule ports mkT clock default_clock reset default_reset args {} - result _read + results {{{port _read} {size 1}}} ready RDY__read args clock default_clock {osc CLK} @@ -36,6 +37,7 @@ Command: submodule ports mkT clock default_clock reset default_reset args {{{port _write_1} {size 1}}} + results {} enable EN__write ready RDY__write method @@ -44,7 +46,7 @@ Command: submodule ports mkT clock default_clock reset default_reset args {} - result _read + results {{{port _read} {size 1}}} ready RDY__read args clock default_clock {osc CLK} @@ -77,6 +79,7 @@ Command: submodule ports mkT clock clk reset rst args {{{port WVAL} {size 4}}} + results {} enable WSET method wget @@ -84,14 +87,14 @@ Command: submodule ports mkT clock clk reset rst args {} - result WGET + results {{{port WGET} {size 4}}} method whas whas clock clk reset rst args {} - result WHAS + results {{{port WHAS} {size 1}}} inout io_out io_out @@ -122,6 +125,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec1_0__write_1} {size 1}}} + results {} enable EN_vec1_0__write ready RDY_vec1_0__write method @@ -130,7 +134,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec1_0__read + results {{{port vec1_0__read} {size 1}}} ready RDY_vec1_0__read interface 1 @@ -140,6 +144,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec1_1__write_1} {size 1}}} + results {} enable EN_vec1_1__write ready RDY_vec1_1__write method @@ -148,7 +153,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec1_1__read + results {{{port vec1_1__read} {size 1}}} ready RDY_vec1_1__read interface vec2 @@ -162,6 +167,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec2_0_0__write_1} {size 1}}} + results {} enable EN_vec2_0_0__write ready RDY_vec2_0_0__write method @@ -170,7 +176,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec2_0_0__read + results {{{port vec2_0_0__read} {size 1}}} ready RDY_vec2_0_0__read interface 1 @@ -180,6 +186,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec2_0_1__write_1} {size 1}}} + results {} enable EN_vec2_0_1__write ready RDY_vec2_0_1__write method @@ -188,7 +195,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec2_0_1__read + results {{{port vec2_0_1__read} {size 1}}} ready RDY_vec2_0_1__read interface 1 @@ -200,6 +207,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec2_1_0__write_1} {size 1}}} + results {} enable EN_vec2_1_0__write ready RDY_vec2_1_0__write method @@ -208,7 +216,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec2_1_0__read + results {{{port vec2_1_0__read} {size 1}}} ready RDY_vec2_1_0__read interface 1 @@ -218,6 +226,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec2_1_1__write_1} {size 1}}} + results {} enable EN_vec2_1_1__write ready RDY_vec2_1_1__write method @@ -226,7 +235,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec2_1_1__read + results {{{port vec2_1_1__read} {size 1}}} ready RDY_vec2_1_1__read interface vec3 @@ -242,6 +251,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_0_0_0__write_1} {size 1}}} + results {} enable EN_vec3_0_0_0__write ready RDY_vec3_0_0_0__write method @@ -250,7 +260,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_0_0_0__read + results {{{port vec3_0_0_0__read} {size 1}}} ready RDY_vec3_0_0_0__read interface 1 @@ -260,6 +270,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_0_0_1__write_1} {size 1}}} + results {} enable EN_vec3_0_0_1__write ready RDY_vec3_0_0_1__write method @@ -268,7 +279,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_0_0_1__read + results {{{port vec3_0_0_1__read} {size 1}}} ready RDY_vec3_0_0_1__read interface 1 @@ -280,6 +291,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_0_1_0__write_1} {size 1}}} + results {} enable EN_vec3_0_1_0__write ready RDY_vec3_0_1_0__write method @@ -288,7 +300,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_0_1_0__read + results {{{port vec3_0_1_0__read} {size 1}}} ready RDY_vec3_0_1_0__read interface 1 @@ -298,6 +310,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_0_1_1__write_1} {size 1}}} + results {} enable EN_vec3_0_1_1__write ready RDY_vec3_0_1_1__write method @@ -306,7 +319,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_0_1_1__read + results {{{port vec3_0_1_1__read} {size 1}}} ready RDY_vec3_0_1_1__read interface 1 @@ -320,6 +333,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_1_0_0__write_1} {size 1}}} + results {} enable EN_vec3_1_0_0__write ready RDY_vec3_1_0_0__write method @@ -328,7 +342,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_1_0_0__read + results {{{port vec3_1_0_0__read} {size 1}}} ready RDY_vec3_1_0_0__read interface 1 @@ -338,6 +352,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_1_0_1__write_1} {size 1}}} + results {} enable EN_vec3_1_0_1__write ready RDY_vec3_1_0_1__write method @@ -346,7 +361,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_1_0_1__read + results {{{port vec3_1_0_1__read} {size 1}}} ready RDY_vec3_1_0_1__read interface 1 @@ -358,6 +373,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_1_1_0__write_1} {size 1}}} + results {} enable EN_vec3_1_1_0__write ready RDY_vec3_1_1_0__write method @@ -366,7 +382,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_1_1_0__read + results {{{port vec3_1_1_0__read} {size 1}}} ready RDY_vec3_1_1_0__read interface 1 @@ -376,6 +392,7 @@ Command: submodule ports mkT clock clks1_1 reset no_reset args {{{port vec3_1_1_1__write_1} {size 1}}} + results {} enable EN_vec3_1_1_1__write ready RDY_vec3_1_1_1__write method @@ -384,7 +401,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result vec3_1_1_1__read + results {{{port vec3_1_1_1__read} {size 1}}} ready RDY_vec3_1_1_1__read method data1 @@ -392,7 +409,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result data1 + results {{{port data1} {size 2}}} ready RDY_data1 method data2 @@ -400,7 +417,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result data2 + results {{{port data2} {size 4}}} ready RDY_data2 method data3 @@ -408,7 +425,7 @@ Command: submodule ports mkT clock no_clock reset no_reset args {} - result data3 + results {{{port data3} {size 8}}} ready RDY_data3 interface clks1 @@ -458,6 +475,7 @@ Command: submodule ports mkM clock _clk__1 reset _rst__1 args {{{port D_IN} {size 1}}} + results {} enable EN method _read @@ -465,7 +483,7 @@ Command: submodule ports mkM clock _clk__1 reset _rst__1 args {} - result Q_OUT + results {{{port Q_OUT} {size 1}}} args clock _clk__1 {osc CLK} reset _rst__1 {port RST} {clock _clk__1} @@ -480,6 +498,7 @@ Command: submodule ports mkM clock _clk__1 reset _rst__1 args {{{port D_IN} {size 1}}} + results {} enable EN method _read @@ -487,7 +506,7 @@ Command: submodule ports mkM clock _clk__1 reset _rst__1 args {} - result Q_OUT + results {{{port Q_OUT} {size 1}}} args clock _clk__1 {osc CLK} reset _rst__1 {port RST} {clock _clk__1} @@ -502,6 +521,7 @@ Command: submodule ports mkM clock _clk__1 reset _rst__1 args {{{port D_IN} {size 1}}} + results {} enable EN method _read @@ -509,7 +529,7 @@ Command: submodule ports mkM clock _clk__1 reset _rst__1 args {} - result Q_OUT + results {{{port Q_OUT} {size 1}}} args clock _clk__1 {osc CLK} reset _rst__1 {port RST} {clock _clk__1} diff --git a/testsuite/bsc.bluetcl/targeted/port_types/inhigh.tcl.bluetcl-bh-out.expected b/testsuite/bsc.bluetcl/targeted/port_types/inhigh.tcl.bluetcl-bh-out.expected index f7972c0b8..dadadf149 100644 --- a/testsuite/bsc.bluetcl/targeted/port_types/inhigh.tcl.bluetcl-bh-out.expected +++ b/testsuite/bsc.bluetcl/targeted/port_types/inhigh.tcl.bluetcl-bh-out.expected @@ -1,11 +1,11 @@ -verilog mkInhighEnable_Sub sysInhighEnable ---------- -{rg1 MOD {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {{{port Q_IN} {size 1}}}}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {result D_OUT}}}} {args {{reset _rst__1 {port RST} {clock _clk__1}} {clock _clk__1 {osc CLK} {gate CLK_GATE}}}}} {rg2 mkInhighEnable_Sub {interface {{method _write _write {clock default_clock} {reset no_reset} {args {{{port _write_1} {size 1}}}}} {method _read _read {clock default_clock} {reset no_reset} {args {}} {result _read}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}}} +{rg1 MOD {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {{{port Q_IN} {size 1}}}} {results {}}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {results {{{port D_OUT} {size 1}}}}}}} {args {{reset _rst__1 {port RST} {clock _clk__1}} {clock _clk__1 {osc CLK} {gate CLK_GATE}}}}} {rg2 mkInhighEnable_Sub {interface {{method _write _write {clock default_clock} {reset no_reset} {args {{{port _write_1} {size 1}}}} {results {}}} {method _read _read {clock default_clock} {reset no_reset} {args {}} {results {{{port _read} {size 1}}}}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}}} {rg1 MOD {ports {{RST Prelude.Reset} {CLK Prelude.Clock} {CLK_GATE Prelude.Bool} {Q_IN Prelude.Bool} {D_OUT Prelude.Bool}}}} {rg2 mkInhighEnable_Sub {ports {{CLK Prelude.Clock} {RST_N Prelude.Reset} {_write_1 Prelude.Bool} {_read Prelude.Bool}}}} ---------- -{interface {{method _write _write {clock default_clock} {reset no_reset} {args {{{name _write_1} {port _write_1} {size 1}}}}} {method _read _read {clock default_clock} {reset no_reset} {args {}} {result _read}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}} +{interface {{method _write _write {clock default_clock} {reset no_reset} {args {{{name _write_1} {port _write_1} {size 1}}}} {results {}}} {method _read _read {clock default_clock} {reset no_reset} {args {}} {results {{{port _read} {size 1}}}}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}} {CLK Prelude.Clock} {RST_N Prelude.Reset} {_write_1 Prelude.Bool} {_read Prelude.Bool} ---------- diff --git a/testsuite/bsc.bluetcl/targeted/port_types/inhigh.tcl.bluetcl-out.expected b/testsuite/bsc.bluetcl/targeted/port_types/inhigh.tcl.bluetcl-out.expected index 1bf3c6e11..127dc8996 100644 --- a/testsuite/bsc.bluetcl/targeted/port_types/inhigh.tcl.bluetcl-out.expected +++ b/testsuite/bsc.bluetcl/targeted/port_types/inhigh.tcl.bluetcl-out.expected @@ -1,11 +1,11 @@ -verilog mkInhighEnable_Sub sysInhighEnable ---------- -{rg1 MOD {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {{{port Q_IN} {size 1}}}}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {result D_OUT}}}} {args {{reset _rst__1 {port RST} {clock _clk__1}} {clock _clk__1 {osc CLK} {gate CLK_GATE}}}}} {rg2 mkInhighEnable_Sub {interface {{method _write _write {clock default_clock} {reset no_reset} {args {{{port _write_1} {size 1}}}}} {method _read _read {clock default_clock} {reset no_reset} {args {}} {result _read}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}}} +{rg1 MOD {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {{{port Q_IN} {size 1}}}} {results {}}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {results {{{port D_OUT} {size 1}}}}}}} {args {{reset _rst__1 {port RST} {clock _clk__1}} {clock _clk__1 {osc CLK} {gate CLK_GATE}}}}} {rg2 mkInhighEnable_Sub {interface {{method _write _write {clock default_clock} {reset no_reset} {args {{{port _write_1} {size 1}}}} {results {}}} {method _read _read {clock default_clock} {reset no_reset} {args {}} {results {{{port _read} {size 1}}}}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}}} {rg1 MOD {ports {{RST Reset} {CLK Clock} {CLK_GATE Bool} {Q_IN Bool} {D_OUT Bool}}}} {rg2 mkInhighEnable_Sub {ports {{CLK Clock} {RST_N Reset} {_write_1 Bool} {_read Bool}}}} ---------- -{interface {{method _write _write {clock default_clock} {reset no_reset} {args {{{name _write_1} {port _write_1} {size 1}}}}} {method _read _read {clock default_clock} {reset no_reset} {args {}} {result _read}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}} +{interface {{method _write _write {clock default_clock} {reset no_reset} {args {{{name _write_1} {port _write_1} {size 1}}}} {results {}}} {method _read _read {clock default_clock} {reset no_reset} {args {}} {results {{{port _read} {size 1}}}}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}} {CLK Clock} {RST_N Reset} {_write_1 Bool} {_read Bool} ---------- diff --git a/testsuite/bsc.bluetcl/targeted/port_types/prims.tcl.bluetcl-bh-out.expected b/testsuite/bsc.bluetcl/targeted/port_types/prims.tcl.bluetcl-bh-out.expected index 547da936a..59b75dd63 100644 --- a/testsuite/bsc.bluetcl/targeted/port_types/prims.tcl.bluetcl-bh-out.expected +++ b/testsuite/bsc.bluetcl/targeted/port_types/prims.tcl.bluetcl-bh-out.expected @@ -1,75 +1,75 @@ -verilog sysPrims ---------- -rg RegN {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable EN}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {result Q_OUT}}}} {args {{clock _clk__1 {osc CLK}} {reset _rst__1 {port RST} {clock _clk__1}} {parameter width {param width}} {parameter init {param init}}}} +rg RegN {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable EN}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {results {{{port Q_OUT} {size 32}}}}}}} {args {{clock _clk__1 {osc CLK}} {reset _rst__1 {port RST} {clock _clk__1}} {parameter width {param width}} {parameter init {param init}}}} rg RegN {ports {{CLK Prelude.Clock} {RST Prelude.Reset} {D_IN {Prelude.Int 32}} {EN Prelude.Bool} {Q_OUT {Prelude.Int 32}}}} ---------- -rgA RegA {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable EN}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {result Q_OUT}}}} {args {{clock _clk__1 {osc CLK}} {reset _rst__1 {port RST} {clock _clk__1}} {parameter width {param width}} {parameter init {param init}}}} +rgA RegA {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable EN}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {results {{{port Q_OUT} {size 32}}}}}}} {args {{clock _clk__1 {osc CLK}} {reset _rst__1 {port RST} {clock _clk__1}} {parameter width {param width}} {parameter init {param init}}}} rgA RegA {ports {{CLK Prelude.Clock} {RST Prelude.Reset} {D_IN {Prelude.Int 32}} {EN Prelude.Bool} {Q_OUT {Prelude.Int 32}}}} ---------- -rgU RegUN {interface {{method _write _write {clock _clk__1} {reset no_reset} {args {{{port D_IN} {size 32}}}} {enable EN}} {method _read _read {clock _clk__1} {reset no_reset} {args {}} {result Q_OUT}}}} {args {{clock _clk__1 {osc CLK}} {parameter width {param width}}}} +rgU RegUN {interface {{method _write _write {clock _clk__1} {reset no_reset} {args {{{port D_IN} {size 32}}}} {results {}} {enable EN}} {method _read _read {clock _clk__1} {reset no_reset} {args {}} {results {{{port Q_OUT} {size 32}}}}}}} {args {{clock _clk__1 {osc CLK}} {parameter width {param width}}}} rgU RegUN {ports {{CLK Prelude.Clock} {D_IN {Prelude.Int 32}} {EN Prelude.Bool} {Q_OUT {Prelude.Int 32}}}} ---------- -rw RWire {interface {{method wset wset {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {enable WSET}} {method wget wget {clock clk} {reset rst} {args {}} {result WGET} {ready WHAS}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} +rw RWire {interface {{method wset wset {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {results {}} {enable WSET}} {method wget wget {clock clk} {reset rst} {args {}} {results {{{port WGET} {size 32}}}} {ready WHAS}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} rw RWire {ports {{WVAL {Prelude.Int 32}} {WSET Prelude.Bool} {WGET {Prelude.Int 32}} {WHAS Prelude.Bool}}} ---------- -rw0 RWire0 {interface {{method wset wset {clock clk} {reset rst} {args {}} {enable WSET}} {method wget wget {clock clk} {reset rst} {args {}} {ready WHAS}}}} {args {{clock clk} {reset rst {clock clk}}}} +rw0 RWire0 {interface {{method wset wset {clock clk} {reset rst} {args {}} {results {}} {enable WSET}} {method wget wget {clock clk} {reset rst} {args {}} {results {}} {ready WHAS}}}} {args {{clock clk} {reset rst {clock clk}}}} rw0 RWire0 {ports {{WSET Prelude.Bool} {WHAS Prelude.Bool}}} ---------- -w RWire {interface {{method _write _write {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {result WGET} {ready WHAS}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} +w RWire {interface {{method _write _write {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {results {}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {results {{{port WGET} {size 32}}}} {ready WHAS}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} w RWire {ports {{WVAL {Prelude.Int 32}} {WSET Prelude.Bool} {WGET {Prelude.Int 32}} {WHAS Prelude.Bool}}} ---------- -dw RWire {interface {{method _write _write {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {result WGET} {ready WHAS}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} +dw RWire {interface {{method _write _write {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {results {}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {results {{{port WGET} {size 32}}}} {ready WHAS}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} dw RWire {ports {{WVAL {Prelude.Int 32}} {WSET Prelude.Bool} {WGET {Prelude.Int 32}} {WHAS Prelude.Bool}}} ---------- -bw BypassWire {interface {{method _write _write {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}}} {method _read _read {clock clk} {reset rst} {args {}} {result WGET}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} +bw BypassWire {interface {{method _write _write {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {results {}}} {method _read _read {clock clk} {reset rst} {args {}} {results {{{port WGET} {size 32}}}}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} bw BypassWire {ports {{WVAL {Prelude.Int 32}} {WGET {Prelude.Int 32}}}} ---------- -pw RWire0 {interface {{method send send {clock clk} {reset rst} {args {}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {result WHAS}}}} {args {{clock clk} {reset rst {clock clk}}}} +pw RWire0 {interface {{method send send {clock clk} {reset rst} {args {}} {results {}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {results {{{port WHAS} {size 1}}}}}}} {args {{clock clk} {reset rst {clock clk}}}} pw RWire0 {ports {{WSET Prelude.Bool} {WHAS Prelude.Bool}}} ---------- -pwo RWire0 {interface {{method send send {clock clk} {reset rst} {args {}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {result WHAS}}}} {args {{clock clk} {reset rst {clock clk}}}} +pwo RWire0 {interface {{method send send {clock clk} {reset rst} {args {}} {results {}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {results {{{port WHAS} {size 1}}}}}}} {args {{clock clk} {reset rst {clock clk}}}} pwo RWire0 {ports {{WSET Prelude.Bool} {WHAS Prelude.Bool}}} ---------- -rf RegFile {interface {{method upd upd {clock _clk__1} {reset no_reset} {args {{{port ADDR_IN} {size 2}} {{port D_IN} {size 32}}}} {enable WE}} {method sub_1 sub_1 {clock _clk__1} {reset no_reset} {args {{{port ADDR_1} {size 2}}}} {result D_OUT_1}} {method sub_2 sub_2 {clock _clk__1} {reset no_reset} {args {{{port ADDR_2} {size 2}}}} {result D_OUT_2}} {method sub_3 sub_3 {clock _clk__1} {reset no_reset} {args {{{port ADDR_3} {size 2}}}} {result D_OUT_3}} {method sub_4 sub_4 {clock _clk__1} {reset no_reset} {args {{{port ADDR_4} {size 2}}}} {result D_OUT_4}} {method sub_5 sub_5 {clock _clk__1} {reset no_reset} {args {{{port ADDR_5} {size 2}}}} {result D_OUT_5}}}} {args {{clock _clk__1 {osc CLK}} {parameter addr_width {param addr_width}} {parameter data_width {param data_width}} {parameter lo {param lo}} {parameter hi {param hi}}}} +rf RegFile {interface {{method upd upd {clock _clk__1} {reset no_reset} {args {{{port ADDR_IN} {size 2}} {{port D_IN} {size 32}}}} {results {}} {enable WE}} {method sub_1 sub_1 {clock _clk__1} {reset no_reset} {args {{{port ADDR_1} {size 2}}}} {results {{{port D_OUT_1} {size 32}}}}} {method sub_2 sub_2 {clock _clk__1} {reset no_reset} {args {{{port ADDR_2} {size 2}}}} {results {{{port D_OUT_2} {size 32}}}}} {method sub_3 sub_3 {clock _clk__1} {reset no_reset} {args {{{port ADDR_3} {size 2}}}} {results {{{port D_OUT_3} {size 32}}}}} {method sub_4 sub_4 {clock _clk__1} {reset no_reset} {args {{{port ADDR_4} {size 2}}}} {results {{{port D_OUT_4} {size 32}}}}} {method sub_5 sub_5 {clock _clk__1} {reset no_reset} {args {{{port ADDR_5} {size 2}}}} {results {{{port D_OUT_5} {size 32}}}}}}} {args {{clock _clk__1 {osc CLK}} {parameter addr_width {param addr_width}} {parameter data_width {param data_width}} {parameter lo {param lo}} {parameter hi {param hi}}}} rf RegFile {ports {{CLK Prelude.Clock} {ADDR_IN {Prelude.Bit 2}} {D_IN {Prelude.Int 32}} {WE Prelude.Bool} {ADDR_1 {Prelude.Bit 2}} {D_OUT_1 {Prelude.Int 32}} {ADDR_2 {Prelude.Bit 2}} {D_OUT_2 {Prelude.Int 32}} {ADDR_3 {Prelude.Bit 2}} {D_OUT_3 {Prelude.Int 32}} {ADDR_4 {Prelude.Bit 2}} {D_OUT_4 {Prelude.Int 32}} {ADDR_5 {Prelude.Bit 2}} {D_OUT_5 {Prelude.Int 32}}}} ---------- -ff1 FIFO2 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {result D_OUT} {ready EMPTY_N}} {method notFull notFull {clock clk} {reset _rst__1} {args {}} {result FULL_N}} {method notEmpty notEmpty {clock clk} {reset _rst__1} {args {}} {result EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}} {parameter guarded {param guarded}}}} +ff1 FIFO2 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {{{port D_OUT} {size 32}}}} {ready EMPTY_N}} {method notFull notFull {clock clk} {reset _rst__1} {args {}} {results {{{port FULL_N} {size 1}}}}} {method notEmpty notEmpty {clock clk} {reset _rst__1} {args {}} {results {{{port EMPTY_N} {size 1}}}}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}} {parameter guarded {param guarded}}}} ff1 FIFO2 {ports {{RST Prelude.Reset} {CLK Prelude.Clock} {D_IN {Prelude.Int 32}} {ENQ Prelude.Bool} {FULL_N Prelude.Bool} {DEQ Prelude.Bool} {EMPTY_N Prelude.Bool} {D_OUT {Prelude.Int 32}} {CLR Prelude.Bool}}} ---------- -f1 FIFO1 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {result D_OUT} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}} {parameter guarded {param guarded}}}} +f1 FIFO1 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {{{port D_OUT} {size 32}}}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}} {parameter guarded {param guarded}}}} f1 FIFO1 {ports {{RST Prelude.Reset} {CLK Prelude.Clock} {D_IN {Prelude.Int 32}} {ENQ Prelude.Bool} {FULL_N Prelude.Bool} {DEQ Prelude.Bool} {EMPTY_N Prelude.Bool} {D_OUT {Prelude.Int 32}} {CLR Prelude.Bool}}} ---------- -f10 FIFO10 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter guarded {param guarded}}}} +f10 FIFO10 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter guarded {param guarded}}}} f10 FIFO10 {ports {{RST Prelude.Reset} {CLK Prelude.Clock} {ENQ Prelude.Bool} {FULL_N Prelude.Bool} {DEQ Prelude.Bool} {EMPTY_N Prelude.Bool} {CLR Prelude.Bool}}} ---------- -f2 FIFO2 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {result D_OUT} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}} {parameter guarded {param guarded}}}} +f2 FIFO2 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {{{port D_OUT} {size 32}}}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}} {parameter guarded {param guarded}}}} f2 FIFO2 {ports {{RST Prelude.Reset} {CLK Prelude.Clock} {D_IN {Prelude.Int 32}} {ENQ Prelude.Bool} {FULL_N Prelude.Bool} {DEQ Prelude.Bool} {EMPTY_N Prelude.Bool} {D_OUT {Prelude.Int 32}} {CLR Prelude.Bool}}} ---------- -f20 FIFO20 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter guarded {param guarded}}}} +f20 FIFO20 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter guarded {param guarded}}}} f20 FIFO20 {ports {{RST Prelude.Reset} {CLK Prelude.Clock} {ENQ Prelude.Bool} {FULL_N Prelude.Bool} {DEQ Prelude.Bool} {EMPTY_N Prelude.Bool} {CLR Prelude.Bool}}} ---------- -fs SizedFIFO {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {result D_OUT} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter p1width {param p1width}} {parameter p2depth {param p2depth}} {parameter p3cntr_width {param p3cntr_width}} {parameter guarded {param guarded}}}} +fs SizedFIFO {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {{{port D_OUT} {size 32}}}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter p1width {param p1width}} {parameter p2depth {param p2depth}} {parameter p3cntr_width {param p3cntr_width}} {parameter guarded {param guarded}}}} fs SizedFIFO {ports {{RST Prelude.Reset} {CLK Prelude.Clock} {D_IN {Prelude.Int 32}} {ENQ Prelude.Bool} {FULL_N Prelude.Bool} {DEQ Prelude.Bool} {EMPTY_N Prelude.Bool} {D_OUT {Prelude.Int 32}} {CLR Prelude.Bool}}} ---------- -fs0 SizedFIFO0 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter p1depth {param p1depth}} {parameter p2cntr_width {param p2cntr_width}} {parameter guarded {param guarded}}}} +fs0 SizedFIFO0 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter p1depth {param p1depth}} {parameter p2cntr_width {param p2cntr_width}} {parameter guarded {param guarded}}}} fs0 SizedFIFO0 {ports {{RST Prelude.Reset} {CLK Prelude.Clock} {ENQ Prelude.Bool} {FULL_N Prelude.Bool} {DEQ Prelude.Bool} {EMPTY_N Prelude.Bool} {CLR Prelude.Bool}}} ---------- -fL1 FIFOL1 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {result D_OUT} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}}}} +fL1 FIFOL1 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {{{port D_OUT} {size 32}}}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}}}} fL1 FIFOL1 {ports {{RST Prelude.Reset} {CLK Prelude.Clock} {D_IN {Prelude.Int 32}} {ENQ Prelude.Bool} {FULL_N Prelude.Bool} {DEQ Prelude.Bool} {EMPTY_N Prelude.Bool} {D_OUT {Prelude.Int 32}} {CLR Prelude.Bool}}} ---------- -fL10 FIFO20 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter guarded {param guarded}}}} +fL10 FIFO20 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter guarded {param guarded}}}} fL10 FIFO20 {ports {{RST Prelude.Reset} {CLK Prelude.Clock} {ENQ Prelude.Bool} {FULL_N Prelude.Bool} {DEQ Prelude.Bool} {EMPTY_N Prelude.Bool} {CLR Prelude.Bool}}} ---------- dclk ClockGen {interface {{clock gen_clk gen_clk {osc CLK_OUT}}}} {args {{parameter v1Width {param v1Width}} {parameter v2Width {param v2Width}} {parameter initDelay {param initDelay}} {parameter initValue {param initValue}} {parameter otherValue {param otherValue}}}} dclk ClockGen {ports {{CLK_OUT Prelude.Clock}}} ---------- -sr SyncRegister {interface {{method _write _write {clock clk_src} {reset sRstIn} {args {{{port sD_IN} {size 32}}}} {enable sEN} {ready sRDY}} {method _read _read {clock clk_dst} {reset no_reset} {args {}} {result dD_OUT}}}} {args {{parameter width {param width}} {parameter init {param init}} {clock clk_src {osc sCLK}} {clock clk_dst {osc dCLK}} {reset sRstIn {port sRST} {clock clk_src}}}} +sr SyncRegister {interface {{method _write _write {clock clk_src} {reset sRstIn} {args {{{port sD_IN} {size 32}}}} {results {}} {enable sEN} {ready sRDY}} {method _read _read {clock clk_dst} {reset no_reset} {args {}} {results {{{port dD_OUT} {size 32}}}}}}} {args {{parameter width {param width}} {parameter init {param init}} {clock clk_src {osc sCLK}} {clock clk_dst {osc dCLK}} {reset sRstIn {port sRST} {clock clk_src}}}} sr SyncRegister {ports {{sCLK Prelude.Clock} {dCLK Prelude.Clock} {sRST Prelude.Reset} {sD_IN {Prelude.Int 32}} {sEN Prelude.Bool} {sRDY Prelude.Bool} {dD_OUT {Prelude.Int 32}}}} ---------- -bcw CrossingBypassWire {interface {{method wset wset {clock clk} {reset no_reset} {args {{{port WVAL} {size 32}}}}} {method wget wget {clock dstClk} {reset no_reset} {args {}} {result WGET}}}} {args {{parameter width {param width}} {clock clk {osc CLK}} {clock dstClk}}} +bcw CrossingBypassWire {interface {{method wset wset {clock clk} {reset no_reset} {args {{{port WVAL} {size 32}}}} {results {}}} {method wget wget {clock dstClk} {reset no_reset} {args {}} {results {{{port WGET} {size 32}}}}}}} {args {{parameter width {param width}} {clock clk {osc CLK}} {clock dstClk}}} bcw CrossingBypassWire {ports {{CLK Prelude.Clock} {WVAL {Prelude.Int 32}} {WGET {Prelude.Int 32}}}} ---------- -ncw CrossingBypassWire {interface {{method wset wset {clock clk} {reset no_reset} {args {{{port WVAL} {size 32}}}}} {method wget wget {clock dstClk} {reset no_reset} {args {}} {result WGET}}}} {args {{parameter width {param width}} {clock clk {osc CLK}} {clock dstClk}}} +ncw CrossingBypassWire {interface {{method wset wset {clock clk} {reset no_reset} {args {{{port WVAL} {size 32}}}} {results {}}} {method wget wget {clock dstClk} {reset no_reset} {args {}} {results {{{port WGET} {size 32}}}}}}} {args {{parameter width {param width}} {clock clk {osc CLK}} {clock dstClk}}} ncw CrossingBypassWire {ports {{CLK Prelude.Clock} {WVAL {Prelude.Int 32}} {WGET {Prelude.Int 32}}}} ---------- diff --git a/testsuite/bsc.bluetcl/targeted/port_types/prims.tcl.bluetcl-out.expected b/testsuite/bsc.bluetcl/targeted/port_types/prims.tcl.bluetcl-out.expected index 56f80bdcd..d1099dcef 100644 --- a/testsuite/bsc.bluetcl/targeted/port_types/prims.tcl.bluetcl-out.expected +++ b/testsuite/bsc.bluetcl/targeted/port_types/prims.tcl.bluetcl-out.expected @@ -1,75 +1,75 @@ -verilog sysPrims ---------- -rg RegN {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable EN}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {result Q_OUT}}}} {args {{clock _clk__1 {osc CLK}} {reset _rst__1 {port RST} {clock _clk__1}} {parameter width {param width}} {parameter init {param init}}}} +rg RegN {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable EN}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {results {{{port Q_OUT} {size 32}}}}}}} {args {{clock _clk__1 {osc CLK}} {reset _rst__1 {port RST} {clock _clk__1}} {parameter width {param width}} {parameter init {param init}}}} rg RegN {ports {{CLK Clock} {RST Reset} {D_IN Int#(32)} {EN Bool} {Q_OUT Int#(32)}}} ---------- -rgA RegA {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable EN}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {result Q_OUT}}}} {args {{clock _clk__1 {osc CLK}} {reset _rst__1 {port RST} {clock _clk__1}} {parameter width {param width}} {parameter init {param init}}}} +rgA RegA {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable EN}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {results {{{port Q_OUT} {size 32}}}}}}} {args {{clock _clk__1 {osc CLK}} {reset _rst__1 {port RST} {clock _clk__1}} {parameter width {param width}} {parameter init {param init}}}} rgA RegA {ports {{CLK Clock} {RST Reset} {D_IN Int#(32)} {EN Bool} {Q_OUT Int#(32)}}} ---------- -rgU RegUN {interface {{method _write _write {clock _clk__1} {reset no_reset} {args {{{port D_IN} {size 32}}}} {enable EN}} {method _read _read {clock _clk__1} {reset no_reset} {args {}} {result Q_OUT}}}} {args {{clock _clk__1 {osc CLK}} {parameter width {param width}}}} +rgU RegUN {interface {{method _write _write {clock _clk__1} {reset no_reset} {args {{{port D_IN} {size 32}}}} {results {}} {enable EN}} {method _read _read {clock _clk__1} {reset no_reset} {args {}} {results {{{port Q_OUT} {size 32}}}}}}} {args {{clock _clk__1 {osc CLK}} {parameter width {param width}}}} rgU RegUN {ports {{CLK Clock} {D_IN Int#(32)} {EN Bool} {Q_OUT Int#(32)}}} ---------- -rw RWire {interface {{method wset wset {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {enable WSET}} {method wget wget {clock clk} {reset rst} {args {}} {result WGET} {ready WHAS}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} +rw RWire {interface {{method wset wset {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {results {}} {enable WSET}} {method wget wget {clock clk} {reset rst} {args {}} {results {{{port WGET} {size 32}}}} {ready WHAS}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} rw RWire {ports {{WVAL Int#(32)} {WSET Bool} {WGET Int#(32)} {WHAS Bool}}} ---------- -rw0 RWire0 {interface {{method wset wset {clock clk} {reset rst} {args {}} {enable WSET}} {method wget wget {clock clk} {reset rst} {args {}} {ready WHAS}}}} {args {{clock clk} {reset rst {clock clk}}}} +rw0 RWire0 {interface {{method wset wset {clock clk} {reset rst} {args {}} {results {}} {enable WSET}} {method wget wget {clock clk} {reset rst} {args {}} {results {}} {ready WHAS}}}} {args {{clock clk} {reset rst {clock clk}}}} rw0 RWire0 {ports {{WSET Bool} {WHAS Bool}}} ---------- -w RWire {interface {{method _write _write {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {result WGET} {ready WHAS}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} +w RWire {interface {{method _write _write {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {results {}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {results {{{port WGET} {size 32}}}} {ready WHAS}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} w RWire {ports {{WVAL Int#(32)} {WSET Bool} {WGET Int#(32)} {WHAS Bool}}} ---------- -dw RWire {interface {{method _write _write {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {result WGET} {ready WHAS}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} +dw RWire {interface {{method _write _write {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {results {}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {results {{{port WGET} {size 32}}}} {ready WHAS}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} dw RWire {ports {{WVAL Int#(32)} {WSET Bool} {WGET Int#(32)} {WHAS Bool}}} ---------- -bw BypassWire {interface {{method _write _write {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}}} {method _read _read {clock clk} {reset rst} {args {}} {result WGET}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} +bw BypassWire {interface {{method _write _write {clock clk} {reset rst} {args {{{port WVAL} {size 32}}}} {results {}}} {method _read _read {clock clk} {reset rst} {args {}} {results {{{port WGET} {size 32}}}}}}} {args {{parameter width {param width}} {clock clk} {reset rst {clock clk}}}} bw BypassWire {ports {{WVAL Int#(32)} {WGET Int#(32)}}} ---------- -pw RWire0 {interface {{method send send {clock clk} {reset rst} {args {}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {result WHAS}}}} {args {{clock clk} {reset rst {clock clk}}}} +pw RWire0 {interface {{method send send {clock clk} {reset rst} {args {}} {results {}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {results {{{port WHAS} {size 1}}}}}}} {args {{clock clk} {reset rst {clock clk}}}} pw RWire0 {ports {{WSET Bool} {WHAS Bool}}} ---------- -pwo RWire0 {interface {{method send send {clock clk} {reset rst} {args {}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {result WHAS}}}} {args {{clock clk} {reset rst {clock clk}}}} +pwo RWire0 {interface {{method send send {clock clk} {reset rst} {args {}} {results {}} {enable WSET}} {method _read _read {clock clk} {reset rst} {args {}} {results {{{port WHAS} {size 1}}}}}}} {args {{clock clk} {reset rst {clock clk}}}} pwo RWire0 {ports {{WSET Bool} {WHAS Bool}}} ---------- -rf RegFile {interface {{method upd upd {clock _clk__1} {reset no_reset} {args {{{port ADDR_IN} {size 2}} {{port D_IN} {size 32}}}} {enable WE}} {method sub_1 sub_1 {clock _clk__1} {reset no_reset} {args {{{port ADDR_1} {size 2}}}} {result D_OUT_1}} {method sub_2 sub_2 {clock _clk__1} {reset no_reset} {args {{{port ADDR_2} {size 2}}}} {result D_OUT_2}} {method sub_3 sub_3 {clock _clk__1} {reset no_reset} {args {{{port ADDR_3} {size 2}}}} {result D_OUT_3}} {method sub_4 sub_4 {clock _clk__1} {reset no_reset} {args {{{port ADDR_4} {size 2}}}} {result D_OUT_4}} {method sub_5 sub_5 {clock _clk__1} {reset no_reset} {args {{{port ADDR_5} {size 2}}}} {result D_OUT_5}}}} {args {{clock _clk__1 {osc CLK}} {parameter addr_width {param addr_width}} {parameter data_width {param data_width}} {parameter lo {param lo}} {parameter hi {param hi}}}} +rf RegFile {interface {{method upd upd {clock _clk__1} {reset no_reset} {args {{{port ADDR_IN} {size 2}} {{port D_IN} {size 32}}}} {results {}} {enable WE}} {method sub_1 sub_1 {clock _clk__1} {reset no_reset} {args {{{port ADDR_1} {size 2}}}} {results {{{port D_OUT_1} {size 32}}}}} {method sub_2 sub_2 {clock _clk__1} {reset no_reset} {args {{{port ADDR_2} {size 2}}}} {results {{{port D_OUT_2} {size 32}}}}} {method sub_3 sub_3 {clock _clk__1} {reset no_reset} {args {{{port ADDR_3} {size 2}}}} {results {{{port D_OUT_3} {size 32}}}}} {method sub_4 sub_4 {clock _clk__1} {reset no_reset} {args {{{port ADDR_4} {size 2}}}} {results {{{port D_OUT_4} {size 32}}}}} {method sub_5 sub_5 {clock _clk__1} {reset no_reset} {args {{{port ADDR_5} {size 2}}}} {results {{{port D_OUT_5} {size 32}}}}}}} {args {{clock _clk__1 {osc CLK}} {parameter addr_width {param addr_width}} {parameter data_width {param data_width}} {parameter lo {param lo}} {parameter hi {param hi}}}} rf RegFile {ports {{CLK Clock} {ADDR_IN Bit#(2)} {D_IN Int#(32)} {WE Bool} {ADDR_1 Bit#(2)} {D_OUT_1 Int#(32)} {ADDR_2 Bit#(2)} {D_OUT_2 Int#(32)} {ADDR_3 Bit#(2)} {D_OUT_3 Int#(32)} {ADDR_4 Bit#(2)} {D_OUT_4 Int#(32)} {ADDR_5 Bit#(2)} {D_OUT_5 Int#(32)}}} ---------- -ff1 FIFO2 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {result D_OUT} {ready EMPTY_N}} {method notFull notFull {clock clk} {reset _rst__1} {args {}} {result FULL_N}} {method notEmpty notEmpty {clock clk} {reset _rst__1} {args {}} {result EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}} {parameter guarded {param guarded}}}} +ff1 FIFO2 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {{{port D_OUT} {size 32}}}} {ready EMPTY_N}} {method notFull notFull {clock clk} {reset _rst__1} {args {}} {results {{{port FULL_N} {size 1}}}}} {method notEmpty notEmpty {clock clk} {reset _rst__1} {args {}} {results {{{port EMPTY_N} {size 1}}}}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}} {parameter guarded {param guarded}}}} ff1 FIFO2 {ports {{RST Reset} {CLK Clock} {D_IN Int#(32)} {ENQ Bool} {FULL_N Bool} {DEQ Bool} {EMPTY_N Bool} {D_OUT Int#(32)} {CLR Bool}}} ---------- -f1 FIFO1 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {result D_OUT} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}} {parameter guarded {param guarded}}}} +f1 FIFO1 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {{{port D_OUT} {size 32}}}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}} {parameter guarded {param guarded}}}} f1 FIFO1 {ports {{RST Reset} {CLK Clock} {D_IN Int#(32)} {ENQ Bool} {FULL_N Bool} {DEQ Bool} {EMPTY_N Bool} {D_OUT Int#(32)} {CLR Bool}}} ---------- -f10 FIFO10 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter guarded {param guarded}}}} +f10 FIFO10 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter guarded {param guarded}}}} f10 FIFO10 {ports {{RST Reset} {CLK Clock} {ENQ Bool} {FULL_N Bool} {DEQ Bool} {EMPTY_N Bool} {CLR Bool}}} ---------- -f2 FIFO2 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {result D_OUT} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}} {parameter guarded {param guarded}}}} +f2 FIFO2 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {{{port D_OUT} {size 32}}}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}} {parameter guarded {param guarded}}}} f2 FIFO2 {ports {{RST Reset} {CLK Clock} {D_IN Int#(32)} {ENQ Bool} {FULL_N Bool} {DEQ Bool} {EMPTY_N Bool} {D_OUT Int#(32)} {CLR Bool}}} ---------- -f20 FIFO20 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter guarded {param guarded}}}} +f20 FIFO20 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter guarded {param guarded}}}} f20 FIFO20 {ports {{RST Reset} {CLK Clock} {ENQ Bool} {FULL_N Bool} {DEQ Bool} {EMPTY_N Bool} {CLR Bool}}} ---------- -fs SizedFIFO {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {result D_OUT} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter p1width {param p1width}} {parameter p2depth {param p2depth}} {parameter p3cntr_width {param p3cntr_width}} {parameter guarded {param guarded}}}} +fs SizedFIFO {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {{{port D_OUT} {size 32}}}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter p1width {param p1width}} {parameter p2depth {param p2depth}} {parameter p3cntr_width {param p3cntr_width}} {parameter guarded {param guarded}}}} fs SizedFIFO {ports {{RST Reset} {CLK Clock} {D_IN Int#(32)} {ENQ Bool} {FULL_N Bool} {DEQ Bool} {EMPTY_N Bool} {D_OUT Int#(32)} {CLR Bool}}} ---------- -fs0 SizedFIFO0 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter p1depth {param p1depth}} {parameter p2cntr_width {param p2cntr_width}} {parameter guarded {param guarded}}}} +fs0 SizedFIFO0 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter p1depth {param p1depth}} {parameter p2cntr_width {param p2cntr_width}} {parameter guarded {param guarded}}}} fs0 SizedFIFO0 {ports {{RST Reset} {CLK Clock} {ENQ Bool} {FULL_N Bool} {DEQ Bool} {EMPTY_N Bool} {CLR Bool}}} ---------- -fL1 FIFOL1 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {result D_OUT} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}}}} +fL1 FIFOL1 {interface {{method enq enq {clock clk} {reset _rst__1} {args {{{port D_IN} {size 32}}}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {{{port D_OUT} {size 32}}}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter width {param width}}}} fL1 FIFOL1 {ports {{RST Reset} {CLK Clock} {D_IN Int#(32)} {ENQ Bool} {FULL_N Bool} {DEQ Bool} {EMPTY_N Bool} {D_OUT Int#(32)} {CLR Bool}}} ---------- -fL10 FIFO20 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter guarded {param guarded}}}} +fL10 FIFO20 {interface {{method enq enq {clock clk} {reset _rst__1} {args {}} {results {}} {enable ENQ} {ready FULL_N}} {method deq deq {clock clk} {reset _rst__1} {args {}} {results {}} {enable DEQ} {ready EMPTY_N}} {method first first {clock clk} {reset _rst__1} {args {}} {results {}} {ready EMPTY_N}} {method clear clear {clock clk} {reset _rst__1} {args {}} {results {}} {enable CLR}}}} {args {{reset _rst__1 {port RST} {clock clk}} {clock clk {osc CLK}} {parameter guarded {param guarded}}}} fL10 FIFO20 {ports {{RST Reset} {CLK Clock} {ENQ Bool} {FULL_N Bool} {DEQ Bool} {EMPTY_N Bool} {CLR Bool}}} ---------- dclk ClockGen {interface {{clock gen_clk gen_clk {osc CLK_OUT}}}} {args {{parameter v1Width {param v1Width}} {parameter v2Width {param v2Width}} {parameter initDelay {param initDelay}} {parameter initValue {param initValue}} {parameter otherValue {param otherValue}}}} dclk ClockGen {ports {{CLK_OUT Clock}}} ---------- -sr SyncRegister {interface {{method _write _write {clock clk_src} {reset sRstIn} {args {{{port sD_IN} {size 32}}}} {enable sEN} {ready sRDY}} {method _read _read {clock clk_dst} {reset no_reset} {args {}} {result dD_OUT}}}} {args {{parameter width {param width}} {parameter init {param init}} {clock clk_src {osc sCLK}} {clock clk_dst {osc dCLK}} {reset sRstIn {port sRST} {clock clk_src}}}} +sr SyncRegister {interface {{method _write _write {clock clk_src} {reset sRstIn} {args {{{port sD_IN} {size 32}}}} {results {}} {enable sEN} {ready sRDY}} {method _read _read {clock clk_dst} {reset no_reset} {args {}} {results {{{port dD_OUT} {size 32}}}}}}} {args {{parameter width {param width}} {parameter init {param init}} {clock clk_src {osc sCLK}} {clock clk_dst {osc dCLK}} {reset sRstIn {port sRST} {clock clk_src}}}} sr SyncRegister {ports {{sCLK Clock} {dCLK Clock} {sRST Reset} {sD_IN Int#(32)} {sEN Bool} {sRDY Bool} {dD_OUT Int#(32)}}} ---------- -bcw CrossingBypassWire {interface {{method wset wset {clock clk} {reset no_reset} {args {{{port WVAL} {size 32}}}}} {method wget wget {clock dstClk} {reset no_reset} {args {}} {result WGET}}}} {args {{parameter width {param width}} {clock clk {osc CLK}} {clock dstClk}}} +bcw CrossingBypassWire {interface {{method wset wset {clock clk} {reset no_reset} {args {{{port WVAL} {size 32}}}} {results {}}} {method wget wget {clock dstClk} {reset no_reset} {args {}} {results {{{port WGET} {size 32}}}}}}} {args {{parameter width {param width}} {clock clk {osc CLK}} {clock dstClk}}} bcw CrossingBypassWire {ports {{CLK Clock} {WVAL Int#(32)} {WGET Int#(32)}}} ---------- -ncw CrossingBypassWire {interface {{method wset wset {clock clk} {reset no_reset} {args {{{port WVAL} {size 32}}}}} {method wget wget {clock dstClk} {reset no_reset} {args {}} {result WGET}}}} {args {{parameter width {param width}} {clock clk {osc CLK}} {clock dstClk}}} +ncw CrossingBypassWire {interface {{method wset wset {clock clk} {reset no_reset} {args {{{port WVAL} {size 32}}}} {results {}}} {method wget wget {clock dstClk} {reset no_reset} {args {}} {results {{{port WGET} {size 32}}}}}}} {args {{parameter width {param width}} {clock clk {osc CLK}} {clock dstClk}}} ncw CrossingBypassWire {ports {{CLK Clock} {WVAL Int#(32)} {WGET Int#(32)}}} ---------- diff --git a/testsuite/bsc.bluetcl/targeted/port_types/zero_size.tcl.bluetcl-bh-out.expected b/testsuite/bsc.bluetcl/targeted/port_types/zero_size.tcl.bluetcl-bh-out.expected index e3facb44e..bb0527ecb 100644 --- a/testsuite/bsc.bluetcl/targeted/port_types/zero_size.tcl.bluetcl-bh-out.expected +++ b/testsuite/bsc.bluetcl/targeted/port_types/zero_size.tcl.bluetcl-bh-out.expected @@ -1,11 +1,11 @@ -verilog mkZeroSize_Sub sysZeroSize ---------- -{rg1 MOD {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {}} {enable EN}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}}}}} {args {{reset _rst__1 {port RST} {clock _clk__1}} {clock _clk__1 {osc CLK} {gate CLK_GATE}}}}} {rg2 mkZeroSize_Sub {interface {{method m1 m1 {clock no_clock} {reset no_reset} {args {}} {ready RDY_m1}} {method m2 m2 {clock default_clock} {reset no_reset} {args {{{port m2_y} {size 1}}}} {enable EN_m2} {ready RDY_m2}} {method m3 m3 {clock default_clock} {reset no_reset} {args {}} {enable EN_m3} {ready RDY_m3}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}}} +{rg1 MOD {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {}} {results {}} {enable EN}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {results {}}}}} {args {{reset _rst__1 {port RST} {clock _clk__1}} {clock _clk__1 {osc CLK} {gate CLK_GATE}}}}} {rg2 mkZeroSize_Sub {interface {{method m1 m1 {clock no_clock} {reset no_reset} {args {}} {results {}} {ready RDY_m1}} {method m2 m2 {clock default_clock} {reset no_reset} {args {{{port m2_y} {size 1}}}} {results {}} {enable EN_m2} {ready RDY_m2}} {method m3 m3 {clock default_clock} {reset no_reset} {args {}} {results {}} {enable EN_m3} {ready RDY_m3}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}}} {rg1 MOD {ports {{RST Prelude.Reset} {CLK Prelude.Clock} {CLK_GATE Prelude.Bool} {EN Prelude.Bool}}}} {rg2 mkZeroSize_Sub {ports {{CLK Prelude.Clock} {RST_N Prelude.Reset} {RDY_m1 Prelude.Bool} {m2_y Prelude.Bool} {EN_m2 Prelude.Bool} {RDY_m2 Prelude.Bool} {EN_m3 Prelude.Bool} {RDY_m3 Prelude.Bool}}}} ---------- -{interface {{method m1 m1 {clock no_clock} {reset no_reset} {args {}} {ready RDY_m1}} {method m2 m2 {clock default_clock} {reset no_reset} {args {{{name m2_y} {port m2_y} {size 1}}}} {enable EN_m2} {ready RDY_m2}} {method m3 m3 {clock default_clock} {reset no_reset} {args {}} {enable EN_m3} {ready RDY_m3}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}} +{interface {{method m1 m1 {clock no_clock} {reset no_reset} {args {}} {results {}} {ready RDY_m1}} {method m2 m2 {clock default_clock} {reset no_reset} {args {{{name m2_y} {port m2_y} {size 1}}}} {results {}} {enable EN_m2} {ready RDY_m2}} {method m3 m3 {clock default_clock} {reset no_reset} {args {}} {results {}} {enable EN_m3} {ready RDY_m3}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}} {CLK Prelude.Clock} {RST_N Prelude.Reset} {RDY_m1 Prelude.Bool} {m2_y Prelude.Bool} {EN_m2 Prelude.Bool} {RDY_m2 Prelude.Bool} {EN_m3 Prelude.Bool} {RDY_m3 Prelude.Bool} ---------- diff --git a/testsuite/bsc.bluetcl/targeted/port_types/zero_size.tcl.bluetcl-out.expected b/testsuite/bsc.bluetcl/targeted/port_types/zero_size.tcl.bluetcl-out.expected index 4d5264b9d..e62ad7fa7 100644 --- a/testsuite/bsc.bluetcl/targeted/port_types/zero_size.tcl.bluetcl-out.expected +++ b/testsuite/bsc.bluetcl/targeted/port_types/zero_size.tcl.bluetcl-out.expected @@ -1,11 +1,11 @@ -verilog mkZeroSize_Sub sysZeroSize ---------- -{rg1 MOD {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {}} {enable EN}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}}}}} {args {{reset _rst__1 {port RST} {clock _clk__1}} {clock _clk__1 {osc CLK} {gate CLK_GATE}}}}} {rg2 mkZeroSize_Sub {interface {{method m1 m1 {clock no_clock} {reset no_reset} {args {}} {ready RDY_m1}} {method m2 m2 {clock default_clock} {reset no_reset} {args {{{port m2_y} {size 1}}}} {enable EN_m2} {ready RDY_m2}} {method m3 m3 {clock default_clock} {reset no_reset} {args {}} {enable EN_m3} {ready RDY_m3}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}}} +{rg1 MOD {interface {{method _write _write {clock _clk__1} {reset _rst__1} {args {}} {results {}} {enable EN}} {method _read _read {clock _clk__1} {reset _rst__1} {args {}} {results {}}}}} {args {{reset _rst__1 {port RST} {clock _clk__1}} {clock _clk__1 {osc CLK} {gate CLK_GATE}}}}} {rg2 mkZeroSize_Sub {interface {{method m1 m1 {clock no_clock} {reset no_reset} {args {}} {results {}} {ready RDY_m1}} {method m2 m2 {clock default_clock} {reset no_reset} {args {{{port m2_y} {size 1}}}} {results {}} {enable EN_m2} {ready RDY_m2}} {method m3 m3 {clock default_clock} {reset no_reset} {args {}} {results {}} {enable EN_m3} {ready RDY_m3}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}}} {rg1 MOD {ports {{RST Reset} {CLK Clock} {CLK_GATE Bool} {EN Bool}}}} {rg2 mkZeroSize_Sub {ports {{CLK Clock} {RST_N Reset} {RDY_m1 Bool} {m2_y Bool} {EN_m2 Bool} {RDY_m2 Bool} {EN_m3 Bool} {RDY_m3 Bool}}}} ---------- -{interface {{method m1 m1 {clock no_clock} {reset no_reset} {args {}} {ready RDY_m1}} {method m2 m2 {clock default_clock} {reset no_reset} {args {{{name m2_y} {port m2_y} {size 1}}}} {enable EN_m2} {ready RDY_m2}} {method m3 m3 {clock default_clock} {reset no_reset} {args {}} {enable EN_m3} {ready RDY_m3}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}} +{interface {{method m1 m1 {clock no_clock} {reset no_reset} {args {}} {results {}} {ready RDY_m1}} {method m2 m2 {clock default_clock} {reset no_reset} {args {{{name m2_y} {port m2_y} {size 1}}}} {results {}} {enable EN_m2} {ready RDY_m2}} {method m3 m3 {clock default_clock} {reset no_reset} {args {}} {results {}} {enable EN_m3} {ready RDY_m3}}}} {args {{clock default_clock {osc CLK}} {reset default_reset {port RST_N} {clock default_clock}}}} {CLK Clock} {RST_N Reset} {RDY_m1 Bool} {m2_y Bool} {EN_m2 Bool} {RDY_m2 Bool} {EN_m3 Bool} {RDY_m3 Bool} ---------- diff --git a/testsuite/bsc.bugs/bluespec_inc/b1354/mkMulti.v.expected b/testsuite/bsc.bugs/bluespec_inc/b1354/mkMulti.v.expected index dc2fccd28..e8decbc3c 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b1354/mkMulti.v.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b1354/mkMulti.v.expected @@ -194,22 +194,22 @@ module mkMulti(CLK, wire rs_3$WE; // inputs to muxes for submodule ports - wire MUX_vec_0$write_1__SEL_1, - MUX_vec_1$write_1__SEL_1, - MUX_vec_10$write_1__SEL_1, - MUX_vec_11$write_1__SEL_1, - MUX_vec_12$write_1__SEL_1, - MUX_vec_13$write_1__SEL_1, - MUX_vec_14$write_1__SEL_1, - MUX_vec_15$write_1__SEL_1, - MUX_vec_2$write_1__SEL_1, - MUX_vec_3$write_1__SEL_1, - MUX_vec_4$write_1__SEL_1, - MUX_vec_5$write_1__SEL_1, - MUX_vec_6$write_1__SEL_1, - MUX_vec_7$write_1__SEL_1, - MUX_vec_8$write_1__SEL_1, - MUX_vec_9$write_1__SEL_1; + wire MUX_vec_0$write_ARG_1__SEL_1, + MUX_vec_1$write_ARG_1__SEL_1, + MUX_vec_10$write_ARG_1__SEL_1, + MUX_vec_11$write_ARG_1__SEL_1, + MUX_vec_12$write_ARG_1__SEL_1, + MUX_vec_13$write_ARG_1__SEL_1, + MUX_vec_14$write_ARG_1__SEL_1, + MUX_vec_15$write_ARG_1__SEL_1, + MUX_vec_2$write_ARG_1__SEL_1, + MUX_vec_3$write_ARG_1__SEL_1, + MUX_vec_4$write_ARG_1__SEL_1, + MUX_vec_5$write_ARG_1__SEL_1, + MUX_vec_6$write_ARG_1__SEL_1, + MUX_vec_7$write_ARG_1__SEL_1, + MUX_vec_8$write_ARG_1__SEL_1, + MUX_vec_9$write_ARG_1__SEL_1; // remaining internal signals reg SEL_ARR_vec_0_vec_1_vec_2_vec_3_vec_4_vec_5_ve_ETC___d18, @@ -312,115 +312,115 @@ module mkMulti(CLK, .D_OUT_5()); // inputs to muxes for submodule ports - assign MUX_vec_0$write_1__SEL_1 = EN_write2 && write2_addr == 4'd0 ; - assign MUX_vec_1$write_1__SEL_1 = EN_write2 && write2_addr == 4'd1 ; - assign MUX_vec_10$write_1__SEL_1 = EN_write2 && write2_addr == 4'd10 ; - assign MUX_vec_11$write_1__SEL_1 = EN_write2 && write2_addr == 4'd11 ; - assign MUX_vec_12$write_1__SEL_1 = EN_write2 && write2_addr == 4'd12 ; - assign MUX_vec_13$write_1__SEL_1 = EN_write2 && write2_addr == 4'd13 ; - assign MUX_vec_14$write_1__SEL_1 = EN_write2 && write2_addr == 4'd14 ; - assign MUX_vec_15$write_1__SEL_1 = EN_write2 && write2_addr == 4'd15 ; - assign MUX_vec_2$write_1__SEL_1 = EN_write2 && write2_addr == 4'd2 ; - assign MUX_vec_3$write_1__SEL_1 = EN_write2 && write2_addr == 4'd3 ; - assign MUX_vec_4$write_1__SEL_1 = EN_write2 && write2_addr == 4'd4 ; - assign MUX_vec_5$write_1__SEL_1 = EN_write2 && write2_addr == 4'd5 ; - assign MUX_vec_6$write_1__SEL_1 = EN_write2 && write2_addr == 4'd6 ; - assign MUX_vec_7$write_1__SEL_1 = EN_write2 && write2_addr == 4'd7 ; - assign MUX_vec_8$write_1__SEL_1 = EN_write2 && write2_addr == 4'd8 ; - assign MUX_vec_9$write_1__SEL_1 = EN_write2 && write2_addr == 4'd9 ; + assign MUX_vec_0$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd0 ; + assign MUX_vec_1$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd1 ; + assign MUX_vec_10$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd10 ; + assign MUX_vec_11$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd11 ; + assign MUX_vec_12$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd12 ; + assign MUX_vec_13$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd13 ; + assign MUX_vec_14$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd14 ; + assign MUX_vec_15$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd15 ; + assign MUX_vec_2$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd2 ; + assign MUX_vec_3$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd3 ; + assign MUX_vec_4$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd4 ; + assign MUX_vec_5$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd5 ; + assign MUX_vec_6$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd6 ; + assign MUX_vec_7$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd7 ; + assign MUX_vec_8$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd8 ; + assign MUX_vec_9$write_ARG_1__SEL_1 = EN_write2 && write2_addr == 4'd9 ; // register vec_0 - assign vec_0$D_IN = MUX_vec_0$write_1__SEL_1 ; + assign vec_0$D_IN = MUX_vec_0$write_ARG_1__SEL_1 ; assign vec_0$EN = EN_write1 && write1_addr == 4'd0 || EN_write2 && write2_addr == 4'd0 ; // register vec_1 - assign vec_1$D_IN = MUX_vec_1$write_1__SEL_1 ; + assign vec_1$D_IN = MUX_vec_1$write_ARG_1__SEL_1 ; assign vec_1$EN = EN_write1 && write1_addr == 4'd1 || EN_write2 && write2_addr == 4'd1 ; // register vec_10 - assign vec_10$D_IN = MUX_vec_10$write_1__SEL_1 ; + assign vec_10$D_IN = MUX_vec_10$write_ARG_1__SEL_1 ; assign vec_10$EN = EN_write1 && write1_addr == 4'd10 || EN_write2 && write2_addr == 4'd10 ; // register vec_11 - assign vec_11$D_IN = MUX_vec_11$write_1__SEL_1 ; + assign vec_11$D_IN = MUX_vec_11$write_ARG_1__SEL_1 ; assign vec_11$EN = EN_write1 && write1_addr == 4'd11 || EN_write2 && write2_addr == 4'd11 ; // register vec_12 - assign vec_12$D_IN = MUX_vec_12$write_1__SEL_1 ; + assign vec_12$D_IN = MUX_vec_12$write_ARG_1__SEL_1 ; assign vec_12$EN = EN_write1 && write1_addr == 4'd12 || EN_write2 && write2_addr == 4'd12 ; // register vec_13 - assign vec_13$D_IN = MUX_vec_13$write_1__SEL_1 ; + assign vec_13$D_IN = MUX_vec_13$write_ARG_1__SEL_1 ; assign vec_13$EN = EN_write1 && write1_addr == 4'd13 || EN_write2 && write2_addr == 4'd13 ; // register vec_14 - assign vec_14$D_IN = MUX_vec_14$write_1__SEL_1 ; + assign vec_14$D_IN = MUX_vec_14$write_ARG_1__SEL_1 ; assign vec_14$EN = EN_write1 && write1_addr == 4'd14 || EN_write2 && write2_addr == 4'd14 ; // register vec_15 - assign vec_15$D_IN = MUX_vec_15$write_1__SEL_1 ; + assign vec_15$D_IN = MUX_vec_15$write_ARG_1__SEL_1 ; assign vec_15$EN = EN_write1 && write1_addr == 4'd15 || EN_write2 && write2_addr == 4'd15 ; // register vec_2 - assign vec_2$D_IN = MUX_vec_2$write_1__SEL_1 ; + assign vec_2$D_IN = MUX_vec_2$write_ARG_1__SEL_1 ; assign vec_2$EN = EN_write1 && write1_addr == 4'd2 || EN_write2 && write2_addr == 4'd2 ; // register vec_3 - assign vec_3$D_IN = MUX_vec_3$write_1__SEL_1 ; + assign vec_3$D_IN = MUX_vec_3$write_ARG_1__SEL_1 ; assign vec_3$EN = EN_write1 && write1_addr == 4'd3 || EN_write2 && write2_addr == 4'd3 ; // register vec_4 - assign vec_4$D_IN = MUX_vec_4$write_1__SEL_1 ; + assign vec_4$D_IN = MUX_vec_4$write_ARG_1__SEL_1 ; assign vec_4$EN = EN_write1 && write1_addr == 4'd4 || EN_write2 && write2_addr == 4'd4 ; // register vec_5 - assign vec_5$D_IN = MUX_vec_5$write_1__SEL_1 ; + assign vec_5$D_IN = MUX_vec_5$write_ARG_1__SEL_1 ; assign vec_5$EN = EN_write1 && write1_addr == 4'd5 || EN_write2 && write2_addr == 4'd5 ; // register vec_6 - assign vec_6$D_IN = MUX_vec_6$write_1__SEL_1 ; + assign vec_6$D_IN = MUX_vec_6$write_ARG_1__SEL_1 ; assign vec_6$EN = EN_write1 && write1_addr == 4'd6 || EN_write2 && write2_addr == 4'd6 ; // register vec_7 - assign vec_7$D_IN = MUX_vec_7$write_1__SEL_1 ; + assign vec_7$D_IN = MUX_vec_7$write_ARG_1__SEL_1 ; assign vec_7$EN = EN_write1 && write1_addr == 4'd7 || EN_write2 && write2_addr == 4'd7 ; // register vec_8 - assign vec_8$D_IN = MUX_vec_8$write_1__SEL_1 ; + assign vec_8$D_IN = MUX_vec_8$write_ARG_1__SEL_1 ; assign vec_8$EN = EN_write1 && write1_addr == 4'd8 || EN_write2 && write2_addr == 4'd8 ; // register vec_9 - assign vec_9$D_IN = MUX_vec_9$write_1__SEL_1 ; + assign vec_9$D_IN = MUX_vec_9$write_ARG_1__SEL_1 ; assign vec_9$EN = EN_write1 && write1_addr == 4'd9 || EN_write2 && write2_addr == 4'd9 ; diff --git a/testsuite/bsc.bugs/bluespec_inc/b1490/b1490.exp b/testsuite/bsc.bugs/bluespec_inc/b1490/b1490.exp index 0982c1fa2..b529df206 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b1490/b1490.exp +++ b/testsuite/bsc.bugs/bluespec_inc/b1490/b1490.exp @@ -9,7 +9,7 @@ proc rts_flags { heapsize } { # ----- compile_verilog_pass Bug1490Bool.bsv {} $rtsflags -compile_verilog_pass Bug1490MyBool.bsv {} $rtsflags +compile_verilog_pass Bug1490MyBool.bsv {} [rts_flags 300] compile_verilog_pass Bug1490MyUnion.bsv {} [rts_flags 272] compile_verilog_pass Bug1490MyEnum.bsv {} $rtsflags diff --git a/testsuite/bsc.bugs/bluespec_inc/b1610/Test2.bs b/testsuite/bsc.bugs/bluespec_inc/b1610/Test2.bs index 20b45d091..9eb201aa5 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b1610/Test2.bs +++ b/testsuite/bsc.bugs/bluespec_inc/b1610/Test2.bs @@ -1,7 +1,7 @@ package Test2 where interface RegPrimPairBoolMaybeBitSizeOfBit32_ = - _write :: Bit 34 -> ActionValue_ 0 + _write :: Bit 34 -> ActionValue_ (Bit 0) fromRegPrimPairBoolMaybeBitSizeOfBit32_ :: (Bits (Bool, Maybe (Bit (SizeOf (Bit 32)))) 34) => diff --git a/testsuite/bsc.bugs/bluespec_inc/b1758/b1758.exp b/testsuite/bsc.bugs/bluespec_inc/b1758/b1758.exp index e9dcc3bca..5a00dd66b 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b1758/b1758.exp +++ b/testsuite/bsc.bugs/bluespec_inc/b1758/b1758.exp @@ -8,12 +8,10 @@ compile_verilog_pass ZeroBitValueMethod.bsv {} {-dexpanded -dATS} # Test that the method reference has been replaced by 0 in the evaluator if { $vtest == 1 } { - # XXX This still need to be fixed - find_regexp ZeroBitValueMethod.bsv.bsc-vcomp-out \ + find_regexp_fail ZeroBitValueMethod.bsv.bsc-vcomp-out \ {\= \.ZeroBitValueMethod\.getVal g} - # XXX AConv doesn't replace it either find_regexp ZeroBitValueMethod.bsv.bsc-vcomp-out \ - {\= g\.getVal} + {\=\=> Prelude\.\$display#0 "v \= %b" 0} } # ----- @@ -23,12 +21,10 @@ compile_verilog_pass ZeroBitActionValueMethod.bsv {} {-dexpanded -dATS} # Test that the method reference has been replaced by 0 in the evaluator if { $vtest == 1 } { - # XXX This still need to be fixed - find_regexp ZeroBitActionValueMethod.bsv.bsc-vcomp-out \ + find_regexp_fail ZeroBitActionValueMethod.bsv.bsc-vcomp-out \ {\= \.Prelude\.avValue_ ·0 \(\.ZeroBitActionValueMethod\.get g\)} - # At least AConv replaces it find_regexp ZeroBitActionValueMethod.bsv.bsc-vcomp-out \ - {g\.get\; p\.put 0\'d0\;} + {g\.get\; p\.put\;} } # ----- diff --git a/testsuite/bsc.bugs/bluespec_inc/b262/sysBug262Opt.v.expected b/testsuite/bsc.bugs/bluespec_inc/b262/sysBug262Opt.v.expected index 8c0f18456..c1b756af0 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b262/sysBug262Opt.v.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b262/sysBug262Opt.v.expected @@ -39,10 +39,10 @@ module sysBug262Opt(CLK, wire r$EN; // inputs to muxes for submodule ports - wire [19 : 0] MUX_r$write_1__VAL_1; + wire [19 : 0] MUX_r$write_ARG_1__VAL_1; // inputs to muxes for submodule ports - assign MUX_r$write_1__VAL_1 = + assign MUX_r$write_ARG_1__VAL_1 = { 1'd0, 19'b0101010101010101010 /* unspecified value */ } ; // register done @@ -50,7 +50,7 @@ module sysBug262Opt(CLK, assign done$EN = !done ; // register r - assign r$D_IN = done ? MUX_r$write_1__VAL_1 : 20'd524293 ; + assign r$D_IN = done ? MUX_r$write_ARG_1__VAL_1 : 20'd524293 ; assign r$EN = 1'b1 ; // handling of inlined registers diff --git a/testsuite/bsc.bugs/bluespec_inc/b292/mkDesign.v.expected b/testsuite/bsc.bugs/bluespec_inc/b292/mkDesign.v.expected index 7d9339f4a..81ac871ff 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b292/mkDesign.v.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b292/mkDesign.v.expected @@ -86,8 +86,8 @@ module mkDesign(clk, wire i_multiplicand$EN; // remaining internal signals - wire [7 : 0] x__h508, x__h592, x__h741; - wire [3 : 0] x__h704, x__h778; + wire [7 : 0] x__h1117, x__h825, x__h919; + wire [3 : 0] x__h1081, x__h1152; // value method done assign done = i_done_reg ; @@ -99,7 +99,7 @@ module mkDesign(clk, assign i_acc$D_IN = (shift_and_add_load && i_count == 4'd0) ? 8'd0 : - (i_mult[0] ? x__h508 : i_acc) ; + (i_mult[0] ? x__h825 : i_acc) ; assign i_acc$EN = shift_and_add_load && i_count == 4'd0 || i_enable && i_count != 4'd4 ; @@ -108,7 +108,7 @@ module mkDesign(clk, assign i_count$D_IN = (shift_and_add_load && i_count == 4'd0) ? 4'd0 : - ((i_enable && i_count != 4'd4) ? x__h778 : 4'd0) ; + ((i_enable && i_count != 4'd4) ? x__h1152 : 4'd0) ; assign i_count$EN = 1'd1 ; // register i_done_reg @@ -127,24 +127,24 @@ module mkDesign(clk, assign i_mult$D_IN = (shift_and_add_load && i_count == 4'd0) ? shift_and_add_b : - x__h704 ; + x__h1081 ; assign i_mult$EN = shift_and_add_load && i_count == 4'd0 || i_enable && i_count != 4'd4 ; // register i_multiplicand assign i_multiplicand$D_IN = - (shift_and_add_load && i_count == 4'd0) ? x__h592 : x__h741 ; + (shift_and_add_load && i_count == 4'd0) ? x__h919 : x__h1117 ; assign i_multiplicand$EN = shift_and_add_load && i_count == 4'd0 || i_enable && i_count != 4'd4 ; // remaining internal signals - assign x__h592 = { 4'b0, shift_and_add_a } ; - assign x__h508 = i_acc + i_multiplicand ; - assign x__h704 = { 1'd0, i_mult[3:1] } ; - assign x__h741 = { i_multiplicand[6:0], 1'd0 } ; - assign x__h778 = i_count + 4'd1 ; + assign x__h1081 = { 1'd0, i_mult[3:1] } ; + assign x__h1117 = { i_multiplicand[6:0], 1'd0 } ; + assign x__h1152 = i_count + 4'd1 ; + assign x__h825 = i_acc + i_multiplicand ; + assign x__h919 = { 4'b0, shift_and_add_a } ; // handling of inlined registers diff --git a/testsuite/bsc.bugs/bluespec_inc/b293/mkDesign1.v.expected b/testsuite/bsc.bugs/bluespec_inc/b293/mkDesign1.v.expected index f6ee37482..8002f04dc 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b293/mkDesign1.v.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b293/mkDesign1.v.expected @@ -86,8 +86,8 @@ module mkDesign1(clk, wire multiplier$EN; // inputs to muxes for submodule ports - wire [7 : 0] MUX_multiplicand$write_1__VAL_1; - wire MUX_accumulator$write_1__SEL_1; + wire [7 : 0] MUX_multiplicand$write_ARG_1__VAL_1; + wire MUX_accumulator$write_ARG_1__SEL_1; // value method done assign done = done_reg ; @@ -96,13 +96,13 @@ module mkDesign1(clk, assign product = accumulator ; // inputs to muxes for submodule ports - assign MUX_accumulator$write_1__SEL_1 = + assign MUX_accumulator$write_ARG_1__SEL_1 = shift_and_add_load && count == 4'd0 ; - assign MUX_multiplicand$write_1__VAL_1 = { 4'b0, shift_and_add_a } ; + assign MUX_multiplicand$write_ARG_1__VAL_1 = { 4'b0, shift_and_add_a } ; // register accumulator assign accumulator$D_IN = 8'd0 ; - assign accumulator$EN = MUX_accumulator$write_1__SEL_1 ; + assign accumulator$EN = MUX_accumulator$write_ARG_1__SEL_1 ; // register count assign count$D_IN = 4'd0 ; @@ -117,12 +117,12 @@ module mkDesign1(clk, assign enable$EN = 1'b1 ; // register multiplicand - assign multiplicand$D_IN = MUX_multiplicand$write_1__VAL_1 ; - assign multiplicand$EN = MUX_accumulator$write_1__SEL_1 ; + assign multiplicand$D_IN = MUX_multiplicand$write_ARG_1__VAL_1 ; + assign multiplicand$EN = MUX_accumulator$write_ARG_1__SEL_1 ; // register multiplier assign multiplier$D_IN = shift_and_add_b ; - assign multiplier$EN = MUX_accumulator$write_1__SEL_1 ; + assign multiplier$EN = MUX_accumulator$write_ARG_1__SEL_1 ; // handling of inlined registers diff --git a/testsuite/bsc.bugs/bluespec_inc/b302/mkDesign.v.expected b/testsuite/bsc.bugs/bluespec_inc/b302/mkDesign.v.expected index 493ba1aa3..c8146ff36 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b302/mkDesign.v.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b302/mkDesign.v.expected @@ -46,23 +46,23 @@ module mkDesign(clk, wire [10 : 0] result; // remaining internal signals - wire [5 : 0] _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55, - _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56, - _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57, - _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58, - _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59, - x__h144, - x__h146, - x__h240, - x__h242, - x__h336, - x__h338, - x__h432, - x__h434, - x__h528, - x__h530, - y__h147; - wire [4 : 0] IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d54, + wire [5 : 0] _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d45, + _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d36, + _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d27, + _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d18, + _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d9, + x__h353, + x__h355, + x__h431, + x__h433, + x__h509, + x__h511, + x__h587, + x__h589, + x__h665, + x__h667, + y__h356; + wire [4 : 0] IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d42, IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC__q4, IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d53, IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC__q3, @@ -70,15 +70,16 @@ module mkDesign(clk, IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC__q2, IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d51, IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC__q1, - _theResult_____1_snd__h939, - notB__h48, - quotient__h63; + notB__h247, + quotient__h262; // value method result assign result = { result_a[9:5] >= result_b, - _theResult_____1_snd__h939, - quotient__h63 } ; + _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d45[5] ? + _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d45[4:0] : + IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d42, + quotient__h262 } ; // remaining internal signals assign IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d54 = @@ -109,45 +110,41 @@ module mkDesign(clk, _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59[5] ? _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59[4:0] : result_a[8:4] ; - assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55 = - x__h144 + 6'd1 ; - assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56 = - x__h240 + 6'd1 ; - assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57 = - x__h336 + 6'd1 ; - assign _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58 = - x__h432 + 6'd1 ; - assign _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59 = - x__h528 + 6'd1 ; - assign _theResult_____1_snd__h939 = - _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55[5] ? - _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55[4:0] : - IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d54 ; - assign notB__h48 = ~result_b ; - assign quotient__h63 = - { _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59[5], - _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58[5], - _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57[5], - _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56[5], - _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55[5] } ; - assign x__h144 = x__h146 + y__h147 ; - assign x__h146 = + assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d45 = + x__h353 + 6'd1 ; + assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d36 = + x__h431 + 6'd1 ; + assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d27 = + x__h509 + 6'd1 ; + assign _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d18 = + x__h587 + 6'd1 ; + assign _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d9 = + x__h665 + 6'd1 ; + assign notB__h247 = ~result_b ; + assign quotient__h262 = + { _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d9[5], + _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d18[5], + _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d27[5], + _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d36[5], + _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d45[5] } ; + assign x__h353 = x__h355 + y__h356 ; + assign x__h355 = { 1'd0, - IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d54 } ; - assign x__h240 = x__h242 + y__h147 ; - assign x__h242 = + IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d42 } ; + assign x__h431 = x__h433 + y__h356 ; + assign x__h433 = { 1'd0, - IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d53 } ; - assign x__h336 = x__h338 + y__h147 ; - assign x__h338 = + IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d33 } ; + assign x__h509 = x__h511 + y__h356 ; + assign x__h511 = { 1'd0, - IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d52 } ; - assign x__h432 = x__h434 + y__h147 ; - assign x__h434 = + IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d24 } ; + assign x__h587 = x__h589 + y__h356 ; + assign x__h589 = { 1'd0, - IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d51 } ; - assign x__h528 = x__h530 + y__h147 ; - assign x__h530 = { 1'd0, result_a[8:4] } ; - assign y__h147 = { 1'd0, notB__h48 } ; + IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d15 } ; + assign x__h665 = x__h667 + y__h356 ; + assign x__h667 = { 1'd0, result_a[8:4] } ; + assign y__h356 = { 1'd0, notB__h247 } ; endmodule // mkDesign diff --git a/testsuite/bsc.codegen/foreign/BDPIActionValue_.bsv b/testsuite/bsc.codegen/foreign/BDPIActionValue_.bsv index 6c4fba560..681ab00ad 100644 --- a/testsuite/bsc.codegen/foreign/BDPIActionValue_.bsv +++ b/testsuite/bsc.codegen/foreign/BDPIActionValue_.bsv @@ -1,4 +1,4 @@ -import "BDPI" function ActionValue_#(32) my_time (Bit#(8) x); +import "BDPI" function ActionValue_#(Bit#(32)) my_time (Bit#(8) x); function ActionValue#(Bit#(32)) my_time2(Bit#(8) x); let y = my_time(x); diff --git a/testsuite/bsc.doc/UserGuide_mkGCD.v.expected b/testsuite/bsc.doc/UserGuide_mkGCD.v.expected index 4882be5fa..97587b770 100644 --- a/testsuite/bsc.doc/UserGuide_mkGCD.v.expected +++ b/testsuite/bsc.doc/UserGuide_mkGCD.v.expected @@ -71,7 +71,7 @@ module mkGCD(CLK, wire WILL_FIRE_RL_flip, WILL_FIRE_RL_sub; // inputs to muxes for submodule ports - wire [50 : 0] MUX_reg_2$write_1__VAL_3; + wire [50 : 0] MUX_reg_2$write_ARG_1__VAL_3; // remaining internal signals wire reg_1_ULE_reg_2___d3; @@ -90,7 +90,7 @@ module mkGCD(CLK, assign WILL_FIRE_RL_sub = reg_1_ULE_reg_2___d3 && reg_2 != 51'd0 ; // inputs to muxes for submodule ports - assign MUX_reg_2$write_1__VAL_3 = reg_2 - reg_1 ; + assign MUX_reg_2$write_ARG_1__VAL_3 = reg_2 - reg_1 ; // register reg_1 assign reg_1$D_IN = EN_start ? start_num1 : reg_2 ; @@ -100,12 +100,12 @@ module mkGCD(CLK, always@(EN_start or start_num2 or WILL_FIRE_RL_flip or - reg_1 or WILL_FIRE_RL_sub or MUX_reg_2$write_1__VAL_3) + reg_1 or WILL_FIRE_RL_sub or MUX_reg_2$write_ARG_1__VAL_3) begin case (1'b1) // synopsys parallel_case EN_start: reg_2$D_IN = start_num2; WILL_FIRE_RL_flip: reg_2$D_IN = reg_1; - WILL_FIRE_RL_sub: reg_2$D_IN = MUX_reg_2$write_1__VAL_3; + WILL_FIRE_RL_sub: reg_2$D_IN = MUX_reg_2$write_ARG_1__VAL_3; default: reg_2$D_IN = 51'h2AAAAAAAAAAAA /* unspecified value */ ; endcase end diff --git a/testsuite/bsc.evaluator/mkTest.atsexpand.expected b/testsuite/bsc.evaluator/mkTest.atsexpand.expected index c51763160..a18e571f8 100644 --- a/testsuite/bsc.evaluator/mkTest.atsexpand.expected +++ b/testsuite/bsc.evaluator/mkTest.atsexpand.expected @@ -25,7 +25,7 @@ slots :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd1] [] - meth types=[([], Nothing, Just (Bit 1)), ([Bit 1], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 1]), ([Bit 1], Just (Bit 1), [])] port types=D_IN -> Prelude.Bool Q_OUT -> Prelude.Bool slots_1 :: ABSTRACT: Prelude.VReg = RegUN @@ -40,7 +40,7 @@ slots_1 :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd1] [] - meth types=[([], Nothing, Just (Bit 1)), ([Bit 1], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 1]), ([Bit 1], Just (Bit 1), [])] port types=D_IN -> Prelude.Bool Q_OUT -> Prelude.Bool ptr :: ABSTRACT: Prelude.VReg = RegUN @@ -55,7 +55,7 @@ ptr :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd5] [] - meth types=[([], Nothing, Just (Bit 5)), ([Bit 5], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 5]), ([Bit 5], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 5 Q_OUT -> Prelude.Bit 5 pred :: ABSTRACT: Prelude.VReg = RegUN @@ -70,7 +70,7 @@ pred :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd1] [] - meth types=[([], Nothing, Just (Bit 1)), ([Bit 1], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 1]), ([Bit 1], Just (Bit 1), [])] port types=D_IN -> Prelude.Bool Q_OUT -> Prelude.Bool -- AP rules diff --git a/testsuite/bsc.evaluator/mkTest.atsexpand.nolift.expandif.expected b/testsuite/bsc.evaluator/mkTest.atsexpand.nolift.expandif.expected index 5fc0e2430..6f9dfc800 100644 --- a/testsuite/bsc.evaluator/mkTest.atsexpand.nolift.expandif.expected +++ b/testsuite/bsc.evaluator/mkTest.atsexpand.nolift.expandif.expected @@ -25,7 +25,7 @@ slots :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd1] [] - meth types=[([], Nothing, Just (Bit 1)), ([Bit 1], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 1]), ([Bit 1], Just (Bit 1), [])] port types=D_IN -> Prelude.Bool Q_OUT -> Prelude.Bool slots_1 :: ABSTRACT: Prelude.VReg = RegUN @@ -40,7 +40,7 @@ slots_1 :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd1] [] - meth types=[([], Nothing, Just (Bit 1)), ([Bit 1], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 1]), ([Bit 1], Just (Bit 1), [])] port types=D_IN -> Prelude.Bool Q_OUT -> Prelude.Bool ptr :: ABSTRACT: Prelude.VReg = RegUN @@ -55,7 +55,7 @@ ptr :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd5] [] - meth types=[([], Nothing, Just (Bit 5)), ([Bit 5], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 5]), ([Bit 5], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 5 Q_OUT -> Prelude.Bit 5 pred :: ABSTRACT: Prelude.VReg = RegUN @@ -70,7 +70,7 @@ pred :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd1] [] - meth types=[([], Nothing, Just (Bit 1)), ([Bit 1], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 1]), ([Bit 1], Just (Bit 1), [])] port types=D_IN -> Prelude.Bool Q_OUT -> Prelude.Bool -- AP rules diff --git a/testsuite/bsc.evaluator/sysITransformConstantAcrossEquals.atsexpand.expected b/testsuite/bsc.evaluator/sysITransformConstantAcrossEquals.atsexpand.expected index 1254465ff..285e1a3f3 100644 --- a/testsuite/bsc.evaluator/sysITransformConstantAcrossEquals.atsexpand.expected +++ b/testsuite/bsc.evaluator/sysITransformConstantAcrossEquals.atsexpand.expected @@ -25,7 +25,7 @@ r :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd3] [] - meth types=[([], Nothing, Just (Bit 3)), ([Bit 3], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 3]), ([Bit 3], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 3 Q_OUT -> Prelude.Bit 3 x :: ABSTRACT: Prelude.VReg = RegUN @@ -40,7 +40,7 @@ x :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd2] [] - meth types=[([], Nothing, Just (Bit 2)), ([Bit 2], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 2]), ([Bit 2], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 2 Q_OUT -> Prelude.Bit 2 y :: ABSTRACT: Prelude.VReg = RegUN @@ -55,7 +55,7 @@ y :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd2] [] - meth types=[([], Nothing, Just (Bit 2)), ([Bit 2], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 2]), ([Bit 2], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 2 Q_OUT -> Prelude.Bit 2 z :: ABSTRACT: Prelude.VReg = RegUN @@ -70,7 +70,7 @@ z :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd2] [] - meth types=[([], Nothing, Just (Bit 2)), ([Bit 2], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 2]), ([Bit 2], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 2 Q_OUT -> Prelude.Bit 2 -- AP rules diff --git a/testsuite/bsc.evaluator/sysShiftMult.ats.expected b/testsuite/bsc.evaluator/sysShiftMult.ats.expected index 031a4133f..9ffec2982 100644 --- a/testsuite/bsc.evaluator/sysShiftMult.ats.expected +++ b/testsuite/bsc.evaluator/sysShiftMult.ats.expected @@ -25,7 +25,7 @@ x :: ABSTRACT: Prelude.VReg = RegN []) [clock { osc: CLK gate: 1'd1 }, reset { wire: RST_N }, 32'd32, 32'd17] [] - meth types=[([], Nothing, Just (Bit 32)), ([Bit 32], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 32]), ([Bit 32], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 32 Q_OUT -> Prelude.Bit 32 y :: ABSTRACT: Prelude.VReg = RegN @@ -40,29 +40,29 @@ y :: ABSTRACT: Prelude.VReg = RegN []) [clock { osc: CLK gate: 1'd1 }, reset { wire: RST_N }, 32'd32, 32'd24] [] - meth types=[([], Nothing, Just (Bit 32)), ([Bit 32], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 32]), ([Bit 32], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 32 Q_OUT -> Prelude.Bit 32 -- AP local definitions -x__h177 :: Bit 32; -x__h177 = x_BITS_28_TO_0___h184 ++ 3'd0; --- IdProp x__h177[IdP_keep] -x__h145 :: Bit 32; -x__h145 = x_BITS_29_TO_0___h174 ++ 2'd0; --- IdProp x__h145[IdP_keep] -x_BITS_28_TO_0___h184 :: Bit 29; -x_BITS_28_TO_0___h184 = extract x___d1 32'd28 32'd0; --- IdProp x_BITS_28_TO_0___h184[IdP_keep] -x_BITS_29_TO_0___h174 :: Bit 30; -x_BITS_29_TO_0___h174 = extract x___d1 32'd29 32'd0; --- IdProp x_BITS_29_TO_0___h174[IdP_keep] +x__h146 :: Bit 32; +x__h146 = x_BITS_28_TO_0___h153 ++ 3'd0; +-- IdProp x__h146[IdP_keep] +x__h105 :: Bit 32; +x__h105 = x_BITS_29_TO_0___h143 ++ 2'd0; +-- IdProp x__h105[IdP_keep] +x_BITS_28_TO_0___h153 :: Bit 29; +x_BITS_28_TO_0___h153 = extract x___d1 32'd28 32'd0; +-- IdProp x_BITS_28_TO_0___h153[IdP_keep] +x_BITS_29_TO_0___h143 :: Bit 30; +x_BITS_29_TO_0___h143 = extract x___d1 32'd29 32'd0; +-- IdProp x_BITS_29_TO_0___h143[IdP_keep] x___d1 :: Bit 32; x___d1 = x.read; -- IdProp x___d1[IdP_from_rhs] -- AP rules rule RL_unnamed "": when 1'd1 - ==> { x.write x__h145; y.write x__h177; } + ==> { x.write x__h105; y.write x__h146; } [] clock domain = Just (0), resets = [0] -- AP scheduling pragmas diff --git a/testsuite/bsc.interra/messages/EResources/EResources.bs.bsc-vcomp-out.expected b/testsuite/bsc.interra/messages/EResources/EResources.bs.bsc-vcomp-out.expected index 1ace575a0..6b022d6a2 100755 --- a/testsuite/bsc.interra/messages/EResources/EResources.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/messages/EResources/EResources.bs.bsc-vcomp-out.expected @@ -5,5 +5,5 @@ Verilog file created: subtractor.v code generation for mkDifference starts Error: "EResources.bs", line 43, column 13: (G0002) `m.minus' needs more than 1 ports for the following uses: - `m.minus b__h230 b__h231' at "EResources.bs", line 43, column 13 - `m.minus b__h231 b__h230' at "EResources.bs", line 43, column 13 + `m.minus x___d1 y___d2' at "EResources.bs", line 43, column 13 + `m.minus y___d2 x___d1' at "EResources.bs", line 43, column 13 diff --git a/testsuite/bsc.misc/lambda_calculus/lc-sysMultiArityConcat.out.expected b/testsuite/bsc.misc/lambda_calculus/lc-sysMultiArityConcat.out.expected index 4f9606823..fa4e214b9 100644 --- a/testsuite/bsc.misc/lambda_calculus/lc-sysMultiArityConcat.out.expected +++ b/testsuite/bsc.misc/lambda_calculus/lc-sysMultiArityConcat.out.expected @@ -27,12 +27,12 @@ dim_sysMultiArityConcat = rule_RL_d_sysMultiArityConcat :: MOD_sysMultiArityConcat -> (Bool, MOD_sysMultiArityConcat, ()); rule_RL_d_sysMultiArityConcat = (\ (state0 :: MOD_sysMultiArityConcat) -> - let { (def__read__h44 :: Bit #3) = meth_read_RegUN (inst_src1__sysMultiArityConcat state0) - ; (def__read__h76 :: Bit #4) = meth_read_RegUN (inst_src2__sysMultiArityConcat state0) - ; (def__read__h108 :: Bit #5) = meth_read_RegUN (inst_src3__sysMultiArityConcat state0) + let { (def_src1___d1 :: Bit #3) = meth_read_RegUN (inst_src1__sysMultiArityConcat state0) + ; (def_src2___d2 :: Bit #4) = meth_read_RegUN (inst_src2__sysMultiArityConcat state0) + ; (def_src3___d3 :: Bit #5) = meth_read_RegUN (inst_src3__sysMultiArityConcat state0) ; (act1 :: (Bool, MOD_RegUN #12, ())) = meth_write_RegUN - (primConcat def__read__h44 (primConcat def__read__h76 def__read__h108)) + (primConcat def_src1___d1 (primConcat def_src2___d2 def_src3___d3)) (inst_snk__sysMultiArityConcat state0) ; (guard1 :: Bool) = fst3 act1 ; (state1 :: MOD_sysMultiArityConcat) = state0 { inst_snk__sysMultiArityConcat = snd3 act1 } diff --git a/testsuite/bsc.misc/lambda_calculus/lc-sysStructs.out.expected b/testsuite/bsc.misc/lambda_calculus/lc-sysStructs.out.expected index 6b74a042f..7078bcb77 100644 --- a/testsuite/bsc.misc/lambda_calculus/lc-sysStructs.out.expected +++ b/testsuite/bsc.misc/lambda_calculus/lc-sysStructs.out.expected @@ -45,25 +45,25 @@ dim_sysStructs = rule_RL_add_em_sysStructs :: MOD_sysStructs -> (Bool, MOD_sysStructs, ()); rule_RL_add_em_sysStructs = (\ (state0 :: MOD_sysStructs) -> - let { (def_x__h549 :: Bit #9) = meth_read_RegN (inst_a__sysStructs state0) - ; (def_x__h557 :: Bit #9) = meth_read_RegN (inst_b__sysStructs state0) - ; (def_x__h541 :: Bit #9) = primAdd def_x__h549 def_x__h557 - ; (def_x__h529 :: Bit #9) = primAdd def_x__h541 (4 :: Bit #9) - ; (def_s__h482 :: Bit #1) = meth_read_RegN (inst_s__sysStructs state0) - ; (act1 :: (Bool, MOD_RegN #9, ())) = meth_write_RegN def_x__h529 (inst_a__sysStructs state0) + let { (def_x__h542 :: Bit #9) = meth_read_RegN (inst_a__sysStructs state0) + ; (def_x__h550 :: Bit #9) = meth_read_RegN (inst_b__sysStructs state0) + ; (def_x__h534 :: Bit #9) = primAdd def_x__h542 def_x__h550 + ; (def_x__h522 :: Bit #9) = primAdd def_x__h534 (4 :: Bit #9) + ; (def_s__h463 :: Bit #1) = meth_read_RegN (inst_s__sysStructs state0) + ; (act1 :: (Bool, MOD_RegN #9, ())) = meth_write_RegN def_x__h522 (inst_a__sysStructs state0) ; (guard1 :: Bool) = fst3 act1 ; (state1 :: MOD_sysStructs) = state0 { inst_a__sysStructs = snd3 act1 } ; (act2 :: (Bool, MOD_RegN #1, ())) = meth_write_RegN (0 :: Bit #1) (inst_s__sysStructs state1) ; (guard2 :: Bool) = guard1 && (fst3 act2) ; (state2 :: MOD_sysStructs) = state1 { inst_s__sysStructs = snd3 act2 } } - in mktuple ((bitToBool def_s__h482) && guard2) state2 ()); + in mktuple ((bitToBool def_s__h463) && guard2) state2 ()); rule_RL_tss_sysStructs :: MOD_sysStructs -> (Bool, MOD_sysStructs, ()); rule_RL_tss_sysStructs = (\ (state0 :: MOD_sysStructs) -> - let { (def_t1___d8 :: Bit #12) = meth_read_RegUN (inst_t1__sysStructs state0) - ; (def_t2___d6 :: Bit #12) = meth_read_RegUN (inst_t2__sysStructs state0) + let { (def_t2___d6 :: Bit #12) = meth_read_RegUN (inst_t2__sysStructs state0) + ; (def_t1___d8 :: Bit #12) = meth_read_RegUN (inst_t1__sysStructs state0) ; (act1 :: (Bool, MOD_RegUN #12, ())) = meth_write_RegUN (primConcat diff --git a/testsuite/bsc.misc/lambda_calculus/lc-sysTb.out.expected b/testsuite/bsc.misc/lambda_calculus/lc-sysTb.out.expected index 2c6cde4f6..950d5f259 100644 --- a/testsuite/bsc.misc/lambda_calculus/lc-sysTb.out.expected +++ b/testsuite/bsc.misc/lambda_calculus/lc-sysTb.out.expected @@ -30,22 +30,22 @@ dim_sysTb = rule_RL_r0_sysTb :: MOD_sysTb -> (Bool, MOD_sysTb, ()); rule_RL_r0_sysTb = (\ (state0 :: MOD_sysTb) -> - let { (def_b__h284 :: Bit #51) = meth_read_RegN (inst_c1__sysTb state0) - ; (def_b__h285 :: Bit #51) = meth_read_RegN (inst_c2__sysTb state0) - ; (def_state__h244 :: Bit #2) = meth_read_RegN (inst_state__sysTb state0) - ; (def_b__h322 :: Bit #51) = noinline_add def_b__h284 (3 :: Bit #51) - ; (def_b__h345 :: Bit #51) = noinline_add def_b__h285 (2 :: Bit #51) + let { (def_state__h528 :: Bit #2) = meth_read_RegN (inst_state__sysTb state0) + ; (def_c2___d6 :: Bit #51) = meth_read_RegN (inst_c2__sysTb state0) + ; (def_b__h871 :: Bit #51) = noinline_add def_c2___d6 (2 :: Bit #51) + ; (def_c1___d5 :: Bit #51) = meth_read_RegN (inst_c1__sysTb state0) + ; (def_b__h747 :: Bit #51) = noinline_add def_c1___d5 (3 :: Bit #51) ; (def_gcd_RDY_start____d1 :: Bool) = meth_RDY_start_sysMethods (inst_gcd__sysTb state0) - ; (def_state_EQ_0___d3 :: Bool) = primEQ def_state__h244 (0 :: Bit #2) + ; (def_state_EQ_0___d3 :: Bool) = primEQ def_state__h528 (0 :: Bit #2) ; (def_gcd_RDY_start_AND_state_EQ_0___d4 :: Bool) = def_gcd_RDY_start____d1 && def_state_EQ_0___d3 ; (act1 :: (Bool, MOD_sysMethods, ())) = - meth_start_sysMethods def_b__h284 def_b__h285 (inst_gcd__sysTb state0) + meth_start_sysMethods def_c1___d5 def_c2___d6 (inst_gcd__sysTb state0) ; (guard1 :: Bool) = fst3 act1 ; (state1 :: MOD_sysTb) = state0 { inst_gcd__sysTb = snd3 act1 } - ; (act2 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h322 (inst_c1__sysTb state1) + ; (act2 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h747 (inst_c1__sysTb state1) ; (guard2 :: Bool) = guard1 && (fst3 act2) ; (state2 :: MOD_sysTb) = state1 { inst_c1__sysTb = snd3 act2 } - ; (act3 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h345 (inst_c2__sysTb state2) + ; (act3 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h871 (inst_c2__sysTb state2) ; (guard3 :: Bool) = guard2 && (fst3 act3) ; (state3 :: MOD_sysTb) = state2 { inst_c2__sysTb = snd3 act3 } ; (act4 :: (Bool, MOD_RegN #2, ())) = meth_write_RegN (1 :: Bit #2) (inst_state__sysTb state3) @@ -57,18 +57,18 @@ rule_RL_r0_sysTb = rule_RL_r1_sysTb :: MOD_sysTb -> (Bool, MOD_sysTb, ()); rule_RL_r1_sysTb = (\ (state0 :: MOD_sysTb) -> - let { (def_b__h284 :: Bit #51) = meth_read_RegN (inst_c1__sysTb state0) - ; (def_b__h285 :: Bit #51) = meth_read_RegN (inst_c2__sysTb state0) - ; (def_state__h244 :: Bit #2) = meth_read_RegN (inst_state__sysTb state0) - ; (def_b__h322 :: Bit #51) = noinline_add def_b__h284 (3 :: Bit #51) - ; (def_b__h345 :: Bit #51) = noinline_add def_b__h285 (2 :: Bit #51) - ; (def_state_EQ_1___d9 :: Bool) = primEQ def_state__h244 (1 :: Bit #2) + let { (def_state__h528 :: Bit #2) = meth_read_RegN (inst_state__sysTb state0) + ; (def_c2___d6 :: Bit #51) = meth_read_RegN (inst_c2__sysTb state0) + ; (def_b__h871 :: Bit #51) = noinline_add def_c2___d6 (2 :: Bit #51) + ; (def_c1___d5 :: Bit #51) = meth_read_RegN (inst_c1__sysTb state0) + ; (def_b__h747 :: Bit #51) = noinline_add def_c1___d5 (3 :: Bit #51) + ; (def_state_EQ_1___d9 :: Bool) = primEQ def_state__h528 (1 :: Bit #2) ; (act1 :: (Bool, MOD_sysMethods, Bit #51)) = - meth_start_and_result_sysMethods def_b__h284 def_b__h285 (inst_gcd__sysTb state0) + meth_start_and_result_sysMethods def_c1___d5 def_c2___d6 (inst_gcd__sysTb state0) ; (guard1 :: Bool) = fst3 act1 ; (state1 :: MOD_sysTb) = state0 { inst_gcd__sysTb = snd3 act1 } - ; (def_b__h381 :: Bit #51) = thd act1 - ; (def_gcd_start_and_result_0_PLUS_1___d11 :: Bit #51) = primAdd def_b__h381 (1 :: Bit #51) + ; (def_b__h1063 :: Bit #51) = thd act1 + ; (def_gcd_start_and_result_0_PLUS_1___d11 :: Bit #51) = primAdd def_b__h1063 (1 :: Bit #51) ; (act2 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN (primConcat @@ -80,10 +80,10 @@ rule_RL_r1_sysTb = (inst_rg__sysTb state1) ; (guard2 :: Bool) = guard1 && (fst3 act2) ; (state2 :: MOD_sysTb) = state1 { inst_rg__sysTb = snd3 act2 } - ; (act3 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h322 (inst_c1__sysTb state2) + ; (act3 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h747 (inst_c1__sysTb state2) ; (guard3 :: Bool) = guard2 && (fst3 act3) ; (state3 :: MOD_sysTb) = state2 { inst_c1__sysTb = snd3 act3 } - ; (act4 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h345 (inst_c2__sysTb state3) + ; (act4 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h871 (inst_c2__sysTb state3) ; (guard4 :: Bool) = guard3 && (fst3 act4) ; (state4 :: MOD_sysTb) = state3 { inst_c2__sysTb = snd3 act4 } ; (act5 :: (Bool, MOD_RegN #2, ())) = meth_write_RegN (2 :: Bit #2) (inst_state__sysTb state4) @@ -95,11 +95,11 @@ rule_RL_r1_sysTb = rule_RL_r2_sysTb :: MOD_sysTb -> (Bool, MOD_sysTb, ()); rule_RL_r2_sysTb = (\ (state0 :: MOD_sysTb) -> - let { (def_state__h244 :: Bit #2) = meth_read_RegN (inst_state__sysTb state0) + let { (def_state__h528 :: Bit #2) = meth_read_RegN (inst_state__sysTb state0) ; (def_gcd_RDY_result____d14 :: Bool) = meth_RDY_result_sysMethods (inst_gcd__sysTb state0) ; (def_gcd_result____d17 :: Bit #51) = meth_result_sysMethods (inst_gcd__sysTb state0) ; (def_gcd_result__7_PLUS_1___d18 :: Bit #51) = primAdd def_gcd_result____d17 (1 :: Bit #51) - ; (def_state_EQ_2___d15 :: Bool) = primEQ def_state__h244 (2 :: Bit #2) + ; (def_state_EQ_2___d15 :: Bool) = primEQ def_state__h528 (2 :: Bit #2) ; (def_gcd_RDY_result__4_AND_state_EQ_2_5___d16 :: Bool) = def_gcd_RDY_result____d14 && def_state_EQ_2___d15 ; (act1 :: (Bool, MOD_RegN #51, ())) = @@ -119,8 +119,8 @@ rule_RL_r2_sysTb = rule_RL_exit_sysTb :: MOD_sysTb -> (Bool, MOD_sysTb, ()); rule_RL_exit_sysTb = (\ (state0 :: MOD_sysTb) -> - let { (def_b__h284 :: Bit #51) = meth_read_RegN (inst_c1__sysTb state0) - ; (def_c1_ULE_100___d21 :: Bool) = primULE def_b__h284 (100 :: Bit #51) - ; (def_v__h538 :: Bit #64) = (primAny :: Bit #64) + let { (def_c1___d5 :: Bit #51) = meth_read_RegN (inst_c1__sysTb state0) + ; (def_c1_ULE_100___d21 :: Bool) = primULE def_c1___d5 (100 :: Bit #51) + ; (def_v__h1286 :: Bit #64) = (primAny :: Bit #64) } in mktuple (not def_c1_ULE_100___d21) state0 ()); diff --git a/testsuite/bsc.misc/sal/CTX_sysMultiArityConcat.sal.expected b/testsuite/bsc.misc/sal/CTX_sysMultiArityConcat.sal.expected index 7c2b10256..734908d60 100644 --- a/testsuite/bsc.misc/sal/CTX_sysMultiArityConcat.sal.expected +++ b/testsuite/bsc.misc/sal/CTX_sysMultiArityConcat.sal.expected @@ -16,12 +16,12 @@ BEGIN #) ; rule_RL_d (state0 : STATE) : [ BOOLEAN, STATE ] = - LET def__read__h44 : Bit{3}!T = CTX_RegUN{3}!meth_read(state0.inst_src1) - IN LET def__read__h76 : Bit{4}!T = CTX_RegUN{4}!meth_read(state0.inst_src2) - IN LET def__read__h108 : Bit{5}!T = CTX_RegUN{5}!meth_read(state0.inst_src3) + LET def_src1___d1 : Bit{3}!T = CTX_RegUN{3}!meth_read(state0.inst_src1) + IN LET def_src2___d2 : Bit{4}!T = CTX_RegUN{4}!meth_read(state0.inst_src2) + IN LET def_src3___d3 : Bit{5}!T = CTX_RegUN{5}!meth_read(state0.inst_src3) IN LET act1 : [ CTX_RegUN{12}!STATE, Unit!T ] = - CTX_RegUN{12}!meth_write(Prim2{3,9}!primConcat(def__read__h44, - Prim2{4,5}!primConcat(def__read__h76, def__read__h108)), + CTX_RegUN{12}!meth_write(Prim2{3,9}!primConcat(def_src1___d1, + Prim2{4,5}!primConcat(def_src2___d2, def_src3___d3)), state0.inst_snk) IN LET state1 : STATE = state0 WITH .inst_snk := act1.1 IN ( TRUE, state1 ) ; diff --git a/testsuite/bsc.misc/sal/CTX_sysStructs.sal.expected b/testsuite/bsc.misc/sal/CTX_sysStructs.sal.expected index 8381f1ead..ff5e6350d 100644 --- a/testsuite/bsc.misc/sal/CTX_sysStructs.sal.expected +++ b/testsuite/bsc.misc/sal/CTX_sysStructs.sal.expected @@ -28,21 +28,21 @@ BEGIN #) ; rule_RL_add_em (state0 : STATE) : [ BOOLEAN, STATE ] = - LET def_x__h549 : Bit{9}!T = CTX_RegN{9}!meth_read(state0.inst_a) - IN LET def_x__h557 : Bit{9}!T = CTX_RegN{9}!meth_read(state0.inst_b) - IN LET def_x__h541 : Bit{9}!T = Prim1{9}!primAdd(def_x__h549, def_x__h557) - IN LET def_x__h529 : Bit{9}!T = Prim1{9}!primAdd(def_x__h541, Bit{9}!mkConst(4)) - IN LET def_s__h482 : Bit{1}!T = CTX_RegN{1}!meth_read(state0.inst_s) - IN LET act1 : [ CTX_RegN{9}!STATE, Unit!T ] = CTX_RegN{9}!meth_write(def_x__h529, state0.inst_a) + LET def_x__h542 : Bit{9}!T = CTX_RegN{9}!meth_read(state0.inst_a) + IN LET def_x__h550 : Bit{9}!T = CTX_RegN{9}!meth_read(state0.inst_b) + IN LET def_x__h534 : Bit{9}!T = Prim1{9}!primAdd(def_x__h542, def_x__h550) + IN LET def_x__h522 : Bit{9}!T = Prim1{9}!primAdd(def_x__h534, Bit{9}!mkConst(4)) + IN LET def_s__h463 : Bit{1}!T = CTX_RegN{1}!meth_read(state0.inst_s) + IN LET act1 : [ CTX_RegN{9}!STATE, Unit!T ] = CTX_RegN{9}!meth_write(def_x__h522, state0.inst_a) IN LET state1 : STATE = state0 WITH .inst_a := act1.1 IN LET act2 : [ CTX_RegN{1}!STATE, Unit!T ] = CTX_RegN{1}!meth_write(Bit{1}!mkConst(0), state1.inst_s) IN LET state2 : STATE = state1 WITH .inst_s := act2.1 - IN ( Prim!bitToBool(def_s__h482), state2 ) ; + IN ( Prim!bitToBool(def_s__h463), state2 ) ; rule_RL_tss (state0 : STATE) : [ BOOLEAN, STATE ] = - LET def_t1___d8 : Bit{12}!T = CTX_RegUN{12}!meth_read(state0.inst_t1) - IN LET def_t2___d6 : Bit{12}!T = CTX_RegUN{12}!meth_read(state0.inst_t2) + LET def_t2___d6 : Bit{12}!T = CTX_RegUN{12}!meth_read(state0.inst_t2) + IN LET def_t1___d8 : Bit{12}!T = CTX_RegUN{12}!meth_read(state0.inst_t1) IN LET act1 : [ CTX_RegUN{12}!STATE, Unit!T ] = CTX_RegUN{12}!meth_write(Prim2{8,4}!primConcat(Prim2{12,8}!primExtract(def_t2___d6), Prim2{12,4}!primExtract(def_t1___d8)), diff --git a/testsuite/bsc.misc/sal/CTX_sysTb.sal.expected b/testsuite/bsc.misc/sal/CTX_sysTb.sal.expected index de1a4e240..00de768b6 100644 --- a/testsuite/bsc.misc/sal/CTX_sysTb.sal.expected +++ b/testsuite/bsc.misc/sal/CTX_sysTb.sal.expected @@ -18,21 +18,21 @@ BEGIN #) ; rule_RL_r0 (state0 : STATE) : [ BOOLEAN, STATE ] = - LET def_b__h284 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c1) - IN LET def_b__h285 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c2) - IN LET def_state__h244 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_state) - IN LET def_b__h322 : Bit{51}!T = CTX_module_add!fn(def_b__h284, Bit{51}!mkConst(3)) - IN LET def_b__h345 : Bit{51}!T = CTX_module_add!fn(def_b__h285, Bit{51}!mkConst(2)) + LET def_state__h528 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_state) + IN LET def_c2___d6 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c2) + IN LET def_b__h871 : Bit{51}!T = CTX_module_add!fn(def_c2___d6, Bit{51}!mkConst(2)) + IN LET def_c1___d5 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c1) + IN LET def_b__h747 : Bit{51}!T = CTX_module_add!fn(def_c1___d5, Bit{51}!mkConst(3)) IN LET def_gcd_RDY_start____d1 : BOOLEAN = CTX_sysMethods!meth_RDY_start(state0.inst_gcd) - IN LET def_state_EQ_0___d3 : BOOLEAN = Prim1{2}!primEQ(def_state__h244, Bit{2}!mkConst(0)) + IN LET def_state_EQ_0___d3 : BOOLEAN = Prim1{2}!primEQ(def_state__h528, Bit{2}!mkConst(0)) IN LET def_gcd_RDY_start_AND_state_EQ_0___d4 : BOOLEAN = def_gcd_RDY_start____d1 AND def_state_EQ_0___d3 IN LET act1 : [ CTX_sysMethods!STATE, Unit!T ] = - CTX_sysMethods!meth_start(def_b__h284, def_b__h285, state0.inst_gcd) + CTX_sysMethods!meth_start(def_c1___d5, def_c2___d6, state0.inst_gcd) IN LET state1 : STATE = state0 WITH .inst_gcd := act1.1 - IN LET act2 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h322, state1.inst_c1) + IN LET act2 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h747, state1.inst_c1) IN LET state2 : STATE = state1 WITH .inst_c1 := act2.1 - IN LET act3 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h345, state2.inst_c2) + IN LET act3 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h871, state2.inst_c2) IN LET state3 : STATE = state2 WITH .inst_c2 := act3.1 IN LET act4 : [ CTX_RegN{2}!STATE, Unit!T ] = CTX_RegN{2}!meth_write(Bit{2}!mkConst(1), state3.inst_state) @@ -40,26 +40,26 @@ BEGIN IN ( def_gcd_RDY_start_AND_state_EQ_0___d4, state4 ) ; rule_RL_r1 (state0 : STATE) : [ BOOLEAN, STATE ] = - LET def_b__h284 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c1) - IN LET def_b__h285 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c2) - IN LET def_state__h244 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_state) - IN LET def_b__h322 : Bit{51}!T = CTX_module_add!fn(def_b__h284, Bit{51}!mkConst(3)) - IN LET def_b__h345 : Bit{51}!T = CTX_module_add!fn(def_b__h285, Bit{51}!mkConst(2)) - IN LET def_state_EQ_1___d9 : BOOLEAN = Prim1{2}!primEQ(def_state__h244, Bit{2}!mkConst(1)) + LET def_state__h528 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_state) + IN LET def_c2___d6 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c2) + IN LET def_b__h871 : Bit{51}!T = CTX_module_add!fn(def_c2___d6, Bit{51}!mkConst(2)) + IN LET def_c1___d5 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c1) + IN LET def_b__h747 : Bit{51}!T = CTX_module_add!fn(def_c1___d5, Bit{51}!mkConst(3)) + IN LET def_state_EQ_1___d9 : BOOLEAN = Prim1{2}!primEQ(def_state__h528, Bit{2}!mkConst(1)) IN LET act1 : [ CTX_sysMethods!STATE, Bit{51}!T ] = - CTX_sysMethods!meth_start_and_result(def_b__h284, def_b__h285, state0.inst_gcd) + CTX_sysMethods!meth_start_and_result(def_c1___d5, def_c2___d6, state0.inst_gcd) IN LET state1 : STATE = state0 WITH .inst_gcd := act1.1 - IN LET def_b__h381 : Bit{51}!T = act1.2 + IN LET def_b__h1063 : Bit{51}!T = act1.2 IN LET def_gcd_start_and_result_0_PLUS_1___d11 : Bit{51}!T = - Prim1{51}!primAdd(def_b__h381, Bit{51}!mkConst(1)) + Prim1{51}!primAdd(def_b__h1063, Bit{51}!mkConst(1)) IN LET act2 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(Prim2{50,1}!primConcat(Prim2{51,50}!primExtract(def_gcd_start_and_result_0_PLUS_1___d11), Bit{1}!mkConst(0)), state1.inst_rg) IN LET state2 : STATE = state1 WITH .inst_rg := act2.1 - IN LET act3 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h322, state2.inst_c1) + IN LET act3 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h747, state2.inst_c1) IN LET state3 : STATE = state2 WITH .inst_c1 := act3.1 - IN LET act4 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h345, state3.inst_c2) + IN LET act4 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h871, state3.inst_c2) IN LET state4 : STATE = state3 WITH .inst_c2 := act4.1 IN LET act5 : [ CTX_RegN{2}!STATE, Unit!T ] = CTX_RegN{2}!meth_write(Bit{2}!mkConst(2), state4.inst_state) @@ -67,12 +67,12 @@ BEGIN IN ( def_state_EQ_1___d9, state5 ) ; rule_RL_r2 (state0 : STATE) : [ BOOLEAN, STATE ] = - LET def_state__h244 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_state) + LET def_state__h528 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_state) IN LET def_gcd_RDY_result____d14 : BOOLEAN = CTX_sysMethods!meth_RDY_result(state0.inst_gcd) IN LET def_gcd_result____d17 : Bit{51}!T = CTX_sysMethods!meth_result(state0.inst_gcd) IN LET def_gcd_result__7_PLUS_1___d18 : Bit{51}!T = Prim1{51}!primAdd(def_gcd_result____d17, Bit{51}!mkConst(1)) - IN LET def_state_EQ_2___d15 : BOOLEAN = Prim1{2}!primEQ(def_state__h244, Bit{2}!mkConst(2)) + IN LET def_state_EQ_2___d15 : BOOLEAN = Prim1{2}!primEQ(def_state__h528, Bit{2}!mkConst(2)) IN LET def_gcd_RDY_result__4_AND_state_EQ_2_5___d16 : BOOLEAN = def_gcd_RDY_result____d14 AND def_state_EQ_2___d15 IN LET act1 : [ CTX_RegN{51}!STATE, Unit!T ] = @@ -86,9 +86,9 @@ BEGIN IN ( def_gcd_RDY_result__4_AND_state_EQ_2_5___d16, state2 ) ; rule_RL_exit (state0 : STATE) : [ BOOLEAN, STATE ] = - LET def_b__h284 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c1) - IN LET def_c1_ULE_100___d21 : BOOLEAN = Prim1{51}!primULE(def_b__h284, Bit{51}!mkConst(100)) - IN LET def_v__h538 : Bit{64}!T = Bit{64}!undef + LET def_c1___d5 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c1) + IN LET def_c1_ULE_100___d21 : BOOLEAN = Prim1{51}!primULE(def_c1___d5, Bit{51}!mkConst(100)) + IN LET def_v__h1286 : Bit{64}!T = Bit{64}!undef IN ( NOT def_c1_ULE_100___d21, state0 ) ; END diff --git a/testsuite/bsc.names/signal_names/LiteralNum_ENotation.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/LiteralNum_ENotation.bsv.bsc-vcomp-out.expected index 2a9e805ae..5e2438935 100644 --- a/testsuite/bsc.names/signal_names/LiteralNum_ENotation.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.names/signal_names/LiteralNum_ENotation.bsv.bsc-vcomp-out.expected @@ -30,7 +30,7 @@ rg_start :: ABSTRACT: Prelude.VReg = RegN []) [clock { osc: CLK gate: 1'd1 }, reset { wire: RST_N }, 32'd1, 1'd1] [] - meth types=[([], Nothing, Just (Bit 1)), ([Bit 1], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 1]), ([Bit 1], Just (Bit 1), [])] port types=D_IN -> Prelude.Bool Q_OUT -> Prelude.Bool -- AP local definitions diff --git a/testsuite/bsc.names/signal_names/Method.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/Method.bsv.bsc-vcomp-out.expected index 451dbc6c4..2d9926515 100644 --- a/testsuite/bsc.names/signal_names/Method.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.names/signal_names/Method.bsv.bsc-vcomp-out.expected @@ -35,9 +35,9 @@ rg :: ABSTRACT: PreludeBSV._PreludeBSV.VRWire103 = RWire [(WSET, WHAS), (WVAL, WGET)]) [32'd8, clock { osc: CLK gate: 1'd1 }, reset { wire: RST_N }] [] - meth types=[([Bit 8], Just (Bit 1), Nothing), - ([], Nothing, Just (Bit 1)), - ([], Nothing, Just (Bit 8))] + meth types=[([Bit 8], Just (Bit 1), []), + ([], Nothing, [Bit 1]), + ([], Nothing, [Bit 8])] port types=WGET -> Prelude.Bit 8 WHAS -> Prelude.Bool WVAL -> Prelude.Bit 8 diff --git a/testsuite/bsc.names/signal_names/MethodActionValue.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/MethodActionValue.bsv.bsc-vcomp-out.expected index fbb8b66c2..e840f3161 100644 --- a/testsuite/bsc.names/signal_names/MethodActionValue.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.names/signal_names/MethodActionValue.bsv.bsc-vcomp-out.expected @@ -81,18 +81,18 @@ i :: ABSTRACT: MethodActionValue.Ifc­ = mkMethodActionValue_Sub []) [clock { osc: CLK gate: 1'd1 }, reset { wire: RST_N }] [] - meth types=[([], Just (Bit 1), Just (Bit 8)), ([], Nothing, Just (Bit 1))] + meth types=[([], Just (Bit 1), [Bit 8]), ([], Nothing, [Bit 1])] port types=m -> Prelude.Bit 8 -- AP local definitions i_m_PLUS_8___d2 :: Bit 8; -i_m_PLUS_8___d2 = v__h90 + 8'd8; +i_m_PLUS_8___d2 = v__h105 + 8'd8; -- IdProp i_m_PLUS_8___d2[IdP_from_rhs] i_m_MINUS_1___d3 :: Bit 8; -i_m_MINUS_1___d3 = v__h90 - 8'd1; +i_m_MINUS_1___d3 = v__h105 - 8'd1; -- IdProp i_m_MINUS_1___d3[IdP_from_rhs] -v__h90 :: Bit 8; -v__h90 = i.m; --- IdProp v__h90[IdP_keep] +v__h105 :: Bit 8; +v__h105 = i.m; +-- IdProp v__h105[IdP_keep] -- AP rules rule RL_r "r": when 1'd1 diff --git a/testsuite/bsc.names/signal_names/MethodRead.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/MethodRead.bsv.bsc-vcomp-out.expected index bdc7919c7..4175d0edd 100644 --- a/testsuite/bsc.names/signal_names/MethodRead.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.names/signal_names/MethodRead.bsv.bsc-vcomp-out.expected @@ -29,19 +29,19 @@ rg :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd8] [] - meth types=[([], Nothing, Just (Bit 8)), ([Bit 8], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 8]), ([Bit 8], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 8 Q_OUT -> Prelude.Bit 8 -- AP local definitions rg_PLUS_8___d2 :: Bit 8; -rg_PLUS_8___d2 = x__h140 + 8'd8; +rg_PLUS_8___d2 = x__h115 + 8'd8; -- IdProp rg_PLUS_8___d2[IdP_from_rhs] rg_MINUS_1___d3 :: Bit 8; -rg_MINUS_1___d3 = x__h140 - 8'd1; +rg_MINUS_1___d3 = x__h115 - 8'd1; -- IdProp rg_MINUS_1___d3[IdP_from_rhs] -x__h140 :: Bit 8; -x__h140 = rg.read; --- IdProp x__h140[IdP_keep] +x__h115 :: Bit 8; +x__h115 = rg.read; +-- IdProp x__h115[IdP_keep] -- AP rules rule RL_r "r": when 1'd1 diff --git a/testsuite/bsc.names/signal_names/NoInline.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/NoInline.bsv.bsc-vcomp-out.expected index 2b1f8c987..f986c4b8b 100644 --- a/testsuite/bsc.names/signal_names/NoInline.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.names/signal_names/NoInline.bsv.bsc-vcomp-out.expected @@ -19,11 +19,11 @@ arg info [clockarg default_clock;, resetarg default_reset;] -- AP state elements -- AP local definitions fnNoInline_PLUS_8___d2 :: Bit 8; -fnNoInline_PLUS_8___d2 = x__h46 + 8'd8; +fnNoInline_PLUS_8___d2 = fnNoInline___d1 + 8'd8; -- IdProp fnNoInline_PLUS_8___d2[IdP_from_rhs] -x__h46 :: Bit 8; -x__h46 = NoInline.fnNoInline 8'd0; --- IdProp x__h46[IdP_keep] +fnNoInline___d1 :: Bit 8; +fnNoInline___d1 = NoInline.fnNoInline 8'd0; +-- IdProp fnNoInline___d1[IdP_from_rhs] -- AP rules rule RL_r "r": when 1'd1 diff --git a/testsuite/bsc.scheduler/SplitIf.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/SplitIf.bsv.bsc-sched-out.expected index 609f5b7a0..a1e4f3cb5 100644 --- a/testsuite/bsc.scheduler/SplitIf.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/SplitIf.bsv.bsc-sched-out.expected @@ -25,7 +25,7 @@ order: [RL_toggle2, xfer_T, xfer_F, RL_toggle1] (r2.read, [(r2.read, 1)]), (r2.write, [(r2.write xfer_sel, 1), (r2.write NOT_r2___d4, 1)]), (w.whas, [(w.whas, 1)]), - (w.wset, [(w.wset r2__h256, 1)])] + (w.wset, [(w.wset r2__h277, 1)])] ----- @@ -70,7 +70,7 @@ order: [RL_r, RL_toggleDir, RL_done, RL_incr] (dir.read, [(dir.read, 1)]), (dir.write, [(dir.write NOT_dir___d2, 1)]), (test.RDY_xfer, [(test.RDY_xfer, 1)]), - (test.xfer, [(test.xfer dir__h205, 1)])] + (test.xfer, [(test.xfer dir___d1, 1)])] ----- diff --git a/testsuite/bsc.scheduler/SplitIf2.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/SplitIf2.bsv.bsc-sched-out.expected index e836279c1..ed63926e8 100644 --- a/testsuite/bsc.scheduler/SplitIf2.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/SplitIf2.bsv.bsc-sched-out.expected @@ -20,11 +20,11 @@ order: [RL_toggle1, RL_toggle2, xfer] === resources: [(r1.read, [(r1.read, 1)]), - (r1.write, [(if xfer_sel then r1.write r2__h256, 1), (r1.write NOT_r1___d2, 1)]), + (r1.write, [(if xfer_sel then r1.write r2__h277, 1), (r1.write NOT_r1___d2, 1)]), (r2.read, [(r2.read, 1)]), - (r2.write, [(if NOT_xfer_sel___d5 then r2.write r1__h225, 1), (r2.write NOT_r2___d4, 1)]), + (r2.write, [(if NOT_xfer_sel___d5 then r2.write r1__h237, 1), (r2.write NOT_r2___d4, 1)]), (w.whas, [(w.whas, 1)]), - (w.wset, [(w.wset r2__h256, 1)])] + (w.wset, [(w.wset r2__h277, 1)])] ----- @@ -75,7 +75,7 @@ order: [RL_r, RL_toggleDir, RL_done, RL_incr] (dir.read, [(dir.read, 1)]), (dir.write, [(dir.write NOT_dir___d2, 1)]), (test.RDY_xfer, [(test.RDY_xfer, 1)]), - (test.xfer, [(test.xfer dir__h208, 1)])] + (test.xfer, [(test.xfer dir___d1, 1)])] ----- diff --git a/testsuite/bsc.scheduler/avmeth/AVArgUse_C.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/avmeth/AVArgUse_C.bsv.bsc-sched-out.expected index 23677e3f3..9780b14fa 100644 --- a/testsuite/bsc.scheduler/avmeth/AVArgUse_C.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/avmeth/AVArgUse_C.bsv.bsc-sched-out.expected @@ -45,7 +45,7 @@ order: [RL_rA, RL_rB] ----- === resources: -[(dut.m, [(dut.m b__h178 32'd1, 1), (dut.m 32'd5 b__h178, 1)]), +[(dut.m, [(dut.m r1___d1 32'd1, 1), (dut.m 32'd5 r1___d1, 1)]), (r1.read, [(r1.read, 1)]), (r1.write, [(r1.write r1_PLUS_1___d4, 1)])] diff --git a/testsuite/bsc.scheduler/avmeth/AVArgUse_SBR.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/avmeth/AVArgUse_SBR.bsv.bsc-sched-out.expected index 3d3ab3c0b..a4a61ef48 100644 --- a/testsuite/bsc.scheduler/avmeth/AVArgUse_SBR.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/avmeth/AVArgUse_SBR.bsv.bsc-sched-out.expected @@ -43,7 +43,7 @@ order: [RL_rB, RL_rA] ----- === resources: -[(dut.m, [(dut.m b__h178 32'd1, 1), (dut.m 32'd5 b__h178, 1)]), +[(dut.m, [(dut.m r1___d1 32'd1, 1), (dut.m 32'd5 r1___d1, 1)]), (r1.read, [(r1.read, 1)]), (r1.write, [(r1.write r1_PLUS_1___d4, 1)])] diff --git a/testsuite/bsc.syntax/bsv05/statename/sysStateNameTest.atsexpand.expected b/testsuite/bsc.syntax/bsv05/statename/sysStateNameTest.atsexpand.expected index b9ac53b34..7964c30bc 100644 --- a/testsuite/bsc.syntax/bsv05/statename/sysStateNameTest.atsexpand.expected +++ b/testsuite/bsc.syntax/bsv05/statename/sysStateNameTest.atsexpand.expected @@ -25,7 +25,7 @@ b :: ABSTRACT: Prelude.VReg = RegN []) [clock { osc: CLK gate: 1'd1 }, reset { wire: RST_N }, 32'd16, 16'd11] [] - meth types=[([], Nothing, Just (Bit 16)), ([Bit 16], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 16]), ([Bit 16], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 16 Q_OUT -> Prelude.Bit 16 -- AP rules diff --git a/testsuite/bsc.syntax/bsv05/statename/sysStateNameTest2.atsexpand.expected b/testsuite/bsc.syntax/bsv05/statename/sysStateNameTest2.atsexpand.expected index a5088811c..0aa1e913a 100644 --- a/testsuite/bsc.syntax/bsv05/statename/sysStateNameTest2.atsexpand.expected +++ b/testsuite/bsc.syntax/bsv05/statename/sysStateNameTest2.atsexpand.expected @@ -25,7 +25,7 @@ b :: ABSTRACT: Prelude.VReg = RegN []) [clock { osc: CLK gate: 1'd1 }, reset { wire: RST_N }, 32'd16, 16'd11] [] - meth types=[([], Nothing, Just (Bit 16)), ([Bit 16], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 16]), ([Bit 16], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 16 Q_OUT -> Prelude.Bit 16 -- AP rules diff --git a/testsuite/bsc.syntax/bsv05/statename/sysUseMod2.atsexpand.expected b/testsuite/bsc.syntax/bsv05/statename/sysUseMod2.atsexpand.expected index bf9d2f8ff..9d747f2d5 100644 --- a/testsuite/bsc.syntax/bsv05/statename/sysUseMod2.atsexpand.expected +++ b/testsuite/bsc.syntax/bsv05/statename/sysUseMod2.atsexpand.expected @@ -26,7 +26,7 @@ the_e_the_r :: ABSTRACT: Prelude.VReg = RegN []) [clock { osc: CLK gate: 1'd1 }, reset { wire: RST_N }, 32'd32, 32'd0] [] - meth types=[([], Nothing, Just (Bit 32)), ([Bit 32], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 32]), ([Bit 32], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 32 Q_OUT -> Prelude.Bit 32 -- AP rules diff --git a/testsuite/bsc.syntax/bsv05/statename/sysUseMod2Arrow.atsexpand.expected b/testsuite/bsc.syntax/bsv05/statename/sysUseMod2Arrow.atsexpand.expected index 062972d8b..d885d56e0 100644 --- a/testsuite/bsc.syntax/bsv05/statename/sysUseMod2Arrow.atsexpand.expected +++ b/testsuite/bsc.syntax/bsv05/statename/sysUseMod2Arrow.atsexpand.expected @@ -26,7 +26,7 @@ e_r :: ABSTRACT: Prelude.VReg = RegN []) [clock { osc: CLK gate: 1'd1 }, reset { wire: RST_N }, 32'd32, 32'd0] [] - meth types=[([], Nothing, Just (Bit 32)), ([Bit 32], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 32]), ([Bit 32], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 32 Q_OUT -> Prelude.Bit 32 -- AP rules diff --git a/testsuite/bsc.typechecker/dontcare/DummyInRuleQual.bs.bsc-vcomp-out.expected b/testsuite/bsc.typechecker/dontcare/DummyInRuleQual.bs.bsc-vcomp-out.expected index 9145850f1..289b6fd14 100644 --- a/testsuite/bsc.typechecker/dontcare/DummyInRuleQual.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.typechecker/dontcare/DummyInRuleQual.bs.bsc-vcomp-out.expected @@ -33,7 +33,7 @@ r :: ABSTRACT: Prelude.VReg = RegUN []) [clock { osc: CLK gate: 1'd1 }, 32'd12] [] - meth types=[([], Nothing, Just (Bit 12)), ([Bit 12], Just (Bit 1), Nothing)] + meth types=[([], Nothing, [Bit 12]), ([Bit 12], Just (Bit 1), [])] port types=D_IN -> Prelude.Bit 12 Q_OUT -> Prelude.Bit 12 -- AP local definitions diff --git a/testsuite/bsc.verilog/astate/astate.exp b/testsuite/bsc.verilog/astate/astate.exp index 603ef0be2..af69d082b 100644 --- a/testsuite/bsc.verilog/astate/astate.exp +++ b/testsuite/bsc.verilog/astate/astate.exp @@ -29,9 +29,9 @@ set fname {sysPriMux_SharedValue.astate} compile_verilog_pass PriMux_SharedValue.bsv {} "-dastate=$fname" if { $vtest == 1 } { find_regexp $fname { -r\$write_1 \= primux \(WILL_FIRE_RL_rA, MUX_r\$write_1__VAL_1\) - \(WILL_FIRE_RL_rB, MUX_r\$write_1__VAL_2\) - \(WILL_FIRE_RL_rC, MUX_r\$write_1__VAL_3\)} +r\$write_ARG_1 \= primux \(WILL_FIRE_RL_rA, MUX_r\$write_ARG_1__VAL_1\) + \(WILL_FIRE_RL_rB, MUX_r\$write_ARG_1__VAL_2\) + \(WILL_FIRE_RL_rC, MUX_r\$write_ARG_1__VAL_3\)} } # ---------- diff --git a/testsuite/bsc.verilog/inline/inline.exp b/testsuite/bsc.verilog/inline/inline.exp index ac441269b..8396769df 100644 --- a/testsuite/bsc.verilog/inline/inline.exp +++ b/testsuite/bsc.verilog/inline/inline.exp @@ -4,8 +4,8 @@ # there is only one use. (Inlining for optimization is OK.) if {$vtest == 1} { compile_verilog_pass RWireOneUse.bsv "" -keep-inlined-boundaries - find_n_strings sysRWireOneUse.v {assign rw$wget = } 1 - find_n_strings sysRWireOneUse.v {assign rw$whas = } 1 + find_n_strings sysRWireOneUse.v {assign rw$wget_RES_1 = } 1 + find_n_strings sysRWireOneUse.v {assign rw$whas_RES_1 = } 1 } # Test that inlined registers with no_reset do not generate Verilog diff --git a/testsuite/bsc.verilog/noinline/NoInline_ResNotInBits.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/noinline/NoInline_ResNotInBits.bsv.bsc-vcomp-out.expected index d2fe133e0..3633a7724 100644 --- a/testsuite/bsc.verilog/noinline/NoInline_ResNotInBits.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/noinline/NoInline_ResNotInBits.bsv.bsc-vcomp-out.expected @@ -10,9 +10,3 @@ Error: "NoInline_ResNotInBits.bsv", line 4, column 12: (T0043) Cannot synthesize `module_fnNoInline_ResNotInBits­': The interface method `fnNoInline_ResNotInBits' uses type(s) that are not in the Bits or SplitPorts typeclasses: NoInline_ResNotInBits::L -Error: "NoInline_ResNotInBits.bsv", line 4, column 12: (T0029) - Signature mismatch (given too general): - given: - function b__ f(Bit#(1) x1) provisos (Bits#(NoInline_ResNotInBits::L, a__)) - deduced: - function Bit#(c__) f(Bit#(1) x1) provisos (Bits#(NoInline_ResNotInBits::L, c__)) diff --git a/testsuite/bsc.verilog/splitports/DeepSplit.bs b/testsuite/bsc.verilog/splitports/DeepSplit.bs index 9cab5afea..4c4761167 100644 --- a/testsuite/bsc.verilog/splitports/DeepSplit.bs +++ b/testsuite/bsc.verilog/splitports/DeepSplit.bs @@ -47,11 +47,19 @@ interface SplitTest = putBaz :: DeepSplit Baz -> Action putZug :: DeepSplit Zug -> Action + getFoo :: DeepSplit Foo + getBar :: DeepSplit Foo -> DeepSplit Bar {-# result = "GET_BAR" #-} + getZug :: DeepSplit Zug + + update :: DeepSplit Foo -> ActionValue (DeepSplit Bar) + {-# synthesize mkDeepSplitTest #-} mkDeepSplitTest :: Module SplitTest mkDeepSplitTest = module + theCond <- mkReg False + theFoo <- mkReg (Foo { x = 0; y = 0; }) interface putFoo (DeepSplit x) = $display "putFoo: " (cshow x) putBar (DeepSplit x) = $display "putBar: " (cshow x) @@ -59,6 +67,13 @@ mkDeepSplitTest = putFoos (DeepSplit x) = $display "putFoos: " (cshow x) putBaz (DeepSplit x) = $display "putBaz: " (cshow x) putZug (DeepSplit x) = $display "putZug: " (cshow x) + getFoo = DeepSplit $ Foo { x = 42; y = 43; } + getBar (DeepSplit f) = DeepSplit $ Bar { v = vec True False True; w = (False, 0x4321); z = f; } + getZug = DeepSplit $ Zug { qs = vec (Quix { q = negate 2; v = True }) (Quix { q = 2; v = False }); blob = True; } + update (DeepSplit f) = do + theCond := not theCond + theFoo := f + return $ DeepSplit $ Bar { v = vec (f.x == 33) theCond (not theCond); w = (theCond, 0xDEAD); z = theFoo; } {-# synthesize sysDeepSplit #-} sysDeepSplit :: Module Empty @@ -74,4 +89,13 @@ sysDeepSplit = when i == 3 ==> s.putFoos $ DeepSplit $ genWith $ \ j -> Foo { x = fromInteger $ 9 + j / 2; y = fromInteger $ 10 - 2*j / 3; } when i == 4 ==> s.putBaz $ DeepSplit $ Baz { a = Just $ Foo { x = 9; y = 10; }; b = Bar { v = vec True False False; w = (True, 0x1234); z = Foo { x = 3; y = 4; }; }; c = vec (vec (Foo { x = 11; y = 12; }) (Foo { x = 13; y = 14; }) (Foo { x = 15; y = 16; }) (Foo { x = 17; y = 18; }) (Foo { x = 19; y = 20; }) (Foo { x = 21; y = 22; }) (Foo { x = 23; y = 24; }) (Foo { x = 25; y = 26; }), Bar { v = vec True False True; w = (True, 0xBEEF); z = Foo { x = 3; y = 4; } }) (vec (Foo { x = 27; y = 28; }) (Foo { x = 29; y = 30; }) (Foo { x = 31; y = 32; }) (Foo { x = 33; y = 34; }) (Foo { x = 35; y = 36; }) (Foo { x = 37; y = 38; }) (Foo { x = 39; y = 40; }) (Foo { x = 41; y = 42; }), Bar { v = vec True False True; w = (True, 0x4321); z = Foo { x = 123; y = 42; } }) (vec (Foo { x = 43; y = 44; }) (Foo { x = 45; y = 46; }) (Foo { x = 47; y = 48; }) (Foo { x = 49; y = 50; }) (Foo { x = 51; y = 52; }) (Foo { x = 53; y = 54; }) (Foo { x = 55; y = 56; }) (Foo { x = 57; y = 58; }), Bar { v = vec True True True; w = (True, 0xAABB); z = Foo { x = 3; y = 4; } }); d = (); e = nil; } when i == 5 ==> s.putZug $ DeepSplit $ Zug { qs = vec (Quix { q = 1; v = True }) (Quix { q = 2; v = False }); blob = False; } - when i == 6 ==> $finish + when i == 6 ==> $display "getFoo: " (cshow s.getFoo) + when i == 7 ==> $display "getBar: " (cshow $ s.getBar s.getFoo) + when i == 8 ==> $display "getZug: " (cshow s.getZug) + when i == 9 ==> do + res <- s.update (DeepSplit $ Foo { x = 77; y = 88; }) + $display "update: " (cshow res) + when i == 10 ==> do + res <- s.update (DeepSplit $ Foo { x = 33; y = 44; }) + $display "update: " (cshow res) + when i == 11 ==> $finish \ No newline at end of file diff --git a/testsuite/bsc.verilog/splitports/InstanceSplit.bs b/testsuite/bsc.verilog/splitports/InstanceSplit.bs index 83c2ce7da..19a24e268 100644 --- a/testsuite/bsc.verilog/splitports/InstanceSplit.bs +++ b/testsuite/bsc.verilog/splitports/InstanceSplit.bs @@ -48,17 +48,30 @@ interface SplitTest = putFoos :: (Vector 50 Foo) -> Action putBaz :: Baz -> Action + getFoo :: Foo + getBar :: Foo -> Bar {-# result = "GET_BAR" #-} + + update :: Foo -> ActionValue Bar + {-# synthesize mkInstanceSplitTest #-} mkInstanceSplitTest :: Module SplitTest mkInstanceSplitTest = module + theCond <- mkReg False + theFoo <- mkReg (Foo { x = 0; y = 0; }) interface putFoo x = $display "putFoo: " (cshow x) putBar x = $display "putBar: " (cshow x) putFooBar x y = $display "putFooBar: " (cshow x) " " (cshow y) putFoos x = $display "putFoos: " (cshow x) putBaz x = $display "putBaz: " (cshow x) + getFoo = Foo { x = 42; y = 43; } + getBar f = Bar { v = vec True False True; w = (False, 0x4321); z = f; } + update f = do + theCond := not theCond + theFoo := f + return $ Bar { v = vec (f.x == 33) theCond (not theCond); w = (theCond, 0xDEAD); z = theFoo; } {-# synthesize sysInstanceSplit #-} sysInstanceSplit :: Module Empty @@ -73,4 +86,12 @@ sysInstanceSplit = when i == 2 ==> s.putFooBar (Foo { x = 5; y = 6; }) (Bar { v = vec False True False; w = (False, 0x5678); z = Foo { x = 7; y = 8; } }) when i == 3 ==> s.putFoos $ genWith $ \ j -> Foo { x = fromInteger $ 9 + j / 2; y = fromInteger $ 10 - 2*j / 3; } when i == 4 ==> s.putBaz $ Baz { a = Just $ Foo { x = 9; y = 10; }; b = Bar { v = vec True False False; w = (True, 0x1234); z = Foo { x = 3; y = 4; }; }; c = vec (vec (Foo { x = 11; y = 12; }) (Foo { x = 13; y = 14; }) (Foo { x = 15; y = 16; }) (Foo { x = 17; y = 18; }) (Foo { x = 19; y = 20; }) (Foo { x = 21; y = 22; }) (Foo { x = 23; y = 24; }) (Foo { x = 25; y = 26; }), Bar { v = vec True False True; w = (True, 0xBEEF); z = Foo { x = 3; y = 4; } }) (vec (Foo { x = 27; y = 28; }) (Foo { x = 29; y = 30; }) (Foo { x = 31; y = 32; }) (Foo { x = 33; y = 34; }) (Foo { x = 35; y = 36; }) (Foo { x = 37; y = 38; }) (Foo { x = 39; y = 40; }) (Foo { x = 41; y = 42; }), Bar { v = vec True False True; w = (True, 0x4321); z = Foo { x = 123; y = 42; } }) (vec (Foo { x = 43; y = 44; }) (Foo { x = 45; y = 46; }) (Foo { x = 47; y = 48; }) (Foo { x = 49; y = 50; }) (Foo { x = 51; y = 52; }) (Foo { x = 53; y = 54; }) (Foo { x = 55; y = 56; }) (Foo { x = 57; y = 58; }), Bar { v = vec True True True; w = (True, 0xAABB); z = Foo { x = 3; y = 4; } }); d = (); e = nil; } - when i == 5 ==> $finish + when i == 5 ==> $display "getFoo: " (cshow s.getFoo) + when i == 6 ==> $display "getBar: " (cshow $ s.getBar (s.getFoo)) + when i == 7 ==> do + res <- s.update (Foo { x = 77; y = 88; }) + $display "update: " (cshow res) + when i == 8 ==> do + res <- s.update (Foo { x = 33; y = 44; }) + $display "update: " (cshow res) + when i == 9 ==> $finish diff --git a/testsuite/bsc.verilog/splitports/ShallowSplit.bs b/testsuite/bsc.verilog/splitports/ShallowSplit.bs index 1c96ac47b..9c7f9e294 100644 --- a/testsuite/bsc.verilog/splitports/ShallowSplit.bs +++ b/testsuite/bsc.verilog/splitports/ShallowSplit.bs @@ -31,17 +31,30 @@ interface SplitTest = putFoos :: ShallowSplit (Vector 50 Foo) -> Action putBaz :: ShallowSplit Baz -> Action + getFoo :: ShallowSplit Foo + getBar :: ShallowSplit Foo -> ShallowSplit Bar {-# result = "GET_BAR" #-} + + update :: ShallowSplit Foo -> ActionValue (ShallowSplit Bar) + {-# synthesize mkShallowSplitTest #-} mkShallowSplitTest :: Module SplitTest mkShallowSplitTest = module + theCond <- mkReg False + theFoo <- mkReg (Foo { x = 0; y = 0; }) interface putFoo (ShallowSplit x) = $display "putFoo: " (cshow x) putBar (ShallowSplit x) = $display "putBar: " (cshow x) putFooBar (ShallowSplit x) (ShallowSplit y) = $display "putFooBar: " (cshow x) " " (cshow y) putFoos (ShallowSplit x) = $display "putFoos: " (cshow x) putBaz (ShallowSplit x) = $display "putBaz: " (cshow x) + getFoo = ShallowSplit $ Foo { x = 42; y = 43; } + getBar (ShallowSplit f) = ShallowSplit $ Bar { v = vec True False True; w = (False, 0x4321); z = f; } + update (ShallowSplit f) = do + theCond := not theCond + theFoo := f + return $ ShallowSplit $ Bar { v = vec (f.x == 33) theCond (not theCond); w = (theCond, 0xDEAD); z = theFoo; } {-# synthesize sysShallowSplit #-} sysShallowSplit :: Module Empty @@ -56,4 +69,12 @@ sysShallowSplit = when i == 2 ==> s.putFooBar (ShallowSplit $ Foo { x = 5; y = 6; }) (ShallowSplit $ Bar { v = vec False True False; w = (False, 0x5678); z = Foo { x = 7; y = 8; } }) when i == 3 ==> s.putFoos $ ShallowSplit $ genWith $ \ j -> Foo { x = fromInteger $ 9 + j / 2; y = fromInteger $ 10 - 2*j / 3; } when i == 4 ==> s.putBaz $ ShallowSplit $ Baz { a = Just $ Foo { x = 9; y = 10; }; b = Bar { v = vec True False False; w = (True, 0x1234); z = Foo { x = 3; y = 4; }; }; c = vec (vec (Foo { x = 11; y = 12; }) (Foo { x = 13; y = 14; }) (Foo { x = 15; y = 16; }) (Foo { x = 17; y = 18; }) (Foo { x = 19; y = 20; }) (Foo { x = 21; y = 22; }) (Foo { x = 23; y = 24; }) (Foo { x = 25; y = 26; }), Bar { v = vec True False True; w = (True, 0xBEEF); z = Foo { x = 3; y = 4; } }) (vec (Foo { x = 27; y = 28; }) (Foo { x = 29; y = 30; }) (Foo { x = 31; y = 32; }) (Foo { x = 33; y = 34; }) (Foo { x = 35; y = 36; }) (Foo { x = 37; y = 38; }) (Foo { x = 39; y = 40; }) (Foo { x = 41; y = 42; }), Bar { v = vec True False True; w = (True, 0x4321); z = Foo { x = 123; y = 42; } }) (vec (Foo { x = 43; y = 44; }) (Foo { x = 45; y = 46; }) (Foo { x = 47; y = 48; }) (Foo { x = 49; y = 50; }) (Foo { x = 51; y = 52; }) (Foo { x = 53; y = 54; }) (Foo { x = 55; y = 56; }) (Foo { x = 57; y = 58; }), Bar { v = vec True True True; w = (True, 0xAABB); z = Foo { x = 3; y = 4; } }); d = (); e = nil; } - when i == 5 ==> $finish + when i == 5 ==> $display "getFoo: " (cshow s.getFoo) + when i == 6 ==> $display "getBar: " (cshow $ s.getBar s.getFoo) + when i == 7 ==> do + res <- s.update (ShallowSplit $ Foo { x = 77; y = 88; }) + $display "update: " (cshow res) + when i == 8 ==> do + res <- s.update (ShallowSplit $ Foo { x = 33; y = 44; }) + $display "update: " (cshow res) + when i == 9 ==> $finish diff --git a/testsuite/bsc.verilog/splitports/splitports.exp b/testsuite/bsc.verilog/splitports/splitports.exp index 0987ba1ba..12c8fa783 100644 --- a/testsuite/bsc.verilog/splitports/splitports.exp +++ b/testsuite/bsc.verilog/splitports/splitports.exp @@ -9,6 +9,17 @@ if { $vtest == 1 } { find_regexp mkShallowSplitTest.v {input \[15 : 0\] putFoos_1_49;} find_regexp mkShallowSplitTest.v {input \[16 : 0\] putBaz_1_a;} find_regexp mkShallowSplitTest.v {input \[491 : 0\] putBaz_1_c;} + find_regexp mkShallowSplitTest.v {output \[7 : 0\] getFoo_x;} + find_regexp mkShallowSplitTest.v {output \[7 : 0\] getFoo_y;} + find_regexp mkShallowSplitTest.v {output \[2 : 0\] GET_BAR_v;} + find_regexp mkShallowSplitTest.v {output \[15 : 0\] GET_BAR_z;} + find_regexp mkShallowSplitTest.v {input \[7 : 0\] update_1_x;} + find_regexp mkShallowSplitTest.v {input EN_update;} + find_regexp mkShallowSplitTest.v {output \[16 : 0\] update_w;} + find_regexp mkShallowSplitTest.v {output RDY_update;} + + find_regexp mkShallowSplitTest.v {\(getBar_1_x, getBar_1_y\) -> GET_BAR_z} + find_regexp mkShallowSplitTest.v {update_1_x -> update_v} } test_c_veri DeepSplit @@ -24,6 +35,23 @@ if { $vtest == 1 } { find_regexp mkDeepSplitTest.v {input \[7 : 0\] putBaz_1_c_2_1_7_y;} find_regexp mkDeepSplitTest.v {input \[15 : 0\] putBaz_1_c_2_2_w_2;} find_regexp mkDeepSplitTest.v {input \[3 : 0\] putZug_1_qs_1;} + find_regexp mkDeepSplitTest.v {output \[7 : 0\] getFoo_x;} + find_regexp mkDeepSplitTest.v {output \[7 : 0\] getFoo_y;} + find_regexp mkDeepSplitTest.v {output GET_BAR_v_0;} + find_regexp mkDeepSplitTest.v {output GET_BAR_v_2;} + find_regexp mkDeepSplitTest.v {output \[15 : 0\] GET_BAR_w_2;} + find_regexp mkDeepSplitTest.v {output \[7 : 0\] GET_BAR_z_y;} + find_regexp mkDeepSplitTest.v {output \[3 : 0\] getZug_qs_0;} + find_regexp mkDeepSplitTest.v {output \[3 : 0\] getZug_qs_1;} + find_regexp mkDeepSplitTest.v {output getZug_blob;} + find_regexp mkDeepSplitTest.v {input \[7 : 0\] update_1_x;} + find_regexp mkDeepSplitTest.v {input EN_update;} + find_regexp mkDeepSplitTest.v {output \[15 : 0\] update_w_2;} + find_regexp mkDeepSplitTest.v {output RDY_update;} + + find_regexp mkDeepSplitTest.v {getBar_1_x -> GET_BAR_z_x} + find_regexp mkDeepSplitTest.v {getBar_1_y -> GET_BAR_z_y} + find_regexp mkDeepSplitTest.v {update_1_x -> update_v_0} } test_c_veri InstanceSplit @@ -37,6 +65,20 @@ if { $vtest == 1 } { find_regexp mkInstanceSplitTest.v {input \[799 : 0\] putFoos_1;} find_regexp mkInstanceSplitTest.v {input \[16 : 0\] putBaz_1_a;} find_regexp mkInstanceSplitTest.v {input \[491 : 0\] putBaz_1_c;} + find_regexp mkInstanceSplitTest.v {output \[7 : 0\] getFoo_x;} + find_regexp mkInstanceSplitTest.v {output getFoo_ysign;} + find_regexp mkInstanceSplitTest.v {output \[6 : 0\] getFoo_yvalue;} + find_regexp mkInstanceSplitTest.v {output \[2 : 0\] GET_BAR_v;} + find_regexp mkInstanceSplitTest.v {output GET_BAR_z_ysign;} + find_regexp mkInstanceSplitTest.v {input \[7 : 0\] update_1_x;} + find_regexp mkInstanceSplitTest.v {input EN_update;} + find_regexp mkInstanceSplitTest.v {output \[6 : 0\] update_z_yvalue;} + find_regexp mkInstanceSplitTest.v {output RDY_update;} + + find_regexp mkInstanceSplitTest.v {getBar_1_x -> GET_BAR_z_x} + find_regexp mkInstanceSplitTest.v {\(getBar_1_ysign, getBar_1_yvalue\) -> GET_BAR_z_ysign} + find_regexp mkInstanceSplitTest.v {\(getBar_1_ysign, getBar_1_yvalue\) -> GET_BAR_z_yvalue} + find_regexp mkInstanceSplitTest.v {update_1_x -> update_v} } # Supplying an arg_names pragma that is shorter than the number of arguments diff --git a/testsuite/bsc.verilog/splitports/sysDeepSplit.out.expected b/testsuite/bsc.verilog/splitports/sysDeepSplit.out.expected index fa26cd6e1..af9d18ba2 100644 --- a/testsuite/bsc.verilog/splitports/sysDeepSplit.out.expected +++ b/testsuite/bsc.verilog/splitports/sysDeepSplit.out.expected @@ -4,3 +4,8 @@ putFooBar: Foo {x= 5; y= 6} Bar {v=[False, True, False]; w=(False, 22136); z putFoos: [Foo {x= 9; y= 10}, Foo {x= 9; y= 10}, Foo {x= 10; y= 9}, Foo {x= 10; y= 8}, Foo {x= 11; y= 8}, Foo {x= 11; y= 7}, Foo {x= 12; y= 6}, Foo {x= 12; y= 6}, Foo {x= 13; y= 5}, Foo {x= 13; y= 4}, Foo {x= 14; y= 4}, Foo {x= 14; y= 3}, Foo {x= 15; y= 2}, Foo {x= 15; y= 2}, Foo {x= 16; y= 1}, Foo {x= 16; y= 0}, Foo {x= 17; y= 0}, Foo {x= 17; y= -1}, Foo {x= 18; y= -2}, Foo {x= 18; y= -2}, Foo {x= 19; y= -3}, Foo {x= 19; y= -4}, Foo {x= 20; y= -4}, Foo {x= 20; y= -5}, Foo {x= 21; y= -6}, Foo {x= 21; y= -6}, Foo {x= 22; y= -7}, Foo {x= 22; y= -8}, Foo {x= 23; y= -8}, Foo {x= 23; y= -9}, Foo {x= 24; y= -10}, Foo {x= 24; y= -10}, Foo {x= 25; y= -11}, Foo {x= 25; y= -12}, Foo {x= 26; y= -12}, Foo {x= 26; y= -13}, Foo {x= 27; y= -14}, Foo {x= 27; y= -14}, Foo {x= 28; y= -15}, Foo {x= 28; y= -16}, Foo {x= 29; y= -16}, Foo {x= 29; y= -17}, Foo {x= 30; y= -18}, Foo {x= 30; y= -18}, Foo {x= 31; y= -19}, Foo {x= 31; y= -20}, Foo {x= 32; y= -20}, Foo {x= 32; y= -21}, Foo {x= 33; y= -22}, Foo {x= 33; y= -22}] putBaz: Baz {a=Valid (Foo {x= 9; y= 10}); b=Bar {v=[True, False, False]; w=(True, 4660); z=Foo {x= 3; y= 4}}; c=[([Foo {x= 11; y= 12}, Foo {x= 13; y= 14}, Foo {x= 15; y= 16}, Foo {x= 17; y= 18}, Foo {x= 19; y= 20}, Foo {x= 21; y= 22}, Foo {x= 23; y= 24}, Foo {x= 25; y= 26}], Bar {v=[True, False, True]; w=(True, 48879); z=Foo {x= 3; y= 4}}), ([Foo {x= 27; y= 28}, Foo {x= 29; y= 30}, Foo {x= 31; y= 32}, Foo {x= 33; y= 34}, Foo {x= 35; y= 36}, Foo {x= 37; y= 38}, Foo {x= 39; y= 40}, Foo {x= 41; y= 42}], Bar {v=[True, False, True]; w=(True, 17185); z=Foo {x= 123; y= 42}}), ([Foo {x= 43; y= 44}, Foo {x= 45; y= 46}, Foo {x= 47; y= 48}, Foo {x= 49; y= 50}, Foo {x= 51; y= 52}, Foo {x= 53; y= 54}, Foo {x= 55; y= 56}, Foo {x= 57; y= 58}], Bar {v=[True, True, True]; w=(True, 43707); z=Foo {x= 3; y= 4}})]; d=(); e=[]} putZug: Zug {qs=[Quix {q= 1; v=True}, Quix {q= 2; v=False}]; blob=False} +getFoo: DeepSplit (Foo {x= 42; y= 43}) +getBar: DeepSplit (Bar {v=[True, False, True]; w=(False, 17185); z=Foo {x= 42; y= 43}}) +getZug: DeepSplit (Zug {qs=[Quix {q=-2; v=True}, Quix {q= 2; v=False}]; blob=True}) +update: DeepSplit (Bar {v=[False, False, True]; w=(False, 57005); z=Foo {x= 0; y= 0}}) +update: DeepSplit (Bar {v=[True, True, False]; w=(True, 57005); z=Foo {x= 77; y= 88}}) diff --git a/testsuite/bsc.verilog/splitports/sysInstanceSplit.out.expected b/testsuite/bsc.verilog/splitports/sysInstanceSplit.out.expected index bb4f2dc03..00bf5618c 100644 --- a/testsuite/bsc.verilog/splitports/sysInstanceSplit.out.expected +++ b/testsuite/bsc.verilog/splitports/sysInstanceSplit.out.expected @@ -3,3 +3,7 @@ putBar: Bar {v=[True, False, True]; w=(True, 4660); z=Foo {x= 3; y= 4}} putFooBar: Foo {x= 5; y= 6} Bar {v=[False, True, False]; w=(False, 22136); z=Foo {x= 7; y= 8}} putFoos: [Foo {x= 9; y= 10}, Foo {x= 9; y= 10}, Foo {x= 10; y= 9}, Foo {x= 10; y= 8}, Foo {x= 11; y= 8}, Foo {x= 11; y= 7}, Foo {x= 12; y= 6}, Foo {x= 12; y= 6}, Foo {x= 13; y= 5}, Foo {x= 13; y= 4}, Foo {x= 14; y= 4}, Foo {x= 14; y= 3}, Foo {x= 15; y= 2}, Foo {x= 15; y= 2}, Foo {x= 16; y= 1}, Foo {x= 16; y= 0}, Foo {x= 17; y= 0}, Foo {x= 17; y= -1}, Foo {x= 18; y= -2}, Foo {x= 18; y= -2}, Foo {x= 19; y= -3}, Foo {x= 19; y= -4}, Foo {x= 20; y= -4}, Foo {x= 20; y= -5}, Foo {x= 21; y= -6}, Foo {x= 21; y= -6}, Foo {x= 22; y= -7}, Foo {x= 22; y= -8}, Foo {x= 23; y= -8}, Foo {x= 23; y= -9}, Foo {x= 24; y= -10}, Foo {x= 24; y= -10}, Foo {x= 25; y= -11}, Foo {x= 25; y= -12}, Foo {x= 26; y= -12}, Foo {x= 26; y= -13}, Foo {x= 27; y= -14}, Foo {x= 27; y= -14}, Foo {x= 28; y= -15}, Foo {x= 28; y= -16}, Foo {x= 29; y= -16}, Foo {x= 29; y= -17}, Foo {x= 30; y= -18}, Foo {x= 30; y= -18}, Foo {x= 31; y= -19}, Foo {x= 31; y= -20}, Foo {x= 32; y= -20}, Foo {x= 32; y= -21}, Foo {x= 33; y= -22}, Foo {x= 33; y= -22}] putBaz: Baz {a=Valid (Foo {x= 9; y= 10}); b=Bar {v=[True, False, False]; w=(True, 4660); z=Foo {x= 3; y= 4}}; c=[([Foo {x= 11; y= 12}, Foo {x= 13; y= 14}, Foo {x= 15; y= 16}, Foo {x= 17; y= 18}, Foo {x= 19; y= 20}, Foo {x= 21; y= 22}, Foo {x= 23; y= 24}, Foo {x= 25; y= 26}], Bar {v=[True, False, True]; w=(True, 48879); z=Foo {x= 3; y= 4}}), ([Foo {x= 27; y= 28}, Foo {x= 29; y= 30}, Foo {x= 31; y= 32}, Foo {x= 33; y= 34}, Foo {x= 35; y= 36}, Foo {x= 37; y= 38}, Foo {x= 39; y= 40}, Foo {x= 41; y= 42}], Bar {v=[True, False, True]; w=(True, 17185); z=Foo {x= 123; y= 42}}), ([Foo {x= 43; y= 44}, Foo {x= 45; y= 46}, Foo {x= 47; y= 48}, Foo {x= 49; y= 50}, Foo {x= 51; y= 52}, Foo {x= 53; y= 54}, Foo {x= 55; y= 56}, Foo {x= 57; y= 58}], Bar {v=[True, True, True]; w=(True, 43707); z=Foo {x= 3; y= 4}})]; d=(); e=[]} +getFoo: Foo {x= 42; y= 43} +getBar: Bar {v=[True, False, True]; w=(False, 17185); z=Foo {x= 42; y= 43}} +update: Bar {v=[False, False, True]; w=(False, 57005); z=Foo {x= 0; y= 0}} +update: Bar {v=[True, True, False]; w=(True, 57005); z=Foo {x= 77; y= 88}} diff --git a/testsuite/bsc.verilog/splitports/sysShallowSplit.out.expected b/testsuite/bsc.verilog/splitports/sysShallowSplit.out.expected index bb4f2dc03..40e21a373 100644 --- a/testsuite/bsc.verilog/splitports/sysShallowSplit.out.expected +++ b/testsuite/bsc.verilog/splitports/sysShallowSplit.out.expected @@ -3,3 +3,7 @@ putBar: Bar {v=[True, False, True]; w=(True, 4660); z=Foo {x= 3; y= 4}} putFooBar: Foo {x= 5; y= 6} Bar {v=[False, True, False]; w=(False, 22136); z=Foo {x= 7; y= 8}} putFoos: [Foo {x= 9; y= 10}, Foo {x= 9; y= 10}, Foo {x= 10; y= 9}, Foo {x= 10; y= 8}, Foo {x= 11; y= 8}, Foo {x= 11; y= 7}, Foo {x= 12; y= 6}, Foo {x= 12; y= 6}, Foo {x= 13; y= 5}, Foo {x= 13; y= 4}, Foo {x= 14; y= 4}, Foo {x= 14; y= 3}, Foo {x= 15; y= 2}, Foo {x= 15; y= 2}, Foo {x= 16; y= 1}, Foo {x= 16; y= 0}, Foo {x= 17; y= 0}, Foo {x= 17; y= -1}, Foo {x= 18; y= -2}, Foo {x= 18; y= -2}, Foo {x= 19; y= -3}, Foo {x= 19; y= -4}, Foo {x= 20; y= -4}, Foo {x= 20; y= -5}, Foo {x= 21; y= -6}, Foo {x= 21; y= -6}, Foo {x= 22; y= -7}, Foo {x= 22; y= -8}, Foo {x= 23; y= -8}, Foo {x= 23; y= -9}, Foo {x= 24; y= -10}, Foo {x= 24; y= -10}, Foo {x= 25; y= -11}, Foo {x= 25; y= -12}, Foo {x= 26; y= -12}, Foo {x= 26; y= -13}, Foo {x= 27; y= -14}, Foo {x= 27; y= -14}, Foo {x= 28; y= -15}, Foo {x= 28; y= -16}, Foo {x= 29; y= -16}, Foo {x= 29; y= -17}, Foo {x= 30; y= -18}, Foo {x= 30; y= -18}, Foo {x= 31; y= -19}, Foo {x= 31; y= -20}, Foo {x= 32; y= -20}, Foo {x= 32; y= -21}, Foo {x= 33; y= -22}, Foo {x= 33; y= -22}] putBaz: Baz {a=Valid (Foo {x= 9; y= 10}); b=Bar {v=[True, False, False]; w=(True, 4660); z=Foo {x= 3; y= 4}}; c=[([Foo {x= 11; y= 12}, Foo {x= 13; y= 14}, Foo {x= 15; y= 16}, Foo {x= 17; y= 18}, Foo {x= 19; y= 20}, Foo {x= 21; y= 22}, Foo {x= 23; y= 24}, Foo {x= 25; y= 26}], Bar {v=[True, False, True]; w=(True, 48879); z=Foo {x= 3; y= 4}}), ([Foo {x= 27; y= 28}, Foo {x= 29; y= 30}, Foo {x= 31; y= 32}, Foo {x= 33; y= 34}, Foo {x= 35; y= 36}, Foo {x= 37; y= 38}, Foo {x= 39; y= 40}, Foo {x= 41; y= 42}], Bar {v=[True, False, True]; w=(True, 17185); z=Foo {x= 123; y= 42}}), ([Foo {x= 43; y= 44}, Foo {x= 45; y= 46}, Foo {x= 47; y= 48}, Foo {x= 49; y= 50}, Foo {x= 51; y= 52}, Foo {x= 53; y= 54}, Foo {x= 55; y= 56}, Foo {x= 57; y= 58}], Bar {v=[True, True, True]; w=(True, 43707); z=Foo {x= 3; y= 4}})]; d=(); e=[]} +getFoo: ShallowSplit (Foo {x= 42; y= 43}) +getBar: ShallowSplit (Bar {v=[True, False, True]; w=(False, 17185); z=Foo {x= 42; y= 43}}) +update: ShallowSplit (Bar {v=[False, False, True]; w=(False, 57005); z=Foo {x= 0; y= 0}}) +update: ShallowSplit (Bar {v=[True, True, False]; w=(True, 57005); z=Foo {x= 77; y= 88}}) From 0c374379a3ad5575dcfae738151fcbcf44f392c1 Mon Sep 17 00:00:00 2001 From: Lucas Kramer Date: Mon, 12 Jan 2026 11:21:46 -0800 Subject: [PATCH 2/5] Fix findSupport demanding ae_objid and ameth_id on ATupleSel --- src/comp/DisjointTest.hs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/comp/DisjointTest.hs b/src/comp/DisjointTest.hs index 1de2481ce..896c3ac11 100644 --- a/src/comp/DisjointTest.hs +++ b/src/comp/DisjointTest.hs @@ -281,12 +281,12 @@ buildSupportMap adefs avis rs = --trace ("XXX support map:" ++ ppReadable res) $ [vlogport] -> [DMethod (ae_objid e) vlogport] ports -> internalError ("buildSupportMap: unexpected output ports: " ++ ppReadable (ae_objid e, ameth_id e, ports)) - findSupport e@(ATupleSel _ (AMethCall {ae_args = es}) idx) = + findSupport (ATupleSel _ e@(AMethCall {ae_args = es}) idx) = findAExprs findSupport es ++ [DMethod (ae_objid e) vlogport] where ports = getMethodOutputPorts portMap (ae_objid e) (ameth_id e) vlogport = genericIndex ports (idx - 1) - findSupport e@(ATupleSel _ (AMethValue {}) idx) = + findSupport (ATupleSel _ e@(AMethValue {}) idx) = [DMethod (ae_objid e) vlogport] where ports = getMethodOutputPorts portMap (ae_objid e) (ameth_id e) From 8e7f7bfcfc5d51c26ad8ad4fc93554fa0f2c8e95 Mon Sep 17 00:00:00 2001 From: Lucas Kramer Date: Mon, 12 Jan 2026 11:27:24 -0800 Subject: [PATCH 3/5] Handle ATuple and ATupleSel in rankMethCalls --- src/comp/ARankMethCalls.hs | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/comp/ARankMethCalls.hs b/src/comp/ARankMethCalls.hs index 9b6a946f6..6efc07bdb 100644 --- a/src/comp/ARankMethCalls.hs +++ b/src/comp/ARankMethCalls.hs @@ -121,13 +121,18 @@ class RankMethCalls ats_t where rankMethCalls :: Int -> ats_t -> (ats_t, [Id] {- local defs to rank -}) instance RankMethCalls AExpr where - -- TODO handle ATupleSel here? rankMethCalls ver expr@(AMethCall { ameth_id = name, ae_args = args }) = let (ranked_args, defs_to_rewrite) = rankMethCalls ver args in (expr { ameth_id = rankId ver name, ae_args = ranked_args }, defs_to_rewrite) rankMethCalls ver expr@(AMethValue { ameth_id = name }) = (expr { ameth_id = rankId ver name }, []) + rankMethCalls ver expr@(ATuple { ae_elems = elems }) = + let (ranked_elems, defs_to_rewrite) = rankMethCalls ver elems + in (expr { ae_elems = ranked_elems }, defs_to_rewrite) + rankMethCalls ver expr@(ATupleSel { ae_exp = e }) = + let (ranked_e, defs_to_rewrite) = rankMethCalls ver e + in (expr { ae_exp = ranked_e }, defs_to_rewrite) rankMethCalls ver expr@(ANoInlineFunCall { ae_args = args }) = let (ranked_args, defs_to_rewrite) = rankMethCalls ver args in (expr { ae_args = ranked_args }, defs_to_rewrite) From 6d3a36b0c054d3b68f68f559f381eaf23544c2fc Mon Sep 17 00:00:00 2001 From: Lucas Kramer Date: Wed, 14 Jan 2026 19:52:35 -0800 Subject: [PATCH 4/5] Tuple operations can be wop --- src/comp/SimCCBlock.hs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/comp/SimCCBlock.hs b/src/comp/SimCCBlock.hs index ef6418276..ec15e634b 100644 --- a/src/comp/SimCCBlock.hs +++ b/src/comp/SimCCBlock.hs @@ -523,6 +523,8 @@ adjustInstQuals id = -- check if an aexpr is just a var id, or other situation not to deal by wop hasWop :: AExpr -> Bool hasWop (APrim { aprim_prim = p }) = (p /= PrimIf) +hasWop (ATuple _ _) = True +hasWop (ATupleSel _ _ _) = True hasWop _ = False -- --------------------- From 76a2d19b50e1da8ec9967cc14269372765dbeb0b Mon Sep 17 00:00:00 2001 From: Lucas Kramer Date: Wed, 14 Jan 2026 19:53:33 -0800 Subject: [PATCH 5/5] Fix wop_primExtractWide to accept a const reference --- src/bluesim/bs_prim_ops.h | 2 +- src/bluesim/bs_wide_data.h | 2 +- src/bluesim/wide_data.cxx | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/bluesim/bs_prim_ops.h b/src/bluesim/bs_prim_ops.h index 08e3d1fd7..2ed2ea9d4 100644 --- a/src/bluesim/bs_prim_ops.h +++ b/src/bluesim/bs_prim_ops.h @@ -1654,7 +1654,7 @@ static inline void wop_primExtractWide(unsigned int dst_sz, static inline void wop_primExtractWide(unsigned int dst_sz, unsigned int src_sz, - tUWide & src, + const tUWide & src, unsigned int high_sz, unsigned int high, unsigned int low_sz, unsigned int low, tUWide &dst) diff --git a/src/bluesim/bs_wide_data.h b/src/bluesim/bs_wide_data.h index 2c056b3f7..dd4496fa8 100644 --- a/src/bluesim/bs_wide_data.h +++ b/src/bluesim/bs_wide_data.h @@ -102,7 +102,7 @@ class WideData unsigned int extract32(unsigned int hi, unsigned int lo) const; unsigned long long extract64(unsigned int hi, unsigned int lo) const; WideData extractWide(unsigned int hi, unsigned int lo) const; - void wop_extractWide(unsigned int hi, unsigned int lo, WideData& result); + void wop_extractWide(unsigned int hi, unsigned int lo, WideData& result) const; void clear(unsigned int from = 0); void clear(unsigned int from, unsigned int to); void set(unsigned int from = 0); diff --git a/src/bluesim/wide_data.cxx b/src/bluesim/wide_data.cxx index f718ce233..f30f1169c 100644 --- a/src/bluesim/wide_data.cxx +++ b/src/bluesim/wide_data.cxx @@ -1755,7 +1755,7 @@ void wop_rem(const WideData& v1, const WideData& v2, WideData &result) /*** function calls ***/ /* maybe useful */ -void WideData::wop_extractWide(uint hi, uint lo, WideData& result) +void WideData::wop_extractWide(uint hi, uint lo, WideData& result) const { copy_bits_to_0(result.data, data, lo, (hi-lo+1)); clear_bits(result.data, (hi-lo+1), (result.numWords() * WORD_SIZE) - 1);