The user valentin4077 from the BeagleBoard discord has got UART reading to work with R5 cores. His code was based off the example in R5_SIDE/r5_code/src/io_test_functions/uart_tests.c. Anyway, his fixes need to be brought over and tested.
Here is little working example from discord
#include "ti/csl/csl_uart.h"
#include "stdio.h"
#define BAUD_RATE_9600 (9600U)
#define BAUD_RATE_14400 (14400U)
#define BAUD_RATE_19200 (19200U)
#define BAUD_RATE_38400 (38400U)
#define BAUD_RATE_57600 (57600U)
#define BAUD_RATE_115200 (115200U)
#define BAUD_RATE_230400 (230400U)
#define BAUD_RATE_460800 (460800U)
#define BAUD_RATE_921600 (921600U)
#define BAUD_RATE BAUD_RATE_921600
#define WORD_LENGTH UART_FRAME_WORD_LENGTH_8 // define issu de "uart.h" du CSL
#define STOP_BIT UART_FRAME_NUM_STB_1 // define issu de "uart.h" du CSL
#define PARITY UART_PARITY_NONE // define issu de "uart.h" du CSL
#define UART_MODE UART16x_OPER_MODE // define issu de "uart.h" du CSL
#define UART_CLOCK_HZ (48000000U) // 48MHz est la fréquence nominale du périph par défaut, permettant de monter jusqu'à 3.6Mbps. (cf. chapitre 12.1.6.1.1 du doc TI SPRUIL1D)
#define UART2 (0x2820000U)
#define UART3 (0x2830000U)
#define UART4 (0x2840000U)
#define UART5 (0x2850000U)
#define UART6 (0x2860000U)
#define UART7 (0x2870000U)
#define UART8 (0x2880000U)
volatile uint32_t UARTx;
#define TX_DISABLE (1U)
#define TX_ENABLE (0U)
#define RX_ACTIVE (1U)
#define RX_INACTIVE (0U)
#define PULL_DOWN (0U)
#define PULL_UP (1U)
#define PULL_ENABLED (0U)
#define PULL_DISABLED (1U)
#define MUX_MODE_3 (3U) // pour UART6 - BBAI64 P9.14 et P9.16
#define MUX_MODE_14 (14U) // pour UART6 - BBAI64 P9.31 et P8.26 + UART2 - TDA4VM_EVM P8 et P10
#define PINMUX_VALUE(_txdisable,_rxActive, _pullType, _pull, _mux) ((_txdisable << 21) | (_rxActive << 18) | (_pullType << 17) | (_pull << 16) | (0x0 << 4) | (_mux << 0))
#define PADCONFIG_ADDR71 (0x0011C11CU) // pour UART2 TX - TDA4VM_EVM => BALL AA26
#define PADCONFIG_ADDR82 (0x0011C148U) // pour UART2 RX - TDA4VM_EVM => BALL AA24
#define PADCONFIG_ADDR53 (0x0011C0D4U) // pour UART6 TX - BBAI64 P9.31 => BALL AB26
#define PADCONFIG_ADDR52 (0x0011C0D0U) // pour UART6 RX - BBAI64 P8.26 => BALL AC27
#define PADCONFIG_ADDR94 (0x0011C178U) // pour UART6 TX - BBAI64 P9.14 => BALL U27
#define PADCONFIG_ADDR95 (0x0011C17CU) // pour UART6 RX - BBAI64 P9.16 => BALL U24
volatile uint32_t *padconfig_UARTx_tx;
volatile uint32_t *padconfig_UARTx_rx;
#define BOARD_KICK0_UNLOCK_VAL (0x68EF3490U) // Keys to unlock partitions MMR0
#define BOARD_KICK1_UNLOCK_VAL (0xD172BC5AU) // Keys to unlock partitions MMR0
#define BOARD_KICK0_LOCK_VAL (0U)
#define BOARD_KICK1_LOCK_VAL (0U)
#define ADDR_LOCK0_KICK0 (0x00101008U)
#define ADDR_LOCK0_KICK1 (0x0010100CU)
#define ADDR_LOCK1_KICK0 (0x00105008U)
#define ADDR_LOCK1_KICK1 (0x0010500CU)
#define ADDR_LOCK2_KICK0 (0x00109008U)
#define ADDR_LOCK2_KICK1 (0x0010900CU)
#define ADDR_LOCK3_KICK0 (0x0010D008U)
#define ADDR_LOCK3_KICK1 (0x0010D00CU)
#define ADDR_LOCK4_KICK0 (0x00111008U)
#define ADDR_LOCK4_KICK1 (0x0011100CU)
#define ADDR_LOCK5_KICK0 (0x00115008U)
#define ADDR_LOCK5_KICK1 (0x0011500CU)
#define ADDR_LOCK6_KICK0 (0x00119008U)
#define ADDR_LOCK6_KICK1 (0x0011900CU)
#define ADDR_LOCK7_KICK0 (0x0011D008U)
#define ADDR_LOCK7_KICK1 (0x0011D00CU)
volatile uint32_t *LOCKx_KICK0;
volatile uint32_t *LOCKx_KICK1;
void main()
{
/* ========================== For UART5 - BBAI64 RX-P8.38 et TX-P8.37 ================================== */
UARTx = (uint32_t)UART5;
/* ============================================================================================== */
/* INIT UART */
/* ============================================================================================== */
UARTModuleReset(UARTx);
UARTOperatingModeSelect(UARTx, UART_MODE);
uint32_t divisorValue = UARTDivisorValCompute(UART_CLOCK_HZ, BAUD_RATE, UART_MODE, 0);
UARTDivisorLatchEnable(UARTx);
UARTDivisorLatchWrite(UARTx, divisorValue);
UARTDivisorLatchDisable(UARTx);
UARTLineCharacConfig(UARTx, (WORD_LENGTH | STOP_BIT), PARITY);
uint32_t fifoconfig = UART_FIFO_CONFIG(
UART_TRIG_LVL_GRANULARITY_1,
UART_TRIG_LVL_GRANULARITY_1,
0,
0,
0,
0,
UART_DMA_EN_PATH_SCR,
UART_DMA_MODE_0_ENABLE
);
UARTFIFOConfig(UARTx, fifoconfig);
UARTOperatingModeSelect(UARTx, UART_MODE);
/* ============================================================================================== */
/* UART TEST (loopback tx->rx on same UART) */
/* ============================================================================================== */
volatile char received = '0';
volatile char i = 0;
printf("Starting UART test on UARTx: 0x%08lX\n", UARTx);
while(1)
{
while(!UARTSpaceAvail(UARTx));
UARTCharPut(UARTx, 'a'+i++%26);
printf("Send character \n");
received = UARTCharGet(UARTx);
printf("Received character: %c\n", received);
}
}https://discord.com/channels/1108795636956024986/1108811712112623746/1394965404694085686
The user valentin4077 from the BeagleBoard discord has got UART reading to work with R5 cores. His code was based off the example in
R5_SIDE/r5_code/src/io_test_functions/uart_tests.c. Anyway, his fixes need to be brought over and tested.Here is little working example from discord
https://discord.com/channels/1108795636956024986/1108811712112623746/1394965404694085686