diff --git a/briefs/riscv-blockchain-compilation-target.md b/briefs/riscv-blockchain-compilation-target.md new file mode 100644 index 0000000..775e505 --- /dev/null +++ b/briefs/riscv-blockchain-compilation-target.md @@ -0,0 +1,119 @@ +# RISC-V as a Blockchain Compilation Target + +**Authors:** Pattermesh, Abhishek Krishna +**Date:** June 2026 +**Status:** Draft — for internal review + +--- + +## Abstract + +We propose RISC-V as a native compilation target for blockchain execution environments, leveraging Tenstorrent's open-source processor cores and AI accelerator hardware. By compiling smart contracts to RISC-V with cryptographic ISA extensions (Zkn, Zvk*), blockchain workloads gain hardware-accelerated hashing, signing, and field arithmetic without proprietary silicon dependencies. We identify Fully Homomorphic Encryption (FHE), zero-knowledge proof generation, and multi-party computation as the highest-value acceleration targets, and outline how Tenstorrent's Tensix matrix architecture can provide orders-of-magnitude improvement over software-only FHE bootstrapping. + +--- + +## 1. Problem + +Blockchain virtual machines execute on general-purpose CPUs. The cryptographic primitives that dominate blockchain workloads — Keccak-256 (Ethereum), SHA-256 (Bitcoin/Merkle trees), ECDSA (transaction signing), NTT (ZK proofs), and polynomial multiplication (FHE) — run in software without hardware assistance. + +Meanwhile, the RISC-V ISA has standardized cryptographic extensions: +- **Zkn** (NIST): Hardware AES, SHA-256, SHA-512 +- **Zks** (ShangMi): Hardware SM3, SM4 +- **Zvk***: Vectorized cryptographic operations +- **Zkr**: Hardware entropy source + +These extensions provide 3-10x speedup over software implementations of standard crypto primitives. Yet no blockchain project has adopted RISC-V as a compilation target to leverage them. + +## 2. Opportunity + +Tenstorrent, led by Jim Keller, has open-sourced: + +1. **Ocelot** — an out-of-order RV64GC processor core with vector extension support (250 GitHub stars, BSD/Apache licensed, boots Linux, FPGA-deployable) +2. **Whisper** — a RISC-V instruction set simulator implementing the full Zkn/Zks/Zvk* crypto extension suite +3. **Blackhole** — an AI accelerator chip with 120 Tensix cores (664 TFLOPS matrix compute), 16 "Big RISC-V" cores, and 180 MB on-chip SRAM +4. **Caliptra** — a Root of Trust IP block with dedicated hardware for ECC, SHA-2/3, AES, ML-DSA (post-quantum), and key management + +No one has built the software bridge between this hardware ecosystem and blockchain execution. The opportunity is first-mover: the team that builds RISC-V crypto acceleration for blockchain defines the standard. + +## 3. Architecture + +The compilation pipeline: + +``` +Smart Contract (Solidity/Rust) → WASM → RISC-V (rv64gc + Zkn) + ↓ + ┌──────┴──────┐ + │ Ocelot Core │ → General execution + │ (RV64GC) │ + └──────┬──────┘ + │ Offload + ┌──────▼──────┐ + │ Tensix Cores│ → FHE/ZK/NTT acceleration + │ (664 TFLOPS)│ + └─────────────┘ +``` + +This pattern already exists in production: **Arbitrum Stylus** compiles smart contracts from WASM to a RISC-V-based execution environment. Extending this pattern to target Tenstorrent's open cores — and offloading compute-heavy crypto to Tensix — is architecturally straightforward. + +## 4. Acceleration Targets + +### 4.1 Fully Homomorphic Encryption (FHE) + +FHE enables computation on encrypted data. Its bottleneck is **bootstrapping**, which reduces to: +- Number Theoretic Transform (NTT): structured butterfly operations → matrix multiplication +- Polynomial multiplication: convolution via NTT → matrix-vector products +- Key switching: large matrix-vector multiply + +Tenstorrent Blackhole's Tensix cores are purpose-built for matrix operations. With 664 TFLOPS and 180 MB SRAM (sufficient to hold FHE keys for moderate parameters without external memory), we project 10-100x bootstrapping speedup over CPU and competitive performance with GPU approaches — without the GPU memory bandwidth bottleneck. + +### 4.2 Zero-Knowledge Proofs + +ZK-SNARK proof generation is dominated by NTT/iNTT and multi-scalar multiplication (MSM). Both decompose into parallelizable structured operations that map to Tensix. Vector crypto extensions (Zvknha/b) additionally accelerate the hash computations within recursive proof systems. + +### 4.3 Multi-Party Computation (MPC) + +MPC protocols rely on ECC operations (key generation, signing), AES (garbled circuits), and SHA (commitments). Caliptra's dedicated hardware accelerators provide: +- Side-channel-resistant ECC (critical for key shares) +- Hardware AES for garbled circuit evaluation +- ML-DSA for post-quantum MPC protocols + +## 5. Competitive Landscape + +| Approach | Openness | Crypto Accel | Matrix Compute | Status | +|---|---|---|---|---| +| NVIDIA GPU (CUDA) | Proprietary | Software only | High TFLOPS | Production FHE/ZK | +| FPGA (Xilinx/Intel) | Proprietary bitstreams | Custom | Moderate | Research prototypes | +| Custom ASIC | Fully proprietary | Purpose-built | High | Ingonyama, Cysic (ZK) | +| **RISC-V + Tenstorrent** | **Fully open** | **ISA-native (Zkn/Zvk*)** | **664 TFLOPS (Tensix)** | **Proposed** | + +The open-source advantage is decisive for blockchain: verifiable execution on auditable hardware, no vendor lock-in, community-extensible. + +## 6. Roadmap + +| Phase | Deliverable | Timeline | +|---|---|---| +| 0 | Fork Ocelot, crypto benchmarks, this brief | Week 1-2 | +| 1 | Rust crypto primitives targeting rv64gc (Whisper ISS) | Week 2-4 | +| 2 | TT-Metalium FHE kernels (NTT, polynomial multiply) | Week 4-8 | +| 3 | LUX → RISC-V compilation path, full benchmarks | Week 8-12 | +| 4 | Research paper with benchmarks, upstream contributions | Week 12+ | + +## 7. Conclusion + +RISC-V with cryptographic extensions and Tenstorrent's open AI accelerator hardware presents a unique opportunity for blockchain execution. The compilation path (contract → WASM → RISC-V → Tensix offload) is architecturally proven by Arbitrum Stylus. The hardware is open, available ($999 for a Wormhole card), and crypto-capable. The software bridge does not yet exist. We intend to build it. + +--- + +## References + +1. Tenstorrent riscv-ocelot: https://github.com/tenstorrent/riscv-ocelot +2. Tenstorrent tt-metal: https://github.com/tenstorrent/tt-metal +3. Tenstorrent whisper: https://github.com/tenstorrent/whisper +4. RISC-V Cryptography Extensions: https://github.com/riscv/riscv-crypto +5. Arbitrum Stylus documentation: https://docs.arbitrum.io/stylus +6. Chillotti et al., "TFHE: Fast FHE over the Torus" (2020) +7. kcolbchain FHE fork: https://github.com/kcolbchain/fhe + +--- + +*kcolbchain Research — est. 2015 | CC BY 4.0*