uctypes for DMA CTRL reg

[mkrasuski]

RP2040 docs state that any write to CTRL on Alias 0 (DMA_CHAN_ADDRESS + 0xC offset) starts the transfer... You're mapping this 4 bytes to bitfields uctypes struct, so every write access to any bit field probably writes CTRL, i.e. starts DMA... Results may be unpredictable and hardly depend on sequence of field assignments. We should treat building of CTRL value in transactional manner (compute whole 32bit value and then assign) - C API does it this way. Probably your code works due to update to EN field as last operation, but this is pure luck

[rickado22]

From RP2040 datasheet 2.5.7. List of Registers
--DMA: CH0_CTRL_TRIG
bit 0 EN
DMA Channel Enable.
When 1, the channel will respond to triggering events,
which will cause it to become BUSY and start transferring
data. When 0, the channel will ignore triggers, stop issuing
transfers, and pause the current transfer sequence (i.e.
BUSY will remain high if already high)

As you can see mkrasuski When Bit 0 = 0 The channel will ignore triggers which makes sense (ie it is disabled) so the code works due to the update to EN as last operation, which is pure genius