Wiki "Bit 0 Channel Disable"

[chrisjj]

Dave,

Regarding https://github.com/hoglet67/Music5000/wiki "Bit 0 Channel Disable".

If I recall correctly, what this does is set the phase to 0, and is used to implement a) oscillator sync (by hardware modulation) and b) gate sync, for sharp attacks (by software in the ON GATE code of the M5 module.

[hoglet67]

Thanks for this info Chris. I've updated the wiki, and I'll check what the VHDL does later.

[chrisjj]

PS I did recall correctly. Here's the relevant section from the circuit diagram, page 2: https://i.imgur.com/zljMwSk.png

Adding image inline:

[chrisjj]

PPS Somewhat belatedly :) now I spot a possible optimisation eliminating two ICs! To set the data from IC12 to zero, instead of ICs 8 and 9, use the OE of IC12, going Hi-Z and relying on IC11 and 6 inputs floating high. (24 logic 1's equalling 0's almost exactly in this arithmetic.) My only doubt comes from the fact my 40-years-smarter self didn't use this at the time. :) Even if I'd been wary of breaking the rules to use a floating input, I could have pulled up with a cheap bussed resistor array.

What do you think?

[hoglet67]

I'll think about this more over the weekend.

I think this feature (or something approximating it) is present in the VHDL:
https://github.com/hoglet67/Music5000/blob/master/src/Music5000.vhd

Specifically, it looks like the bit 0 of the freq register is registered as a signal called "load", and when this is high the B input to the ALU is forced to zero.

But it doesn't seem quite the same as the schematic, which surprises me.

I just need to go back in time 8 years when this was all fresh in my memory.

You must know that feeling as well!!

Oh, and I think your optimization might indeed work.

[hoglet67]

Comparing the VHDL and the real hardware....

There is a signal called load that is modelling the state of the LS74 FF (IC3) Q output:

process(clk6)
    begin
        if rising_edge(clk6) then
            if clk6en = '1' then
                if (s1_n = '0') then
                    load <= wave_dout(0);
                elsif (s6_n = '0') then
                    load <= '0';
                end if;
            end if;
        end if;
    end process;

The only difference is this uses s6 as a synchronous clear; the original design uses s7 as an asynchronous clear.

This then controls the B input of the ALU:

    bb <= sum1 when s0_n = '0' and load = '0' else
         phase_dout when addr(0) = '0' and load = '0' else
         (others => '0');

If the channel is disabled (load == 1) then B = 0

If the channel is enabled (load == 0) then B is:

- s0: Sum 
- s1: 0
- s2: Phase RAM Dout
- s3: 0
- s4: Phase RAM Dout
- s5: 0
- s6: Phase RAM Dout
- s7: 0

I think this is equivalent to, but not identical to, the original hardware.

I think it fell out this way because the phase ram in the FPGA has seperate Din and Dout ports, where as these are shared in the realy hardware. I'll have to dig out my old paper notes to check this tomorrow.