Memory Consistency

[ganoam]

In the event of offloaded memory access instructions, there is currently no way to guarantee the order in which the operations are executed. At the moment, no ultimate solution exists in our design.
The fact that outstanding register file writebacks can be detected in the scoreboard of the offloading core provides some measure of control. However, it is not guaranteed that the accelerator will not make memory requests that do not impact the integer register file. To handle this case, we could implement a memory fence instruction, which would need to be sent to each accelerator that is capable of accessing memory.

This may prove to be a bit problematic, as there is no way to send one and the same instruction to multiple accelerators; Our offloading scheme allows only one type of accelerator to accept any one instruction.
In order to send the fence instruction to all accelerators, we would therefore need to define separate fence instructions for each eligible accelerator.

This issue is meant to collect and discuss ideas and ultimately decide on a course of action.

[ganoam]

One possible idea of implementing a fence instruction is described below.

We could define a non-standard use of the instruction rd address field: In case of a fence instruction, this field would be interpreted both as the write-back location for the accelerator answer and the accelerator address. The fence operation would then boil down to two parts:

• fence_send rd=acc_address: This instruction must be offloaded to each of the eligible accelerators to signal that a memory barrier has occured. The accelerator subsystem would need to wait until all load and store instructions associated with the requesting core have retired before responding. Simultaneously, the register corresponding to the accelerator address is reserved.
• fence_wait rs1=acc_address: This instruction is core-local and serves the only purpose of stalling the core until the reservation on the register associated with the accelerator in question is lifted. It has to be executed for each accelerator with a view into memory.

[ganoam]

Another possibility would be to route a dedicated line from each accelerator to every core, signaling outstanding memory accesses in its workload.