risc-v simulator homework for compiler class. Implementation supports rv32imf_zbb(+zicsr) arch.
- C++ compiler (with C++20 support)
- CMake (3.21+)
- Python (3.12+)
- Graphviz (optional)
cmake -B build -S . -DCMAKE_BUILD_TYPE=Release
cmake --build build./build/riscv-sim.x <elf_bin> <args for elf_bin...>This project use generator to produce instruction decoder from the ISA description
(src/isa/include/isa/isa_ext.inc, the MNEMONIC(name, mask, match) table).
During the CMake build, the Python generator (decode/pygen/gen_decoder.py)
builds a decision tree over instruction bits/slices and emits decode.cpp as nested if/switch code.
You can select the decoder backend at configure time: -DDECODE_BACKEND=generated (default) or -DDECODE_BACKEND=linear.
Optionally, add -DDECODE_EMIT_DOT=ON to produce .dot representation of decision tree.
Example of generated decision tree for rv32i:
