From ebfead9d77d9467d98290fba9b65eb2be9866ebc Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 21 Nov 2023 19:05:13 -0800 Subject: [PATCH 1/3] riscv: Add support for kernel-mode FPU This is needed to support recent hardware in the amdgpu DRM driver. The FPU code in that driver is not performance-critical, so only provide the minimal support. Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20231122030621.3759313-2-samuel.holland@sifive.com Signed-off-by: Han Gao --- arch/riscv/include/asm/switch_to.h | 14 ++++++++++++++ arch/riscv/kernel/process.c | 3 +++ 2 files changed, 17 insertions(+) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index a727be723c56..6fd519f9e364 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -63,6 +63,20 @@ static __always_inline bool has_fpu(void) return riscv_has_extension_likely(RISCV_ISA_EXT_f) || riscv_has_extension_likely(RISCV_ISA_EXT_d); } + +static inline void kernel_fpu_begin(void) +{ + preempt_disable(); + fstate_save(current, task_pt_regs(current)); + csr_set(CSR_SSTATUS, SR_FS); +} + +static inline void kernel_fpu_end(void) +{ + csr_clear(CSR_SSTATUS, SR_FS); + fstate_restore(current, task_pt_regs(current)); + preempt_enable(); +} #else static __always_inline bool has_fpu(void) { return false; } #define fstate_save(task, regs) do { } while (0) diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e32d737e039f..88d6760f5ac8 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -207,3 +207,6 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) p->thread.sp = (unsigned long)childregs; /* kernel sp */ return 0; } + +EXPORT_SYMBOL_GPL(__fstate_save); +EXPORT_SYMBOL_GPL(__fstate_restore); From 4975c2e437bcb0b90dbc084ed9b8f3d7b480f62e Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 21 Nov 2023 19:05:14 -0800 Subject: [PATCH 2/3] riscv: Factor out riscv-march-y to a separate Makefile Since it is not possible to incrementally add/remove extensions from the compiler's ISA string by appending arguments, any code that wants to modify the ISA string must recreate the whole thing. To support this, factor out the logic for generating the -march argument so it can be reused where needed. Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20231122030621.3759313-3-samuel.holland@sifive.com Signed-off-by: Han Gao --- arch/riscv/Makefile | 17 +---------------- arch/riscv/Makefile.isa | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 16 deletions(-) create mode 100644 arch/riscv/Makefile.isa diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index b43a6bb7e4dc..7c6bf33479df 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -54,22 +54,7 @@ endif endif endif -# ISA string setting -riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima -riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima -riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd -riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c -riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v - -ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC -KBUILD_CFLAGS += -Wa,-misa-spec=2.2 -KBUILD_AFLAGS += -Wa,-misa-spec=2.2 -else -riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei -endif - -# Check if the toolchain supports Zihintpause extension -riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause +include $(srctree)/arch/riscv/Makefile.isa # Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by # matching non-v and non-multi-letter extensions out with the filter ([^v_]*) diff --git a/arch/riscv/Makefile.isa b/arch/riscv/Makefile.isa new file mode 100644 index 000000000000..322a83958b96 --- /dev/null +++ b/arch/riscv/Makefile.isa @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ISA string setting +riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima +riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima +riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd +riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c +riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v + +ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC +KBUILD_CFLAGS += -Wa,-misa-spec=2.2 +KBUILD_AFLAGS += -Wa,-misa-spec=2.2 +else +riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei +endif + +# Check if the toolchain supports Zihintpause extension +riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause From df27699fc9f19ff3551b2868eb7d7f0f8044dfab Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 21 Nov 2023 19:05:15 -0800 Subject: [PATCH 3/3] drm/amd/display: Support DRM_AMD_DC_FP on RISC-V RISC-V uses kernel_fpu_begin()/kernel_fpu_end() like several other architectures. Enabling hardware FP requires overriding the ISA string for the relevant compilation units. Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20231122030621.3759313-4-samuel.holland@sifive.com Signed-off-by: Han Gao --- drivers/gpu/drm/amd/display/Kconfig | 5 ++++- drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 6 ++++-- drivers/gpu/drm/amd/display/dc/dml/Makefile | 6 ++++++ 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 901d1961b739..49b33b2f6701 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -8,7 +8,10 @@ config DRM_AMD_DC depends on BROKEN || !CC_IS_CLANG || ARM64 || RISCV || SPARC64 || X86_64 select SND_HDA_COMPONENT if SND_HDA_CORE # !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752 - select DRM_AMD_DC_FP if (X86 || LOONGARCH || (PPC64 && ALTIVEC) || (ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG)) + select DRM_AMD_DC_FP if ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG + select DRM_AMD_DC_FP if PPC64 && ALTIVEC + select DRM_AMD_DC_FP if RISCV && FPU + select DRM_AMD_DC_FP if LOONGARCH || X86 help Choose this option if you want to use the new display engine support for AMDGPU. This adds required support for Vega and diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c index 172aa10a8800..53a7122ba98d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -35,6 +35,8 @@ #include #elif defined(CONFIG_LOONGARCH) #include +#elif defined(CONFIG_RISCV) +#include #endif /** @@ -90,7 +92,7 @@ void dc_fpu_begin(const char *function_name, const int line) *pcpu += 1; if (*pcpu == 1) { -#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) || defined(CONFIG_RISCV) migrate_disable(); kernel_fpu_begin(); #elif defined(CONFIG_PPC64) @@ -130,7 +132,7 @@ void dc_fpu_end(const char *function_name, const int line) pcpu = get_cpu_ptr(&fpu_recursion_depth); *pcpu -= 1; if (*pcpu <= 0) { -#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) || defined(CONFIG_RISCV) kernel_fpu_end(); migrate_enable(); #elif defined(CONFIG_PPC64) diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 0ba9a7997d56..96f7110e8e41 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -43,6 +43,12 @@ dml_ccflags := -mfpu=64 dml_rcflags := -msoft-float endif +ifdef CONFIG_RISCV +include $(srctree)/arch/riscv/Makefile.isa +# Remove V from the ISA string, like in arch/riscv/Makefile, but keep F and D. +dml_ccflags := -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)([^v_]*)v?/\1\2/') +endif + ifdef CONFIG_CC_IS_GCC ifneq ($(call gcc-min-version, 70100),y) IS_OLD_GCC = 1