verible-verilog-format does not work correctly from VSCode-SystemVerilog

[hwmland]

verible-verilog-format does add empty line after each comment with //

module serialdp (
    input clk,
    input in,
    input reset,  // Synchronous reset
    output reg [7:0] out_byte,
    output done
); 

becomes after formatting this:

module serialdp (
    input clk,
    input in,
    input reset,  // Synchronous reset

    output reg [7:0] out_byte,
    output done
); 

Each attempt to format adds new empty line (for each line with comment)
I disabled all other extensions. When I run verible-verilog-format from command-line everything is OK.
I have no command-line parameters, I'm running on Windows, verible installed in c:\verible (so no spaces) directory with full path provided in command. Any idea? I don't what to try next :(