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InstructionSet.cpp
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1837 lines (1794 loc) · 131 KB
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#include "InstructionSet.hpp"
#include "Operand.hpp"
#include <string.h>
#include <stdio.h>
#include <assert.h>
namespace SoftWire
{
const Instruction::Syntax InstructionSet::instructionSet[] =
{
/*
Encoding syntax:
----------------
+r Add register value to opcode
/# Value for Mod R/M register field encoding
/r Effective address encoding
ib Byte immediate
iw Word immediate
id Dword immediate
-b Byte relative address
-i Word or dword relative address
p0 LOCK instruction prefix (F0h)
p2 REPNE/REPNZ instruction prefix (F2h)
p3 REP/REPE/REPZ instruction prefix (F3h) (also SSE prefix)
po Offset override prefix (66h)
pa Address override prefix (67h)
Read Keywords.cpp for operands syntax
*/
// x86 instruction set
{"AAA", "", "37", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
{"AAD", "", "D5 0A", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
{"AAD", "imm", "D5 ib", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
{"AAM", "", "D4 0A", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
{"AAM", "imm", "D4 ib", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
{"AAS", "", "3F", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
{"ADC", "r/m8,reg8", "10 /r", Instruction::CPU_8086},
{"ADC", "r/m16,reg16", "po 11 /r", Instruction::CPU_8086},
{"ADC", "r/m32,reg32", "po 11 /r", Instruction::CPU_386},
{"ADC", "r/m64,reg64", "po 11 /r", Instruction::CPU_X64},
{"ADC", "reg8,r/m8", "12 /r", Instruction::CPU_8086},
{"ADC", "reg16,r/m16", "po 13 /r", Instruction::CPU_8086},
{"ADC", "reg32,r/m32", "po 13 /r", Instruction::CPU_386},
{"ADC", "reg64,r/m64", "po 13 /r", Instruction::CPU_X64},
{"ADC", "BYTE r/m8,imm8", "80 /2 ib", Instruction::CPU_8086},
{"ADC", "WORD r/m16,imm16", "po 81 /2 iw", Instruction::CPU_8086},
{"ADC", "DWORD r/m32,imm32", "po 81 /2 id", Instruction::CPU_386},
{"ADC", "QWORD r/m64,imm32", "po 81 /2 id", Instruction::CPU_X64},
{"ADC", "WORD r/m16,imm8", "po 83 /2 ib", Instruction::CPU_8086},
{"ADC", "DWORD r/m32,imm8", "po 83 /2 ib", Instruction::CPU_386},
{"ADC", "QWORD r/m64,imm8", "po 83 /2 ib", Instruction::CPU_X64},
{"ADC", "AL,imm8", "14 ib", Instruction::CPU_8086},
{"ADC", "AX,imm16", "po 15 iw", Instruction::CPU_8086},
{"ADC", "EAX,imm32", "po 15 id", Instruction::CPU_386},
{"ADC", "RAX,imm32", "po 15 id", Instruction::CPU_X64},
{"ADD", "r/m8,reg8", "00 /r", Instruction::CPU_8086},
{"ADD", "r/m16,reg16", "po 01 /r", Instruction::CPU_8086},
{"ADD", "r/m32,reg32", "po 01 /r", Instruction::CPU_386},
{"ADD", "r/m64,reg64", "po 01 /r", Instruction::CPU_X64},
{"ADD", "reg8,r/m8", "02 /r", Instruction::CPU_8086},
{"ADD", "reg16,r/m16", "po 03 /r", Instruction::CPU_8086},
{"ADD", "reg32,r/m32", "po 03 /r", Instruction::CPU_386},
{"ADD", "reg64,r/m64", "po 03 /r", Instruction::CPU_X64},
{"ADD", "BYTE r/m8,imm8", "80 /0 ib", Instruction::CPU_8086},
{"ADD", "WORD r/m16,imm16", "po 81 /0 iw", Instruction::CPU_8086},
{"ADD", "DWORD r/m32,imm32", "po 81 /0 id", Instruction::CPU_386},
{"ADD", "QWORD r/m64,imm32", "po 81 /0 id", Instruction::CPU_X64},
{"ADD", "WORD r/m16,imm8", "po 83 /0 ib", Instruction::CPU_8086},
{"ADD", "DWORD r/m32,imm8", "po 83 /0 ib", Instruction::CPU_386},
{"ADD", "QWORD r/m64,imm8", "po 83 /0 ib", Instruction::CPU_X64},
{"ADD", "AL,imm8", "04 ib", Instruction::CPU_8086},
{"ADD", "AX,imm16", "po 05 iw", Instruction::CPU_8086},
{"ADD", "EAX,imm32", "po 05 id", Instruction::CPU_386},
{"ADD", "RAX,imm32", "po 05 id", Instruction::CPU_X64},
{"ADDPD", "xmmreg,r/m128", "66 0F 58 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"ADDPS", "xmmreg,r/m128", "0F 58 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"ADDSD", "xmmreg,xmm64", "p2 0F 58 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"ADDSS", "xmmreg,xmm32", "p3 0F 58 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"ADDSUBPD", "xmmreg,r/m128", "66 0F D0 /r", Instruction::CPU_PNI},
{"ADDSUBPS", "xmmreg,r/m128", "p2 0F D0 /r", Instruction::CPU_PNI},
{"ALIGN", "imm", "p1 90"}, // Special 'instruction', indicated by the 'p1' prefix
{"AND", "r/m8,reg8", "20 /r", Instruction::CPU_8086},
{"AND", "r/m16,reg16", "po 21 /r", Instruction::CPU_8086},
{"AND", "r/m32,reg32", "po 21 /r", Instruction::CPU_386},
{"AND", "r/m64,reg64", "po 21 /r", Instruction::CPU_X64},
{"AND", "reg8,r/m8", "22 /r", Instruction::CPU_8086},
{"AND", "reg16,r/m16", "po 23 /r", Instruction::CPU_8086},
{"AND", "reg32,r/m32", "po 23 /r", Instruction::CPU_386},
{"AND", "reg64,r/m64", "po 23 /r", Instruction::CPU_X64},
{"AND", "BYTE r/m8,imm8", "80 /4 ib", Instruction::CPU_8086},
{"AND", "WORD r/m16,imm16", "po 81 /4 iw", Instruction::CPU_8086},
{"AND", "DWORD r/m32,imm32", "po 81 /4 id", Instruction::CPU_386},
{"AND", "QWORD r/m64,imm32", "po 81 /4 id", Instruction::CPU_X64},
{"AND", "WORD r/m16,imm8", "po 83 /4 ib", Instruction::CPU_8086},
{"AND", "DWORD r/m32,imm8", "po 83 /4 ib", Instruction::CPU_386},
{"AND", "QWORD r/m64,imm8", "po 83 /4 ib", Instruction::CPU_X64},
{"AND", "AL,imm8", "24 ib", Instruction::CPU_8086},
{"AND", "AX,imm16", "po 25 iw", Instruction::CPU_8086},
{"AND", "EAX,imm32", "po 25 id", Instruction::CPU_386},
{"AND", "RAX,imm32", "po 25 id", Instruction::CPU_X64},
{"ANDNPD", "xmmreg,r/m128", "66 0F 55 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"ANDNPS", "xmmreg,r/m128", "0F 55 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"ANDPD", "xmmreg,r/m128", "66 0F 54 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"ANDPS", "xmmreg,r/m128", "0F 54 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
// {"ARPL", "r/m16,reg16", "63 /r", Instruction::CPU_286 | Instruction::CPU_PRIV},
{"BOUND", "reg16,mem", "po 62 /r", Instruction::CPU_186 | Instruction::CPU_INVALID64},
{"BOUND", "reg32,mem", "po 62 /r", Instruction::CPU_386 | Instruction::CPU_INVALID64},
{"BSF", "reg16,r/m16", "po 0F BC /r", Instruction::CPU_386},
{"BSF", "reg32,r/m32", "po 0F BC /r", Instruction::CPU_386},
{"BSF", "reg64,r/m64", "po 0F BC /r", Instruction::CPU_X64},
{"BSR", "reg16,r/m16", "po 0F BD /r", Instruction::CPU_386},
{"BSR", "reg32,r/m32", "po 0F BD /r", Instruction::CPU_386},
{"BSR", "reg64,r/m64", "po 0F BD /r", Instruction::CPU_X64},
{"BSWAP", "reg32", "po 0F C8 +r", Instruction::CPU_486},
{"BSWAP", "reg64", "po 0F C8 +r", Instruction::CPU_X64},
{"BT", "r/m16,reg16", "po 0F A3 /r", Instruction::CPU_386},
{"BT", "r/m32,reg32", "po 0F A3 /r", Instruction::CPU_386},
{"BT", "r/m64,reg64", "po 0F A3 /r", Instruction::CPU_X64},
{"BT", "WORD r/m16,imm8", "po 0F BA /4 ib", Instruction::CPU_386},
{"BT", "DWORD r/m32,imm8", "po 0F BA /4 ib", Instruction::CPU_386},
{"BT", "QWORD r/m64,imm8", "po 0F BA /4 ib", Instruction::CPU_X64},
{"BTC", "r/m16,reg16", "po 0F BB /r", Instruction::CPU_386},
{"BTC", "r/m32,reg32", "po 0F BB /r", Instruction::CPU_386},
{"BTC", "r/m64,reg64", "po 0F BB /r", Instruction::CPU_X64},
{"BTC", "WORD r/m16,imm8", "po 0F BA /7 ib", Instruction::CPU_386},
{"BTC", "DWORD r/m32,imm8", "po 0F BA /7 ib", Instruction::CPU_386},
{"BTC", "QWORD r/m64,imm8", "po 0F BA /7 ib", Instruction::CPU_X64},
{"BTR", "r/m16,reg16", "po 0F B3 /r", Instruction::CPU_386},
{"BTR", "r/m32,reg32", "po 0F B3 /r", Instruction::CPU_386},
{"BTR", "r/m64,reg64", "po 0F B3 /r", Instruction::CPU_X64},
{"BTR", "WORD r/m16,imm8", "po 0F BA /6 ib", Instruction::CPU_386},
{"BTR", "DWORD r/m32,imm8", "po 0F BA /6 ib", Instruction::CPU_386},
{"BTR", "QWORD r/m64,imm8", "po 0F BA /6 ib", Instruction::CPU_X64},
{"BTS", "r/m16,reg16", "po 0F AB /r", Instruction::CPU_386},
{"BTS", "r/m32,reg32", "po 0F AB /r", Instruction::CPU_386},
{"BTS", "r/m64,reg64", "po 0F AB /r", Instruction::CPU_X64},
{"BTS", "WORD r/m16,imm8", "po 0F BA /5 ib", Instruction::CPU_386},
{"BTS", "DWORD r/m32,imm8", "po 0F BA /5 ib", Instruction::CPU_386},
{"BTS", "QWORD r/m64,imm8", "po 0F BA /5 ib", Instruction::CPU_X64},
{"CALL", "imm", "E8 -i", Instruction::CPU_8086},
// {"CALL", "imm:imm16", "po 9A iw iw", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
// {"CALL", "imm:imm32", "po 9A id iw", Instruction::CPU_386 | Instruction::CPU_INVALID64},
// {"CALL", "FAR mem16", "po FF /3", Instruction::CPU_8086},
// {"CALL", "FAR mem32", "po FF /3", Instruction::CPU_386},
{"CALL", "WORD r/m16", "po FF /2", Instruction::CPU_8086},
{"CALL", "DWORD r/m32", "po FF /2", Instruction::CPU_386},
{"CALL", "QWORD r/m64", "po FF /2", Instruction::CPU_X64},
{"CBW", "", "po 98", Instruction::CPU_8086},
{"CDQ", "", "po 99", Instruction::CPU_386},
{"CDQE", "", "po 98", Instruction::CPU_X64},
{"CLC", "", "F8", Instruction::CPU_8086},
{"CLD", "", "FC", Instruction::CPU_8086},
{"CLFLUSH", "mem", "0F AE /7", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CLI", "", "FA", Instruction::CPU_8086},
// {"CLTS", "", "0F 06", Instruction::CPU_286 | Instruction::CPU_PRIV},
{"CMC", "", "F5", Instruction::CPU_8086},
{"CMOVA", "reg16,r/m16", "po 0F 47 /r", Instruction::CPU_P6},
{"CMOVA", "reg32,r/m32", "po 0F 47 /r", Instruction::CPU_P6},
{"CMOVA", "reg64,r/m64", "po 0F 47 /r", Instruction::CPU_X64},
{"CMOVAE", "reg16,r/m16", "po 0F 43 /r", Instruction::CPU_P6},
{"CMOVAE", "reg32,r/m32", "po 0F 43 /r", Instruction::CPU_P6},
{"CMOVAE", "reg64,r/m64", "po 0F 43 /r", Instruction::CPU_X64},
{"CMOVB", "reg16,r/m16", "po 0F 42 /r", Instruction::CPU_P6},
{"CMOVB", "reg32,r/m32", "po 0F 42 /r", Instruction::CPU_P6},
{"CMOVB", "reg64,r/m64", "po 0F 42 /r", Instruction::CPU_X64},
{"CMOVBE", "reg16,r/m16", "po 0F 46 /r", Instruction::CPU_P6},
{"CMOVBE", "reg32,r/m32", "po 0F 46 /r", Instruction::CPU_P6},
{"CMOVBE", "reg64,r/m64", "po 0F 46 /r", Instruction::CPU_X64},
{"CMOVC", "reg16,r/m16", "po 0F 42 /r", Instruction::CPU_P6},
{"CMOVC", "reg32,r/m32", "po 0F 42 /r", Instruction::CPU_P6},
{"CMOVC", "reg64,r/m64", "po 0F 42 /r", Instruction::CPU_X64},
{"CMOVE", "reg16,r/m16", "po 0F 44 /r", Instruction::CPU_P6},
{"CMOVE", "reg32,r/m32", "po 0F 44 /r", Instruction::CPU_P6},
{"CMOVE", "reg64,r/m64", "po 0F 44 /r", Instruction::CPU_X64},
{"CMOVG", "reg16,r/m16", "po 0F 4F /r", Instruction::CPU_P6},
{"CMOVG", "reg32,r/m32", "po 0F 4F /r", Instruction::CPU_P6},
{"CMOVG", "reg64,r/m64", "po 0F 4F /r", Instruction::CPU_X64},
{"CMOVGE", "reg16,r/m16", "po 0F 4D /r", Instruction::CPU_P6},
{"CMOVGE", "reg32,r/m32", "po 0F 4D /r", Instruction::CPU_P6},
{"CMOVGE", "reg64,r/m64", "po 0F 4D /r", Instruction::CPU_X64},
{"CMOVL", "reg16,r/m16", "po 0F 4C /r", Instruction::CPU_P6},
{"CMOVL", "reg32,r/m32", "po 0F 4C /r", Instruction::CPU_P6},
{"CMOVL", "reg64,r/m64", "po 0F 4C /r", Instruction::CPU_X64},
{"CMOVLE", "reg16,r/m16", "po 0F 4E /r", Instruction::CPU_P6},
{"CMOVLE", "reg32,r/m32", "po 0F 4E /r", Instruction::CPU_P6},
{"CMOVLE", "reg64,r/m64", "po 0F 4E /r", Instruction::CPU_X64},
{"CMOVNA", "reg16,r/m16", "po 0F 46 /r", Instruction::CPU_P6},
{"CMOVNA", "reg32,r/m32", "po 0F 46 /r", Instruction::CPU_P6},
{"CMOVNA", "reg64,r/m64", "po 0F 46 /r", Instruction::CPU_X64},
{"CMOVNB", "reg16,r/m16", "po 0F 43 /r", Instruction::CPU_P6},
{"CMOVNB", "reg32,r/m32", "po 0F 43 /r", Instruction::CPU_P6},
{"CMOVNB", "reg64,r/m64", "po 0F 43 /r", Instruction::CPU_X64},
{"CMOVNBE", "reg16,r/m16", "po 0F 47 /r", Instruction::CPU_P6},
{"CMOVNBE", "reg32,r/m32", "po 0F 47 /r", Instruction::CPU_P6},
{"CMOVNBE", "reg64,r/m64", "po 0F 47 /r", Instruction::CPU_X64},
{"CMOVNC", "reg16,r/m16", "po 0F 43 /r", Instruction::CPU_P6},
{"CMOVNC", "reg32,r/m32", "po 0F 43 /r", Instruction::CPU_P6},
{"CMOVNC", "reg64,r/m64", "po 0F 43 /r", Instruction::CPU_X64},
{"CMOVNE", "reg16,r/m16", "po 0F 45 /r", Instruction::CPU_P6},
{"CMOVNE", "reg32,r/m32", "po 0F 45 /r", Instruction::CPU_P6},
{"CMOVNE", "reg64,r/m64", "po 0F 45 /r", Instruction::CPU_X64},
{"CMOVNEA", "reg16,r/m16", "po 0F 42 /r", Instruction::CPU_P6},
{"CMOVNEA", "reg32,r/m32", "po 0F 42 /r", Instruction::CPU_P6},
{"CMOVNEA", "reg64,r/m64", "po 0F 42 /r", Instruction::CPU_X64},
{"CMOVNG", "reg16,r/m16", "po 0F 4E /r", Instruction::CPU_P6},
{"CMOVNG", "reg32,r/m32", "po 0F 4E /r", Instruction::CPU_P6},
{"CMOVNG", "reg64,r/m64", "po 0F 4E /r", Instruction::CPU_X64},
{"CMOVNGE", "reg16,r/m16", "po 0F 4C /r", Instruction::CPU_P6},
{"CMOVNGE", "reg32,r/m32", "po 0F 4C /r", Instruction::CPU_P6},
{"CMOVNGE", "reg64,r/m64", "po 0F 4C /r", Instruction::CPU_X64},
{"CMOVNL", "reg16,r/m16", "po 0F 4D /r", Instruction::CPU_P6},
{"CMOVNL", "reg32,r/m32", "po 0F 4D /r", Instruction::CPU_P6},
{"CMOVNL", "reg64,r/m64", "po 0F 4D /r", Instruction::CPU_X64},
{"CMOVNLE", "reg16,r/m16", "po 0F 4F /r", Instruction::CPU_P6},
{"CMOVNLE", "reg32,r/m32", "po 0F 4F /r", Instruction::CPU_P6},
{"CMOVNLE", "reg64,r/m64", "po 0F 4F /r", Instruction::CPU_X64},
{"CMOVNO", "reg16,r/m16", "po 0F 41 /r", Instruction::CPU_P6},
{"CMOVNO", "reg32,r/m32", "po 0F 41 /r", Instruction::CPU_P6},
{"CMOVNO", "reg64,r/m64", "po 0F 41 /r", Instruction::CPU_X64},
{"CMOVNP", "reg16,r/m16", "po 0F 4B /r", Instruction::CPU_P6},
{"CMOVNP", "reg32,r/m32", "po 0F 4B /r", Instruction::CPU_P6},
{"CMOVNP", "reg64,r/m64", "po 0F 4B /r", Instruction::CPU_X64},
{"CMOVNS", "reg16,r/m16", "po 0F 49 /r", Instruction::CPU_P6},
{"CMOVNS", "reg32,r/m32", "po 0F 49 /r", Instruction::CPU_P6},
{"CMOVNS", "reg64,r/m64", "po 0F 49 /r", Instruction::CPU_X64},
{"CMOVNZ", "reg16,r/m16", "po 0F 45 /r", Instruction::CPU_P6},
{"CMOVNZ", "reg32,r/m32", "po 0F 45 /r", Instruction::CPU_P6},
{"CMOVNZ", "reg64,r/m64", "po 0F 45 /r", Instruction::CPU_X64},
{"CMOVO", "reg16,r/m16", "po 0F 40 /r", Instruction::CPU_P6},
{"CMOVO", "reg32,r/m32", "po 0F 40 /r", Instruction::CPU_P6},
{"CMOVO", "reg64,r/m64", "po 0F 40 /r", Instruction::CPU_X64},
{"CMOVP", "reg16,r/m16", "po 0F 4A /r", Instruction::CPU_P6},
{"CMOVP", "reg32,r/m32", "po 0F 4A /r", Instruction::CPU_P6},
{"CMOVP", "reg64,r/m64", "po 0F 4A /r", Instruction::CPU_X64},
{"CMOVPE", "reg16,r/m16", "po 0F 4A /r", Instruction::CPU_P6},
{"CMOVPE", "reg32,r/m32", "po 0F 4A /r", Instruction::CPU_P6},
{"CMOVPE", "reg64,r/m64", "po 0F 4A /r", Instruction::CPU_X64},
{"CMOVPO", "reg16,r/m16", "po 0F 4B /r", Instruction::CPU_P6},
{"CMOVPO", "reg32,r/m32", "po 0F 4B /r", Instruction::CPU_P6},
{"CMOVPO", "reg64,r/m64", "po 0F 4B /r", Instruction::CPU_X64},
{"CMOVS", "reg16,r/m16", "po 0F 48 /r", Instruction::CPU_P6},
{"CMOVS", "reg32,r/m32", "po 0F 48 /r", Instruction::CPU_P6},
{"CMOVS", "reg32,r/m64", "po 0F 48 /r", Instruction::CPU_X64},
{"CMOVZ", "reg16,r/m16", "po 0F 44 /r", Instruction::CPU_P6},
{"CMOVZ", "reg32,r/m32", "po 0F 44 /r", Instruction::CPU_P6},
{"CMOVZ", "reg64,r/m64", "po 0F 44 /r", Instruction::CPU_X64},
{"CMP", "r/m8,reg8", "38 /r", Instruction::CPU_8086},
{"CMP", "r/m16,reg16", "po 39 /r", Instruction::CPU_8086},
{"CMP", "r/m32,reg32", "po 39 /r", Instruction::CPU_386},
{"CMP", "r/m64,reg64", "po 39 /r", Instruction::CPU_X64},
{"CMP", "reg8,r/m8", "3A /r", Instruction::CPU_8086},
{"CMP", "reg16,r/m16", "po 3B /r", Instruction::CPU_8086},
{"CMP", "reg32,r/m32", "po 3B /r", Instruction::CPU_386},
{"CMP", "reg64,r/m64", "po 3B /r", Instruction::CPU_X64},
{"CMP", "BYTE r/m8,imm8", "80 /7 ib", Instruction::CPU_8086},
{"CMP", "WORD r/m16,imm16", "po 81 /7 iw", Instruction::CPU_8086},
{"CMP", "DWORD r/m32,imm32", "po 81 /7 id", Instruction::CPU_386},
{"CMP", "QWORD r/m64,imm32", "po 81 /7 id", Instruction::CPU_X64},
{"CMP", "WORD r/m16,imm8", "po 83 /7 ib", Instruction::CPU_8086},
{"CMP", "DWORD r/m32,imm8", "po 83 /7 ib", Instruction::CPU_386},
{"CMP", "QWORD r/m64,imm8", "po 83 /7 ib", Instruction::CPU_X64},
{"CMP", "AL,imm8", "3C ib", Instruction::CPU_8086},
{"CMP", "AX,imm16", "po 3D iw", Instruction::CPU_8086},
{"CMP", "EAX,imm32", "po 3D id", Instruction::CPU_386},
{"CMP", "RAX,imm32", "po 3D id", Instruction::CPU_X64},
{"CMPEQPD", "xmmreg,r/m128", "66 0F C2 /r 00", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPEQPS", "xmmreg,r/m128", "0F C2 /r 00", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPEQSD", "xmmreg,xmm64", "p2 0F C2 /r 00", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPEQSS", "xmmreg,xmm32", "p3 0F C2 /r 00", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPLEPD", "xmmreg,r/m128", "66 0F C2 /r 02", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPLEPS", "xmmreg,r/m128", "0F C2 /r 02", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPLESD", "xmmreg,xmm64", "p2 0F C2 /r 02", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPLESS", "xmmreg,xmm32", "p3 0F C2 /r 02", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPLTPD", "xmmreg,r/m128", "66 0F C2 /r 01", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPLTPS", "xmmreg,r/m128", "0F C2 /r 01", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPLTSD", "xmmreg,xmm64", "p2 0F C2 /r 01", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPLTSS", "xmmreg,xmm32", "p3 0F C2 /r 01", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPNEQPD", "xmmreg,r/m128", "66 0F C2 /r 04", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPNEQPS", "xmmreg,r/m128", "0F C2 /r 04", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPNEQSD", "xmmreg,xmm64", "p2 0F C2 /r 04", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPNEQSS", "xmmreg,xmm32", "p3 0F C2 /r 04", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPNLEPD", "xmmreg,r/m128", "66 0F C2 /r 06", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPNLEPS", "xmmreg,r/m128", "0F C2 /r 06", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPNLESD", "xmmreg,xmm64", "p2 0F C2 /r 06", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPNLESS", "xmmreg,xmm32", "p3 0F C2 /r 06", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPNLTPD", "xmmreg,r/m128", "66 0F C2 /r 05", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPNLTPS", "xmmreg,r/m128", "0F C2 /r 05", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPNLTSD", "xmmreg,xmm64", "p2 0F C2 /r 05", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPNLTSS", "xmmreg,xmm32", "p3 0F C2 /r 05", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPORDPD", "xmmreg,r/m128", "66 0F C2 /r 07", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPORDPS", "xmmreg,r/m128", "0F C2 /r 07", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPORDSD", "xmmreg,xmm64", "p2 0F C2 /r 07", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPORDSS", "xmmreg,xmm32", "p3 0F C2 /r 07", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPPD", "xmmreg,r/m128,imm8", "66 0F C2 /r ib", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPPS", "xmmreg,r/m128,imm8", "0F C2 /r ib", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPSB", "", "A6", Instruction::CPU_8086},
{"CMPSD", "", "po A7", Instruction::CPU_386},
{"CMPSD", "xmmreg,xmm64,imm8", "p2 0F C2 /r ib", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPSQ", "", "po A7", Instruction::CPU_X64},
{"CMPSS", "xmmreg,xmm32,imm8", "p3 0F C2 /r ib", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPSW", "", "po A7", Instruction::CPU_8086},
{"CMPUNORDPD", "xmmreg,r/m128", "66 0F C2 /r 03", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPUNORDPS", "xmmreg,r/m128", "0F C2 /r 03", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPUNORDSD", "xmmreg,xmm64", "p2 0F C2 /r 03", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CMPUNORDSS", "xmmreg,xmm32", "p3 0F C2 /r 03", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CMPXCHG", "r/m8,reg8", "0F B0 /r", Instruction::CPU_PENTIUM},
{"CMPXCHG", "r/m16,reg16", "po 0F B1 /r", Instruction::CPU_PENTIUM},
{"CMPXCHG", "r/m32,reg32", "po 0F B1 /r", Instruction::CPU_PENTIUM},
{"CMPXCHG", "r/m64,reg64", "po 0F B1 /r", Instruction::CPU_X64},
// {"CMPXCHG486", "r/m8,reg8", "0F A6 /r", Instruction::CPU_486 | Instruction::CPU_UNDOC},
// {"CMPXCHG486", "r/m16,reg16", "po 0F A7 /r", Instruction::CPU_486 | Instruction::CPU_UNDOC},
// {"CMPXCHG486", "r/m32,reg32", "po 0F A7 /r", Instruction::CPU_486 | Instruction::CPU_UNDOC},
{"CMPXCHG16B", "mem", "0F C7 /1", Instruction::CPU_X64},
{"CMPXCHG8B", "mem", "0F C7 /1", Instruction::CPU_PENTIUM},
{"COMISD", "xmmreg,xmm64", "66 0F 2F /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"COMISS", "xmmreg,xmm32", "0F 2F /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CPUID", "", "0F A2", Instruction::CPU_PENTIUM},
{"CQO", "", "po 99", Instruction::CPU_X64},
{"CVTDQ2PD", "xmmreg,xmm64", "p3 0F E6 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTDQ2PS", "xmmreg,r/m128", "0F 5B /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTPD2DQ", "xmmreg,r/m128", "p2 0F E6 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTPD2PI", "mmreg,r/m128", "66 0F 2D /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTPD2PS", "xmmreg,r/m128", "66 0F 5A /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTPI2PD", "xmmreg,mm64", "66 0F 2A /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTPI2PS", "xmmreg,mm64", "0F 2A /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CVTPS2DQ", "xmmreg,r/m128", "66 0F 5B /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTPS2PD", "xmmreg,xmm64", "0F 5A /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTPS2PI", "mmreg,xmm64", "0F 2D /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CVTSD2SI", "reg32,xmm64", "p2 0F 2D /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTSI2SD", "xmmreg,r/m32", "p2 0F 2A /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTSI2SS", "xmmreg,r/m32", "p3 0F 2A /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CVTSS2SD", "xmmreg,xmm32", "p3 0F 5A /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTSS2SI", "reg32,xmm32", "p3 0F 2D /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CVTTPD2DQ", "xmmreg,r/m128", "66 0F E6 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTTPD2PI", "mmreg,r/m128", "66 0F 2C /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTTPS2DQ", "xmmreg,r/m128", "p3 0F 5B /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTTPS2PI", "mmreg,xmm64", "0F 2C /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CVTTSD2SI", "reg32,xmm64", "p2 0F 2C /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"CVTTSS2SI", "reg32,xmm32", "p3 0F 2C /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"CWD", "", "po 99", Instruction::CPU_8086},
{"CWDE", "", "po 98", Instruction::CPU_386},
{"DAA", "", "27", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
{"DAS", "", "2F", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
{"DB", "", "p1 ib"}, // Special 'instruction', indicated by the 'p1' prefix
{"DB", "imm8", "p1 ib"}, // Special 'instruction', indicated by the 'p1' prefix
{"DB", "mem", "p1 01"}, // Special 'instruction', indicated by the 'p1' prefix
{"DD", "", "p1 id"}, // Special 'instruction', indicated by the 'p1' prefix
{"DD", "imm32", "p1 id"}, // Special 'instruction', indicated by the 'p1' prefix
{"DD", "mem", "p1 04"}, // Special 'instruction', indicated by the 'p1' prefix
// {"DEC", "reg16", "po 48 +r", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
// {"DEC", "reg32", "po 48 +r", Instruction::CPU_386 | Instruction::CPU_INVALID64},
{"DEC", "BYTE r/m8", "FE /1", Instruction::CPU_8086},
{"DEC", "WORD r/m16", "po FF /1", Instruction::CPU_8086},
{"DEC", "DWORD r/m32", "po FF /1", Instruction::CPU_386},
{"DEC", "QWORD r/m64", "po FF /1", Instruction::CPU_X64},
{"DIV", "BYTE r/m8", "F6 /6", Instruction::CPU_8086},
{"DIV", "WORD r/m16", "po F7 /6", Instruction::CPU_8086},
{"DIV", "DWORD r/m32", "po F7 /6", Instruction::CPU_386},
{"DIV", "QWORD r/m64", "po F7 /6", Instruction::CPU_X64},
{"DIVPD", "xmmreg,r/m128", "66 0F 5E /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"DIVPS", "xmmreg,r/m128", "0F 5E /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"DIVSD", "xmmreg,xmm64", "p2 0F 5E /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"DIVSS", "xmmreg,xmm32", "p3 0F 5E /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"DW", "", "p1 iw"}, // Special 'instruction', indicated by the 'p1' prefix
{"DW", "imm16", "p1 iw"}, // Special 'instruction', indicated by the 'p1' prefix
{"DW", "mem", "p1 02"}, // Special 'instruction', indicated by the 'p1' prefix
{"EMMS", "", "0F 77", Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
// {"ENTER", "imm,imm", "C8 iw ib", Instruction::CPU_186},
{"F2XM1", "", "D9 F0", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FABS", "", "D9 E1", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FADD", "DWORD mem32", "D8 /0", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FADD", "QWORD mem64", "DC /0", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FADD", "fpureg", "D8 C0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FADD", "ST0,fpureg", "D8 C0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
// {"FADD", "TO fpureg", "DC C0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FADD", "fpureg,ST0", "DC C0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FADDP", "", "DE C1", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FADDP", "fpureg", "DE C0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FADDP", "fpureg,ST0", "DE C0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
// {"FBLD", "mem80", "DF /4", Instruction::CPU_8086 | Instruction::CPU_FPU},
// {"FBSTP", "mem80", "DF /6", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FCHS", "", "D9 E0", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FCLEX", "", "9B DB E2", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FCMOVB", "fpureg", "DA C0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVB", "ST0,fpureg", "DA C0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVBE", "fpureg", "DA D0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVBE", "ST0,fpureg", "DA D0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVE", "fpureg", "DA C8 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVE", "ST0,fpureg", "DA C8 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVNB", "fpureg", "DB C0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVNB", "ST0,fpureg", "DB C0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVNBE", "fpureg", "DB D0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVNBE", "ST0,fpureg", "DB D0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVNE", "fpureg", "DB C8 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVNE", "ST0,fpureg", "DB C8 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVNU", "fpureg", "DB D8 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVNU", "ST0,fpureg", "DB D8 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVU", "fpureg", "DA D8 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCMOVU", "ST0,fpureg", "DA D8 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCOM", "DWORD mem32", "D8 /2", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FCOM", "QWORD mem64", "DC /2", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FCOM", "fpureg", "D8 D0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FCOM", "ST0,fpureg", "D8 D0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FCOMI", "fpureg", "DB F0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCOMI", "ST0,fpureg", "DB F0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCOMIP", "fpureg", "DF F0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCOMIP", "ST0,fpureg", "DF F0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FCOMP", "DWORD mem32", "D8 /3", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FCOMP", "QWORD mem64", "DC /3", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FCOMP", "fpureg", "D8 D8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FCOMP", "ST0,fpureg", "D8 D8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FCOMPP", "", "DE D9", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FCOS", "", "D9 FF", Instruction::CPU_386 | Instruction::CPU_FPU},
{"FDECSTP", "", "D9 F6", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDISI", "", "9B DB E1", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIV", "DWORD mem32", "D8 /6", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIV", "QWORD mem64", "DC /6", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIV", "fpureg", "D8 F0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIV", "ST0,fpureg", "D8 F0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
// {"FDIV", "TO fpureg", "DC F8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIV", "fpureg,ST0", "DC F8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIVP", "", "DE F9", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIVP", "fpureg", "DE F8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIVP", "fpureg,ST0", "DE F8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIVR", "DWORD mem32", "D8 /7", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIVR", "QWORD mem64", "DC /7", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIVR", "fpureg", "D8 F8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIVR", "ST0,fpureg", "D8 F8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
// {"FDIVR", "TO fpureg", "DC F0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIVR", "fpureg,ST0", "DC F0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIVRP", "", "DE F1", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIVRP", "fpureg", "DE F0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FDIVRP", "fpureg,ST0", "DE F0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FEMMS", "", "0F 0E", Instruction::CPU_3DNOW},
{"FENI", "", "9B DB E0", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FFREE", "fpureg", "DD C0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
// {"FFREEP", "fpureg", "DF C0 +r", Instruction::CPU_P6 | Instruction::CPU_FPU | Instruction::CPU_UNDOC},
{"FIADD", "WORD mem16", "DE /0", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FIADD", "DWORD mem32", "DA /0", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FICOM", "WORD mem16", "DE /2", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FICOM", "DWORD mem32", "DA /2", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FICOMP", "WORD mem16", "DE /3", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FICOMP", "DWORD mem32", "DA /3", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FIDIV", "WORD mem16", "DE /6", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FIDIV", "DWORD mem32", "DA /6", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FIDIVR", "WORD mem16", "DE /7", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FIDIVR", "DWORD mem32", "DA /7", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FILD", "WORD mem16", "DF /0", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FILD", "DWORD mem32", "DB /0", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FILD", "QWORD mem64", "DF /5", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FIMUL", "WORD mem16", "DE /1", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FIMUL", "DWORD mem32", "DA /1", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FINCSTP", "", "D9 F7", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FINIT", "", "9B DB E3", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FIST", "WORD mem16", "DF /2", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FIST", "DWORD mem32", "DB /2", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FISTP", "WORD mem16", "DF /3", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FISTP", "DWORD mem32", "DB /3", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FISTP", "QWORD mem64", "DF /7", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FISTTP", "WORD mem16", "DF /1", Instruction::CPU_PNI},
{"FISTTP", "DWORD mem32", "DB /1", Instruction::CPU_PNI},
{"FISTTP", "QWORD mem64", "DD /1", Instruction::CPU_PNI},
{"FISUB", "WORD mem16", "DE /4", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FISUB", "DWORD mem32", "DA /4", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FISUBR", "WORD mem16", "DE /5", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FISUBR", "DWORD mem32", "DA /5", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FLD", "DWORD mem32", "D9 /0", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FLD", "QWORD mem64", "DD /0", Instruction::CPU_8086 | Instruction::CPU_FPU},
// {"FLD", "mem80", "DB /5", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FLD", "fpureg", "D9 C0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FLD1", "", "D9 E8", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FLDCW", "mem16", "D9 /5", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FLDENV", "mem", "D9 /4", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FLDL2E", "", "D9 EA", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FLDL2T", "", "D9 E9", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FLDLG2", "", "D9 EC", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FLDLN2", "", "D9 ED", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FLDPI", "", "D9 EB", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FLDZ", "", "D9 EE", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FMUL", "DWORD mem32", "D8 /1", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FMUL", "QWORD mem64", "DC /1", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FMUL", "", "D8 C9", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FMUL", "fpureg", "D8 C8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FMUL", "ST0,fpureg", "D8 C8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
// {"FMUL", "TO fpureg", "DC C8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FMUL", "fpureg,ST0", "DC C8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FMULP", "fpureg", "DE C8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FMULP", "fpureg,ST0", "DE C8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FMULP", "", "DE C9", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FNCLEX", "", "DB E2", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FNDISI", "", "DB E1", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FNENI", "", "DB E0", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FNINIT", "", "DB E3", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FNOP", "", "D9 D0", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FNSAVE", "mem", "DD /6", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FNSTCW", "mem16", "D9 /7", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FNSTENV", "mem", "D9 /6", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FNSTSW", "mem16", "DD /7", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FNSTSW", "AX", "DF E0", Instruction::CPU_286 | Instruction::CPU_FPU},
{"FPATAN", "", "D9 F3", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FPREM", "", "D9 F8", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FPREM1", "", "D9 F5", Instruction::CPU_386 | Instruction::CPU_FPU},
{"FPTAN", "", "D9 F2", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FRNDINT", "", "D9 FC", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FRSTOR", "mem", "DD /4", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSAVE", "mem", "9B DD /6", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSCALE", "", "D9 FD", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSETPM", "", "DB E4", Instruction::CPU_286 | Instruction::CPU_FPU},
{"FSIN", "", "D9 FE", Instruction::CPU_386 | Instruction::CPU_FPU},
{"FSINCOS", "", "D9 FB", Instruction::CPU_386 | Instruction::CPU_FPU},
{"FSQRT", "", "D9 FA", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FST", "DWORD mem32", "D9 /2", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FST", "QWORD mem64", "DD /2", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FST", "fpureg", "DD D0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSTCW", "mem16", "9B D9 /7", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSTENV", "mem", "9B D9 /6", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSTP", "DWORD mem32", "D9 /3", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSTP", "QWORD mem64", "DD /3", Instruction::CPU_8086 | Instruction::CPU_FPU},
// {"FSTP", "mem80", "DB /7", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSTP", "fpureg", "DD D8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSTSW", "mem16", "9B DD /7", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSTSW", "AX", "9B DF E0", Instruction::CPU_286 | Instruction::CPU_FPU},
{"FSUB", "DWORD mem32", "D8 /4", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUB", "QWORD mem64", "DC /4", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUB", "fpureg", "D8 E0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUB", "ST0,fpureg", "D8 E0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
// {"FSUB", "TO fpureg", "DC E8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUB", "fpureg,ST0", "DC E8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUBP", "", "DE E9", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUBP", "fpureg", "DE E8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUBP", "fpureg,ST0", "DE E8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUBR", "DWORD mem32", "D8 /5", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUBR", "QWORD mem64", "DC /5", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUBR", "fpureg", "D8 E8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUBR", "ST0,fpureg", "D8 E8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
// {"FSUBR", "TO fpureg", "DC E0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUBR", "fpureg,ST0", "DC E0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUBRP", "", "DE E1", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUBRP", "fpureg", "DE E0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FSUBRP", "fpureg,ST0", "DE E0 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FTST", "", "D9 E4", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FUCOM", "fpureg", "DD E0 +r", Instruction::CPU_386 | Instruction::CPU_FPU},
{"FUCOM", "ST0,fpureg", "DD E0 +r", Instruction::CPU_386 | Instruction::CPU_FPU},
{"FUCOMI", "fpureg", "DB E8 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FUCOMI", "ST0,fpureg", "DB E8 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FUCOMIP", "fpureg", "DF E8 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FUCOMIP", "ST0,fpureg", "DF E8 +r", Instruction::CPU_P6 | Instruction::CPU_FPU},
{"FUCOMP", "fpureg", "DD E8 +r", Instruction::CPU_386 | Instruction::CPU_FPU},
{"FUCOMP", "ST0,fpureg", "DD E8 +r", Instruction::CPU_386 | Instruction::CPU_FPU},
{"FUCOMPP", "", "DA E9", Instruction::CPU_386 | Instruction::CPU_FPU},
{"FWAIT", "", "9B", Instruction::CPU_8086},
{"FXAM", "", "D9 E5", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FXCH", "", "D9 C9", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FXCH", "fpureg", "D9 C8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FXCH", "fpureg,ST0", "D9 C8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FXCH", "ST0,fpureg", "D9 C8 +r", Instruction::CPU_8086 | Instruction::CPU_FPU},
// {"FXRSTOR", "mem", "0F AE /1", Instruction::CPU_P6 | Instruction::CPU_SSE | Instruction::CPU_FPU},
// {"FXSAVE", "mem", "0F AE /0", Instruction::CPU_P6 | Instruction::CPU_SSE | Instruction::CPU_FPU},
{"FXTRACT", "", "D9 F4", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FYL2X", "", "D9 F1", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"FYL2XP1", "", "D9 F9", Instruction::CPU_8086 | Instruction::CPU_FPU},
{"HADDPD", "xmmreg,r/m128", "66 0F 7C /r", Instruction::CPU_PNI},
{"HADDPS", "xmmreg,r/m128", "p2 0F 7C /r", Instruction::CPU_PNI},
{"HLT", "", "F4", Instruction::CPU_8086},
{"HSUBPD", "xmmreg,r/m128", "66 0F 7D /r", Instruction::CPU_PNI},
{"HSUBPS", "xmmreg,r/m128", "p2 0F 7D /r", Instruction::CPU_PNI},
// {"IBTS", "r/m16,reg16", "po 0F A7 /r", Instruction::CPU_386 | Instruction::CPU_UNDOC},
// {"IBTS", "r/m32,reg32", "po 0F A7 /r", Instruction::CPU_386 | Instruction::CPU_UNDOC},
{"IDIV", "BYTE r/m8", "F6 /7", Instruction::CPU_8086},
{"IDIV", "WORD r/m16", "po F7 /7", Instruction::CPU_8086},
{"IDIV", "DWORD r/m32", "po F7 /7", Instruction::CPU_386},
{"IDIV", "QWORD r/m64", "po F7 /7", Instruction::CPU_X64},
{"IMUL", "BYTE r/m8", "F6 /5", Instruction::CPU_8086},
{"IMUL", "WORD r/m16", "po F7 /5", Instruction::CPU_8086},
{"IMUL", "DWORD r/m32", "po F7 /5", Instruction::CPU_386},
{"IMUL", "QWORD r/m64", "po F7 /5", Instruction::CPU_X64},
{"IMUL", "reg16,r/m16", "po 0F AF /r", Instruction::CPU_386},
{"IMUL", "reg32,r/m32", "po 0F AF /r", Instruction::CPU_386},
{"IMUL", "reg64,r/m64", "po 0F AF /r", Instruction::CPU_X64},
{"IMUL", "reg16,imm8", "po 6B /r ib", Instruction::CPU_286},
{"IMUL", "reg32,imm8", "po 6B /r ib", Instruction::CPU_386},
{"IMUL", "reg64,imm8", "po 6B /r ib", Instruction::CPU_X64},
{"IMUL", "reg16,imm16", "po 69 /r iw", Instruction::CPU_286},
{"IMUL", "reg32,imm32", "po 69 /r id", Instruction::CPU_386},
{"IMUL", "reg64,imm32", "po 69 /r id", Instruction::CPU_X64},
{"IMUL", "reg16,r/m16,imm8", "po 6B /r ib", Instruction::CPU_286},
{"IMUL", "reg32,r/m32,imm8", "po 6B /r ib", Instruction::CPU_386},
{"IMUL", "reg64,r/m64,imm8", "po 6B /r ib", Instruction::CPU_X64},
{"IMUL", "reg16,r/m16,imm16", "po 69 /r iw", Instruction::CPU_286},
{"IMUL", "reg32,r/m32,imm32", "po 69 /r id", Instruction::CPU_386},
{"IMUL", "reg64,r/m64,imm32", "po 69 /r id", Instruction::CPU_X64},
{"IN", "AL,imm8", "E4 ib", Instruction::CPU_8086},
{"IN", "AX,imm8", "po E5 ib", Instruction::CPU_8086},
{"IN", "EAX,imm8", "po E5 ib", Instruction::CPU_386},
{"IN", "AL,DX", "EC", Instruction::CPU_8086},
{"IN", "AX,DX", "po ED", Instruction::CPU_8086},
{"IN", "EAX,DX", "po ED", Instruction::CPU_386},
// {"INC", "reg16", "po 40 +r", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
// {"INC", "reg32", "po 40 +r", Instruction::CPU_386 | Instruction::CPU_INVALID64},
{"INC", "BYTE r/m8", "FE /0", Instruction::CPU_8086},
{"INC", "WORD r/m16", "po FF /0", Instruction::CPU_8086},
{"INC", "DWORD r/m32", "po FF /0", Instruction::CPU_386},
{"INC", "QWORD r/m64", "po FF /0", Instruction::CPU_X64},
{"INSB", "", "6C", Instruction::CPU_186},
{"INSD", "", "po 6D", Instruction::CPU_386},
{"INSW", "", "po 6D", Instruction::CPU_186},
// {"INT", "imm8", "CD ib", Instruction::CPU_8086},
// {"INT1", "", "F1", Instruction::CPU_P6 | Instruction::CPU_UNDOC},
// {"ICEBP", "", "F1", Instruction::CPU_P6 | Instruction::CPU_UNDOC},
// {"INT01", "", "F1", Instruction::CPU_P6 | Instruction::CPU_UNDOC},
{"INT03", "", "CC", Instruction::CPU_8086},
{"INT3", "", "CC", Instruction::CPU_8086},
{"INTO", "", "CE", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
// {"INVD", "", "0F 08", Instruction::CPU_486},
// {"INVLPG", "mem", "0F 01 /7", Instruction::CPU_486},
// {"IRET", "", "CF", Instruction::CPU_8086},
// {"IRETW", "", "po CF", Instruction::CPU_8086},
// {"IRETD", "", "po CF", Instruction::CPU_386},
{"JA", "NEAR imm8", "77 -b", Instruction::CPU_8086},
{"JA", "imm", "0F 87 -i", Instruction::CPU_386},
{"JAE", "NEAR imm8", "73 -b", Instruction::CPU_8086},
{"JAE", "imm", "0F 83 -i", Instruction::CPU_386},
{"JB", "NEAR imm8", "72 -b", Instruction::CPU_8086},
{"JB", "imm", "0F 82 -i", Instruction::CPU_386},
{"JBE", "NEAR imm8", "76 -b", Instruction::CPU_8086},
{"JBE", "imm", "0F 86 -i", Instruction::CPU_386},
{"JC", "NEAR imm8", "72 -b", Instruction::CPU_8086},
{"JC", "imm", "0F 82 -i", Instruction::CPU_386},
{"JCXZ", "NEAR imm8", "po E3 -b", Instruction::CPU_8086},
{"JE", "NEAR imm8", "74 -b", Instruction::CPU_8086},
{"JE", "imm", "0F 84 -i", Instruction::CPU_386},
{"JECXZ", "NEAR imm8", "po E3 -b", Instruction::CPU_386},
{"JG", "NEAR imm8", "7F -b", Instruction::CPU_8086},
{"JG", "imm", "0F 8F -i", Instruction::CPU_386},
{"JGE", "NEAR imm8", "7D -b", Instruction::CPU_8086},
{"JGE", "imm", "0F 8D -i", Instruction::CPU_386},
{"JL", "NEAR imm8", "7C -b", Instruction::CPU_8086},
{"JL", "imm", "0F 8C -i", Instruction::CPU_386},
{"JLE", "NEAR imm8", "7E -b", Instruction::CPU_8086},
{"JLE", "imm", "0F 8E -i", Instruction::CPU_386},
{"JMP", "imm", "E9 -i", Instruction::CPU_8086},
{"JMP", "NEAR imm8", "EB -b", Instruction::CPU_8086},
// {"JMP", "imm:imm16", "po EA iw iw", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
// {"JMP", "imm:imm32", "po EA id iw", Instruction::CPU_386 | Instruction::CPU_INVALID64},
{"JMP", "mem", "po FF /5", Instruction::CPU_8086},
// {"JMP", "FAR mem", "po FF /5", Instruction::CPU_386},
{"JMP", "WORD r/m16", "po FF /4", Instruction::CPU_8086},
{"JMP", "DWORD r/m32", "po FF /4", Instruction::CPU_386},
{"JMP", "QWORD r/m64", "po FF /4", Instruction::CPU_X64},
{"JNA", "NEAR imm8", "76 -b", Instruction::CPU_8086},
{"JNA", "imm", "0F 86 -i", Instruction::CPU_386},
{"JNAE", "NEAR imm8", "72 -b", Instruction::CPU_8086},
{"JNAE", "imm", "0F 82 -i", Instruction::CPU_386},
{"JNB", "NEAR imm8", "73 -b", Instruction::CPU_8086},
{"JNB", "imm", "0F 83 -i", Instruction::CPU_386},
{"JNBE", "NEAR imm8", "77 -b", Instruction::CPU_8086},
{"JNBE", "imm", "0F 87 -i", Instruction::CPU_386},
{"JNC", "NEAR imm8", "73 -b", Instruction::CPU_8086},
{"JNC", "imm", "0F 83 -i", Instruction::CPU_386},
{"JNE", "NEAR imm8", "75 -b", Instruction::CPU_8086},
{"JNE", "imm", "0F 85 -i", Instruction::CPU_386},
{"JNG", "NEAR imm8", "7E -b", Instruction::CPU_8086},
{"JNG", "imm", "0F 8E -i", Instruction::CPU_386},
{"JNGE", "NEAR imm8", "7C -b", Instruction::CPU_8086},
{"JNGE", "imm", "0F 8C -i", Instruction::CPU_386},
{"JNL", "NEAR imm8", "7D -b", Instruction::CPU_8086},
{"JNL", "imm", "0F 8D -i", Instruction::CPU_386},
{"JNLE", "NEAR imm8", "7F -b", Instruction::CPU_8086},
{"JNLE", "imm", "0F 8F -i", Instruction::CPU_386},
{"JNO", "NEAR imm8", "71 -b", Instruction::CPU_8086},
{"JNO", "imm", "0F 81 -i", Instruction::CPU_386},
{"JNP", "NEAR imm8", "7B -b", Instruction::CPU_8086},
{"JNP", "imm", "0F 8B -i", Instruction::CPU_386},
{"JNS", "NEAR imm8", "79 -b", Instruction::CPU_8086},
{"JNS", "imm", "0F 89 -i", Instruction::CPU_386},
{"JNZ", "NEAR imm8", "75 -b", Instruction::CPU_8086},
{"JNZ", "imm", "0F 85 -i", Instruction::CPU_386},
{"JO", "NEAR imm8", "70 -b", Instruction::CPU_8086},
{"JO", "imm", "0F 80 -i", Instruction::CPU_386},
{"JP", "NEAR imm8", "7A -b", Instruction::CPU_8086},
{"JP", "imm", "0F 8A -i", Instruction::CPU_386},
{"JPE", "NEAR imm8", "7A -b", Instruction::CPU_8086},
{"JPE", "imm", "0F 8A -i", Instruction::CPU_386},
{"JPO", "NEAR imm8", "7B -b", Instruction::CPU_8086},
{"JPO", "imm", "0F 8B -i", Instruction::CPU_386},
{"JRCXZ", "NEAR imm8", "po E3 -b", Instruction::CPU_X64},
{"JS", "NEAR imm8", "78 -b", Instruction::CPU_8086},
{"JS", "imm", "0F 88 -i", Instruction::CPU_386},
{"JZ", "NEAR imm8", "74 -b", Instruction::CPU_8086},
{"JZ", "imm", "0F 84 -i", Instruction::CPU_386},
{"LAHF", "", "9F", Instruction::CPU_8086},
// {"LAR", "reg16,r/m16", "po 0F 02 /r", Instruction::CPU_286 | Instruction::CPU_PRIV},
// {"LAR", "reg32,r/m32", "po 0F 02 /r", Instruction::CPU_286 | Instruction::CPU_PRIV},
{"LDDQU", "xmmreg,mem", "p2 0F F0 /r", Instruction::CPU_PNI},
{"LDMXCSR", "mem32", "0F AE /2", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"LDS", "reg16,mem", "po C5 /r", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
{"LDS", "reg32,mem", "po C5 /r", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
{"LEA", "reg16,mem", "po 8D /r", Instruction::CPU_8086},
{"LEA", "reg32,mem", "po 8D /r", Instruction::CPU_386},
{"LEA", "reg64,mem", "po 8D /r", Instruction::CPU_X64},
{"LEAVE", "", "C9", Instruction::CPU_186},
{"LES", "reg16,mem", "po C4 /r", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
{"LES", "reg32,mem", "po C4 /r", Instruction::CPU_8086 | Instruction::CPU_INVALID64},
{"LFENCE", "", "0F AE E8", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"LFS", "reg16,mem", "po 0F B4 /r", Instruction::CPU_386},
{"LFS", "reg32,mem", "po 0F B4 /r", Instruction::CPU_386},
{"LGS", "reg16,mem", "po 0F B5 /r", Instruction::CPU_386},
{"LGS", "reg32,mem", "po 0F B5 /r", Instruction::CPU_386},
// {"LGDT", "mem", "0F 01 /2", Instruction::CPU_286 | Instruction::CPU_PRIV},
// {"LIDT", "mem", "0F 01 /3", Instruction::CPU_286 | Instruction::CPU_PRIV},
// {"LLDT", "r/m16", "0F 00 /2", Instruction::CPU_286 | Instruction::CPU_PRIV},
// {"LMSW", "r/m16", "0F 01 /6", Instruction::CPU_286 | Instruction::CPU_PRIV},
// {"LOADALL", "", "0F 07", Instruction::CPU_386 | Instruction::CPU_UNDOC},
// {"LOADALL286", "", "0F 05", Instruction::CPU_286 | Instruction::CPU_UNDOC},
{"LOCK ADC", "mem8,reg8", "p0 10 /r", Instruction::CPU_8086},
{"LOCK ADC", "mem16,reg16", "p0 po 11 /r", Instruction::CPU_8086},
{"LOCK ADC", "mem32,reg32", "p0 po 11 /r", Instruction::CPU_386},
{"LOCK ADC", "BYTE mem8,imm8", "p0 80 /2 ib", Instruction::CPU_8086},
{"LOCK ADC", "WORD mem16,imm16", "p0 po 81 /2 iw", Instruction::CPU_8086},
{"LOCK ADC", "DWORD mem32,imm32", "p0 po 81 /2 id", Instruction::CPU_386},
{"LOCK ADC", "WORD mem16,imm8", "p0 po 83 /2 ib", Instruction::CPU_8086},
{"LOCK ADC", "DWORD mem32,imm8", "p0 po 83 /2 ib", Instruction::CPU_386},
{"LOCK ADD", "mem8,reg8", "p0 00 /r", Instruction::CPU_8086},
{"LOCK ADD", "mem16,reg16", "p0 po 01 /r", Instruction::CPU_8086},
{"LOCK ADD", "mem32,reg32", "p0 po 01 /r", Instruction::CPU_386},
{"LOCK ADD", "BYTE mem8,imm8", "p0 80 /0 ib", Instruction::CPU_8086},
{"LOCK ADD", "WORD mem16,imm16", "p0 po 81 /0 iw", Instruction::CPU_8086},
{"LOCK ADD", "DWORD mem32,imm32", "p0 po 81 /0 id", Instruction::CPU_386},
{"LOCK ADD", "WORD mem16,imm8", "p0 po 83 /0 ib", Instruction::CPU_8086},
{"LOCK ADD", "DWORD mem32,imm8", "p0 po 83 /0 ib", Instruction::CPU_386},
{"LOCK AND", "mem8,reg8", "p0 20 /r", Instruction::CPU_8086},
{"LOCK AND", "mem16,reg16", "p0 po 21 /r", Instruction::CPU_8086},
{"LOCK AND", "mem32,reg32", "p0 po 21 /r", Instruction::CPU_386},
{"LOCK AND", "BYTE mem8,imm8", "80 /4 ib", Instruction::CPU_8086},
{"LOCK AND", "WORD mem16,imm16", "p0 po 81 /4 iw", Instruction::CPU_8086},
{"LOCK AND", "DWORD mem32,imm32", "p0 po 81 /4 id", Instruction::CPU_386},
{"LOCK AND", "WORD mem16,imm8", "p0 po 83 /4 ib", Instruction::CPU_8086},
{"LOCK AND", "DWORD mem32,imm8", "p0 po 83 /4 ib", Instruction::CPU_386},
{"LOCK BTC", "mem16,reg16", "p0 po 0F BB /r", Instruction::CPU_386},
{"LOCK BTC", "mem32,reg32", "p0 po 0F BB /r", Instruction::CPU_386},
{"LOCK BTC", "WORD mem16,imm8", "p0 po 0F BA /7 ib", Instruction::CPU_386},
{"LOCK BTC", "DWORD mem32,imm8", "p0 po 0F BA /7 ib", Instruction::CPU_386},
{"LOCK BTR", "mem16,reg16", "p0 po 0F B3 /r", Instruction::CPU_386},
{"LOCK BTR", "mem32,reg32", "p0 po 0F B3 /r", Instruction::CPU_386},
{"LOCK BTR", "WORD mem16,imm8", "p0 po 0F BA /6 ib", Instruction::CPU_386},
{"LOCK BTR", "DWORD mem32,imm8", "p0 po 0F BA /6 ib", Instruction::CPU_386},
{"LOCK BTS", "mem16,reg16", "p0 po 0F AB /r", Instruction::CPU_386},
{"LOCK BTS", "mem32,reg32", "p0 po 0F AB /r", Instruction::CPU_386},
{"LOCK BTS", "WORD mem16,imm8", "p0 po 0F BA /5 ib", Instruction::CPU_386},
{"LOCK BTS", "DWORD mem32,imm8", "p0 po 0F BA /5 ib", Instruction::CPU_386},
{"LOCK CMPXCHG", "mem8,reg8", "p0 0F B0 /r", Instruction::CPU_PENTIUM},
{"LOCK CMPXCHG", "mem16,reg16", "p0 po 0F B1 /r", Instruction::CPU_PENTIUM},
{"LOCK CMPXCHG", "mem32,reg32", "p0 po 0F B1 /r", Instruction::CPU_PENTIUM},
{"LOCK CMPXCHG8B", "mem", "p0 0F C7 /1", Instruction::CPU_PENTIUM},
{"LOCK DEC", "BYTE mem8", "p0 FE /1", Instruction::CPU_8086},
{"LOCK DEC", "WORD mem16", "p0 po FF /1", Instruction::CPU_8086},
{"LOCK DEC", "DWORD mem32", "p0 po FF /1", Instruction::CPU_386},
{"LOCK INC", "BYTE mem8", "p0 FE /0", Instruction::CPU_8086},
{"LOCK INC", "WORD mem16", "p0 po FF /0", Instruction::CPU_8086},
{"LOCK INC", "DWORD mem32", "p0 po FF /0", Instruction::CPU_386},
{"LOCK NEG", "BYTE mem8", "p0 F6 /3", Instruction::CPU_8086},
{"LOCK NEG", "WORD mem16", "p0 po F7 /3", Instruction::CPU_8086},
{"LOCK NEG", "DWORD mem32", "p0 po F7 /3", Instruction::CPU_386},
{"LOCK NOT", "BYTE mem8", "p0 F6 /2", Instruction::CPU_8086},
{"LOCK NOT", "WORD mem16", "p0 po F7 /2", Instruction::CPU_8086},
{"LOCK NOT", "DWORD mem32", "p0 po F7 /2", Instruction::CPU_386},
{"LOCK OR", "mem8,reg8", "p0 08 /r", Instruction::CPU_8086},
{"LOCK OR", "mem16,reg16", "p0 po 09 /r", Instruction::CPU_8086},
{"LOCK OR", "mem32,reg32", "p0 po 09 /r", Instruction::CPU_386},
{"LOCK OR", "BYTE mem8,imm8", "p0 80 /1 ib", Instruction::CPU_8086},
{"LOCK OR", "WORD mem16,imm16", "p0 po 81 /1 iw", Instruction::CPU_8086},
{"LOCK OR", "DWORD mem32,imm32", "p0 po 81 /1 id", Instruction::CPU_386},
{"LOCK OR", "WORD mem16,imm8", "p0 po 83 /1 ib", Instruction::CPU_8086},
{"LOCK OR", "DWORD mem32,imm8", "p0 po 83 /1 ib", Instruction::CPU_386},
{"LOCK SBB", "mem8,reg8", "p0 18 /r", Instruction::CPU_8086},
{"LOCK SBB", "mem16,reg16", "p0 po 19 /r", Instruction::CPU_8086},
{"LOCK SBB", "mem32,reg32", "p0 po 19 /r", Instruction::CPU_386},
{"LOCK SBB", "BYTE mem8,imm8", "p0 80 /3 ib", Instruction::CPU_8086},
{"LOCK SBB", "WORD mem16,imm16", "p0 po 81 /3 iw", Instruction::CPU_8086},
{"LOCK SBB", "DWORD mem32,imm32", "p0 po 81 /3 id", Instruction::CPU_386},
{"LOCK SBB", "WORD mem16,imm8", "p0 po 83 /3 ib", Instruction::CPU_8086},
{"LOCK SBB", "DWORD mem32,imm8", "p0 po 83 /3 ib", Instruction::CPU_8086},
{"LOCK SUB", "BYTE mem8,imm8", "p0 80 /5 ib", Instruction::CPU_8086},
{"LOCK SUB", "WORD mem16,imm16", "p0 po 81 /5 iw", Instruction::CPU_8086},
{"LOCK SUB", "DWORD mem32,imm32", "p0 po 81 /5 id", Instruction::CPU_386},
{"LOCK SUB", "WORD mem16,imm8", "p0 po 83 /5 ib", Instruction::CPU_8086},
{"LOCK SUB", "DWORD mem32,imm8", "p0 po 83 /5 ib", Instruction::CPU_386},
{"LOCK SUB", "mem8,reg8", "p0 28 /r", Instruction::CPU_8086},
{"LOCK SUB", "mem16,reg16", "p0 po 29 /r", Instruction::CPU_8086},
{"LOCK SUB", "mem32,reg32", "p0 po 29 /r", Instruction::CPU_386},
{"LOCK XADD", "mem8,reg8", "p0 0F C0 /r", Instruction::CPU_486},
{"LOCK XADD", "mem16,reg16", "p0 po 0F C1 /r", Instruction::CPU_486},
{"LOCK XADD", "mem32,reg32", "p0 po 0F C1 /r", Instruction::CPU_486},
{"LOCK XCHG", "mem8,reg8", "p0 86 /r", Instruction::CPU_8086},
{"LOCK XCHG", "mem16,reg16", "p0 po 87 /r", Instruction::CPU_8086},
{"LOCK XCHG", "mem32,reg32", "p0 po 87 /r", Instruction::CPU_386},
{"LOCK XOR", "mem8,reg8", "p0 30 /r", Instruction::CPU_8086},
{"LOCK XOR", "mem16,reg16", "p0 po 31 /r", Instruction::CPU_8086},
{"LOCK XOR", "mem32,reg32", "p0 po 31 /r", Instruction::CPU_386},
{"LOCK XOR", "BYTE mem8,imm8", "p0 80 /6 ib", Instruction::CPU_8086},
{"LOCK XOR", "WORD mem16,imm16", "p0 po 81 /6 iw", Instruction::CPU_8086},
{"LOCK XOR", "DWORD mem32,imm32", "p0 po 81 /6 id", Instruction::CPU_386},
{"LOCK XOR", "WORD mem16,imm8", "p0 po 83 /6 ib", Instruction::CPU_8086},
{"LOCK XOR", "DWORD mem32,imm8", "p0 po 83 /6 ib", Instruction::CPU_386},
{"LODSB", "", "AC", Instruction::CPU_8086},
{"LODSD", "", "po AD", Instruction::CPU_386},
{"LODSQ", "", "po AD", Instruction::CPU_X64},
{"LODSW", "", "po AD", Instruction::CPU_8086},
{"LOOP", "imm", "E2 -b", Instruction::CPU_8086},
{"LOOP", "imm,CX", "pa E2 -b", Instruction::CPU_8086},
{"LOOP", "imm,ECX", "pa E2 -b", Instruction::CPU_386},
{"LOOPE", "imm", "E1 -b", Instruction::CPU_8086},
{"LOOPE", "imm,CX", "pa E1 -b", Instruction::CPU_8086},
{"LOOPE", "imm,ECX", "pa E1 -b", Instruction::CPU_386},
{"LOOPNE", "imm", "E0 -b", Instruction::CPU_8086},
{"LOOPNE", "imm,CX", "pa E0 -b", Instruction::CPU_8086},
{"LOOPNE", "imm,ECX", "pa E0 -b", Instruction::CPU_386},
{"LOOPNZ", "imm", "E0 -b", Instruction::CPU_8086},
{"LOOPNZ", "imm,CX", "pa E0 -b", Instruction::CPU_8086},
{"LOOPNZ", "imm,ECX", "pa E0 -b", Instruction::CPU_386},
{"LOOPZ", "imm", "E1 -b", Instruction::CPU_8086},
{"LOOPZ", "imm,CX", "pa E1 -b", Instruction::CPU_8086},
{"LOOPZ", "imm,ECX", "pa E1 -b", Instruction::CPU_386},
// {"LSL", "reg16,r/m16", "po 0F 03 /r", Instruction::CPU_286 | Instruction::CPU_PRIV},
// {"LSL", "reg32,r/m32", "po 0F 03 /r", Instruction::CPU_286 | Instruction::CPU_PRIV},
// {"LTR", "r/m16", "0F 00 /3", Instruction::CPU_286 | Instruction::CPU_PRIV},
{"LSS", "reg16,mem", "po 0F B2 /r", Instruction::CPU_386},
{"LSS", "reg32,mem", "po 0F B2 /r", Instruction::CPU_386},
{"MASKMOVDQU", "xmmreg,xmmreg", "66 0F F7 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MASKMOVQ", "mmreg,mmreg", "0F F7 /r", Instruction::CPU_KATMAI},
{"MAXPD", "xmmreg,r/m128", "66 0F 5F /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MAXPS", "xmmreg,r/m128", "0F 5F /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MAXSD", "xmmreg,xmm64", "p2 0F 5F /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MAXSS", "xmmreg,xmm32", "p3 0F 5F /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MFENCE", "", "0F AE F0", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MINPD", "xmmreg,r/m128", "66 0F 5D /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MINPS", "xmmreg,r/m128", "0F 5D /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MINSD", "xmmreg,xmm64", "p2 0F 5D /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MINSS", "xmmreg,xmm32", "p3 0F 5D /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MONITOR", "", "0F 01 C8", Instruction::CPU_PNI},
{"MOV", "r/m8,reg8", "88 /r", Instruction::CPU_8086},
{"MOV", "r/m16,reg16", "po 89 /r", Instruction::CPU_8086},
{"MOV", "r/m32,reg32", "po 89 /r", Instruction::CPU_386},
{"MOV", "r/m64,reg64", "po 89 /r", Instruction::CPU_X64},
{"MOV", "reg8,r/m8", "8A /r", Instruction::CPU_8086},
{"MOV", "reg16,r/m16", "po 8B /r", Instruction::CPU_8086},
{"MOV", "reg32,r/m32", "po 8B /r", Instruction::CPU_386},
{"MOV", "reg64,r/m64", "po 8B /r", Instruction::CPU_X64},
{"MOV", "reg8,imm8", "B0 +r ib", Instruction::CPU_8086},
{"MOV", "reg16,imm16", "po B8 +r iw", Instruction::CPU_8086},
{"MOV", "reg32,imm32", "po B8 +r id", Instruction::CPU_386},
// {"MOV", "reg64,imm64", "po B8 +r iq", Instruction::CPU_X64}, // FIXME: imm64 unimplemented
{"MOV", "BYTE r/m8,imm8", "C6 /0 ib", Instruction::CPU_8086},
{"MOV", "WORD r/m16,imm16", "po C7 /0 iw", Instruction::CPU_8086},
{"MOV", "DWORD r/m32,imm32", "po C7 /0 id", Instruction::CPU_386},
{"MOV", "QWORD r/m64,imm32", "po C7 /0 id", Instruction::CPU_X64},
// {"MOV", "AL,memoffs8", "A0 id", Instruction::CPU_8086},
// {"MOV", "AX,memoffs16", "po A1 id", Instruction::CPU_8086},
// {"MOV", "EAX,memoffs32", "po A1 id", Instruction::CPU_386},
// {"MOV", "memoffs8,AL", "A2 id", Instruction::CPU_8086},
// {"MOV", "memoffs16,AX", "po A3 id", Instruction::CPU_8086},
// {"MOV", "memoffs32,EAX", "po A3 id", Instruction::CPU_386},
// {"MOV", "r/m16,segreg", "po 8C /r", Instruction::CPU_8086},
// {"MOV", "r/m32,segreg", "po 8C /r", Instruction::CPU_386},
// {"MOV", "segreg,r/m16", "po 8E /r", Instruction::CPU_8086},
// {"MOV", "segreg,r/m32", "po 8E /r", Instruction::CPU_386},
// {"MOV", "reg32,CR", "0F 20 /r", Instruction::CPU_386},
// {"MOV", "reg32,DR", "0F 21 /r", Instruction::CPU_386},
// {"MOV", "reg32,TR", "0F 24 /r", Instruction::CPU_386},
// {"MOV", "CR,reg32", "0F 22 /r", Instruction::CPU_386},
// {"MOV", "DR,reg32", "0F 23 /r", Instruction::CPU_386},
// {"MOV", "TR,reg32", "0F 26 /r", Instruction::CPU_386},
{"MOVAPD", "xmmreg,r/m128", "66 0F 28 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVAPD", "r/m128,xmmreg", "66 0F 29 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVAPS", "xmmreg,r/m128", "0F 28 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVAPS", "r/m128,xmmreg", "0F 29 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVD", "mmreg,r/m32", "0F 6E /r", Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
{"MOVD", "mmreg,r/m64", "0F 6E /r", Instruction::CPU_X64},
{"MOVD", "r/m32,mmreg", "0F 7E /r", Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
{"MOVD", "r/m64,mmreg", "0F 7E /r", Instruction::CPU_X64},
{"MOVD", "xmmreg,r/m32", "66 0F 6E /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVD", "xmmreg,r/m64", "66 0F 6E /r", Instruction::CPU_X64},
{"MOVD", "r/m32,xmmreg", "66 0F 7E /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVD", "r/m64,xmmreg", "66 0F 7E /r", Instruction::CPU_X64},
{"MOVDDUP", "xmmreg,r/m128", "p2 0F 12 /r", Instruction::CPU_PNI},
{"MOVDQ2Q", "mmreg,xmmreg", "p2 0F D6 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVDQA", "xmmreg,r/m128", "66 0F 6F /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVDQA", "r/m128,xmmreg", "66 0F 7F /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVDQU", "xmmreg,r/m128", "p3 0F 6F /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVDQU", "r/m128,xmmreg", "p3 0F 7F /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVHLPS", "xmmreg,xmmreg", "0F 12 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVHPD", "xmmreg,mem64", "66 0F 16 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVHPD", "mem64,xmmreg", "66 0F 17 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVHPS", "xmmreg,mem64", "0F 16 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVHPS", "mem64,xmmreg", "0F 17 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVHPS", "xmmreg,xmmreg", "0F 16 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVLHPS", "xmmreg,xmmreg", "0F 16 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVLPD", "xmmreg,mem64", "66 0F 12 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVLPD", "mem64,xmmreg", "66 0F 13 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVLPS", "xmmreg,mem64", "0F 12 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVLPS", "mem64,xmmreg", "0F 13 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVMSKPD", "reg32,xmmreg", "66 0F 50 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVMSKPS", "reg32,xmmreg", "0F 50 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVNTDQ", "mem128,xmmreg", "66 0F E7 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVNTI", "mem32,reg32", "0F C3 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVNTI", "mem64,reg64", "0F C3 /r", Instruction::CPU_X64},
{"MOVNTPD", "mem128,xmmreg", "66 0F 2B /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVNTPS", "mem128,xmmreg", "0F 2B /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVNTQ", "mem64,mmreg", "0F E7 /r", Instruction::CPU_KATMAI},
{"MOVQ", "mmreg,mm64", "0F 6F /r", Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
{"MOVQ", "mm64,mmreg", "0F 7F /r", Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
{"MOVQ", "xmmreg,xmm64", "p3 0F 7E /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVQ", "xmm64,xmmreg", "66 0F D6 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVQ2DQ", "xmmreg,mmreg", "p3 0F D6 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVSB", "", "A4", Instruction::CPU_8086},
{"MOVSD", "", "po A5", Instruction::CPU_386},
{"MOVSD", "xmmreg,xmm64", "p2 0F 10 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVSD", "xmm64,xmmreg", "p2 0F 11 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVSHDUP", "xmmreg,r/m128", "p3 0F 16 /r", Instruction::CPU_PNI},
{"MOVSLDUP", "xmmreg,r/m128", "p3 0F 12 /r", Instruction::CPU_PNI},
{"MOVSQ", "", "po A5", Instruction::CPU_X64},
{"MOVSS", "xmmreg,xmm32", "p3 0F 10 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVSS", "xmm32,xmmreg", "p3 0F 11 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVSW", "", "po A5", Instruction::CPU_8086},
{"MOVSX", "reg16,r/m8", "po 0F BE /r", Instruction::CPU_386},
{"MOVSX", "reg32,r/m8", "po 0F BE /r", Instruction::CPU_386},
{"MOVSX", "reg64,r/m8", "po 0F BE /r", Instruction::CPU_X64},
{"MOVSX", "reg32,r/m16", "po 0F BF /r", Instruction::CPU_386},
{"MOVSX", "reg64,r/m16", "po 0F BF /r", Instruction::CPU_X64},
{"MOVSXD", "reg64,r/m32", "po 63 /r", Instruction::CPU_X64},
{"MOVUPD", "xmmreg,r/m128", "66 0F 10 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVUPD", "r/m128,xmmreg", "66 0F 11 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MOVUPS", "xmmreg,r/m128", "0F 10 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVUPS", "r/m128,xmmreg", "0F 11 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MOVZX", "reg16,r/m8", "po 0F B6 /r", Instruction::CPU_386},
{"MOVZX", "reg32,r/m8", "po 0F B6 /r", Instruction::CPU_386},
{"MOVZX", "reg64,r/m8", "po 0F B6 /r", Instruction::CPU_X64},
{"MOVZX", "reg32,r/m16", "po 0F B7 /r", Instruction::CPU_386},
{"MOVZX", "reg64,r/m16", "po 0F B7 /r", Instruction::CPU_X64},
{"MUL", "BYTE r/m8", "F6 /4", Instruction::CPU_8086},
{"MUL", "WORD r/m16", "po F7 /4", Instruction::CPU_8086},
{"MUL", "DWORD r/m32", "po F7 /4", Instruction::CPU_386},
{"MUL", "QWORD r/m64", "po F7 /4", Instruction::CPU_X64},
{"MULPD", "xmmreg,r/m128", "66 0F 59 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MULPS", "xmmreg,r/m128", "0F 59 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MULSD", "xmmreg,xmm64", "p2 0F 59 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"MULSS", "xmmreg,xmm32", "p3 0F 59 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"MWAIT", "", "0F 01 C9", Instruction::CPU_PNI},
{"NEG", "BYTE r/m8", "F6 /3", Instruction::CPU_8086},
{"NEG", "WORD r/m16", "po F7 /3", Instruction::CPU_8086},
{"NEG", "DWORD r/m32", "po F7 /3", Instruction::CPU_386},
{"NEG", "QWORD r/m64", "po F7 /3", Instruction::CPU_X64},
{"NOP", "", "90", Instruction::CPU_8086},
{"NOT", "BYTE r/m8", "F6 /2", Instruction::CPU_8086},
{"NOT", "WORD r/m16", "po F7 /2", Instruction::CPU_8086},
{"NOT", "DWORD r/m32", "po F7 /2", Instruction::CPU_386},
{"NOT", "QWORD r/m64", "po F7 /2", Instruction::CPU_X64},
{"NULL", "", ""}, // Empty 'instruction', placeholder for annotations
{"OR", "r/m8,reg8", "08 /r", Instruction::CPU_8086},
{"OR", "r/m16,reg16", "po 09 /r", Instruction::CPU_8086},
{"OR", "r/m32,reg32", "po 09 /r", Instruction::CPU_386},
{"OR", "r/m64,reg64", "po 09 /r", Instruction::CPU_X64},
{"OR", "reg8,r/m8", "0A /r", Instruction::CPU_8086},
{"OR", "reg16,r/m16", "po 0B /r", Instruction::CPU_8086},
{"OR", "reg32,r/m32", "po 0B /r", Instruction::CPU_386},
{"OR", "reg64,r/m64", "po 0B /r", Instruction::CPU_X64},
{"OR", "BYTE r/m8,imm8", "80 /1 ib", Instruction::CPU_8086},
{"OR", "WORD r/m16,imm16", "po 81 /1 iw", Instruction::CPU_8086},
{"OR", "DWORD r/m32,imm32", "po 81 /1 id", Instruction::CPU_386},
{"OR", "QWORD r/m64,imm32", "po 81 /1 id", Instruction::CPU_X64},
{"OR", "WORD r/m16,imm8", "po 83 /1 ib", Instruction::CPU_8086},
{"OR", "DWORD r/m32,imm8", "po 83 /1 ib", Instruction::CPU_386},
{"OR", "QWORD r/m64,imm8", "po 83 /1 ib", Instruction::CPU_X64},
{"OR", "AL,imm8", "0C ib", Instruction::CPU_8086},
{"OR", "AX,imm16", "po 0D iw", Instruction::CPU_8086},
{"OR", "EAX,imm32", "po 0D id", Instruction::CPU_386},
{"OR", "RAX,imm32", "po 0D id", Instruction::CPU_X64},
{"ORPD", "xmmreg,r/m128", "66 0F 56 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"ORPS", "xmmreg,r/m128", "0F 56 /r", Instruction::CPU_KATMAI | Instruction::CPU_SSE},
{"OUT", "imm8,AL", "E6 ib", Instruction::CPU_8086},
{"OUT", "imm8,AX", "po E7 ib", Instruction::CPU_8086},
{"OUT", "imm8,EAX", "po E7 ib", Instruction::CPU_386},
{"OUT", "DX,AL", "EE", Instruction::CPU_8086},
{"OUT", "DX,AX", "po EF", Instruction::CPU_8086},
{"OUT", "DX,EAX", "po EF", Instruction::CPU_386},
{"OUTSB", "", "6E", Instruction::CPU_186},
{"OUTSD", "", "po 6F", Instruction::CPU_386},
{"OUTSW", "", "po 6F", Instruction::CPU_186},
{"PACKSSDW", "mmreg,mm64", "0F 6B /r", Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
{"PACKSSDW", "xmmreg,r/m128", "66 0F 6B /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"PACKSSWB", "mmreg,mm64", "0F 63 /r", Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
{"PACKSSWB", "xmmreg,r/m128", "66 0F 63 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"PACKUSWB", "mmreg,mm64", "0F 67 /r", Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
{"PACKUSWB", "xmmreg,r/m128", "66 0F 67 /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"PADDB", "mmreg,mm64", "0F FC /r", Instruction::CPU_PENTIUM | Instruction::CPU_MMX},
{"PADDB", "xmmreg,r/m128", "66 0F FC /r", Instruction::CPU_WILLAMETTE | Instruction::CPU_SSE2},
{"PADDD", "mmreg,mm64", "0F FE /r", Instruction::CPU_PENTIUM | Instruction::CPU_MMX},