Unsigned data from the FPGA is being presented as signed.

From VHDL:

```
if(ir = X"00") then
    dr <= X"12345678";
elsif(ir = X"09") then
    dr <= X"87654321";
```

Reported by terminal.py:

```
>> 1457294678.948 Address[0, 0x00] Data[0, 0x00000000]
<< 1457294678.963138 Address[0, 0x00] Data[305419896, 0x12345678]

>> 1457294682.773 Address[9, 0x09] Data[0, 0x00000000]
<< 1457294682.787391 Address[9, 0x09] Data[-2023406815, 0x-789ABCDF]
```
