From 5d322a366cc6691d0e4b50441926d5a7a3e09e12 Mon Sep 17 00:00:00 2001 From: Stefan Unrein Date: Tue, 17 Feb 2026 02:10:19 +0100 Subject: [PATCH 1/2] add some AXI modules Co-authored-by: Srikanth Boppudi Co-authored-by: Nimitha Mallikarjuna <> Co-authored-by: Adrian Weiland Co-authored-by: Patrick Lehmann Co-authored-by: Asif Iqbal Co-authored-by: Jonas Schreiner --- .gitlab-ci.yml | 485 +++++++++++++++++- .sigasi/project.sigasi | 59 +++ AUTHORS.md | 35 +- .../axi4lite/axi4lite_HighResolutionClock.rst | 260 ++++++++++ .../bus/axi4lite/axi4lite_Ocram_Adapter.rst | 220 ++++++++ docs/IPCores/bus/axi4lite/axi4lite_UART.rst | 341 ++++++++++++ docs/IPCores/bus/axi4lite/index.rst | 6 + docs/_extensions/DocumentMember.py | 12 +- docs/make.bat | 7 +- docs/requirements.txt | 18 +- lib/OSVVM-AXI4 | 2 +- lib/OSVVM-Common | 2 +- lib/OSVVM-Scripts | 2 +- lib/OSVVM-UART | 2 +- lib/OsvvmLibraries.pro | 23 +- lib/osvvm | 2 +- poc.ps1 | 2 +- poc.sh | 2 +- regression.tcl | 73 ++- src/PoC.pro | 11 +- src/arith/arith.pkg.vhdl | 5 +- src/arith/arith.pro | 8 +- src/arith/arith_addw.vhdl | 3 - src/arith/arith_carrychain_inc.vhdl | 3 - src/arith/arith_convert_bin2bcd.vhdl | 5 +- src/arith/arith_counter_bcd.vhdl | 3 - src/arith/arith_counter_free.vhdl | 3 - src/arith/arith_counter_gray.vhdl | 3 - src/arith/arith_counter_ring.vhdl | 3 - src/arith/arith_div.vhdl | 3 - src/arith/arith_firstone.vhdl | 3 - src/arith/arith_prng.vhdl | 5 +- src/arith/arith_scaler.vhdl | 7 +- src/arith/arith_shifter_barrel.vhdl | 3 - src/arith/arith_trng.vhdl | 13 +- src/arith/xilinx/arith_addw_xilinx.vhdl | 3 - .../xilinx/arith_carrychain_inc_xilinx.vhdl | 3 - src/bus/axi4/AXI4Lite/AXI4Lite.pkg.vhdl | 10 +- src/bus/axi4/AXI4Lite/AXI4Lite_FIFO.vhdl | 10 +- src/bus/axi4/AXI4Lite/AXI4Lite_FIFO_cdc.vhdl | 10 +- .../AXI4Lite/AXI4Lite_GitVersionRegister.vhdl | 5 +- .../AXI4Lite_HighResolutionClock.vhdl | 242 +++++++++ src/bus/axi4/AXI4Lite/AXI4Lite_OSVVM.pkg.vhdl | 5 +- .../axi4/AXI4Lite/AXI4Lite_Ocram_Adapter.vhdl | 234 +++++++++ src/bus/axi4/AXI4Lite/AXI4Lite_Register.vhdl | 18 +- .../AXI4Lite_Termination_Manager.vhdl | 5 +- .../AXI4Lite_Termination_Subordinate.vhdl | 9 +- src/bus/axi4/AXI4Lite/AXI4Lite_Uart.vhdl | 238 +++++++++ src/bus/axi4/AXI4Stream/AXI4Stream.pkg.vhdl | 5 +- src/bus/axi4/AXI4Stream/AXI4Stream_DeMux.vhdl | 5 +- src/bus/axi4/AXI4Stream/AXI4Stream_FIFO.vhdl | 5 +- .../axi4/AXI4Stream/AXI4Stream_FIFO_cdc.vhdl | 5 +- .../AXI4Stream/AXI4Stream_FIFO_tempgot.vhdl | 5 +- .../AXI4Stream/AXI4Stream_FIFO_tempput.vhdl | 5 +- src/bus/axi4/AXI4Stream/AXI4Stream_Mux.vhdl | 5 +- src/bus/axi4/AXI4Stream/AXI4Stream_Stage.vhdl | 5 +- src/bus/axi4/AXI4_Common.pkg.vhdl | 5 +- src/bus/axi4/AXI4_FIFO.vhdl | 5 +- src/bus/axi4/AXI4_FIFO_cdc.vhdl | 5 +- src/bus/axi4/AXI4_Full.pkg.vhdl | 6 +- src/bus/axi4/AXI4_OSVVM.pkg.vhdl | 15 +- src/bus/axi4/AXI4_Termination_Manager.vhdl | 13 +- .../axi4/AXI4_Termination_Subordinate.vhdl | 14 +- src/bus/axi4/AXI4_to_AXI4Lite.vhdl | 13 +- src/bus/axi4/axi4.pkg.vhdl | 12 +- src/bus/axi4/axi4.pro | 45 +- src/bus/bus.pro | 16 +- src/bus/bus_Arbiter.vhdl | 5 +- src/bus/drp/DRP_To_AXI4Lite_Bridge.vhdl | 228 ++++++++ src/bus/drp/drp.generic.vhdl | 56 ++ src/bus/drp/drp.pkg.vhdl | 95 ++++ src/bus/stream/stream.pkg.vhdl | 5 +- src/bus/stream/stream.pro | 27 +- src/bus/stream/stream_DeMux.vhdl | 3 - src/bus/stream/stream_FIFO.vhdl | 5 +- src/bus/stream/stream_FrameGenerator.vhdl | 5 +- src/bus/stream/stream_Mirror.vhdl | 3 - src/bus/stream/stream_Mux.vhdl | 5 +- src/bus/stream/stream_Source.vhdl | 3 - src/cache/cache.pkg.vhdl | 6 - src/cache/cache.pro | 17 + src/cache/cache_cpu.vhdl | 3 - src/cache/cache_mem.vhdl | 3 - src/cache/cache_par.vhdl | 3 - src/cache/cache_par2.vhdl | 3 - src/cache/cache_replacement_policy.vhdl | 3 - src/cache/cache_tagunit_par.vhdl | 3 - src/cache/cache_tagunit_seq.vhdl | 5 +- src/comm/comm.pkg.vhdl | 3 - src/comm/comm.pro | 3 +- src/comm/comm_crc.vhdl | 3 - src/comm/comm_scramble.vhdl | 3 - src/common/README.md | 18 +- src/common/common.pro | 2 +- src/common/common.vhdl | 3 - src/common/components.vhdl | 14 +- src/common/config.vhdl | 5 +- src/common/debug.vhdl | 3 - src/common/math.vhdl | 7 +- src/common/physical.vhdl | 5 +- src/common/protected.v08.vhdl | 5 - src/common/strings.vhdl | 145 +++--- src/common/utils.vhdl | 5 +- src/common/vectors.vhdl | 5 +- src/dstruct/dstruct.pkg.vhdl | 3 - src/dstruct/dstruct.pro | 3 +- src/dstruct/dstruct_deque.vhdl | 3 - src/dstruct/dstruct_stack.vhdl | 3 - src/fifo/fifo.pkg.vhdl | 3 - src/fifo/fifo.pro | 5 +- src/fifo/fifo_cc_got.vhdl | 5 +- src/fifo/fifo_cc_got_tempgot.vhdl | 5 +- src/fifo/fifo_cc_got_tempput.vhdl | 22 +- src/fifo/fifo_ic_assembly.vhdl | 11 +- src/fifo/fifo_ic_got.vhdl | 5 +- src/fifo/fifo_shift.vhdl | 5 +- src/fifo/fifo_stage.vhdl | 94 ++-- src/io/ddrio/ddrio.pkg.vhdl | 3 - src/io/ddrio/ddrio_in.vhdl | 3 - src/io/ddrio/ddrio_in_altera.vhdl | 3 - src/io/ddrio/ddrio_in_xilinx.vhdl | 3 - src/io/ddrio/ddrio_inout.vhdl | 3 - src/io/ddrio/ddrio_inout_altera.vhdl | 3 - src/io/ddrio/ddrio_inout_xilinx.vhdl | 3 - src/io/ddrio/ddrio_out.vhdl | 3 - src/io/ddrio/ddrio_out_altera.vhdl | 3 - src/io/ddrio/ddrio_out_xilinx.vhdl | 3 - src/io/fan/fan.pro | 12 + src/io/iic/iic.pkg.vhdl | 5 +- src/io/iic/iic.pro | 10 +- src/io/io.pkg.vhdl | 76 +-- src/io/io.pro | 13 +- src/io/io_7SegmentMux_BCD.vhdl | 5 +- src/io/io_7SegmentMux_HEX.vhdl | 5 +- src/io/io_Debounce.vhdl | 97 ++-- src/io/io_FanControl.vhdl | 22 +- src/io/io_FrequencyCounter.vhdl | 69 +-- src/io/io_GlitchFilter.vhdl | 5 +- src/io/io_KeyPadScanner.vhdl | 5 +- src/io/io_PulseWidthModulation.vhdl | 73 ++- src/io/io_TimingCounter.vhdl | 27 +- src/io/pmod/pmod.pkg.vhdl | 5 +- src/io/pmod/pmod_KYPD.vhdl | 3 - src/io/pmod/pmod_SSD.vhdl | 3 - src/io/pmod/pmod_USBUART.vhdl | 3 - src/io/spi/spi.pro | 14 + src/io/uart/uart.pkg.vhdl | 20 +- src/io/uart/uart.pro | 2 +- src/io/uart/uart_bclk.vhdl | 41 +- src/io/uart/uart_fifo.vhdl | 390 ++++++++------ src/io/uart/uart_ft245.vhdl | 7 +- src/io/uart/uart_rx.vhdl | 160 ++++-- src/io/uart/uart_tx.vhdl | 136 +++-- src/mem/lut/lut_Sine.vhdl | 7 +- src/mem/mem.pkg.vhdl | 45 +- src/mem/mem.pro | 7 +- src/mem/mem_GitVersionRegister.pkg.vhdl | 5 +- src/mem/ocram/altera/ocram_sp_altera.vhdl | 3 - src/mem/ocram/altera/ocram_tdp_altera.vhdl | 3 - src/mem/ocram/ocram.pkg.vhdl | 3 - src/mem/ocram/ocram_esdp.vhdl | 3 - src/mem/ocram/ocram_sdp.vhdl | 5 +- src/mem/ocram/ocram_sdp_optimized.vhdl | 5 +- src/mem/ocram/ocram_sdp_wf.vhdl | 3 - src/mem/ocram/ocram_sp.vhdl | 3 - src/mem/ocram/ocram_tdp.vhdl | 3 - src/mem/ocram/ocram_tdp_sim.vhdl | 3 - src/mem/ocram/ocram_tdp_wf.vhdl | 3 - src/mem/ocrom/ocrom.pkg.vhdl | 3 - src/mem/ocrom/ocrom_dp.vhdl | 3 - src/mem/ocrom/ocrom_sp.vhdl | 3 - src/mem/sdram/sdram_ctrl_de0.vhdl | 3 - src/mem/sdram/sdram_ctrl_fsm.vhdl | 3 - src/mem/sdram/sdram_ctrl_phy_de0.vhdl | 3 - src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl | 3 - src/mem/sdram/sdram_ctrl_s3esk.vhdl | 3 - src/misc/clock/clock.pkg.vhdl | 103 ++++ src/misc/clock/clock_Counter.vhdl | 77 +++ src/misc/clock/clock_HighResolution.vhdl | 202 ++++++++ src/misc/clock/clock_Timer.vhdl | 154 ++++++ src/misc/filter/filter_and.vhdl | 3 - src/misc/filter/filter_mean.vhdl | 3 - src/misc/filter/filter_or.vhdl | 3 - src/misc/gearbox/gearbox.pro | 2 +- src/misc/gearbox/gearbox_down_cc.vhdl | 3 - src/misc/gearbox/gearbox_down_dc.vhdl | 3 - src/misc/gearbox/gearbox_up_cc.vhdl | 3 - src/misc/gearbox/gearbox_up_dc.vhdl | 3 - src/misc/misc.pro | 13 +- src/misc/misc_Delay.vhdl | 3 - src/misc/misc_FrequencyMeasurement.vhdl | 3 - src/misc/misc_StrobeGenerator.vhdl | 5 +- src/misc/misc_StrobeLimiter.vhdl | 5 +- src/misc/misc_StrobeStretcher.vhdl | 5 +- src/misc/misc_bit_lz.vhdl | 3 - src/misc/stat/stat.pro | 2 +- src/misc/stat/stat_Average.vhdl | 3 - src/misc/stat/stat_Histogram.vhdl | 3 - src/misc/stat/stat_Maximum.vhdl | 3 - src/misc/stat/stat_Minimum.vhdl | 3 - src/net/arp/arp.pro | 2 +- src/net/arp/arp_BroadCast_Receiver.vhdl | 3 - src/net/arp/arp_BroadCast_Requester.vhdl | 3 - src/net/arp/arp_Cache.vhdl | 3 - src/net/arp/arp_IPPool.vhdl | 3 - src/net/arp/arp_UniCast_Receiver.vhdl | 3 - src/net/arp/arp_UniCast_Responder.vhdl | 3 - src/net/arp/arp_Wrapper.vhdl | 3 - src/net/icmpv4/icmpv4.pro | 2 +- src/net/icmpv4/icmpv4_RX.vhdl | 3 - src/net/icmpv4/icmpv4_TX.vhdl | 3 - src/net/icmpv4/icmpv4_Wrapper.vhdl | 3 - src/net/ipv4/ipv4.pro | 2 +- src/net/ipv4/ipv4_FrameLoopback.vhdl | 3 - src/net/ipv4/ipv4_RX.vhdl | 3 - src/net/ipv4/ipv4_TX.vhdl | 3 - src/net/ipv4/ipv4_Wrapper.vhdl | 3 - src/net/ipv6/ipv6.pro | 2 +- src/net/ipv6/ipv6_FrameLoopback.vhdl | 3 - src/net/ipv6/ipv6_RX.vhdl | 3 - src/net/ipv6/ipv6_TX.vhdl | 3 - src/net/ipv6/ipv6_Wrapper.vhdl | 3 - src/net/mac/mac.pro | 2 +- src/net/mac/mac_FrameLoopback.vhdl | 3 - src/net/mac/mac_RX_DestMAC_Switch.vhdl | 3 - src/net/mac/mac_RX_SrcMAC_Filter.vhdl | 3 - src/net/mac/mac_RX_Type_Switch.vhdl | 3 - src/net/mac/mac_TX_DestMAC_Prepender.vhdl | 3 - src/net/mac/mac_TX_SrcMAC_Prepender.vhdl | 3 - src/net/mac/mac_TX_Type_Prepender.vhdl | 5 +- src/net/mac/mac_Wrapper.vhdl | 3 - src/net/net.pkg.vhdl | 5 +- src/net/net.pro | 2 +- src/net/net_FrameChecksum.vhdl | 3 - src/net/udp/udp.pro | 2 +- src/net/udp/udp_FrameLoopback.vhdl | 3 - src/net/udp/udp_RX.vhdl | 3 - src/net/udp/udp_TX.vhdl | 3 - src/net/udp/udp_Wrapper.vhdl | 3 - src/sim/README.md | 18 +- src/sim/sim.pro | 2 +- src/sim/sim_VCDParser.vhdl | 3 - src/sort/sort.pro | 2 +- src/sort/sort_lru_list.vhdl | 3 - src/sort/sortnet/sortnet.pkg.vhdl | 3 - src/sort/sortnet/sortnet.pro | 2 +- src/sort/sortnet/sortnet_BitonicSort.vhdl | 3 - .../sortnet/sortnet_MergeSort_Streamed.vhdl | 3 - .../sortnet/sortnet_OddEvenMergeSort.vhdl | 3 - src/sort/sortnet/sortnet_OddEvenSort.vhdl | 3 - src/sort/sortnet/sortnet_Stream_Adapter.vhdl | 3 - src/sort/sortnet/sortnet_Stream_Adapter2.vhdl | 3 - src/sort/sortnet/sortnet_Transform.vhdl | 3 - src/sync/sync.pkg.vhdl | 5 +- src/sync/sync.pro | 4 +- src/sync/sync_Bits.vhdl | 5 +- src/sync/sync_Bits_Altera.vhdl | 3 - src/sync/sync_Bits_Xilinx.vhdl | 5 +- src/sync/sync_Command.vhdl | 5 +- src/sync/sync_Pulse.vhdl | 3 - src/sync/sync_Pulse_Altera.vhdl | 3 - src/sync/sync_Pulse_Xilinx.vhdl | 3 - src/sync/sync_Reset.vhdl | 5 +- src/sync/sync_Reset_Altera.vhdl | 5 +- src/sync/sync_Reset_Xilinx.vhdl | 5 +- src/sync/sync_Strobe.vhdl | 5 +- src/sync/sync_Vector.vhdl | 5 +- src/xil/xil.pkg.vhdl | 5 +- src/xil/xil.pro | 2 +- src/xil/xil_BSCAN.vhdl | 3 - src/xil/xil_DNAPort.vhdl | 5 +- src/xil/xil_Reconfigurator.vhdl | 3 - src/xil/xil_SystemMonitor.vhdl | 3 - tb/OsvvmCommon.pkg.vhdl | 28 + tb/RunAllTests.pro | 12 +- tb/arith/RunAllTests.pro | 5 +- tb/arith/addw/RunAllTests.pro | 2 +- tb/arith/addw/arith_addw_Simple.vhdl | 5 +- tb/arith/addw/arith_addw_TestController.vhdl | 5 +- .../addw/arith_addw_TestController_pkg.vhdl | 5 +- tb/arith/addw/arith_addw_TestHarness.vhdl | 5 +- tb/arith/carrychain_inc/RunAllTests.pro | 2 +- .../arith_carrychain_inc_Simple.vhdl | 5 +- .../arith_carrychain_inc_TestController.vhdl | 5 +- .../arith_carrychain_inc_TestHarness.vhdl | 5 +- tb/arith/cca/RunAllTests.pro | 2 +- tb/arith/cca/arith_cca_Simple.vhdl | 5 +- tb/arith/cca/arith_cca_TestController.vhdl | 5 +- tb/arith/cca/arith_cca_TestHarness.vhdl | 5 +- tb/arith/convert_bin2bcd/RunAllTests.pro | 2 +- .../arith_convert_bin2bcd_Simple.vhdl | 5 +- .../arith_convert_bin2bcd_TestController.vhdl | 5 +- .../arith_convert_bin2bcd_TestHarness.vhdl | 5 +- tb/arith/counter_bcd/RunAllTests.pro | 2 +- .../counter_bcd/arith_counter_bcd_Simple.vhdl | 5 +- .../arith_counter_bcd_TestController.vhdl | 5 +- .../arith_counter_bcd_TestHarness.vhdl | 5 +- tb/arith/counter_free/RunAllTests.pro | 2 +- .../arith_counter_free_Simple.vhdl | 5 +- .../arith_counter_free_TestController.vhdl | 5 +- .../arith_counter_free_TestHarness.vhdl | 5 +- tb/arith/counter_gray/RunAllTests.pro | 2 +- .../arith_counter_gray_Simple.vhdl | 5 +- .../arith_counter_gray_TestController.vhdl | 5 +- .../arith_counter_gray_TestHarness.vhdl | 5 +- tb/arith/counter_ring/RunAllTests.pro | 2 +- .../arith_counter_ring_Simple.vhdl | 5 +- .../arith_counter_ring_TestController.vhdl | 5 +- .../arith_counter_ring_TestHarness.vhdl | 5 +- tb/arith/div/RunAllTests.pro | 2 +- tb/arith/div/arith_div_Simple.vhdl | 5 +- tb/arith/div/arith_div_TestController.vhdl | 5 +- tb/arith/div/arith_div_TestHarness.vhdl | 5 +- tb/arith/firstone/RunAllTests.pro | 2 +- tb/arith/firstone/arith_firstone_Simple.vhdl | 5 +- .../arith_firstone_TestController.vhdl | 5 +- .../firstone/arith_firstone_TestHarness.vhdl | 5 +- tb/arith/prefix_and/RunAllTests.pro | 2 +- .../arith_prefix_and_Exhaustive.vhdl | 5 +- .../prefix_and/arith_prefix_and_Simple.vhdl | 5 +- .../arith_prefix_and_TestController.vhdl | 5 +- .../arith_prefix_and_TestHarness.vhdl | 5 +- tb/arith/prefix_or/RunAllTests.pro | 2 +- .../prefix_or/arith_prefix_or_Exhaustive.vhdl | 5 +- .../prefix_or/arith_prefix_or_Simple.vhdl | 5 +- .../arith_prefix_or_TestController.vhdl | 5 +- .../arith_prefix_or_TestHarness.vhdl | 5 +- tb/arith/prng/arith_prng_Simple.vhdl | 5 +- tb/arith/prng/arith_prng_TestController.vhdl | 5 +- tb/arith/prng/arith_prng_TestHarness.vhdl | 5 +- tb/arith/same/RunAllTests.pro | 2 +- tb/arith/same/arith_same_Simple.vhdl | 5 +- tb/arith/same/arith_same_TestController.vhdl | 5 +- tb/arith/same/arith_same_TestHarness.vhdl | 5 +- tb/arith/scaler/RunAllTests.pro | 2 +- tb/arith/scaler/arith_scaler_Simple.vhdl | 5 +- .../scaler/arith_scaler_TestController.vhdl | 5 +- tb/arith/scaler/arith_scaler_TestHarness.vhdl | 5 +- tb/arith/shifter_barrel/RunAllTests.pro | 2 +- .../arith_shifter_barrel_Simple.vhdl | 5 +- .../arith_shifter_barrel_TestController.vhdl | 5 +- .../arith_shifter_barrel_TestHarness.vhdl | 5 +- tb/arith/sqrt/RunAllTests.pro | 2 +- tb/arith/sqrt/arith_sqrt_Simple.vhdl | 5 +- tb/arith/sqrt/arith_sqrt_TestController.vhdl | 5 +- tb/arith/sqrt/arith_sqrt_TestHarness.vhdl | 5 +- tb/arith/trng/RunAllTests.pro | 2 +- tb/arith/trng/arith_trng_Simple.vhdl | 5 +- tb/arith/trng/arith_trng_TestController.vhdl | 5 +- tb/arith/trng/arith_trng_TestHarness.vhdl | 5 +- tb/bus/RunAllTests.pro | 4 +- .../RunAllTests.pro | 32 ++ ...xi4lite_HighResolutionClock_correction.tcl | 5 + ...i4lite_HighResolutionClock_correction.vhdl | 156 ++++++ ...xi4lite_HighResolutionClock_load_times.tcl | 5 + ...i4lite_HighResolutionClock_load_times.vhdl | 170 ++++++ .../axi4lite_HighResolutionClock_tb_pkg.vhdl | 58 +++ .../axi4lite_HighResolutionClock_tc.vhdl | 56 ++ .../axi4lite_HighResolutionClock_th.vhdl | 178 +++++++ ...AXI4Lite_Ocram_Adapter_TestController.vhdl | 51 ++ .../AXI4Lite_Ocram_Adapter_TestHarness.vhdl | 204 ++++++++ .../AXI4Lite_Ocram_Adapter/RunAllTests.pro | 31 ++ .../TC_AsyncReadWrite.vhdl | 151 ++++++ .../TC_SimpleReadWrite.vhdl | 95 ++++ ...al.vhdl => AXI4Lite_Register_Initial.vhdl} | 13 +- .../AXI4Lite_Register_ReadWrite.vhdl | 13 +- .../AXI4Lite_Register_TestController.vhdl | 13 +- .../AXI4Lite_Register_TestHarness.vhdl | 13 +- .../AXI4Lite_Register_pkg.vhdl | 13 +- .../AXI4Lite_Register/RunAllTests.pro | 7 +- .../AXI4Lite/AXI4Lite_Uart/RunAllTests.pro | 33 ++ .../AXI4Lite_Uart/axi4lite_UART_SWFC.vhdl | 256 +++++++++ .../AXI4Lite_Uart/axi4lite_UART_receive.vhdl | 95 ++++ .../axi4lite_UART_receive_burst.vhdl | 225 ++++++++ .../axi4lite_UART_receive_parity.vhdl | 118 +++++ .../AXI4Lite_Uart/axi4lite_UART_tc.vhdl | 74 +++ .../AXI4Lite_Uart/axi4lite_UART_th.vhdl | 186 +++++++ .../axi4lite_UART_transmit_burst.vhdl | 184 +++++++ tb/bus/axi4/AXI4Lite/RunAllTests.pro | 10 +- tb/bus/axi4/RunAllTests.pro | 2 +- tb/common.pro | 24 + tb/mem/ocram/ocram_sp_tb.vhdl | 3 - tb/misc/RunAllTests.pro | 28 + tb/misc/clock/RunAllTests.pro | 31 ++ tb/misc/clock/clock_HighResolution_load.tcl | 2 + tb/misc/clock/clock_HighResolution_load.vhdl | 187 +++++++ tb/misc/clock/clock_HighResolution_tc.vhdl | 58 +++ tb/misc/clock/clock_HighResolution_th.vhdl | 193 +++++++ tb/sim/sim_VCDParser_tb.vhdl | 3 - tb/sync/Bits/RunAllTests.pro | 2 +- tb/sync/Bits/sync_Bits_Simple.vhdl | 5 +- tb/sync/Bits/sync_Bits_TestController.vhdl | 5 +- tb/sync/Bits/sync_Bits_TestHarness.vhdl | 5 +- tb/sync/Command/RunAllTests.pro | 2 +- tb/sync/Command/sync_Command_Simple.vhdl | 5 +- .../Command/sync_Command_TestController.vhdl | 5 +- tb/sync/Command/sync_Command_TestHarness.vhdl | 5 +- tb/sync/Reset/RunAllTests.pro | 2 +- tb/sync/Reset/sync_Reset_Simple.vhdl | 5 +- tb/sync/Reset/sync_Reset_TestController.vhdl | 5 +- tb/sync/Reset/sync_Reset_TestHarness.vhdl | 5 +- tb/sync/RunAllTests.pro | 2 +- tb/sync/Strobe/RunAllTests.pro | 2 +- tb/sync/Strobe/sync_Strobe_Simple.vhdl | 5 +- .../Strobe/sync_Strobe_TestController.vhdl | 5 +- tb/sync/Strobe/sync_Strobe_TestHarness.vhdl | 5 +- tb/sync/Vector/RunAllTests.pro | 2 +- tb/sync/Vector/sync_Vector_Simple.vhdl | 5 +- .../Vector/sync_Vector_TestController.vhdl | 5 +- tb/sync/Vector/sync_Vector_TestHarness.vhdl | 5 +- temp/README.md | 2 +- .../preSynth_GitVersionRegister_Vivado.tcl | 2 +- tools/precompile/compile-altera.sh | 2 +- tools/precompile/compile-lattice.sh | 2 +- tools/precompile/compile-osvvm.sh | 2 +- tools/precompile/compile-xilinx-vivado.sh | 2 +- tools/precompile/precompile.sh | 2 +- ucf/sync/sync_Reset.xdc | 11 + ucf/sync/sync_Reset_Xilinx.xdc | 11 +- ucf/sync/sync_Vector.xdc | 2 +- vhdl_coding.md | 12 +- xst/README.md | 3 - xst/Series-7.xst | 55 -- xst/Spartan-3.xst | 58 --- xst/Spartan-6.xst | 55 -- xst/default.filter | 0 xst/empty.xcf | 0 xst/xil/mig/mig_Atlys_1x128.rules | 36 -- xst/xil/mig/mig_Atlys_1x128.xcf | 3 - xst/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rules | 88 ---- 430 files changed, 7304 insertions(+), 2195 deletions(-) create mode 100644 .sigasi/project.sigasi create mode 100644 docs/IPCores/bus/axi4lite/axi4lite_HighResolutionClock.rst create mode 100644 docs/IPCores/bus/axi4lite/axi4lite_Ocram_Adapter.rst create mode 100644 docs/IPCores/bus/axi4lite/axi4lite_UART.rst create mode 100644 src/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock.vhdl create mode 100644 src/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter.vhdl create mode 100644 src/bus/axi4/AXI4Lite/AXI4Lite_Uart.vhdl create mode 100644 src/bus/drp/DRP_To_AXI4Lite_Bridge.vhdl create mode 100644 src/bus/drp/drp.generic.vhdl create mode 100644 src/bus/drp/drp.pkg.vhdl create mode 100644 src/io/fan/fan.pro create mode 100644 src/io/spi/spi.pro create mode 100644 src/misc/clock/clock.pkg.vhdl create mode 100644 src/misc/clock/clock_Counter.vhdl create mode 100644 src/misc/clock/clock_HighResolution.vhdl create mode 100644 src/misc/clock/clock_Timer.vhdl create mode 100644 tb/OsvvmCommon.pkg.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/RunAllTests.pro create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_correction.tcl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_correction.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_load_times.tcl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_load_times.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_tb_pkg.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_tc.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_th.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/AXI4Lite_Ocram_Adapter_TestController.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/AXI4Lite_Ocram_Adapter_TestHarness.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/RunAllTests.pro create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/TC_AsyncReadWrite.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/TC_SimpleReadWrite.vhdl rename tb/bus/axi4/AXI4Lite/AXI4Lite_Register/{AXI4Lite_Register_initial.vhdl => AXI4Lite_Register_Initial.vhdl} (91%) create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/RunAllTests.pro create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_SWFC.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_receive.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_receive_burst.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_receive_parity.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_tc.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_th.vhdl create mode 100644 tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_transmit_burst.vhdl create mode 100644 tb/common.pro create mode 100644 tb/misc/RunAllTests.pro create mode 100644 tb/misc/clock/RunAllTests.pro create mode 100644 tb/misc/clock/clock_HighResolution_load.tcl create mode 100644 tb/misc/clock/clock_HighResolution_load.vhdl create mode 100644 tb/misc/clock/clock_HighResolution_tc.vhdl create mode 100644 tb/misc/clock/clock_HighResolution_th.vhdl create mode 100644 ucf/sync/sync_Reset.xdc delete mode 100644 xst/README.md delete mode 100644 xst/Series-7.xst delete mode 100644 xst/Spartan-3.xst delete mode 100644 xst/Spartan-6.xst delete mode 100644 xst/default.filter delete mode 100644 xst/empty.xcf delete mode 100644 xst/xil/mig/mig_Atlys_1x128.rules delete mode 100644 xst/xil/mig/mig_Atlys_1x128.xcf delete mode 100644 xst/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rules diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index b5d202152..1d68b9a9f 100755 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,15 +1,484 @@ stages: - - Selftest + - prepare + - build_osvvm + - build_poc + - test + - pages variables: GIT_SUBMODULE_STRATEGY: recursive + SIMULATOR_PAGES: "GHDL" # simulator from which the results should be published on GitLab pages (GHDL, Riviera-PRO) -pyIPCMI-Selftest: - stage: Selftest +#pyIPCMI-Selftest: +# stage: Selftest +# image: ${CI_REGISTRY}/docker-images/base-image:latest +# before_script: +# - pip3 install -r tools/GitLab-CI/requirements.txt +## - ./tools/GitLab-CI/ghdl.setup.sh +# - ./tools/GitLab-CI/poc.setup.sh +# script: +## - ./tools/GitLab-CI/poc.dryrun.sh +# - ./tools/GitLab-CI/poc.run.sh "PoC.*" + +Scripts: + stage: prepare + image: ${CI_REGISTRY}/docker-images/base-image:alpine + script: + - cp src/common/my_project.vhdl.template tb/common/my_project.vhdl # use CopyFile when its supporting renaming + - sed -i 's#\(constant\sMY_PROJECT_DIR\s*:\s*string\s*:=\s*\)".*";#\1"'"$(pwd)"'";#' tb/common/my_project.vhdl + - sed -i 's#\(constant\sMY_OPERATING_SYSTEM\s*:\s*string\s*:=\s*\)".*";#\1"LINUX";#' tb/common/my_project.vhdl + + - CreateAndChangeDirectory "temp" "Simulation working directory" + - | + tee poc_namespace.tcl << EOF + namespace eval ::poc { + variable myConfigFile "../tb/common/my_config_GENERIC.vhdl" + variable myProjectFile "../tb/common/my_project.vhdl" + variable vendor "GENERIC"; # GENERIC for vendor-less build; Xilinx, Altera,... for vendor specific build + } + EOF + + tee select_simulator.tcl << EOF + if {[info exists nvc_dataDir]} { + source ../../lib/OSVVM-Scripts/StartNVC.tcl + } else { + source ../../lib/OSVVM-Scripts/StartUp.tcl + } + EOF + + tee setup_simulator.tcl << EOF + source ../select_simulator.tcl + + if {$::osvvm::ToolName eq "GHDL"} { + SetExtendedAnalyzeOptions {-frelaxed -Wno-specs -Wno-elaboration} + SetExtendedSimulateOptions {-frelaxed -Wno-specs -Wno-binding} + + } elseif {$::osvvm::ToolName eq "RivieraPRO"} { + set RivieraSimOptions {-unbounderror} + + } elseif {$::osvvm::ToolName eq "NVC"} { + SetExtendedAnalyzeOptions {--relaxed} + + } elseif {$::osvvm::ToolName eq "Sigasi"} { + + } else { + error [format { + ====================================== + Unknown simulator selected: %s + + Supported simulators: + - GHDL + - RivieraPRO + - NVC + Other tools: + - Sigasi in VSCode + ====================================== + } $::osvvm::ToolName] + } + + proc disabled {file} { + puts "Diabled from analysis: $file" + } + proc duplicate {file} { + puts "Duplicate file: $file" + } + EOF + + tee osvvm_compile.tcl < "$tmp_file" + mv "$tmp_file" "$tcl_file" + done + + artifacts: + paths: + - tb/common/my_project.vhdl + - temp/osvvm_compile.tcl + - temp/select_simulator.tcl + - temp/setup_simulator.tcl + - temp/poc_compile.tcl + - temp/osvvm_sim.tcl + - temp/poc_sim.tcl + expire_in: 1 hour + + +# -------------------- +# ---- Templates ----- +# -------------------- +.collect_com: + artifacts: + paths: + - temp/$SIMULATOR + - lib/osvvm/*_generated.vhd + expire_in: 1 week + when: always + +.collect_sim: + artifacts: + paths: + - temp/$SIMULATOR + reports: + junit: "temp/$SIMULATOR/$RESULT_NAME/*.xml" + expire_in: 1 week + when: always + +.compile: + extends: + - .collect_com + script: exec-$SIMULATOR.sh -n --tcl-file=temp/${TCL_FILE} + +.compileNVC: # intermediate solution until exec-NVC exists + extends: + - .collect_com + script: + - CreateAndChangeDirectory "temp/NVC" "Simulation working directory" + - nvc --do ../${TCL_FILE} + +.simulate: + extends: + - .collect_sim + script: + - exec-$SIMULATOR.sh -n --tcl-file=temp/${TCL_FILE} + - | + if grep "temp/$SIMULATOR/$RESULT_NAME/logs/$RESULT_NAME.log" -e "^#\?\s*Build: $RESULT_NAME PASSED"; then + echo "Build passed!" + else + echo "Error: Simulation for $RESULT_NAME did not pass!" && exit 1 + fi + + allow_failure: true # if case the Riviera license is in use + +.simulateNVC: # intermediate solution until exec-NVC exists + extends: + - .collect_sim + script: + - CreateAndChangeDirectory "temp/NVC" "Simulation working directory" + - nvc --do ../${TCL_FILE} + - | + if grep "$RESULT_NAME/logs/$RESULT_NAME.log" -e "^#\?\s*Build: $RESULT_NAME PASSED"; then + echo "Build passed!" + else + echo "Error: Simulation for $RESULT_NAME did not pass!" && exit 1 + fi + + +# --------------- +# ---- GHDL ----- +# --------------- +.GHDL: + parallel: + matrix: + - GHDL_BACKEND: "llvm" + - GHDL_BACKEND: "mcode" + image: ${CI_REGISTRY}/docker-images/ghdl:${GHDL_BACKEND} + variables: + SIMULATOR: "GHDL" + +GHDL_OSVVM_compile: + stage: build_osvvm + extends: + - .GHDL + - .compile + needs: + job: Scripts + artifacts: true + variables: + TCL_FILE: "osvvm_compile.tcl" + +GHDL_PoC_compile: + stage: build_poc + extends: + - .GHDL + - .compile + needs: + - job: Scripts + artifacts: true + - job: GHDL_OSVVM_compile + artifacts: true + variables: + TCL_FILE: "poc_compile.tcl" + +GHDL_OSVVM_sim: + stage: test + extends: + - .GHDL + - .simulate + needs: + - job: Scripts + artifacts: true + - job: GHDL_OSVVM_compile + artifacts: true + only: + - main + - master + - dev + variables: + TCL_FILE: "osvvm_sim.tcl" + RESULT_NAME: "lib_RunAllTests" + +GHDL_PoC_sim: + stage: test + extends: + - .GHDL + - .simulate + needs: + - job: Scripts + artifacts: true + - job: GHDL_PoC_compile + artifacts: true + variables: + TCL_FILE: "poc_sim.tcl" + RESULT_NAME: "tb_RunAllTests" + +# ------------------ +# ---- Riviera ----- +# ------------------ +.RIVIERA-PRO: + image: ${CI_REGISTRY}/docker-images/rivierapro:latest + variables: + SIMULATOR: "Riviera-PRO" + LM_LICENSE_FILE: "1717@flexlm.plc2.de:1718@flexlm.plc2.de:1719@flexlm.plc2.de" + +RIVIERA_OSVVM_compile: + stage: build_osvvm + extends: + - .RIVIERA-PRO + - .compile + needs: + job: Scripts + artifacts: true + variables: + TCL_FILE: "osvvm_compile.tcl" + +RIVIERA_PoC_compile: + stage: build_poc + extends: + - .RIVIERA-PRO + - .compile + needs: + - job: Scripts + artifacts: true + - job: RIVIERA_OSVVM_compile + artifacts: true + variables: + TCL_FILE: "poc_compile.tcl" + +RIVIERA_OSVVM_sim: + stage: test + extends: + - .RIVIERA-PRO + - .simulate + needs: + - job: Scripts + artifacts: true + - job: RIVIERA_OSVVM_compile + artifacts: true + - job: RIVIERA_PoC_compile # avoid license blocking + artifacts: true + only: + - main + - master + - dev + allow_failure: true + variables: + TCL_FILE: "osvvm_sim.tcl" + RESULT_NAME: "lib_RunAllTests" + +RIVIERA_PoC_sim: + stage: test + extends: + - .RIVIERA-PRO + - .simulate + needs: + - job: Scripts + artifacts: true + - job: RIVIERA_PoC_compile + artifacts: true + - job: RIVIERA_OSVVM_sim # avoid license blocking + optional: true + artifacts: false + variables: + TCL_FILE: "poc_sim.tcl" + RESULT_NAME: "tb_RunAllTests" + + +# -------------- +# ---- NVC ----- +# -------------- +.NVC: + image: ${CI_REGISTRY}/docker-images/nvc:latest + variables: + SIMULATOR: "NVC" + +NVC_OSVVM_compile: + stage: build_osvvm + extends: + - .NVC + - .compileNVC + needs: + job: Scripts + artifacts: true + variables: + TCL_FILE: "osvvm_compile.tcl" + +NVC_PoC_compile: + stage: build_poc + extends: + - .NVC + - .compileNVC + needs: + - job: Scripts + artifacts: true + - job: NVC_OSVVM_compile + artifacts: true + variables: + TCL_FILE: "poc_compile.tcl" +NVC_OSVVM_sim: + stage: test + extends: + - .NVC + - .simulateNVC + needs: + - job: Scripts + artifacts: + - job: NVC_OSVVM_compile + artifacts: true + only: + - main + - master + - dev + variables: + TCL_FILE: "osvvm_sim.tcl" + RESULT_NAME: "lib_RunAllTests" + +NVC_PoC_sim: + stage: test + extends: + - .NVC + - .simulateNVC + needs: + - job: Scripts + artifacts: true + - job: NVC_PoC_compile + artifacts: true + variables: + TCL_FILE: "poc_sim.tcl" + RESULT_NAME: "tb_RunAllTests" + +# ------------------ +# ----- Pages ------ +# ------------------ +.pages: + stage: pages + image: ${CI_REGISTRY}/docker-images/base-image:alpine + variables: + GIT_SUBMODULE_STRATEGY: normal before_script: - - pip3 install -r tools/GitLab-CI/requirements.txt -# - ./tools/GitLab-CI/ghdl.setup.sh - - ./tools/GitLab-CI/poc.setup.sh + - apk add rsync script: -# - ./tools/GitLab-CI/poc.dryrun.sh - - ./tools/GitLab-CI/poc.run.sh "PoC.*" + - mkdir -p public/static + - rsync -av --progress temp/$SIMULATOR_PAGES/ ./public --include="*/" --include="*.html" --include="*.log" --include="*.png" --include="*.css" --exclude="*" + - cp temp/$SIMULATOR_PAGES/reports/OsvvmLogo.png public/static/ + - | + echo "Chosen simulator: $SIMULATOR_PAGES" + echo "Write an 'index.html' ..." + tee public/index.html < + + PoC Simulation Results + + +
+

PoC Simulation Results

+ +

OSVVM Analysis Reports

+ OSVVM-Libaries
+ +

OSVVM Simulation Reports

+ OSVVM-Libaries-tests
+ +

PoC Analysis Reports

+ PoC-analysis
+ +

Simulation Reports

+ PoC-tests
+ + + EOF + - tree public + after_script: + - echo "Pages accessible at ${CI_PAGES_URL}" + artifacts: + paths: + - public + +pagesGHDL: + rules: + - if: > + $SIMULATOR_PAGES == "GHDL" && + $CI_PIPELINE_SOURCE == "push" && + $CI_COMMIT_BRANCH =~ /^(main|master|dev)$/ + needs: + - job: GHDL_OSVVM_sim # main only + artifacts: true + optional: true + - job: GHDL_PoC_sim + artifacts: true + optional: true + extends: + - .pages + +pagesRiviera: + rules: + - if: > + $SIMULATOR_PAGES == "Riviera-PRO" && + $CI_PIPELINE_SOURCE == "push" && + $CI_COMMIT_BRANCH =~ /^(main|master|dev)$/ + needs: + - job: RIVIERA_PoC_sim # inherits artifacts from previous jobs + artifacts: true + optional: true + extends: + - .pages + +pagesNVC: + rules: + - if: > + $SIMULATOR_PAGES == "NVC" && + $CI_PIPELINE_SOURCE == "push" && + $CI_COMMIT_BRANCH =~ /^(main|master|dev)$/ + needs: + - job: NVC_OSVVM_sim # main only + artifacts: true + optional: true + - job: NVC_PoC_sim + artifacts: true + optional: true + extends: + - .pages diff --git a/.sigasi/project.sigasi b/.sigasi/project.sigasi new file mode 100644 index 000000000..da529cc2f --- /dev/null +++ b/.sigasi/project.sigasi @@ -0,0 +1,59 @@ +{ + "name": "PoC", + "targets": { + "Generic": { + "environment": { + "BOARD": "GENERIC", + "VENDOR": "GENERIC", + "OSVVM_TOOL": "Sigasi" + }, + "command": "cd temp && vsim -do ../regression.tcl", + "ignore": [ + "temp", + "docs/_build" + ] + }, + "Altera": { + "environment": { + "BOARD": "S2GXAV", + "VENDOR": "Altera", + "OSVVM_TOOL": "Sigasi" + }, + "command": "cd temp && vsim -do ../regression.tcl", + "ignore": [ + "temp", + "docs/_build" + ], + "dependencies": [ + { + "Quartus": [ + "altera_mf" + ] + } + ] + }, + "Xilinx": { + "environment": { + "BOARD": "KC705", + "VENDOR": "Xilinx", + "OSVVM_TOOL": "Sigasi" + }, + "command": "cd temp && vsim -do ../regression.tcl", + "ignore": [ + "temp", + "docs/_build" + ], + "dependencies": [ + { + "Vivado": { + "version": "Vivado2025.2", + "targets": [ + "unisim", + "unimacro" + ] + } + } + ] + } + } +} diff --git a/AUTHORS.md b/AUTHORS.md index b0d98755f..bc2dc0a9b 100644 --- a/AUTHORS.md +++ b/AUTHORS.md @@ -1,21 +1,24 @@ # List of Authors and Contributors (in alphabetical order) -Contributor | Contact E-Mail -------------------|------------------------------------------------------------ -Eschemann, Guy | guy.eschemann@plc2.de -Genßler, Paul | paul.genssler@tu-dresden.de -Iqbal, Asif | asif.iqbal@plc2.de -Köhler, Steffen | steffen.koehler@tu-dresden.de -Kraft-Kugler, Max | max.kraft-kugler@plc2.de -Lehmann, Patrick | patrick.lehmann@plc2.de; paebbels@gmail.com -Preußer, Thomas B.| thomas.preusser@tu-dresden.de; thomas.preusser@utexas.edu -Reichel, Peter | peter.reichel@eas.iis.fraunhofer.de; peter@peterreichel.info -Schirok, Jan | janschirok@gmx.net -Schreiner, Jonas | jonas.schreiner@plc2.de -Unrein, Stefan | stefan.unrein@plc2.de -Voß, Jens | jens.voss@mailbox.tu-dresden.de -Weiland, Adrian | adrian.weiland@plc2.de -Zabel, Martin | martin.zabel@tu-dresden.de +Contributor | Contact E-Mail +----------------------|------------------------------------------------------------ +Boppudi, Srikanth | srikanth.boppudi@plc2.de +Eschemann, Guy | guy.eschemann@plc2.de +Genßler, Paul | paul.genssler@tu-dresden.de +Iqbal, Asif | asif.iqbal@plc2.de +Köhler, Steffen | steffen.koehler@tu-dresden.de +Kraft-Kugler, Max | max.kraft-kugler@plc2.de +Lehmann, Patrick | patrick.lehmann@plc2.de; paebbels@gmail.com +Mallikarjuna, Nimitha | nimitha.mallikarjuna@plc2.de +Martin, Gustavo | gustavo.martin.alcalde@gmail.com +Preußer, Thomas B. | thomas.preusser@tu-dresden.de; thomas.preusser@utexas.edu +Reichel, Peter | peter.reichel@eas.iis.fraunhofer.de; peter@peterreichel.info +Schirok, Jan | janschirok@gmx.net +Schreiner, Jonas | jonas.schreiner@plc2.de +Unrein, Stefan | stefan.unrein@plc2.de +Voß, Jens | jens.voss@mailbox.tu-dresden.de +Weiland, Adrian | adrian.weiland@plc2.de +Zabel, Martin | martin.zabel@tu-dresden.de # List of Contributing Companies and Institutions (in alphabetical order) diff --git a/docs/IPCores/bus/axi4lite/axi4lite_HighResolutionClock.rst b/docs/IPCores/bus/axi4lite/axi4lite_HighResolutionClock.rst new file mode 100644 index 000000000..ff0b8245a --- /dev/null +++ b/docs/IPCores/bus/axi4lite/axi4lite_HighResolutionClock.rst @@ -0,0 +1,260 @@ +.. _IP/axi4lite_HighResolutionClock: +.. index:: + single: AXI4-Lite; axi4lite_HighResolutionClock + +axi4lite_HighResolutionClock +########################### + +Based on :ref:`IP/axi4lite_Register`, :ref:`IP/clock_highresolution` + +.. todo:: + +.. _IP/axi4lite_HighResolutionClock/goals: + +.. topic:: Design Goals + + * *tbd* + + +.. _IP/axi4lite_HighResolutionClock/features: + +.. topic:: Features + + * *tbd* + + +.. _IP/axi4lite_HighResolutionClock/instantiation: + +Instantiation +************* + +.. _IP/axi4lite_HighResolutionClock/inst/Simple: + +.. grid:: 2 + + .. grid-item:: + :columns: 5 + + .. todo:: needs documentation + + .. grid-item-card:: + :columns: 7 + + .. code-block:: vhdl + + HRC : entity PoC.axi4lite_HighResolutionClock + generic map ( + CLOCK_FREQUENCY => 100 MHz + ) port map ( + Clock => Clock, + Reset => Reset, + Nanoseconds => Nanoseconds, + Datetime => Datetime, + + AXI_clock => AXI_clock, + AXI_reset => AXI_reset, + AXI4Lite_m2s => AXI4Lite_m2s, + AXI4Lite_s2m => AXI4Lite_s2m + ); + +.. _IP/axi4lite_HighResolutionClock/inst/Xilinx: + + +Interface +********* + +.. _IP/axi4lite_HighResolutionClock/generics: + +Generics +======== + +.. _IP/axi4lite_HighResolutionClock/gen/CLOCK_FREQUENCY: + +:generic:`CLOCK_FREQUENCY` +---------------------------- + +:Name: :generic:`CLOCK_FREQUENCY` +:Type: :type:`FREQ` +:Default Value: — — — — +:Description: Frequency of input clock signal used by internal time counters. + + +.. _IP/axi4lite_HighResolutionClock/gen/USE_CDC: + +:generic:`USE_CDC` +--------------------------- + +:Name: :generic:`USE_CDC` +:Type: :type:`boolean` +:Default Value: False +:Description: Enable/disable CDC FIFO. + + +.. _IP/axi4lite_HighResolutionClock/gen/REGISTER_NANOSECONDS: + +:generic:`REGISTER_NANOSECONDS` +-------------------------- + +:Name: :generic:`REGISTER_NANOSECONDS` +:Type: :type:`natural` +:Default Value: 0 +:Description: Amount of pipelining stages. + + +.. _IP/axi4lite_HighResolutionClock/gen/SECOND_RESOLUTION: + +:generic:`SECOND_RESOLUTION` +-------------------------------- + +:Name: :generic:`SECOND_RESOLUTION` +:Type: :type:`T_SECOND_RESOLUTION` +:Default Value: ``NANOSECONDS`` +:Description: Set unit for `Time_sec_res` register (``NANOSECONDS``, ``MICROSECONDS`` or ``MILLISECONDS``). + + +.. _IP/axi4lite_HighResolutionClock/ports: + +Ports +===== + +.. _IP/axi4lite_HighResolutionClock/port/Clock: + +:port:`Clock` +------------- + +:Name: :port:`Clock` +:Type: :type:`std_logic` +:Mode: in +:Default Value: — — — — +:Description: Clock + + +.. _IP/axi4lite_HighResolutionClock/port/Reset: + +:port:`Reset` +------------- + +:Name: :port:`Reset` +:Type: :type:`std_logic` +:Mode: in +:Default Value: — — — — +:Description: synchronous high-active reset + + +.. _IP/axi4lite_HighResolutionClock/port/Nanoseconds: + +:port:`Nanoseconds` +-------------------- + +:Name: :port:`Nanoseconds` +:Type: :type:`unsigned(63 downto 0)` +:Mode: out +:Default Value: — — — — +:Description: Current time in nanoseconds. + + +.. _IP/axi4lite_HighResolutionClock/port/Datetime: + +:port:`Datetime` +-------------------- + +:Name: :port:`Datetime` +:Type: :type:`T_CLOCK_DATETIME` +:Mode: out +:Default Value: — — — — +:Description: Curent time in datetime. + + +.. _IP/axi4lite_HighResolutionClock/port/AXI_clock: + +:port:`AXI_clock` +-------------------- + +:Name: :port:`AXI_clock` +:Type: :type:`std_logic` +:Mode: in +:Default Value: — — — — +:Description: AXI clock. + + +.. _IP/axi4lite_HighResolutionClock/port/AXI_reset: + +:port:`AXI_reset` +-------------------- + +:Name: :port:`AXI_reset` +:Type: :type:`std_logic` +:Mode: in +:Default Value: — — — — +:Description: AXI reset. + + +.. _IP/axi4lite_HighResolutionClock/port/AXI4Lite_m2s: + +:port:`AXI4Lite_m2s` +-------------------- + +:Name: :port:`AXI4Lite_m2s` +:Type: :type:`axi4lite.T_AXI4Lite_Bus_m2s` +:Mode: in +:Default Value: — — — — +:Description: AXI4-Lite manager to subordinate signals. + + +.. _IP/axi4lite_HighResolutionClock/port/AXI4Lite_s2m: + +:port:`AXI4Lite_s2m` +-------------------- + +:Name: :port:`AXI4Lite_s2m` +:Type: :type:`axi4lite.T_AXI4Lite_Bus_s2m` +:Mode: out +:Default Value: — — — — +:Description: AXI4-Lite subordinate to manager signals. + + +.. _IP/axi4lite_HighResolutionClock/configuration: + +Configuration +************* + +.. todo:: tbd + + +.. _IP/axi4lite_HighResolutionClock/RegisterMap: + +Register Map +************ + ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Offset | R/W Config | Name | Description | ++=========+==========================+=================================+====================================================================================================================================================================+ +| 0x0000 | — | Reserved | Dummy register for later use | ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x0004 | ReadWrite | `Config_reg` | Configuration register for correction counter: |br| `Config_reg[31]`: `enable` |br| `Config_reg[30]`: `increment` |br| `Config_reg[29..0]`: `correction_threshold` | ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x0008 | ReadOnly | `Nanoseconds_lower` | Current time in nanoseconds (lower 32-bit) | ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x000C | ReadOnly | `Nanoseconds_upper` | Current time in nanoseconds (upper 32-bit) | ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x0010 | ReadOnly | `Time_HMS` | current time: |br| `Time_HMS(31..17)`: reserved |br| `Time_HMS(16..12)`: `hours` |br| `Time_HMS(11..6)`: `minutes` |br| `Time_HMS(5..0)`: `seconds` | ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x0014 | ReadOnly | `Date_Ymd` | current date: |br| `Date_Ymd(31..22)`: reserved |br| `Date_Ymd(21..9)`: `year` |br| `Date_Ymd(8..5)`: `month` |br| `Date_Ymd(4..0)`: `day` | ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x0018 | ReadOnly | `Time_sec_res` | Counter in ms, us or ns (specified by user with a generic) | ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x001C | — | Reserved | Reserved | ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x0020 | ReadWrite_NotRegistered | `Nanoseconds_to_load_lower` | Nanoseconds to load (lower 32-bit) | ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x0024 | ReadWrite_NotRegistered | `Nanoseconds_to_load_uppper` | Nanoseconds to load (upper 32-bit) | ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x0028 | ReadWrite_NotRegistered | `Datetime_to_load_HMS` | Time to load (as described for `Time_HMS`) | ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x002C | ReadWrite_NotRegistered | `Datetime_to_load_Ymd` | Date to load (as described for `Date_Ymd`) | ++---------+--------------------------+---------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Related Files +************* + +*None* diff --git a/docs/IPCores/bus/axi4lite/axi4lite_Ocram_Adapter.rst b/docs/IPCores/bus/axi4lite/axi4lite_Ocram_Adapter.rst new file mode 100644 index 000000000..c13f85306 --- /dev/null +++ b/docs/IPCores/bus/axi4lite/axi4lite_Ocram_Adapter.rst @@ -0,0 +1,220 @@ +.. _IP/AXI4Lite_Ocram_Adapter: +.. index:: + single: AXI4-Lite; AXI4Lite_Ocram_Adapter + +AXI4Lite_Ocram_Adapter +########################### + +.. todo:: + +.. _IP/AXI4Lite_Ocram_Adapter/goals: + +.. topic:: Design Goals + + * *tbd* + + +.. _IP/AXI4Lite_Ocram_Adapter/features: + +.. topic:: Features + + * *tbd* + + +.. _IP/AXI4Lite_Ocram_Adapter/instantiation: + +Instantiation +************* + +.. _IP/AXI4Lite_Ocram_Adapter/inst/Simple: + +.. grid:: 2 + + .. grid-item:: + :columns: 5 + + .. todo:: needs documentation + + .. grid-item-card:: + :columns: 7 + + .. code-block:: vhdl + + Ocram_Adapter : entity PoC.AXI4Lite_Ocram_Adapter + generic map ( + OCRAM_ADDRESS_BITS => 10, + OCRAM_DATA_BITS => 32 + ) port map ( + Clock => Clock, + Reset => Reset, + + AXI4Lite_m2s => AXI4Lite_m2s, + AXI4Lite_s2m => AXI4Lite_s2m, + + Write_En => Write_En, + Address => Address, + Data_In => Data_In, + Data_Out => Data_Out + ); + +.. _IP/AXI4Lite_Ocram_Adapter/inst/Xilinx: + + +Interface +********* + +.. _IP/AXI4Lite_Ocram_Adapter/generics: + +Generics +======== + +.. _IP/AXI4Lite_Ocram_Adapter/gen/OCRAM_ADDRESS_BITS: + +:generic:`OCRAM_ADDRESS_BITS` +---------------------------- + +:Name: :generic:`OCRAM_ADDRESS_BITS` +:Type: :type:`positive` +:Default Value: — — — — +:Description: *tbd* + + +.. _IP/AXI4Lite_Ocram_Adapter/gen/OCRAM_DATA_BITS: + +:generic:`OCRAM_DATA_BITS` +--------------------------- + +:Name: :generic:`OCRAM_DATA_BITS` +:Type: :type:`positive` +:Default Value: — — — — +:Description: *tbd* + + +.. _IP/AXI4Lite_Ocram_Adapter/gen/PREFFERED_READ_ACCESS: + +:generic:`PREFFERED_READ_ACCESS` +-------------------------- + +:Name: :generic:`PREFFERED_READ_ACCESS` +:Type: :type:`boolean` +:Default Value: TRUE +:Description: *tbd* + + +.. _IP/AXI4Lite_Ocram_Adapter/ports: + +Ports +===== + +.. _IP/AXI4Lite_Ocram_Adapter/port/Clock: + +:port:`Clock` +------------- + +:Name: :port:`Clock` +:Type: :type:`std_logic` +:Mode: in +:Default Value: — — — — +:Description: Clock + + +.. _IP/AXI4Lite_Ocram_Adapter/port/Reset: + +:port:`Reset` +------------- + +:Name: :port:``Reset` +:Type: :type:`std_logic` +:Mode: in +:Default Value: — — — — +:Description: synchronous high-active reset + + +.. _IP/AXI4Lite_Ocram_Adapter/port/AXI4Lite_M2S: + +:port:`AXI4Lite_M2S` +-------------------- + +:Name: :port:`AXI4Lite_M2S` +:Type: :type:`axi4lite.T_AXI4Lite_Bus_m2s` +:Mode: in +:Default Value: — — — — +:Description: AXI4-Lite manager to subordinate signals. + + +.. _IP/AXI4Lite_Ocram_Adapter/port/AXI4Lite_s2m: + +:port:`AXI4Lite_s2m` +-------------------- + +:Name: :port:`AXI4Lite_s2m` +:Type: :type:`axi4lite.T_AXI4Lite_Bus_s2m` +:Mode: out +:Default Value: — — — — +:Description: AXI4-Lite subordinate to manager signals. + + +.. _IP/AXI4Lite_Ocram_Adapter/port/Write_En: + +:port:`Write_En` +-------------------- + +:Name: :port:`Write_En` +:Type: :type:`std_logic` +:Mode: out +:Default Value: — — — — +:Description: Write enable. + + +.. _IP/AXI4Lite_Ocram_Adapter/port/Address: + +:port:`Address` +-------------------- + +:Name: :port:`Address` +:Type: :type:`unsigned(OCRAM_ADDRESS_BITS-1 downto 0)` +:Mode: out +:Default Value: — — — — +:Description: *tbd* + + +.. _IP/AXI4Lite_Ocram_Adapter/port/Data_In: + +:port:`Data_In` +-------------------- + +:Name: :port:`Data_In` +:Type: :type:`unsigned(OCRAM_ADDRESS_BITS-1 downto 0)` +:Mode: in +:Default Value: — — — — +:Description: *tbd* + + +.. _IP/AXI4Lite_Ocram_Adapter/port/Data_Out: + +:port:`Data_Out` +-------------------- + +:Name: :port:`Data_Out` +:Type: :type:`unsigned(OCRAM_ADDRESS_BITS-1 downto 0)` +:Mode: out +:Default Value: — — — — +:Description: *tbd* + + +.. _IP/AXI4Lite_Ocram_Adapter/configuration: + +Configuration +************* + +.. _IP/AXI4Lite_Ocram_Adapter/config/User: + +User defined Word +================= + +.. todo:: tbd + +Related Files +************* + +*None* diff --git a/docs/IPCores/bus/axi4lite/axi4lite_UART.rst b/docs/IPCores/bus/axi4lite/axi4lite_UART.rst new file mode 100644 index 000000000..719c19b24 --- /dev/null +++ b/docs/IPCores/bus/axi4lite/axi4lite_UART.rst @@ -0,0 +1,341 @@ +.. _IP/AXI4Lite_UART: +.. index:: + single: AXI4-Lite; AXI4Lite_UART + +AXI4Lite_UART +########################### + +Based on :ref:`IP/axi4lite_Register`, :ref:`IP/uart_fifo` + +.. todo:: + +.. _IP/AXI4Lite_UART/goals: + +.. topic:: Design Goals + + * *tbd* + + +.. _IP/AXI4Lite_UART/features: + +.. topic:: Features + + * *tbd* + + +.. _IP/AXI4Lite_UART/instantiation: + +Instantiation +************* + +.. _IP/AXI4Lite_UART/inst/Simple: + +.. grid:: 2 + + .. grid-item:: + :columns: 5 + + .. todo:: needs documentation + + .. grid-item-card:: + :columns: 7 + + .. code-block:: vhdl + + UART : entity PoC.AXI4Lite_UART + generic map ( + CLOCK_FREQ => 100 MHz, + BAUDRATE => 115.200 kBd + ) + port map ( + Clock => Clock, + Reset => Reset, + + AXI4Lite_m2s => AXI4Lite_m2s, + AXI4Lite_s2m => AXI4Lite_s2m, + Config_irq => Config_irq, + + UART_TX => UART_TX, + UART_RX => UART_RX, + UART_RTS => UART_RTS, + UART_CTS => UART_CTS + ); + +.. _IP/AXI4Lite_UART/inst/Xilinx: + + +Interface +********* + +.. _IP/AXI4Lite_UART/generics: + +Generics +======== + +.. _IP/AXI4Lite_UART/gen/CLOCK_FREQ: + +:generic:`CLOCK_FREQ` +---------------------------- + +:Name: :generic:`CLOCK_FREQ` +:Type: :type:`FREQ` +:Default Value: — — — — +:Description: Frequency of input clock. + + +.. _IP/AXI4Lite_UART/gen/BAUDRATE: + +:generic:`BAUDRATE` +---------------------------- + +:Name: :generic:`BAUDRATE` +:Type: :type:`BAUD` +:Default Value: 115.200 kBd +:Description: *tbd* + +.. _IP/AXI4Lite_UART/gen/PARITY: + +:generic:`PARITY` +--------------------------- + +:Name: :generic:`PARITY` +:Type: :type:`T_UART_PARITY_MODE` +:Default Value: ``PARITY_NONE`` +:Description: ``PARITY_EVEN``, ``PARITY_ODD``, ``PARITY_NONE`` + + +.. _IP/AXI4Lite_UART/gen/PARITY_ERROR_HANDLING: + +:generic:`PARITY_ERROR_HANDLING` +-------------------------- + +:Name: :generic:`PARITY_ERROR_HANDLING` +:Type: :type:`T_UART_PARITY_ERROR_HANDLING` +:Default Value: ``PASSTHROUGH_ERROR_BYTE`` +:Description: ``PASSTHROUGH_ERROR_BYTE``, ``REPLACE_ERROR_BYTE``, ``DROP_ERROR_BYTE`` + + +.. _IP/AXI4Lite_UART/gen/PARITY_ERROR_IDENTIFIER: + +:generic:`PARITY_ERROR_IDENTIFIER` +-------------------------------- + +:Name: :generic:`PARITY_ERROR_IDENTIFIER` +:Type: :type:`std_logic_vector(7 downto 0)` +:Default Value: ``x"15"`` +:Description: *tbd* + + +.. _IP/AXI4Lite_UART/gen/ADD_INPUT_SYNCHRONIZERS: + +:generic:`ADD_INPUT_SYNCHRONIZERS` +-------------------------------- + +:Name: :generic:`ADD_INPUT_SYNCHRONIZERS` +:Type: :type:`boolean` +:Default Value: ``TRUE`` +:Description: *tbd* + + +.. _IP/AXI4Lite_UART/gen/TX_FIFO_DEPTH: + +:generic:`TX_FIFO_DEPTH` +-------------------------------- + +:Name: :generic:`TX_FIFO_DEPTH` +:Type: :type:`positive` +:Default Value: 16 +:Description: *tbd** + + +.. _IP/AXI4Lite_UART/gen/RX_FIFO_DEPTH: + +:generic:`RX_FIFO_DEPTH` +-------------------------------- + +:Name: :generic:`RX_FIFO_DEPTH` +:Type: :type:`positive` +:Default Value: 16 +:Description: *tbd* + + +.. _IP/AXI4Lite_UART/gen/FLOWCONTROL: + +:generic:`FLOWCONTROL` +-------------------------------- + +:Name: :generic:`FLOWCONTROL` +:Type: :type:`T_IO_UART_FLOWCONTROL_KIND` +:Default Value: ``UART_FLOWCONTROL_NONE`` +:Description: *tbd* + + +.. _IP/AXI4Lite_UART/gen/SWFC_XON_CHAR: + +:generic:`SWFC_XON_CHAR` +-------------------------------- + +:Name: :generic:`SWFC_XON_CHAR` +:Type: :type:`std_logic_vector(7 downto 0)` +:Default Value: ``x"11"`` +:Description: *tbd* + + +.. _IP/AXI4Lite_UART/gen/SWFC_XOFF_CHAR: + +:generic:`SWFC_XOFF_CHAR` +-------------------------------- + +:Name: :generic:`SWFC_XOFF_CHAR` +:Type: :type:`std_logic_vector(7 downto 0)` +:Default Value: ``x"13"`` +:Description: *tbd* + + +.. _IP/AXI4Lite_UART/ports: + +Ports +===== + +.. _IP/AXI4Lite_UART/port/Clock: + +:port:`Clock` +------------- + +:Name: :port:`Clock` +:Type: :type:`std_logic` +:Mode: in +:Default Value: — — — — +:Description: Clock + + +.. _IP/AXI4Lite_UART/port/Reset: + +:port:`Reset` +------------- + +:Name: :port:`Reset` +:Type: :type:`std_logic` +:Mode: in +:Default Value: — — — — +:Description: synchronous high-active reset + + +.. _IP/AXI4Lite_UART/port/AXI4Lite_m2s: + +:port:`AXI4Lite_m2s` +-------------------- + +:Name: :port:`AXI4Lite_m2s` +:Type: :type:`axi4lite.T_AXI4Lite_Bus_m2s` +:Mode: in +:Default Value: — — — — +:Description: AXI4-Lite manager to subordinate signals. + + +.. _IP/AXI4Lite_UART/port/AXI4Lite_s2m: + +:port:`AXI4Lite_s2m` +-------------------- + +:Name: :port:`AXI4Lite_s2m` +:Type: :type:`axi4lite.T_AXI4Lite_Bus_s2m` +:Mode: out +:Default Value: — — — — +:Description: AXI4-Lite subordinate to manager signals. + + +.. _IP/AXI4Lite_UART/port/Config_irq: + +:port:`Config_irq` +-------------------- + +:Name: :port:`Config_irq` +:Type: :type:`std_logic` +:Mode: out +:Default Value: — — — — +:Description: AXI4-Lite subordinate to manager signals. + + +.. _IP/AXI4Lite_UART/port/UART_TX: + +:port:`UART_TX` +-------------------- + +:Name: :port:`UART_TX` +:Type: :type:`std_logic` +:Mode: out +:Default Value: — — — — +:Description: *tbd*. + + +.. _IP/AXI4Lite_UART/port/UART_RX: + +:port:`UART_RX` +-------------------- + +:Name: :port:`UART_RX` +:Type: :type:`std_logic` +:Mode: in +:Default Value: — — — — +:Description: *tbd*. + + +.. _IP/AXI4Lite_UART/port/UART_RTS: + +:port:`UART_RTS` +-------------------- + +:Name: :port:`UART_RTS` +:Type: :type:`std_logic` +:Mode: out +:Default Value: — — — — +:Description: *tbd*. + + +.. _IP/AXI4Lite_UART/port/UART_CTS: + +:port:`UART_CTS` +-------------------- + +:Name: :port:`UART_CTS` +:Type: :type:`std_logic` +:Mode: in +:Default Value: — — — — +:Description: *tbd*. + + +.. _IP/AXI4Lite_UART/configuration: + +Configuration +************* + +.. _IP/AXI4Lite_UART/config/User: + +User defined Word +================= + +.. todo:: tbd + + +.. _IP/AXI4Lite_UART/RegisterMap: + +Register Map +************ + ++---------+--------------------------+---------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Offset | R/W Config | Default | Name | Description | ++=========+==========================+=====================+===============================+====================================================================================================================================================================+ +| 0x0000 | ReadOnly_NotRegistered | ``x"00000000"`` | Rx | Read from receive buffer. | ++---------+--------------------------+---------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x0004 | ReadWrite_NotRegistered | ``x"00000000"`` | Tx | Write into transmit buffer. | ++---------+--------------------------+---------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x0008 | ReadOnly | ``x"00000000"`` | Status | Receive status. | ++---------+--------------------------+---------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| 0x000C | ReadWrite | ``x"00000000"`` | Control | Command byte | ++---------+--------------------------+---------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Related Files +************* + +*None* diff --git a/docs/IPCores/bus/axi4lite/index.rst b/docs/IPCores/bus/axi4lite/index.rst index d68f48462..86353b0a7 100644 --- a/docs/IPCores/bus/axi4lite/index.rst +++ b/docs/IPCores/bus/axi4lite/index.rst @@ -16,6 +16,9 @@ PoC.bus.axi4lite * :ref:`IP/axi4lite_FIFO_cdc` * :ref:`IP/axi4lite_Register` * :ref:`IP/axi4lite_GitVersionRegister` + * :ref:`IP/axi4lite_HighResolutionClock` + * :ref:`IP/axi4lite_Ocram_Adapter` + * :ref:`IP/axi4lite_UART` .. toctree:: :hidden: @@ -26,3 +29,6 @@ PoC.bus.axi4lite FIFO_cdc Register GitVersionRegister + HighResolutionClock + Ocram_Adapter + UART diff --git a/docs/_extensions/DocumentMember.py b/docs/_extensions/DocumentMember.py index 58f8a2bb1..e5b3e0572 100644 --- a/docs/_extensions/DocumentMember.py +++ b/docs/_extensions/DocumentMember.py @@ -1,19 +1,11 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# # ============================================================================== # Authors: Patrick Lehmann # # Python Module: # -# Description: -# ------------------------------------ -# - TODO -# # License: # ============================================================================== -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -27,7 +19,7 @@ # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================== -# + from lib.SphinxExtensions import DocumentMemberAttribute diff --git a/docs/make.bat b/docs/make.bat index 2525c9600..a95cb8463 100644 --- a/docs/make.bat +++ b/docs/make.bat @@ -5,11 +5,9 @@ pushd %~dp0 REM Command file for Sphinx documentation if "%SPHINXBUILD%" == "" ( - set SPHINXBUILD=py -3.13 -m sphinx.cmd.build + set SPHINXBUILD=py -3.14 -m sphinx.cmd.build ) -set SOURCEDIR=. set BUILDDIR=_build -set SPHINXOPTS=-v if "%1" == "" goto help @@ -26,7 +24,8 @@ if errorlevel 9009 ( exit /b 1 ) -%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% +REM --fresh-env --write-all +%SPHINXBUILD% --verbose --builder %1 -d %BUILDDIR%/doctrees --jobs 4 -w %BUILDDIR%/%1.log . %BUILDDIR%/%1 goto end :help diff --git a/docs/requirements.txt b/docs/requirements.txt index eb7e7d547..ce5721df7 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,25 +1,25 @@ -r ../requirements.txt colorama >= 0.4.6 -ruamel.yaml ~= 0.18 -setuptools ~= 75.8 +ruamel.yaml ~= 0.19 +setuptools ~= 80.0 # Enforce latest version on ReadTheDocs -sphinx ~= 8.2 -docutils ~= 0.21 +sphinx ~= 9.1 +# docutils ~= 0.21 docutils_stubs ~= 0.0.22 # ReadTheDocs Theme sphinx_rtd_theme ~= 3.0 # Sphinx Extenstions -sphinxcontrib-mermaid ~= 1.0 -sphinxcontrib-autoprogram ~= 0.1 +sphinxcontrib-mermaid ~= 2.0 +sphinxcontrib-autoprogram ~= 0.1.0 autoapi >= 2.0.1 -sphinx_design ~= 0.6.1 +sphinx_design ~= 0.7.0 sphinx-copybutton >= 0.5.2 -sphinx_autodoc_typehints ~= 3.1 -sphinx_reports ~= 0.9 +sphinx_autodoc_typehints ~= 3.6 +sphinx_reports ~= 0.10.0 #pyedaa.osvvm ~= 0.5 sphinxcontrib-wavedrom ~= 3.0 diff --git a/lib/OSVVM-AXI4 b/lib/OSVVM-AXI4 index cfd48398e..0c00f2a26 160000 --- a/lib/OSVVM-AXI4 +++ b/lib/OSVVM-AXI4 @@ -1 +1 @@ -Subproject commit cfd48398e0abb8d30b242f619a659f006d7c0ea9 +Subproject commit 0c00f2a26b6f03488d2f1e29196cdaad6d2746bb diff --git a/lib/OSVVM-Common b/lib/OSVVM-Common index 51eea84b1..cb4fc80da 160000 --- a/lib/OSVVM-Common +++ b/lib/OSVVM-Common @@ -1 +1 @@ -Subproject commit 51eea84b179b478360329612429025be6152809c +Subproject commit cb4fc80da5da1fb3a6761c58df2812173828c3c2 diff --git a/lib/OSVVM-Scripts b/lib/OSVVM-Scripts index 6aada0839..d9cb9aebf 160000 --- a/lib/OSVVM-Scripts +++ b/lib/OSVVM-Scripts @@ -1 +1 @@ -Subproject commit 6aada0839d3d305dfc3bb8750a307b102c060bbc +Subproject commit d9cb9aebf52b105900ca958f4d1ba53002f43e5b diff --git a/lib/OSVVM-UART b/lib/OSVVM-UART index f9bd87ae7..acc635a9f 160000 --- a/lib/OSVVM-UART +++ b/lib/OSVVM-UART @@ -1 +1 @@ -Subproject commit f9bd87ae7e1a5a48c12da21a88b7a3954b019aab +Subproject commit acc635a9f8dbc9ac8fb65b38d87cfb5d68d16e91 diff --git a/lib/OsvvmLibraries.pro b/lib/OsvvmLibraries.pro index 18398aaf7..e74e20578 100644 --- a/lib/OsvvmLibraries.pro +++ b/lib/OsvvmLibraries.pro @@ -38,11 +38,28 @@ # limitations under the License. # include ./osvvm/osvvm.pro -include ./OSVVM-Common/Common.pro +include ./OSVVM-Common if {[DirectoryExists OSVVM-UART]} { - include ./OSVVM-UART/UART.pro + include ./OSVVM-UART } if {[DirectoryExists OSVVM-AXI4]} { - include ./OSVVM-AXI4/AXI4.pro + include ./OSVVM-AXI4 +} +if {[DirectoryExists DpRam]} { + include ./DpRam/DpRam.pro +} +if {[DirectoryExists Ethernet]} { + include ./Ethernet/Ethernet.pro +} +if {[DirectoryExists VideoBus_LouisAdriaens]} { + include ./VideoBus_LouisAdriaens/VideoBus.pro +} +if {[DirectoryExists SPI_GuyEschemann]} { + include ./SPI_GuyEschemann/spi.pro +} +if {($::osvvm::ToolNameVersion ne "XSIM-2023.2") && ($::osvvm::ToolVendor ne "Cadence")} { + if {[DirectoryExists CoSim]} { + include ./CoSim/CoSim.pro + } } diff --git a/lib/osvvm b/lib/osvvm index 1f99ff5ab..fadaece0b 160000 --- a/lib/osvvm +++ b/lib/osvvm @@ -1 +1 @@ -Subproject commit 1f99ff5ab08760a6a375953ef54f7688348f544b +Subproject commit fadaece0b318dfa07451ce719a1f6cd42f4c2534 diff --git a/poc.ps1 b/poc.ps1 index ef60b692c..0fc5114d3 100644 --- a/poc.ps1 +++ b/poc.ps1 @@ -15,7 +15,7 @@ # # License: # ============================================================================== -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair of VLSI-Design, Diagnostics and Architecture # diff --git a/poc.sh b/poc.sh index af4b3b859..f89b50b7f 100755 --- a/poc.sh +++ b/poc.sh @@ -19,7 +19,7 @@ # # License: # ============================================================================== -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair of VLSI-Design, Diagnostics and Architecture # diff --git a/regression.tcl b/regression.tcl index 88e767cd5..87202d4fb 100644 --- a/regression.tcl +++ b/regression.tcl @@ -1,10 +1,13 @@ # ============================================================================= # Authors: -# Jonas Schreiner, Stefan Unrein +# Jonas Schreiner +# Stefan Unrein +# Patrick Lehmann +# Adrian Weiland # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -20,35 +23,71 @@ # ============================================================================= namespace eval ::poc { - variable myConfigFile "../tb/common/my_config_GENERIC.vhdl" + proc getEnv {var {default ""}} { + if {[info exists ::env($var)]} { + return $::env($var) + } + return $default + } + + variable vendorName [getEnv VENDOR "GENERIC"] + variable boardName [getEnv BOARD "GENERIC"] + + variable myConfigFile "../tb/common/my_config_$boardName.vhdl" variable myProjectFile "../tb/common/my_project.vhdl" - variable vendor "GENERIC"; # GENERIC for vendor-less build; Xilinx, Altera,... for vendor specific build + + variable vendor $vendorName; # GENERIC for vendor-less build; Xilinx, Altera,... for vendor specific build } -source ../lib/OSVVM-Scripts/StartUp.tcl -# source ../lib/OSVVM-Scripts/StartNVC.tcl +if {[info exists nvc_dataDir]} { + source ../lib/OSVVM-Scripts/StartNVC.tcl +} else { + source ../lib/OSVVM-Scripts/StartUp.tcl +} build ../lib/OsvvmLibraries.pro if {$::osvvm::ToolName eq "GHDL"} { - SetExtendedAnalyzeOptions {-frelaxed -Wno-specs -Wno-elaboration} - SetExtendedSimulateOptions {-frelaxed -Wno-specs -Wno-binding} -} + SetExtendedAnalyzeOptions {-frelaxed -Wno-specs -Wno-elaboration} + SetExtendedSimulateOptions {-frelaxed -Wno-specs -Wno-binding} -if {$::osvvm::ToolName eq "RiveraPRO"} { - SetExtendedSimulationOptions {-unbounderror} -} +} elseif {$::osvvm::ToolName eq "RivieraPRO"} { + set RivieraSimOptions {-unbounderror} -if {$::osvvm::ToolName eq "NVC"} { - SetExtendedAnalyzeOptions {--relaxed} +} elseif {$::osvvm::ToolName eq "NVC"} { + SetExtendedAnalyzeOptions {--relaxed} + +} elseif {$::osvvm::ToolName eq "Sigasi"} { + +} else { + error [format { +====================================== +Unknown simulator selected: %s + +Supported simulators: + - GHDL + - RivieraPRO + - NVC +Other tools: + - Sigasi in VSCode +====================================== +} $::osvvm::ToolName] } -#set ::osvvm::AnalyzeErrorStopCount 1 -#set ::osvvm::SimulateErrorStopCount 1 +set ::osvvm::AnalyzeErrorStopCount 1 +set ::osvvm::SimulateErrorStopCount 1 +set ::osvvm::TclDebug 1 +set ::osvvm::FailOnBuildErrors 1 +proc disabled {args} { + puts "Disabled from analysis: $args" +} +proc duplicate {args} { + puts "Duplicate file: $args" +} build ../src/PoC.pro -#SetSaveWaves +# SetSaveWaves build ../tb/RunAllTests.pro diff --git a/src/PoC.pro b/src/PoC.pro index 07e8a62b2..2c4d834da 100644 --- a/src/PoC.pro +++ b/src/PoC.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -25,7 +25,11 @@ analyze $::poc::myConfigFile analyze $::poc::myProjectFile include ./common/common.pro +analyze ./xil/./xil.pkg.vhdl +disabled ./misc/misc_ClockBuffer.vhdl include ./sync/sync.pro +include ./arith/arith.pro +include ./misc/misc.pro analyze ./bus/axi4/AXI4_Common.pkg.vhdl analyze ./bus/axi4/AXI4_Full.pkg.vhdl @@ -33,12 +37,12 @@ analyze ./bus/axi4/AXI4Stream/AXI4Stream.pkg.vhdl analyze ./bus/axi4/AXI4Lite/AXI4Lite.pkg.vhdl analyze ./bus/axi4/axi4.pkg.vhdl -include ./arith/arith.pro include ./mem/mem.pro -include ./misc/misc.pro include ./fifo/fifo.pro include ./xil/xil.pro + include ./dstruct/dstruct.pro +include ./io/io.pro include ./bus/bus.pro include ./comm/comm.pro include ./sort/sort.pro @@ -46,7 +50,6 @@ include ./cache/cache.pro analyze ./list/list_expire.vhdl -include ./io/io.pro include ./net/net.pro include ./sim/sim.pro diff --git a/src/arith/arith.pkg.vhdl b/src/arith/arith.pkg.vhdl index 58f18b835..cc3f9a8ed 100644 --- a/src/arith/arith.pkg.vhdl +++ b/src/arith/arith.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel @@ -15,7 +12,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/arith/arith.pro b/src/arith/arith.pro index a5b576b15..aa33056b2 100644 --- a/src/arith/arith.pro +++ b/src/arith/arith.pro @@ -1,10 +1,11 @@ # ============================================================================= # Authors: -# Adrian Weiland, Stefan Unrein +# Adrian Weiland +# Stefan Unrein # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -33,10 +34,11 @@ if { $::poc::vendor eq "Xilinx" } { puts "No Altera files for arith." } elseif { $::poc::vendor ne "GENERIC" } { - puts "Unknow vendor '$::poc::vendor' in arith!" + puts "Unknown vendor '$::poc::vendor'!" exit 1 } +disabled ./arith_accumulator.vhdl analyze ./arith_addw.vhdl analyze ./arith_carrychain_inc.vhdl analyze ./arith_cca.vhdl diff --git a/src/arith/arith_addw.vhdl b/src/arith/arith_addw.vhdl index 7b9a0f34a..f134dc769 100644 --- a/src/arith/arith_addw.vhdl +++ b/src/arith/arith_addw.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- diff --git a/src/arith/arith_carrychain_inc.vhdl b/src/arith/arith_carrychain_inc.vhdl index 3000ad509..8a6f66655 100644 --- a/src/arith/arith_carrychain_inc.vhdl +++ b/src/arith/arith_carrychain_inc.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/arith/arith_convert_bin2bcd.vhdl b/src/arith/arith_convert_bin2bcd.vhdl index a4372e215..7f11c1f0e 100644 --- a/src/arith/arith_convert_bin2bcd.vhdl +++ b/src/arith/arith_convert_bin2bcd.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/arith/arith_counter_bcd.vhdl b/src/arith/arith_counter_bcd.vhdl index 55f245632..66babf22a 100644 --- a/src/arith/arith_counter_bcd.vhdl +++ b/src/arith/arith_counter_bcd.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Thomas B. Preusser diff --git a/src/arith/arith_counter_free.vhdl b/src/arith/arith_counter_free.vhdl index 7eab4c36f..beed1421b 100644 --- a/src/arith/arith_counter_free.vhdl +++ b/src/arith/arith_counter_free.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- diff --git a/src/arith/arith_counter_gray.vhdl b/src/arith/arith_counter_gray.vhdl index 2fea7c5ae..1226cd2c0 100644 --- a/src/arith/arith_counter_gray.vhdl +++ b/src/arith/arith_counter_gray.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel diff --git a/src/arith/arith_counter_ring.vhdl b/src/arith/arith_counter_ring.vhdl index 267c9e057..4a3fdc597 100644 --- a/src/arith/arith_counter_ring.vhdl +++ b/src/arith/arith_counter_ring.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/arith/arith_div.vhdl b/src/arith/arith_div.vhdl index c039acb2a..0c61f9612 100644 --- a/src/arith/arith_div.vhdl +++ b/src/arith/arith_div.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- diff --git a/src/arith/arith_firstone.vhdl b/src/arith/arith_firstone.vhdl index 044d11aa9..383552005 100644 --- a/src/arith/arith_firstone.vhdl +++ b/src/arith/arith_firstone.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- diff --git a/src/arith/arith_prng.vhdl b/src/arith/arith_prng.vhdl index fb06f84b6..a69decd73 100644 --- a/src/arith/arith_prng.vhdl +++ b/src/arith/arith_prng.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann @@ -20,7 +17,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/arith/arith_scaler.vhdl b/src/arith/arith_scaler.vhdl index da4db916d..c9237779c 100644 --- a/src/arith/arith_scaler.vhdl +++ b/src/arith/arith_scaler.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- @@ -129,7 +126,7 @@ begin -- Selection of Multiplier genMultiMul: if MULS'length > 1 generate - signal MS : unsigned(msel'range) := (others => '-'); + signal MS : unsigned(msel'range) := (others => '0'); begin process(clk) begin @@ -157,7 +154,7 @@ begin begin if rising_edge(clk) then if rst = '1' then - DS <= (others => '-'); + DS <= (others => '0'); elsif start = '1' then DS <= unsigned(dsel); end if; diff --git a/src/arith/arith_shifter_barrel.vhdl b/src/arith/arith_shifter_barrel.vhdl index 61f7e444d..346d998bb 100644 --- a/src/arith/arith_shifter_barrel.vhdl +++ b/src/arith/arith_shifter_barrel.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/arith/arith_trng.vhdl b/src/arith/arith_trng.vhdl index db3cdef9d..7e38338ef 100644 --- a/src/arith/arith_trng.vhdl +++ b/src/arith/arith_trng.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- @@ -43,7 +40,9 @@ -- ============================================================================= library IEEE; -use IEEE.std_logic_1164.all; +use IEEE.std_logic_1164.all; + +use work.utils.all; entity arith_trng is generic ( @@ -55,10 +54,6 @@ entity arith_trng is ); end entity; - -use work.utils.all; -use work.sync.sync_Bits; - architecture rtl of arith_trng is signal osc : std_logic_vector(BITS-1 downto 0) := (others => '-'); -- Oscillators attribute KEEP : boolean; @@ -70,7 +65,7 @@ begin osc(i) <= ite(i<3, '1', '0') xor osc((i-1)mod BITS) xor osc(i) xor osc((i+1)mod BITS); end generate; - sync_i : sync_Bits + sync_i : entity work.sync_Bits generic map ( BITS => BITS ) diff --git a/src/arith/xilinx/arith_addw_xilinx.vhdl b/src/arith/xilinx/arith_addw_xilinx.vhdl index 3c06e8778..15b56b626 100644 --- a/src/arith/xilinx/arith_addw_xilinx.vhdl +++ b/src/arith/xilinx/arith_addw_xilinx.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- diff --git a/src/arith/xilinx/arith_carrychain_inc_xilinx.vhdl b/src/arith/xilinx/arith_carrychain_inc_xilinx.vhdl index f0c674366..537e4942d 100644 --- a/src/arith/xilinx/arith_carrychain_inc_xilinx.vhdl +++ b/src/arith/xilinx/arith_carrychain_inc_xilinx.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite.pkg.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite.pkg.vhdl index 44aba0b6c..ec1c81c78 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite.pkg.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite.pkg.vhdl @@ -1,9 +1,7 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Patrick Lehmann --- Stefan Unrein +-- Authors: +-- Patrick Lehmann +-- Stefan Unrein -- -- Package: Generic AMBA AXI4-Lite bus description. -- @@ -35,7 +33,7 @@ -- -- License: -- ============================================================================= --- Copyright 2017-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO.vhdl index 52f829494..d88d3fd91 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO.vhdl @@ -1,10 +1,8 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Stefan Unrein +-- Authors: +-- Stefan Unrein -- --- Entity: AXI4Lite_FIFO +-- Entity: AXI4Lite_FIFO -- -- Description: -- ------------------------------------- @@ -17,7 +15,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO_cdc.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO_cdc.vhdl index 9c710f750..3e51449e4 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO_cdc.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO_cdc.vhdl @@ -1,10 +1,8 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Stefan Unrein +-- Authors: +-- Stefan Unrein -- --- Entity: AXI4Lite_FIFO_cdc +-- Entity: AXI4Lite_FIFO_cdc -- -- Description: -- ------------------------------------- @@ -15,7 +13,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl index 999e932d8..1636f23ec 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Stefan Unrein -- @@ -18,7 +15,7 @@ -- -- License: -- ============================================================================= --- Copyright 2024-2025 The PoC-Library Authors +-- Copyright 2026-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock.vhdl new file mode 100644 index 000000000..420aa4f68 --- /dev/null +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock.vhdl @@ -0,0 +1,242 @@ +-- ============================================================================= +-- Authors: +-- Stefan Unrein +-- Adrian Weiland +-- +-- Entity: +-- +-- Description: +-- ------------------------------------- +-- A BCD counting clock with nanoseconds resolution accessible via AXI4-Lite. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.physical.all; +use work.vectors.all; +use work.axi4lite.all; +use work.clock.all; + + +entity AXI4Lite_HighResolutionClock is + generic ( + CLOCK_FREQUENCY : FREQ; -- Frequency of input clock + USE_CDC : boolean := False; -- enable/disable CDC FIFO + REGISTER_NANOSECONDS : natural := 0 ; -- NUM pipelining stages + SECOND_RESOLUTION : T_SECOND_RESOLUTION := NANOSECONDS -- Time_sec_res in NANOSECONDS, MICROSECONDS or MILLISECONDS + ); + port ( + Clock : in std_logic; + Reset : in std_logic; + + AXI_clock : in std_logic; + AXI_reset : in std_logic; + AXI4Lite_m2s : in T_AXI4Lite_BUS_M2S; + AXI4Lite_s2m : out T_AXI4Lite_BUS_S2M; + + Nanoseconds : out unsigned(63 downto 0); + Datetime : out T_CLOCK_DATETIME + ); +end entity; + + +architecture rtl of AXI4Lite_HighResolutionClock is + constant PERIOD_NANOSECONDS : natural := TimingToCycles(1.0e-9, CLOCK_FREQUENCY); + + function generateRegisterConfiguration return T_AXI4_Register_Vector is + variable temp : T_AXI4_Register_Vector(0 to 9); + variable pos : natural := 0; + variable addr : natural := 0; + begin + -- IRQ + --temp(pos) := to_AXI4_Register(Name => "Dummy_register", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly); -- Dummy register for later use + addr := addr + 4; -- pos := pos + 1; + temp(pos) := to_AXI4_Register(Name => "Config_reg", Address => to_unsigned(addr, 32), RegisterMode => ReadWrite); -- (en, inc, correction_threshold(29..0)) + addr := addr + 4; pos := pos + 1; + temp(pos) := to_AXI4_Register(Name => "Nanoseconds_lower", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly); -- Nanoseconds(31..0) + addr := addr + 4; pos := pos + 1; + temp(pos) := to_AXI4_Register(Name => "Nanoseconds_upper", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly); -- Nanoseconds(63..32) -> trigger on upper + addr := addr + 4; pos := pos + 1; + temp(pos) := to_AXI4_Register(Name => "Time_HMS", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly); -- Time + addr := addr + 4; pos := pos + 1; + temp(pos) := to_AXI4_Register(Name => "Date_Ymd", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly); -- Date + addr := addr + 4; pos := pos + 1; + temp(pos) := to_AXI4_Register(Name => "Time_sec_res", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly); -- ns, ms or us counter + addr := addr + 4; pos := pos + 1; + addr := addr + 4; -- dummy register + temp(pos) := to_AXI4_Register(Name => "Nanoseconds_to_load_lower", Address => to_unsigned(addr, 32), RegisterMode => ReadWrite_NotRegistered); -- todo: clear on read? Nanoseconds to load + addr := addr + 4; pos := pos + 1; + temp(pos) := to_AXI4_Register(Name => "Nanoseconds_to_load_upper", Address => to_unsigned(addr, 32), RegisterMode => ReadWrite_NotRegistered); -- Nanoseconds to load + addr := addr + 4; pos := pos + 1; + temp(pos) := to_AXI4_Register(Name => "Datetime_to_load_HMS", Address => to_unsigned(addr, 32), RegisterMode => ReadWrite_NotRegistered); -- Datetime to be loaded + addr := addr + 4; pos := pos + 1; + temp(pos) := to_AXI4_Register(Name => "Datetime_to_load_Ymd", Address => to_unsigned(addr, 32), RegisterMode => ReadWrite_NotRegistered); -- Datetime to be loaded + addr := addr + 4; pos := pos + 1; + return temp(0 to pos - 1); + end function; + + constant RegisterConfiguration : T_AXI4_Register_Vector := generateRegisterConfiguration; + + signal Reg_WritePort : T_SLVV(0 to (RegisterConfiguration'length - 1))(31 downto 0) := (others => (others => '0')); + signal Reg_ReadPort : T_SLVV(0 to (RegisterConfiguration'length - 1))(31 downto 0) := (others => (others => '0')); + signal Reg_ReadPort_hit : std_logic_vector(0 to (RegisterConfiguration'length - 1)) := (others => '0'); + + signal AXI4Lite_m2s_b : AXI4Lite_m2s'subtype; -- buffered AXI signal + signal AXI4Lite_s2m_b : AXI4Lite_s2m'subtype; -- buffered AXI signal + + signal Nanoseconds_registers : T_SLUV(0 to REGISTER_NANOSECONDS)(63 downto 0) := (others => (others => '0')); + signal Nanoseconds_i : Nanoseconds'subtype; + + signal Load_nanoseconds : std_logic := '0'; + signal Load_datetime : std_logic := '0'; + signal Nanoseconds_to_load : Nanoseconds'subtype; + signal Datetime_to_load_slv : std_logic_vector(63 downto 0) := (others => '0'); + signal Datetime_to_load : Datetime'subtype; + + signal Config_reg : unsigned(31 downto 0); + + -- nanosecond counter correction + signal Ns_inc : std_logic := '0'; + signal Ns_dec : std_logic := '0'; + signal en : std_logic := '0'; + signal inc : std_logic := '0'; + signal disable : std_logic := '0'; + signal correction : std_logic := '0'; + signal correction_counter : unsigned(29 downto 0) := (others => '0'); + signal correction_threshold : unsigned(29 downto 0) := (others => '0'); + +begin + Pipelining_gen: if REGISTER_NANOSECONDS > 0 generate + Pipelining: process(Clock) + begin + if rising_edge(Clock) then + Nanoseconds_registers(0) <= Nanoseconds_i - to_unsigned(REGISTER_NANOSECONDS * PERIOD_NANOSECONDS, 64); -- substract delay of registering from initial value + for i in 1 to REGISTER_NANOSECONDS loop + Nanoseconds_registers(i) <= Nanoseconds_registers(i - 1); + end loop; + end if; + end process; + else generate + Nanoseconds_registers(0) <= Nanoseconds_i; + end generate; + Nanoseconds <= Nanoseconds_registers(REGISTER_NANOSECONDS); + + CDC_gen: if USE_CDC generate + FIFO_CDC: entity work.AXI4Lite_FIFO_CDC + port map ( + -- IN Port + In_Clock => AXI_clock, + In_Reset => AXI_reset, + In_M2S => AXI4Lite_m2s, + In_S2M => AXI4Lite_s2m, + -- OUT Port + Out_Clock => Clock, + Out_Reset => Reset, + Out_M2S => AXI4Lite_m2s_b, + Out_S2M => AXI4Lite_s2m_b + ); + else generate + AXI4Lite_m2s_b <= AXI4Lite_m2s; + AXI4Lite_s2m <= AXI4Lite_s2m_b; + end generate; + + ClockRegister : entity work.AXI4Lite_Register + generic map ( + CONFIG => RegisterConfiguration + ) + port map ( + Clock => Clock, + Reset => Reset, + AXI4Lite_m2s => AXI4Lite_m2s_b, + AXI4Lite_s2m => AXI4Lite_s2m_b, + RegisterFile_ReadPort => Reg_ReadPort, + RegisterFile_ReadPort_hit => Reg_ReadPort_hit, + RegisterFile_WritePort => Reg_WritePort + ); + + Reg_WritePort(get_index("Nanoseconds_lower", RegisterConfiguration)) <= std_logic_vector(Nanoseconds(31 downto 0)); + Reg_WritePort(get_index("Nanoseconds_upper", RegisterConfiguration)) <= std_logic_vector(Nanoseconds(63 downto 32)); + Reg_WritePort(get_index("Time_sec_res", RegisterConfiguration)) <= std_logic_vector(Datetime.secondsResolution); + Reg_WritePort(get_index("Time_HMS", RegisterConfiguration)) <= ( + 5 downto 0 => std_logic_vector(Datetime.Seconds), + 11 downto 6 => std_logic_vector(Datetime.Minutes), + 16 downto 12 => std_logic_vector(Datetime.Hours), + 31 downto 17 => std_logic_vector(to_unsigned(0, 15)) -- reserved + ); + Reg_WritePort(get_index("Date_Ymd", RegisterConfiguration)) <= ( + 4 downto 0 => std_logic_vector(Datetime.Day), + 8 downto 5 => std_logic_vector(Datetime.Month), + 21 downto 9 => std_logic_vector(Datetime.Year), + 31 downto 22 => std_logic_vector(to_unsigned(0, 10)) -- reserved + ); + + -- Register time of load registers when upper register is hit, only writing to the lower register will not have an effect. + Nanoseconds_to_load(31 downto 0) <= unsigned(Reg_ReadPort(get_index("Nanoseconds_to_load_lower", RegisterConfiguration))) when rising_edge(Clock) and Reg_ReadPort_hit(get_index("Nanoseconds_to_load_lower", RegisterConfiguration)) = '1'; + Nanoseconds_to_load(63 downto 32) <= unsigned(Reg_ReadPort(get_index("Nanoseconds_to_load_upper", RegisterConfiguration))) when rising_edge(Clock); + + Datetime_to_load_slv(31 downto 0) <= Reg_ReadPort(get_index("Datetime_to_load_HMS", RegisterConfiguration)) when rising_edge(Clock) and Reg_ReadPort_hit(get_index("Datetime_to_load_HMS", RegisterConfiguration)) = '1'; + Datetime_to_load_slv(63 downto 32) <= Reg_ReadPort(get_index("Datetime_to_load_Ymd", RegisterConfiguration)) when rising_edge(Clock); + Datetime_to_load <= slv_to_datetime(Datetime_to_load_slv(31 downto 0), Datetime_to_load_slv(63 downto 32)); -- type conversion with function from clock.pkg.vhdl + + Load_nanoseconds <= Reg_ReadPort_hit(get_index("Nanoseconds_to_load_upper", RegisterConfiguration)) when rising_edge(Clock); -- flag which indicates that a new time has to be loaded + Load_datetime <= Reg_ReadPort_hit(get_index("Datetime_to_load_Ymd", RegisterConfiguration)) when rising_edge(Clock); -- flag which indicates that a new time has to be loaded + + HRClock: entity work.clock_HighResolution + generic map ( + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + SECOND_RESOLUTION => SECOND_RESOLUTION + ) + port map ( + Clock => Clock, + Reset => Reset, + + Load_nanoseconds => Load_nanoseconds, + Load_datetime => Load_datetime, + Nanoseconds_to_load => Nanoseconds_to_load, + Datetime_to_load => Datetime_to_load, + Ns_inc => Ns_inc, + Ns_dec => Ns_dec, + + Nanoseconds => Nanoseconds_i, + Datetime => Datetime + ); + + Config_reg <= unsigned(Reg_ReadPort(get_index("Config_reg", RegisterConfiguration))); + en <= Config_reg(31); -- enable increment / decrement + inc <= Config_reg(30); -- increment / decrement + correction_threshold <= Config_reg(29 downto 0); -- threshold in amount of clock cycles when a correction should be made + disable <= '1' when correction_threshold = 0 else '0'; -- internal disable signal in case no valid threshold is set + correction_proc: process(all) + begin + if rising_edge(Clock) then + correction <= '0'; + if (Reset or Load_nanoseconds) = '1' then + correction_counter <= (others => '0'); + elsif correction_counter >= correction_threshold - 1 then + correction <= '1'; + correction_counter <= (others => '0'); + else + correction_counter <= correction_counter + 1; + end if; + end if; + end process; + Ns_inc <= en and inc and correction and not disable when rising_edge(Clock); -- en and inc and correction and not disable + Ns_dec <= en and not inc and correction and not disable when rising_edge(Clock); -- en and not inc and correction and not disable +end architecture; diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_OSVVM.pkg.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_OSVVM.pkg.vhdl index b2b8d7d22..acc384bc4 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_OSVVM.pkg.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_OSVVM.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Stefan Unrein -- @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter.vhdl new file mode 100644 index 000000000..472e4ccd9 --- /dev/null +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter.vhdl @@ -0,0 +1,234 @@ +-- ============================================================================= +-- Authors: +-- Iqbal Asif +-- Patrick Lehmann +-- +-- Entity: +-- +-- Description: +-- ------------------------------------- +-- An adapter from AXI4-Lite to OCRAM. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + + +use work.utils.all; +use work.axi4lite.all; + +entity AXI4Lite_Ocram_Adapter is + generic ( + OCRAM_ADDRESS_BITS : positive; + OCRAM_DATA_BITS : positive; + PREFFERED_READ_ACCESS : boolean := TRUE + ); + port ( + Clock : in std_logic; + Reset : in std_logic; + + AXI4Lite_m2s : in T_AXI4Lite_Bus_M2S; + AXI4Lite_s2m : out T_AXI4Lite_Bus_S2M; + + Write_En : out std_logic; + Address : out unsigned(OCRAM_ADDRESS_BITS-1 downto 0); + Data_In : in std_logic_vector(OCRAM_DATA_BITS-1 downto 0); + Data_Out : out std_logic_vector(OCRAM_DATA_BITS-1 downto 0) + ); +end entity; + +architecture rtl of AXI4Lite_Ocram_Adapter is + constant ADDRESS_BITS : positive := AXI4Lite_m2s.AWAddr'length; + constant DATA_BITS : positive := AXI4Lite_m2s.WData'length; + constant DATA_BITS_intern : positive := 32; + constant ADDR_LSB : positive := log2ceil(DATA_BITS_intern) - 3; + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDRESS_BITS - ADDR_LSB - 1 downto 0) := (others => '0'); + signal axi_awready: std_logic := '0'; + signal axi_wready : std_logic := '0'; + signal axi_bresp : std_logic_vector(1 downto 0) := "00"; + signal axi_bvalid : std_logic := '0'; + signal axi_araddr : std_logic_vector(ADDRESS_BITS - ADDR_LSB - 1 downto 0) := (others => '0'); + signal axi_arready: std_logic := '0'; + signal axi_rdata : std_logic_vector(DATA_BITS - 1 downto 0) := (others => '0'); + signal axi_rresp : std_logic_vector(1 downto 0) := "00"; + signal axi_rvalid : std_logic := '0'; + + type t_state is ( + st_idle, + st_await_write_address, + st_await_write_data, + st_write_address_data, + st_read_data_ack, + st_write_response_wait, + st_read_response_wait, + st_error + ); + + signal currentstate : t_state := st_idle; + signal nextstate : t_state; + +begin + AXI4Lite_s2m.AWReady <= axi_awready; + AXI4Lite_s2m.WReady <= axi_wready; + AXI4Lite_s2m.BResp <= axi_bresp; + AXI4Lite_s2m.BValid <= axi_bvalid; + AXI4Lite_s2m.ARReady <= axi_arready; + AXI4Lite_s2m.RData <= axi_rdata; + AXI4Lite_s2m.RResp <= axi_rresp; + AXI4Lite_s2m.RValid <= axi_rvalid; + + process(Clock) + begin + if rising_edge(Clock) then + if (Reset = '1') then + currentstate <= st_idle; + else + currentstate <= nextstate; + end if; + end if; + end process; + + process(all) + variable valid : std_logic_vector(2 downto 0); + begin + nextstate <= currentstate; + Address <= resize(unsigned(AXI4Lite_m2s.AWAddr), Address'length) ; + Write_En <= '0'; + axi_awready <= '0'; + axi_wready <= '0'; + axi_arready <= '0'; + axi_rvalid <= '0'; + axi_bvalid <= '0'; + axi_bresp <= C_AXI4_RESPONSE_OKAY; + axi_rresp <= C_AXI4_RESPONSE_OKAY; + valid := AXI4Lite_m2s.WValid & AXI4Lite_m2s.AWValid & AXI4Lite_m2s.ARValid; + + case currentstate is + + when st_idle => + + case valid is + + when "001" => -- only read address + Address <= resize(unsigned(AXI4Lite_m2s.ARAddr), Address'length) ; + nextstate <= st_read_data_ack; + + when "010" => -- only write address + nextstate <= st_await_write_data; + + when "011" | "101" | "111" => -- read and write address at the same time + if (PREFFERED_READ_ACCESS = TRUE) then + Address <= resize(unsigned(AXI4Lite_m2s.ARAddr), Address'length) ; + nextstate <= st_read_data_ack; + elsif (valid = "011" ) then + nextstate <= st_await_write_data; + elsif (valid = "101" ) then + nextstate <= st_await_write_address; + elsif (valid = "111" ) then + nextstate <= st_write_address_data; + end if; + + when "100" => -- only write data + nextstate <= st_await_write_address; + + when "110" => -- write & address data + nextstate <= st_write_address_data; + + when others => + + end case; + + when st_await_write_address => + if (AXI4Lite_m2s.AWValid = '1') then + axi_awready <= '1'; + axi_wready <= '1'; + Write_En <= '1'; + axi_bvalid <= '1'; + if (AXI4Lite_m2s.BReady = '1') then + nextstate <= st_idle; + else + nextstate <= st_write_response_wait; + end if; + end if; + + when st_await_write_data => + Address <= resize(unsigned(AXI4Lite_m2s.AWAddr), Address'length) ; + if (AXI4Lite_m2s.WValid = '1') then + axi_awready <= '1'; + axi_wready <= '1'; + Write_En <= '1'; + axi_bvalid <= '1'; + if (AXI4Lite_m2s.BReady = '1') then + nextstate <= st_idle; + else + nextstate <= st_write_response_wait; + end if; + end if; + + when st_write_address_data => + Address <= resize(unsigned(AXI4Lite_m2s.AWAddr), Address'length) ; + axi_awready <= '1'; + axi_wready <= '1'; + Write_En <= '1'; + axi_bvalid <= '1'; + if (AXI4Lite_m2s.BReady = '1') then + nextstate <= st_idle; + else + nextstate <= st_write_response_wait; + end if; + + when st_read_data_ack => + axi_rvalid <= '1'; + Address <= resize(unsigned(AXI4Lite_m2s.ARAddr), Address'length) ; + if (AXI4Lite_m2s.RReady = '1') then + axi_arready <= '1'; + nextstate <= st_idle; + else + nextstate <= st_read_response_wait; + end if; + + when st_write_response_wait => + axi_bvalid <= '1'; + if (AXI4Lite_m2s.BReady = '1') then + nextstate <= st_idle; + end if; + + when st_read_response_wait => + axi_rvalid <= '1'; + if (AXI4Lite_m2s.RReady = '1') then + axi_arready <= '1'; + nextstate <= st_idle; + end if; + + when st_error => nextstate <= st_idle; + + when others => nextstate <= st_idle; + + end case; + + end process; + + Data_Out <= resize(AXI4Lite_m2s.WData, Data_Out'length); + axi_rdata <= resize(Data_In, axi_rdata'length); + +end architecture; + diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_Register.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_Register.vhdl index 10e491e0a..20630c253 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_Register.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_Register.vhdl @@ -1,14 +1,12 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Stefan Unrein --- Jonas Schreiner --- Patrick Lehmann --- Asif Iqbal --- Max Kraft-Kugler +-- Authors: +-- Stefan Unrein +-- Jonas Schreiner +-- Patrick Lehmann +-- Asif Iqbal +-- Max Kraft-Kugler -- --- Entity: AXI4Lite_Register +-- Entity: AXI4Lite_Register -- -- Description: -- ------------------------------------- @@ -23,7 +21,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Manager.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Manager.vhdl index c0001bfe5..da20aee9e 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Manager.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Manager.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Stefan Unrein -- @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Subordinate.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Subordinate.vhdl index 867957d31..7f03901a0 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Subordinate.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Subordinate.vhdl @@ -1,8 +1,7 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Stefan Unrein, Max Kraft-Kugler +-- Authors: +-- Stefan Unrein +-- Max Kraft-Kugler -- -- Entity: A slave-side bus termination module for AXI4-Lite. -- @@ -13,7 +12,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_Uart.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_Uart.vhdl new file mode 100644 index 000000000..a8a68e18e --- /dev/null +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_Uart.vhdl @@ -0,0 +1,238 @@ +-- ============================================================================= +-- Authors: +-- Nimitha Mallikarjuna +-- Srikanth Boppudi +-- +-- Entity: +-- +-- Description: +-- ------------------------------------- +-- Implement AXI4-Lite UART with hardware and software flowcontrol. +-- +-- This component has the same register set as AMD's AXI UARTLite. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.axi4lite.all; +use work.vectors.all; +use work.physical.all; +use work.components.all; +use work.utils.all; +use work.uart.all; + +entity AXI4Lite_Uart is + generic ( + + --uart communication parameters + CLOCK_FREQ : FREQ; + BAUDRATE : BAUD := 115.200 kBd; + PARITY : T_UART_PARITY_MODE := PARITY_NONE; --PARITY_EVEN, PARITY_ODD,PARITY_NONE + PARITY_ERROR_HANDLING : T_UART_PARITY_ERROR_HANDLING := PASSTHROUGH_ERROR_BYTE; --PASSTHROUGH_ERROR_BYTE,REPLACE_ERROR_BYTE,DROP_ERROR_BYTE + PARITY_ERROR_IDENTIFIER : std_logic_vector(7 downto 0) := x"15"; --^ NAK + ADD_INPUT_SYNCHRONIZERS : boolean := TRUE; + + --Buffer dimensions + TX_FIFO_DEPTH : positive := 16; + RX_FIFO_DEPTH : positive := 16; + + --Flow Control + FLOWCONTROL : T_IO_UART_FLOWCONTROL_KIND := UART_FLOWCONTROL_NONE; + SWFC_XON_CHAR : std_logic_vector(7 downto 0) := x"11"; -- ^Q + SWFC_XOFF_CHAR : std_logic_vector(7 downto 0) := x"13" -- ^S + ); + port ( + Clock : in std_logic; + Reset : in std_logic; + + AXI4Lite_m2s : in T_AXI4LITE_BUS_M2S; + AXI4Lite_s2m : out T_AXI4LITE_BUS_S2M; + AXI4Lite_irq : out std_logic; + + --External Pins + UART_TX : out std_logic; + UART_RX : in std_logic; + UART_RTS : out std_logic; + UART_CTS : in std_logic + ); +end entity; + + +architecture rtl of AXI4Lite_Uart is + constant TX_EMPTY_STATE_BITS : natural := 4; + constant RX_FULL_STATE_BITS : natural := 4; + + constant Reg_config : T_AXI4_Register_Vector := ( + to_AXI4_Register(Name => "Rx", Address => 32x"00", RegisterMode => ReadOnly_NotRegistered, Init_Value => x"00000000"), + to_AXI4_Register(Name => "Tx", Address => 32x"04", RegisterMode => ReadWrite_NotRegistered, Init_Value => x"00000000"), + to_AXI4_Register(Name => "Status", Address => 32x"08", RegisterMode => ReadOnly, Init_Value => x"00000000"), + to_AXI4_Register(Name => "Control", Address => 32x"0C", RegisterMode => ReadWrite, Init_Value => x"00000000") + ); + + subtype RegPortType is T_SLVV(0 to (Reg_Config'length - 1))(31 downto 0); + signal Reg_ReadPort : RegPortType; + signal Reg_WritePort : RegPortType := (others => (others => '0')); + signal Reg_ReadPort_hit : std_logic_vector(RegPortType'range); + signal Reg_WritePort_hit : std_logic_vector(RegPortType'range); + + --user required axi registers + signal RX_Data : std_logic_vector(7 downto 0); + signal TX_Data : std_logic_vector(7 downto 0); + signal Status : std_logic_vector(31 downto 0); + signal Control : std_logic_vector(31 downto 0); + + --Bit positions of the above registers + signal Status_RX_Valid : std_logic; + signal Status_RX_Valid_d : std_logic; + signal RX_Got : std_logic; + signal Control_RX_Reset : std_logic; + signal Status_InterruptEnable : std_logic; + signal Status_RX_Overrun : std_logic; + signal RX_OverFlow : std_logic; + signal Status_RX_Full : std_logic; + signal RX_StatusReg_hit : std_logic; + --signal status_Frame_Error : std_logic; + signal status_Parity_error : std_logic; + signal parity_error : std_logic; + + signal TX_Put : std_logic; + signal TXFIFO_Empty : std_logic; + signal TXFIFO_Empty_d : std_logic; + signal Status_TX_Full : std_logic; + signal Control_TX_Reset : std_logic; + signal Control_InterruptEnable : std_logic; + + signal Status_TX_EmptyState : std_logic_vector(imax(0, TX_EMPTY_STATE_BITS - 1) downto 0); + signal Status_RX_FullState : std_logic_vector(imax(0, RX_FULL_STATE_BITS - 1) downto 0); + + +begin + Reg : entity work.AXI4Lite_Register + generic map( + INIT_ON_RESET => true, + CONFIG => Reg_config + ) + port map( + Clock => Clock, + Reset => Reset, + + AXI4Lite_m2s => AXI4Lite_m2s, + AXI4Lite_s2m => AXI4Lite_s2m, + + RegisterFile_ReadPort => Reg_ReadPort, + RegisterFile_ReadPort_hit => Reg_ReadPort_hit, + RegisterFile_WritePort => Reg_WritePort, + RegisterFile_WritePort_hit => Reg_WritePort_hit + ); + + + registerAssignments: block + constant RX_IDX : natural := get_index("RX", Reg_config); + constant TX_IDX : natural := get_index("TX", Reg_config); + constant STATUS_IDX : natural := get_index("Status", Reg_config); + constant CONTROL_IDX : natural := get_index("Control", Reg_config); + begin + Reg_WritePort(RX_IDX)(RX_Data'range) <= RX_Data; + RX_Got <= Reg_WritePort_hit(RX_IDX) ; + RX_StatusReg_hit <= Reg_WritePort_hit(STATUS_IDX); -- to check overflow flag read or not + + Reg_WritePort(STATUS_IDX)(0) <= Status_RX_Valid; -- ULITE_STATUS_RXVALID + Reg_WritePort(STATUS_IDX)(1) <= Status_RX_Full; -- ULITE_STATUS_RXFULL + Reg_WritePort(STATUS_IDX)(2) <= TXFIFO_Empty; -- ULITE_STATUS_TXEMPTY + Reg_WritePort(STATUS_IDX)(3) <= Status_TX_Full; -- ULITE_STATUS_TXFULL + Reg_WritePort(STATUS_IDX)(4) <= Status_InterruptEnable; -- ULITE_STATUS_IE + Reg_WritePort(STATUS_IDX)(5) <= Status_RX_Overrun; -- ULITE_STATUS_OVERRUN + --Reg_WritePort(STATUS_IDX)(6) <= status_Frame_Error; -- Need to configure later + Reg_WritePort(STATUS_IDX)(7) <= status_Parity_error; -- Need to configure later + + Control_RX_Reset <= Reg_ReadPort(CONTROL_IDX)(0); + Control_TX_Reset <= Reg_ReadPort(CONTROL_IDX)(1); + Control_InterruptEnable <= Reg_ReadPort(CONTROL_IDX)(4); + + TX_Put <= Reg_ReadPort_hit(TX_IDX); + TX_Data <= Reg_ReadPort(TX_IDX)(TX_Data'range); + end block; + + + + Status_InterruptEnable <= Control_InterruptEnable; + Status_RX_Overrun <= ffrs(q =>Status_RX_Overrun , rst => (Reset or RX_StatusReg_hit) , set => RX_OverFlow) when rising_edge(Clock); + status_Parity_error <= ffrs(q =>status_Parity_error , rst => (Reset or RX_StatusReg_hit) , set => parity_error) when rising_edge(Clock); + + Status_RX_Valid_d <= Status_RX_Valid when rising_edge(Clock); -- Delay flag by one CC + TXFIFO_Empty_d <= TXFIFO_Empty when rising_edge(Clock); -- Delay flag by one CC + AXI4Lite_irq <= Status_InterruptEnable when ((Status_RX_Valid and not Status_RX_Valid_d) or (TXFIFO_Empty and not TXFIFO_Empty_d)) = '1' else '0'; -- Create IRQ for rising-edge of both flags + + + + UART : entity work.uart_fifo + generic map ( + -- Communication Parameters + CLOCK_FREQ => CLOCK_FREQ, + BAUDRATE => BAUDRATE, + PARITY => PARITY, + PARITY_ERROR_HANDLING => PARITY_ERROR_HANDLING, + PARITY_ERROR_IDENTIFIER => PARITY_ERROR_IDENTIFIER, + ADD_INPUT_SYNCHRONIZERS => ADD_INPUT_SYNCHRONIZERS, + + -- Buffer Dimensioning + TX_MIN_DEPTH => TX_FIFO_DEPTH, + TX_ESTATE_BITS => TX_EMPTY_STATE_BITS, + RX_MIN_DEPTH => RX_FIFO_DEPTH, + RX_FSTATE_BITS => RX_FULL_STATE_BITS, + + -- Flow Control + FLOWCONTROL => FLOWCONTROL, + SWFC_XON_CHAR => SWFC_XON_CHAR, + -- SWFC_XON_TRIGGER => , + SWFC_XOFF_CHAR => SWFC_XOFF_CHAR + -- SWFC_XOFF_TRIGGER => + ) + port map ( + Clock => Clock, + Reset => Reset, + + -- FIFO interface + TX_put => TX_Put, + TX_Data => TX_Data, + TX_Full => Status_TX_Full, + TX_EmptyState => Status_TX_EmptyState, + TXFIFO_Reset => Control_TX_Reset, + TXFIFO_Empty => TXFIFO_Empty, + + + RX_Valid => Status_RX_Valid, + RX_Data => RX_Data, + RX_got => RX_Got, + RX_FullState => Status_RX_FullState, + RX_Overflow => RX_OverFlow, + RXFIFO_Full => Status_RX_Full, + RXFIFO_Reset => Control_RX_Reset, + + -- External pins + UART_TX => UART_TX, + UART_RX => UART_RX, + UART_RTS => UART_RTS, + UART_CTS => UART_CTS, + UART_parity_error => parity_error + ); + +end architecture; diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream.pkg.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream.pkg.vhdl index eec417aaf..f6bb57ef3 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream.pkg.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Max Kraft-Kugler -- Stefan Unrein @@ -35,7 +32,7 @@ -- -- License: -- ============================================================================= --- Copyright 2017-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_DeMux.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_DeMux.vhdl index 111aa7281..c28f65225 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_DeMux.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_DeMux.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO.vhdl index 691b8c53a..0d7095ba8 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Stefan Unrein -- @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_cdc.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_cdc.vhdl index b1a43f6bf..200d056fd 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_cdc.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_cdc.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Stefan Unrein -- @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempgot.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempgot.vhdl index 03362e5b8..d01168e77 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempgot.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempgot.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Stefan Unrein -- @@ -18,7 +15,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempput.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempput.vhdl index 559730484..5f5d23e0d 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempput.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempput.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Stefan Unrein -- @@ -27,7 +24,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_Mux.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_Mux.vhdl index 66cde6076..727a18f2e 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_Mux.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_Mux.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -22,7 +19,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_Stage.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_Stage.vhdl index ad1a4689e..2443752ab 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_Stage.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_Stage.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Max Kraft-Kugler -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4_Common.pkg.vhdl b/src/bus/axi4/AXI4_Common.pkg.vhdl index dd41b8fd1..b97ddbd5c 100644 --- a/src/bus/axi4/AXI4_Common.pkg.vhdl +++ b/src/bus/axi4/AXI4_Common.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2017-2025 The PoC-Library Authors +-- Copyright 2017-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4_FIFO.vhdl b/src/bus/axi4/AXI4_FIFO.vhdl index 4c6986d6b..edf39b0c8 100644 --- a/src/bus/axi4/AXI4_FIFO.vhdl +++ b/src/bus/axi4/AXI4_FIFO.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Stefan Unrein -- @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4_FIFO_cdc.vhdl b/src/bus/axi4/AXI4_FIFO_cdc.vhdl index 485bd0d81..7c6839ebf 100644 --- a/src/bus/axi4/AXI4_FIFO_cdc.vhdl +++ b/src/bus/axi4/AXI4_FIFO_cdc.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Stefan Unrein -- @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4_Full.pkg.vhdl b/src/bus/axi4/AXI4_Full.pkg.vhdl index 957a07a12..484ec6a97 100644 --- a/src/bus/axi4/AXI4_Full.pkg.vhdl +++ b/src/bus/axi4/AXI4_Full.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -35,7 +32,7 @@ -- -- License: -- ============================================================================= --- Copyright 2017-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. @@ -49,6 +46,7 @@ -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= + library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; diff --git a/src/bus/axi4/AXI4_OSVVM.pkg.vhdl b/src/bus/axi4/AXI4_OSVVM.pkg.vhdl index 8e91649c5..cd4d7c996 100644 --- a/src/bus/axi4/AXI4_OSVVM.pkg.vhdl +++ b/src/bus/axi4/AXI4_OSVVM.pkg.vhdl @@ -1,8 +1,6 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Jonas Schreiner +-- Authors: +-- Jonas Schreiner -- -- Description: -- ------------------------------------- @@ -11,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. @@ -26,18 +24,17 @@ -- limitations under the License. -- ============================================================================= - library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; +library osvvm_axi4; +use osvvm_axi4.Axi4InterfacePkg.all; + use work.utils.all; use work.AXI4.all; use work.AXI4_FULL.all; -library OSVVM_AXI4; -use OSVVM_AXI4.Axi4InterfacePkg.all; - package AXI4_OSVVM is procedure to_PoC_AXI4_Bus_Slave(signal PoC_M2S : in T_AXI4_BUS_M2S; signal PoC_S2M : out T_AXI4_BUS_S2M; signal OSVVM_Bus : inout Axi4RecType); diff --git a/src/bus/axi4/AXI4_Termination_Manager.vhdl b/src/bus/axi4/AXI4_Termination_Manager.vhdl index 2f57ebb37..86ff0cf4a 100644 --- a/src/bus/axi4/AXI4_Termination_Manager.vhdl +++ b/src/bus/axi4/AXI4_Termination_Manager.vhdl @@ -1,11 +1,9 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Stefan Unrein --- Patrick Lehmann +-- Authors: +-- Stefan Unrein +-- Patrick Lehmann -- --- Entity: A master-side bus termination module for AXI4 (full). +-- Entity: A master-side bus termination module for AXI4 (full). -- -- Description: -- ------------------------------------- @@ -14,7 +12,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. @@ -29,7 +27,6 @@ -- limitations under the License. -- ============================================================================= - library IEEE; use IEEE.std_logic_1164.all; diff --git a/src/bus/axi4/AXI4_Termination_Subordinate.vhdl b/src/bus/axi4/AXI4_Termination_Subordinate.vhdl index ab1ab8ccb..bdedd3d02 100644 --- a/src/bus/axi4/AXI4_Termination_Subordinate.vhdl +++ b/src/bus/axi4/AXI4_Termination_Subordinate.vhdl @@ -1,12 +1,10 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Stefan Unrein --- Patrick Lehmann --- Max Kraft-Kugler +-- Authors: +-- Stefan Unrein +-- Patrick Lehmann +-- Max Kraft-Kugler -- --- Entity: A slave-side bus termination module for AXI4 (full). +-- Entity: A slave-side bus termination module for AXI4 (full). -- -- Description: -- ------------------------------------- @@ -15,7 +13,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/AXI4_to_AXI4Lite.vhdl b/src/bus/axi4/AXI4_to_AXI4Lite.vhdl index 56a9e6bbc..faabfc469 100644 --- a/src/bus/axi4/AXI4_to_AXI4Lite.vhdl +++ b/src/bus/axi4/AXI4_to_AXI4Lite.vhdl @@ -1,17 +1,12 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Stefan Unrein +-- Authors: +-- Stefan Unrein -- --- Entity:. --- --- Description: --- ------------------------------------- +-- Entity: AXI4_to_AXI4Lite -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/axi4.pkg.vhdl b/src/bus/axi4/axi4.pkg.vhdl index e6e44cf5c..ca4865762 100644 --- a/src/bus/axi4/axi4.pkg.vhdl +++ b/src/bus/axi4/axi4.pkg.vhdl @@ -1,11 +1,9 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Patrick Lehmann --- Stefan Unrein +-- Authors: +-- Patrick Lehmann +-- Stefan Unrein -- --- Entity: Generic AMBA AXI4 bus description +-- Entity: Generic AMBA AXI4 bus description -- -- Description: -- ------------------------------------- @@ -17,7 +15,7 @@ -- -- License: -- ============================================================================= --- Copyright 2017-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/bus/axi4/axi4.pro b/src/bus/axi4/axi4.pro index 6637471c2..037ea4960 100644 --- a/src/bus/axi4/axi4.pro +++ b/src/bus/axi4/axi4.pro @@ -1,10 +1,11 @@ # ============================================================================= # Authors: -# Adrian Weiland, Stefan Unrein +# Adrian Weiland +# Stefan Unrein # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -26,29 +27,67 @@ #analyze ./AXI4Lite/AXI4Lite.pkg.vhdl #analyze axi4.pkg.vhdl +disabled AXI4_Address_Data_Aligner.vhdl +disabled AXI4_Address_Translate.vhdl +disabled AXI4_Address_Translate_n_Filter.vhdl +disabled AXI4_Data_Swapper.vhdl analyze AXI4_FIFO.vhdl analyze AXI4_FIFO_cdc.vhdl +disabled AXI4_DeMux.vhdl +disabled AXI4_Mux.vhdl +disabled AXI4_Packet_FIFO.vhdl +disabled AXI4_Sink_Slave.vhdl analyze AXI4_Termination_Manager.vhdl analyze AXI4_Termination_Subordinate.vhdl analyze AXI4_to_AXI4Lite.vhdl analyze AXI4_OSVVM.pkg.vhdl +disabled ./AXI4Lite/AXI4Lite_AddressMask.vhdl +disabled ./AXI4Lite/AXI4Lite_AddressTruncate.vhdl +disabled ./AXI4Lite/AXI4Lite_Writer.vhdl +disabled ./AXI4Lite/AXI4Lite_Reader.vhdl +# analyze ./AXI4Lite/AXI4Lite_Configurator.vhdl ; # Does not work right now +disabled ./AXI4Lite/AXI4Lite_DeMux.vhdl +disabled ./AXI4Lite/AXI4Lite_ErrorFilter.vhdl analyze ./AXI4Lite/AXI4Lite_FIFO.vhdl analyze ./AXI4Lite/AXI4Lite_FIFO_cdc.vhdl analyze ./AXI4Lite/AXI4Lite_Register.vhdl +disabled ./AXI4Lite/AXI4Lite_Register_split.vhdl analyze ./AXI4Lite/AXI4Lite_Termination_Manager.vhdl analyze ./AXI4Lite/AXI4Lite_Termination_Subordinate.vhdl +analyze ./AXI4Lite/AXI4Lite_HighResolutionClock.vhdl +# analyze ./AXI4Lite/AXI4Lite_Interrupt_Controller.vhdl ; # Does not work right now +analyze ./AXI4Lite/AXI4Lite_Ocram_Adapter.vhdl analyze ./AXI4Lite/AXI4Lite_OSVVM.pkg.vhdl analyze ./AXI4Lite/AXI4Lite_GitVersionRegister.vhdl +disabled ./AXI4Lite/AXI4Lite_SimpleInterface.vhdl +analyze ./AXI4Lite/AXI4Lite_Uart.vhdl analyze ./AXI4Stream/AXI4Stream_FIFO.vhdl analyze ./AXI4Stream/AXI4Stream_FIFO_cdc.vhdl analyze ./AXI4Stream/AXI4Stream_FIFO_tempgot.vhdl analyze ./AXI4Stream/AXI4Stream_FIFO_tempput.vhdl analyze ./AXI4Stream/AXI4Stream_Stage.vhdl +disabled ./AXI4Stream/AXI4Stream_Mirror.vhdl analyze ./AXI4Stream/AXI4Stream_Mux.vhdl +disabled ./AXI4Stream/AXI4Stream_Pause.vhdl analyze ./AXI4Stream/AXI4Stream_DeMux.vhdl +disabled ./AXI4Stream/AXI4Stream_DataExtractor.vhdl +disabled ./AXI4Stream/AXI4Stream_PatternFinder.vhdl +disabled ./AXI4Stream/AXI4Stream_FieldReplacer.vhd +disabled ./AXI4Stream/AXI4Stream_Crossbar.vhdl ; # Does not work right now due to Riviera compiler error (bug report is pending) +# analyze ./AXI4Stream/AXI4Stream_Frame_Buffer.vhdl ; #Does not work right now +disabled ./AXI4Stream/AXI4Stream_PRBSGenerator.vhdl +disabled ./AXI4Stream/AXI4Stream_Termination_Manager.vhdl +disabled ./AXI4Stream/AXI4Stream_Termination_Subordinate.vhdl +disabled ./AXI4Stream/AXI4Stream_Buffer_no_backpressure.vhdl +disabled ./AXI4Stream/AXI4Stream_To_Stream.vhdl +disabled ./AXI4Stream/AXI4Stream_Splitter.vhdl +disabled ./AXI4Stream/AXI4Stream_Delay.vhdl +disabled ./AXI4Stream/AXI4Stream_Realign.vhdl + +# FIXME: should be analyzed before PoC.bus, right? analyze ../../misc/gearbox/gearbox_down_cc.vhdl analyze ../../misc/gearbox/gearbox_up_cc.vhdl - +disabled ./AXI4Stream/AXI4Stream_Gearbox.vhdl diff --git a/src/bus/bus.pro b/src/bus/bus.pro index b5a1f68ed..dee247607 100644 --- a/src/bus/bus.pro +++ b/src/bus/bus.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -21,5 +21,17 @@ analyze ./bus_Arbiter.vhdl -include ./stream/stream.pro +analyze ./stream/stream.pkg.vhdl +analyze ./stream/stream_DeMux.vhdl +analyze ./stream/stream_Mux.vhdl +disabled ./stream/stream_To_AXI4Stream.vhdl +disabled ./stream/stream_Delay.vhdl + include ./axi4/axi4.pro +include ./stream/stream.pro + +duplicate ./axi4/AXI4Stream/AXI4Stream_To_Stream.vhdl + +# analyze ./drp/drp.generic.vhdl # Currently not working +analyze ./drp/drp.pkg.vhdl +# analyze ./drp/DRP_To_AXI4Lite_Bridge.vhdl # Currently not working diff --git a/src/bus/bus_Arbiter.vhdl b/src/bus/bus_Arbiter.vhdl index 8ffa1047b..9bfcf6716 100644 --- a/src/bus/bus_Arbiter.vhdl +++ b/src/bus/bus_Arbiter.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -15,7 +12,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/bus/drp/DRP_To_AXI4Lite_Bridge.vhdl b/src/bus/drp/DRP_To_AXI4Lite_Bridge.vhdl new file mode 100644 index 000000000..49c492302 --- /dev/null +++ b/src/bus/drp/DRP_To_AXI4Lite_Bridge.vhdl @@ -0,0 +1,228 @@ +-- ============================================================================= +-- Authors: +-- Stefan Unrein +-- +-- Entity: +-- +-- Description: +-- ------------------------------------- +-- An adapter from AXI4-Lite to DRP (dynamic reconfiguration port). +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.utils.all; +use work.axi4lite.all; +use work.drp.all; + +entity DRP_To_AXI4Lite_Bridge is + generic ( + DRP_COUNT : positive := 1; + DRP_ADDR_BITS : positive := 10 --Register Address, NO Word-Address; 10 bit for US+, 9 bit for US + ); + port ( + Clock : in std_logic; + Reset : in std_logic; + -- IN Port + AXI4Lite_M2S : in T_AXI4Lite_Bus_M2S; + AXI4Lite_S2M : out T_AXI4Lite_Bus_S2M; + -- OUT Port + DRP_M2S : out T_DRP_Bus_M2S_VECTOR(0 to DRP_COUNT - 1); + DRP_S2M : in T_DRP_Bus_S2M_VECTOR(0 to DRP_COUNT - 1) + ); +end entity; +architecture rtl of DRP_To_AXI4Lite_Bridge is + constant DRP_DATA_BITS : positive := 16; + constant C_COUNT_BITS : natural := log2ceil(DRP_COUNT); + constant C_AXI_ADDR_BITS : natural := C_COUNT_BITS + DRP_ADDR_BITS; + + signal DRP_Enable : std_logic_vector(0 to DRP_COUNT - 1); + signal DRP_WriteEnable : std_logic_vector(0 to DRP_COUNT - 1); + + signal DRP_Address : unsigned(DRP_ADDR_BITS - 1 downto 0); + signal DRP_Address_d : unsigned(DRP_ADDR_BITS - 1 downto 0) := (others => '0'); + signal DRP_Address_En : std_logic; + + signal DRP_DataIn : std_logic_vector(DRP_DATA_BITS - 1 downto 0); + signal DRP_DataIn_d : std_logic_vector(DRP_DATA_BITS - 1 downto 0) := (others => '0'); + signal DRP_DataIn_En : std_logic; + + signal DRP_DataOut_i : std_logic_vector(DRP_DATA_BITS - 1 downto 0); + signal DRP_DataOut_d : std_logic_vector(DRP_DATA_BITS - 1 downto 0) := (others => '0'); + + signal DRP_port_i : unsigned(C_COUNT_BITS - 1 downto 0); + signal DRP_port_d : unsigned(C_COUNT_BITS - 1 downto 0) := (others => '0'); + + type T_State is (idle, read, read_wait, read_error, write, write_wait, write_error); + signal State : T_State := idle; + signal State_nxt : T_State; +begin + assert AXI4Lite_M2S.WData'length = 32 report "PoC.DRP_To_AXI4Lite_Bridge:: Bridge can only support 32bit data width for AXI4L!" severity failure; + assert AXI4Lite_M2S.AWAddr'length >= C_AXI_ADDR_BITS +2 report "PoC.DRP_To_AXI4Lite_Bridge:: Not enough address bits in AXI4L!" severity failure; + + process (all) + begin + for i in 0 to DRP_COUNT - 1 loop + DRP_M2S(i).Address <= DRP_Address; + DRP_M2S(i).DataIn <= DRP_DataIn; + DRP_M2S(i).Enable <= DRP_Enable(i); + DRP_M2S(i).WriteEnable <= DRP_WriteEnable(i); + end loop; + end process; + + process (Clock) + begin + if rising_edge(Clock) then + if Reset = '1' then + State <= Idle; + else + State <= State_nxt; + end if; + end if; + end process; + + process (all) + variable DRP_port : unsigned(C_COUNT_BITS - 1 downto 0) := (others => '0'); + begin + State_nxt <= State; + DRP_Enable <= (others => '0'); + DRP_WriteEnable <= (others => '0'); + + DRP_DataIn_En <= '0'; + DRP_DataIn <= DRP_DataIn_d; + DRP_Address_En <= '0'; + DRP_Address <= DRP_Address_d; + DRP_port := (others => '0'); + DRP_port_i <= DRP_port_d; + DRP_DataOut_i <= DRP_DataOut_d; + + AXI4Lite_S2M.AWReady <= '0'; + AXI4Lite_S2M.WReady <= '0'; + AXI4Lite_S2M.BValid <= '0'; + AXI4Lite_S2M.BResp <= C_AXI4_RESPONSE_OKAY; + AXI4Lite_S2M.RResp <= C_AXI4_RESPONSE_OKAY; + + AXI4Lite_S2M.ARReady <= '0'; + AXI4Lite_S2M.RValid <= '0'; + AXI4Lite_S2M.RData <= (others => '0'); + + case State is + when Idle => + if (AXI4Lite_M2S.AWValid and AXI4Lite_M2S.WValid) = '1' then + + DRP_DataIn_En <= '1'; + DRP_DataIn <= AXI4Lite_M2S.WData(DRP_DATA_BITS -1 downto 0); + DRP_Address_En <= '1'; + DRP_Address <= unsigned(AXI4Lite_M2S.AWAddr(DRP_ADDR_BITS + 1 downto 2)); + DRP_port := unsigned(AXI4Lite_M2S.AWAddr(C_AXI_ADDR_BITS + 1 downto DRP_ADDR_BITS + 2)); + DRP_port_i <= DRP_port; + AXI4Lite_S2M.AWReady <= '1'; + AXI4Lite_S2M.WReady <= '1'; + + if DRP_port < DRP_COUNT then + DRP_Enable(to_integer(DRP_port)) <= '1'; + DRP_WriteEnable(to_integer(DRP_port)) <= '1'; + if DRP_S2M(to_integer(DRP_port)).Ready = '1' then + State_nxt <= write_wait; + else + State_nxt <= write; + end if; + else + State_nxt <= write_error; + end if; + elsif AXI4Lite_M2S.ARValid = '1' then + DRP_Address_En <= '1'; + DRP_Address <= unsigned(AXI4Lite_M2S.ARAddr(DRP_ADDR_BITS + 1 downto 2)); + DRP_port := unsigned(AXI4Lite_M2S.ARAddr(C_AXI_ADDR_BITS + 1 downto DRP_ADDR_BITS + 2)); + DRP_port_i <= DRP_port; + AXI4Lite_S2M.ARReady <= '1'; + + if DRP_port < DRP_COUNT then + DRP_Enable(to_integer(DRP_port)) <= '1'; + if DRP_S2M(to_integer(DRP_port)).Ready = '1' then + State_nxt <= read_wait; + AXI4Lite_S2M.RData <= resize(DRP_S2M(to_integer(DRP_port)).DataOut, AXI4Lite_S2M.RData'length); + DRP_DataOut_i <= DRP_S2M(to_integer(DRP_port)).DataOut; + else + State_nxt <= read; + end if; + else + State_nxt <= read_error; + end if; + + end if; + + when read => + if DRP_S2M(to_integer(DRP_port_d)).Ready = '1' then + AXI4Lite_S2M.RValid <= '1'; + AXI4Lite_S2M.RData <= resize(DRP_S2M(to_integer(DRP_port_d)).DataOut, AXI4Lite_S2M.RData'length); + DRP_DataOut_i <= DRP_S2M(to_integer(DRP_port_d)).DataOut; + if AXI4Lite_M2S.RReady = '1' then + State_nxt <= idle; + else + State_nxt <= read_wait; + end if; + end if; + + when read_wait => + AXI4Lite_S2M.RValid <= '1'; + AXI4Lite_S2M.RData <= resize(DRP_DataOut_d, AXI4Lite_S2M.RData'length); + if AXI4Lite_M2S.RReady = '1' then + State_nxt <= idle; + end if; + + when read_error => + AXI4Lite_S2M.RValid <= '1'; + AXI4Lite_S2M.RResp <= C_AXI4_RESPONSE_DECODE_ERROR; + AXI4Lite_S2M.RData <= (others => '0'); + if AXI4Lite_M2S.RReady = '1' then + State_nxt <= idle; + end if; + + when write => + if DRP_S2M(to_integer(DRP_port_d)).Ready = '1' then + AXI4Lite_S2M.BValid <= '1'; + if AXI4Lite_M2S.BReady = '1' then + State_nxt <= idle; + else + State_nxt <= write_wait; + end if; + end if; + when write_wait => + AXI4Lite_S2M.BValid <= '1'; + if AXI4Lite_M2S.BReady = '1' then + State_nxt <= idle; + end if; + when write_error => + AXI4Lite_S2M.BValid <= '1'; + AXI4Lite_S2M.BResp <= C_AXI4_RESPONSE_DECODE_ERROR; + if AXI4Lite_M2S.BReady = '1' then + State_nxt <= idle; + end if; + end case; + end process; + + DRP_DataOut_d <= DRP_DataOut_i when rising_edge(Clock); + DRP_DataIn_d <= DRP_DataIn when rising_edge(Clock) and DRP_DataIn_En = '1'; + DRP_Address_d <= DRP_Address when rising_edge(Clock) and DRP_Address_En = '1'; + DRP_port_d <= DRP_port_i when rising_edge(Clock); + +end architecture; diff --git a/src/bus/drp/drp.generic.vhdl b/src/bus/drp/drp.generic.vhdl new file mode 100644 index 000000000..715a2d353 --- /dev/null +++ b/src/bus/drp/drp.generic.vhdl @@ -0,0 +1,56 @@ +-- ============================================================================= +-- Authors: +-- Stefan Unrein +-- +-- Entity: +-- +-- Description: +-- ------------------------------------- +-- This package implements a generic Dynamic Reconfiguration Port(DRP) description. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +use work.DRP.all; + + +package DRP_Sized is + generic ( + ADDRESS_BITS : natural; + DATA_BITS : natural + ); + + + subtype SIZED_S2M is T_DRP_Bus_S2M( + DataOut(DATA_BITS -1 downto 0) + ); + + subtype SIZED_M2S is T_DRP_Bus_M2S( + Address(ADDRESS_BITS -1 downto 0), + DataIn(DATA_BITS -1 downto 0) + ); + + subtype SIZED_M2S_VECTOR is T_DRP_Bus_M2S_VECTOR(open)( + Address(ADDRESS_BITS -1 downto 0), + DataIn(DATA_BITS -1 downto 0) + ); + + subtype SIZED_S2M_VECTOR is T_DRP_Bus_S2M_VECTOR(open)( + DataOut(DATA_BITS -1 downto 0) + ); + +end package; diff --git a/src/bus/drp/drp.pkg.vhdl b/src/bus/drp/drp.pkg.vhdl new file mode 100644 index 000000000..2bfa1b533 --- /dev/null +++ b/src/bus/drp/drp.pkg.vhdl @@ -0,0 +1,95 @@ +-- ============================================================================= +-- Authors: +-- Stefan Unrein +-- +-- Entity: +-- +-- Description: +-- ------------------------------------- +-- This package implements a generic Dynamic Reconfiguration Port(DRP) description. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.utils.all; + + +package DRP is + + type T_DRP_Bus_S2M is record + Ready : std_logic; + DataOut : std_logic_vector; + end record; + type T_DRP_Bus_S2M_VECTOR is array(natural range <>) of T_DRP_Bus_S2M; + + type T_DRP_Bus_M2S is record + Enable : std_logic; + WriteEnable : std_logic; + Address : unsigned; + DataIn : std_logic_vector; + end record; + type T_DRP_Bus_M2S_VECTOR is array(natural range <>) of T_DRP_Bus_M2S; + + type T_DRP_Bus is record + M2S : T_DRP_Bus_M2S; + S2M : T_DRP_Bus_S2M; + end record; + type T_DRP_Bus_VECTOR is array(natural range <>) of T_DRP_Bus; + + + function Initialize_DRP_Bus_M2S(AddressBits : natural; DataBits : natural := 16; Value : std_logic := 'Z') return T_DRP_Bus_M2S; + function Initialize_DRP_Bus_S2M( DataBits : natural := 16; Value : std_logic := 'Z') return T_DRP_Bus_S2M; + function Initialize_DRP_Bus( AddressBits : natural; DataBits : natural := 16; Value : std_logic := 'Z') return T_DRP_Bus; + +end package; + + +package body DRP is + function Initialize_DRP_Bus_M2S(AddressBits : natural; DataBits : natural := 16; Value : std_logic := 'Z') return T_DRP_Bus_M2S is + variable var : T_DRP_Bus_M2S( + Address(AddressBits -1 downto 0), DataIn(DataBits -1 downto 0)) :=( + Enable => Value, + WriteEnable => Value, + Address => (AddressBits-1 downto 0 => Value), + DataIn => (DataBits - 1 downto 0 => Value) + ); + begin + return var; + end function; + + function Initialize_DRP_Bus_S2M(DataBits : natural := 16; Value : std_logic := 'Z') return T_DRP_Bus_S2M is + variable var : T_DRP_Bus_S2M(DataOut(DataBits -1 downto 0)) :=( + Ready => Value, + DataOut => (DataBits - 1 downto 0 => Value) + ); + begin + return var; + end function; + + function Initialize_DRP_Bus(AddressBits : natural; DataBits : natural := 16; Value : std_logic := 'Z') return T_DRP_Bus is + begin + return ( + M2S => Initialize_DRP_Bus_M2S(AddressBits, DataBits, Value), + S2M => Initialize_DRP_Bus_S2M(DataBits, Value) + ); + end function; + + end package body; diff --git a/src/bus/stream/stream.pkg.vhdl b/src/bus/stream/stream.pkg.vhdl index 496b718f1..fad84e642 100644 --- a/src/bus/stream/stream.pkg.vhdl +++ b/src/bus/stream/stream.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -27,7 +24,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/bus/stream/stream.pro b/src/bus/stream/stream.pro index 746356a68..3a2079e64 100644 --- a/src/bus/stream/stream.pro +++ b/src/bus/stream/stream.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -19,13 +19,28 @@ # limitations under the License. # ============================================================================= -library PoC - -analyze stream.pkg.vhdl +# analyze stream.pkg.vhdl analyze stream_FIFO.vhdl -analyze stream_DeMux.vhdl +disabled stream_FIFO_tempput.vhdl +# analyze stream_Delay.vhdl ; # already analyzed +# analyze stream_DeMux.vhdl ; # already analyzed +disabled stream_fast_cutter.vhdl +disabled stream_fast_to_stream_adapter.vhd analyze stream_FrameGenerator.vhdl +disabled stream_Frame_checker.vhdl +disabled stream_Stage.vhdl +disabled stream_Stage_vector.vhdl analyze stream_Mirror.vhdl -analyze stream_Mux.vhdl +# analyze stream_Mux.vhdl ; # already analyzed +disabled stream_PacketGenerator.vhdl +disabled stream_Padder.vhdl analyze stream_Source.vhdl +disabled stream_Statistics.vhdl +disabled stream_to_stream_fast_adapter.vhd +disabled stream_utils.pkg.vhdl +disabled stream_Presplitter.vhdl +disabled stream_Prepender.vhdl +disabled generic_fast_appender.vhdl +disabled generic_fast_post_splitter.vhdl +disabled generic_fast_pre_splitter.vhdl diff --git a/src/bus/stream/stream_DeMux.vhdl b/src/bus/stream/stream_DeMux.vhdl index d81dc5c2b..5601215f5 100644 --- a/src/bus/stream/stream_DeMux.vhdl +++ b/src/bus/stream/stream_DeMux.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/bus/stream/stream_FIFO.vhdl b/src/bus/stream/stream_FIFO.vhdl index 354e13cb8..740e7c5f0 100644 --- a/src/bus/stream/stream_FIFO.vhdl +++ b/src/bus/stream/stream_FIFO.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -15,7 +12,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/bus/stream/stream_FrameGenerator.vhdl b/src/bus/stream/stream_FrameGenerator.vhdl index b160484ad..58c0fd962 100644 --- a/src/bus/stream/stream_FrameGenerator.vhdl +++ b/src/bus/stream/stream_FrameGenerator.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/bus/stream/stream_Mirror.vhdl b/src/bus/stream/stream_Mirror.vhdl index 071a5ed13..cdfa31abb 100644 --- a/src/bus/stream/stream_Mirror.vhdl +++ b/src/bus/stream/stream_Mirror.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/bus/stream/stream_Mux.vhdl b/src/bus/stream/stream_Mux.vhdl index 52bd18452..4a9792daf 100644 --- a/src/bus/stream/stream_Mux.vhdl +++ b/src/bus/stream/stream_Mux.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/bus/stream/stream_Source.vhdl b/src/bus/stream/stream_Source.vhdl index ec87a8401..b968c1e9d 100644 --- a/src/bus/stream/stream_Source.vhdl +++ b/src/bus/stream/stream_Source.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/cache/cache.pkg.vhdl b/src/cache/cache.pkg.vhdl index e088bed69..eaa30eaea 100644 --- a/src/cache/cache.pkg.vhdl +++ b/src/cache/cache.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -32,9 +29,6 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -library PoC; - - package cache is -- cache-lookup Result type T_CACHE_RESULT is (CACHE_RESULT_NONE, CACHE_RESULT_HIT, CACHE_RESULT_MISS); diff --git a/src/cache/cache.pro b/src/cache/cache.pro index eee6bd784..0034da617 100644 --- a/src/cache/cache.pro +++ b/src/cache/cache.pro @@ -1,6 +1,23 @@ # ============================================================================= # Authors: # Adrian Weiland +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2026 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= analyze cache.pkg.vhdl diff --git a/src/cache/cache_cpu.vhdl b/src/cache/cache_cpu.vhdl index 61283fcce..17cf0fb65 100644 --- a/src/cache/cache_cpu.vhdl +++ b/src/cache/cache_cpu.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/src/cache/cache_mem.vhdl b/src/cache/cache_mem.vhdl index ff5250c70..7989243ed 100644 --- a/src/cache/cache_mem.vhdl +++ b/src/cache/cache_mem.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/src/cache/cache_par.vhdl b/src/cache/cache_par.vhdl index 7fe6619ee..400a24ee9 100644 --- a/src/cache/cache_par.vhdl +++ b/src/cache/cache_par.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Martin Zabel diff --git a/src/cache/cache_par2.vhdl b/src/cache/cache_par2.vhdl index eef54fb91..696b9512d 100644 --- a/src/cache/cache_par2.vhdl +++ b/src/cache/cache_par2.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/cache/cache_replacement_policy.vhdl b/src/cache/cache_replacement_policy.vhdl index 963d0fe81..4e792bb9c 100644 --- a/src/cache/cache_replacement_policy.vhdl +++ b/src/cache/cache_replacement_policy.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Martin Zabel diff --git a/src/cache/cache_tagunit_par.vhdl b/src/cache/cache_tagunit_par.vhdl index 2465c45a9..e95541510 100644 --- a/src/cache/cache_tagunit_par.vhdl +++ b/src/cache/cache_tagunit_par.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Martin Zabel diff --git a/src/cache/cache_tagunit_seq.vhdl b/src/cache/cache_tagunit_seq.vhdl index 907af20bf..2f884c2ad 100644 --- a/src/cache/cache_tagunit_seq.vhdl +++ b/src/cache/cache_tagunit_seq.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/comm/comm.pkg.vhdl b/src/comm/comm.pkg.vhdl index 5b888636b..bac95e18e 100644 --- a/src/comm/comm.pkg.vhdl +++ b/src/comm/comm.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- diff --git a/src/comm/comm.pro b/src/comm/comm.pro index ab766afa1..7e1937cf1 100644 --- a/src/comm/comm.pro +++ b/src/comm/comm.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -21,6 +21,7 @@ analyze ./comm.pkg.vhdl analyze ./comm_crc.vhdl +disabled ./comm_crc_parallel.vhdl analyze ./comm_scramble.vhdl analyze ./remote/remote_terminal_control.vhdl diff --git a/src/comm/comm_crc.vhdl b/src/comm/comm_crc.vhdl index 86cf85a0a..97eb943f6 100644 --- a/src/comm/comm_crc.vhdl +++ b/src/comm/comm_crc.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Patrick Lehmann diff --git a/src/comm/comm_scramble.vhdl b/src/comm/comm_scramble.vhdl index 5e120d534..344a673d1 100644 --- a/src/comm/comm_scramble.vhdl +++ b/src/comm/comm_scramble.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- diff --git a/src/common/README.md b/src/common/README.md index d284e0ab2..b469bac50 100644 --- a/src/common/README.md +++ b/src/common/README.md @@ -21,15 +21,15 @@ The namespace `PoC` offers common packages. **Usage:** ```VHDL -library PoC; -use PoC.config.all; -use PoC.debug.all; -use PoC.fileio.all; -- If supported by the vendor tool -use PoC.math.all; -use PoC.physical.all; -use PoC.strings.all; -use PoC.utils.all; -use PoC.vectors.all; + +use work.config.all; +use work.debug.all; +use work.fileio.all; -- If supported by the vendor tool +use work.math.all; +use work.physical.all; +use work.strings.all; +use work.utils.all; +use work.vectors.all; ``` diff --git a/src/common/common.pro b/src/common/common.pro index 179f83203..381689d34 100644 --- a/src/common/common.pro +++ b/src/common/common.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/common/common.vhdl b/src/common/common.vhdl index ece4e7128..07b0c831d 100644 --- a/src/common/common.vhdl +++ b/src/common/common.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/common/components.vhdl b/src/common/components.vhdl index bc227bff0..a8691727e 100644 --- a/src/common/components.vhdl +++ b/src/common/components.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -18,7 +15,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- @@ -41,7 +38,6 @@ use IEEE.NUMERIC_STD.all; use work.utils.all; - package components is -- implement an optional register stage function registered(signal Clock : std_logic; constant IsRegistered : boolean) return boolean; @@ -52,12 +48,12 @@ package components is function ffrs(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic; -- RS-FlipFlop with dominant rst function ffsr(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic; -- RS-FlipFlop with dominant set -- D-FlipFlops (Delay) - function ffdre(q : std_logic; d : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic; -- D-FlipFlop with reset and enable + function ffdre(q : std_logic; d : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic; -- D-FlipFlop with reset and enable function ffdre(q : std_logic_vector; d : std_logic_vector; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic_vector := (0 to 0 => '0')) return std_logic_vector; -- D-FlipFlop with reset and enable - function ffdse(q : std_logic; d : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic; -- D-FlipFlop with set and enable + function ffdse(q : std_logic; d : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic; -- D-FlipFlop with set and enable -- T-FlipFlops (Toggle) - function fftre(q : std_logic; t : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic; -- T-FlipFlop with reset and enable - function fftse(q : std_logic; t : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic; -- T-FlipFlop with set and enable + function fftre(q : std_logic; t : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic; -- T-FlipFlop with reset and enable + function fftse(q : std_logic; t : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic; -- T-FlipFlop with set and enable -- counter function upcounter_next( cnt : unsigned; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : natural := 0) return unsigned; diff --git a/src/common/config.vhdl b/src/common/config.vhdl index b4f492936..d7647ee2a 100644 --- a/src/common/config.vhdl +++ b/src/common/config.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel @@ -16,7 +13,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/common/debug.vhdl b/src/common/debug.vhdl index d4f240481..3f50674ba 100644 --- a/src/common/debug.vhdl +++ b/src/common/debug.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel diff --git a/src/common/math.vhdl b/src/common/math.vhdl index bd4891306..ac3081532 100644 --- a/src/common/math.vhdl +++ b/src/common/math.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- @@ -149,7 +146,7 @@ package body math is elsif (numerator +1) = denominator then denominator := denominator + 1; else - numerator := numerator + 1; + numerator := numerator + 1; end if; newFraction := real(numerator) / real(denominator); diff --git a/src/common/physical.vhdl b/src/common/physical.vhdl index 159351f3d..2b6390e67 100644 --- a/src/common/physical.vhdl +++ b/src/common/physical.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Martin Zabel @@ -35,7 +32,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- diff --git a/src/common/protected.v08.vhdl b/src/common/protected.v08.vhdl index 6f21b013e..6d7122957 100644 --- a/src/common/protected.v08.vhdl +++ b/src/common/protected.v08.vhdl @@ -31,11 +31,6 @@ library IEEE; use IEEE.math_real.all; -library PoC; --- use work.my_project.all; --- use work.utils.all; - - package ProtectedTypes is -- protected BOOLEAN implementation -- =========================================================================== diff --git a/src/common/strings.vhdl b/src/common/strings.vhdl index a31fa8b1c..25e74dad6 100644 --- a/src/common/strings.vhdl +++ b/src/common/strings.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel @@ -15,7 +12,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- @@ -66,31 +63,31 @@ package strings is function to_IPStyle(str : string) return T_IPSTYLE; -- to_char - function to_char(Value : std_logic) return character; + function to_char(Value : std_logic) return character; function to_char(rawchar : T_RAWCHAR) return character; function to_HexChar(Value : natural) return character; - function to_HexChar(Value : unsigned) return character; + function to_HexChar(Value : unsigned) return character; -- chr_is* function function chr_isDigit(chr : character) return boolean; function chr_isLowerHexDigit(chr : character) return boolean; function chr_isUpperHexDigit(chr : character) return boolean; - function chr_isHexDigit(chr : character) return boolean; + function chr_isHexDigit(chr : character) return boolean; function chr_isLower(chr : character) return boolean; - function chr_isLowerAlpha(chr : character) return boolean; + function chr_isLowerAlpha(chr : character) return boolean; function chr_isUpper(chr : character) return boolean; - function chr_isUpperAlpha(chr : character) return boolean; + function chr_isUpperAlpha(chr : character) return boolean; function chr_isAlpha(chr : character) return boolean; -- raw_format_* functions - function raw_format_bool_bin(Value : boolean) return string; - function raw_format_bool_chr(Value : boolean) return string; - function raw_format_bool_str(Value : boolean) return string; - function raw_format_slv_bin(slv : std_logic_vector) return string; - function raw_format_slv_oct(slv : std_logic_vector) return string; + function raw_format_bool_bin(Value : boolean) return string; + function raw_format_bool_chr(Value : boolean) return string; + function raw_format_bool_str(Value : boolean) return string; + function raw_format_slv_bin(slv : std_logic_vector) return string; + function raw_format_slv_oct(slv : std_logic_vector) return string; function raw_format_slv_dec(slv : std_logic_vector) return string; - function raw_format_slv_hex(slv : std_logic_vector) return string; + function raw_format_slv_hex(slv : std_logic_vector) return string; function raw_format_nat_bin(Value : natural) return string; function raw_format_nat_oct(Value : natural) return string; function raw_format_nat_dec(Value : natural) return string; @@ -101,7 +98,7 @@ package strings is -- to_string function to_string(Value : boolean) return string; - function to_string(Value : integer; base : positive) return string; + function to_string(Value : integer; base : positive := 10) return string; -- Do not initialize base to 10. This causes signature overlap to to_string from std packages function to_string(slv : std_logic_vector; format : character := 'h'; Length : natural := 0; fill : character := '0') return string; function to_string(slv : unsigned; format : character := 'h'; Length : natural := 0; fill : character := '0') return string; function to_string(rawstring : T_RAWSTRING) return string; @@ -132,11 +129,11 @@ package strings is -- to_raw* function to_RawChar(char : character) return T_RAWCHAR; - function to_RawString(str : string) return T_RAWSTRING; + function to_RawString(str : string) return T_RAWSTRING; -- resize - function resize(str : string; size : positive; FillChar : character := C_POC_NUL) return string; --- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING; + function resize(str : string; size : positive; FillChar : character := C_POC_NUL) return string; +-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING; -- Character functions function chr_toLower(chr : character) return character; @@ -145,19 +142,19 @@ package strings is -- String functions function str_low(str : string) return integer; function str_normalize(str : string) return string; - function str_length(str : string) return natural; + function str_length(str : string) return natural; function str_equal(str1 : string; str2 : string) return boolean; function str_match(str1 : string; str2 : string) return boolean; - function str_imatch(str1 : string; str2 : string) return boolean; - function str_pos(str : string; chr : character; start : natural := 0) return integer; + function str_imatch(str1 : string; str2 : string) return boolean; + function str_pos(str : string; chr : character; start : natural := 0) return integer; function str_pos(str : string; pattern : string; start : natural := 0) return integer; function str_ipos(str : string; chr : character; start : natural := 0) return integer; - function str_ipos(str : string; pattern : string; start : natural := 0) return integer; + function str_ipos(str : string; pattern : string; start : natural := 0) return integer; function str_find(str : string; chr : character) return boolean; - function str_find(str : string; pattern : string) return boolean; - function str_ifind(str : string; chr : character) return boolean; + function str_find(str : string; pattern : string) return boolean; + function str_ifind(str : string; chr : character) return boolean; function str_ifind(str : string; pattern : string) return boolean; - function str_replace(str : string; pattern : string; replace : string) return string; + function str_replace(str : string; pattern : string; replace : string) return string; function str_replace_all(str : string; pattern : character; replace : character) return string; function str_substr(str : string; start : integer := 0; Length : integer := 0) return string; function str_ltrim(str : string; char : character := ' ') return string; @@ -209,15 +206,15 @@ package body strings is function to_char(Value : std_logic) return character is begin case Value is - when 'U' => return 'U'; - when 'X' => return 'X'; - when '0' => return '0'; - when '1' => return '1'; - when 'Z' => return 'Z'; - when 'W' => return 'W'; - when 'L' => return 'L'; - when 'H' => return 'H'; - when '-' => return '-'; + when 'U' => return 'U'; + when 'X' => return 'X'; + when '0' => return '0'; + when '1' => return '1'; + when 'Z' => return 'Z'; + when 'W' => return 'W'; + when 'L' => return 'L'; + when 'H' => return 'H'; + when '-' => return '-'; when others => return 'X'; end case; end function; @@ -304,7 +301,7 @@ package body strings is function raw_format_slv_bin(slv : std_logic_vector) return string is variable Value : std_logic_vector(slv'length - 1 downto 0); - variable Result : string(1 to slv'length); + variable Result : string(1 to slv'length); variable j : natural; begin -- convert input slv to a downto ranged vector and normalize range to slv'low = 0 @@ -321,7 +318,7 @@ package body strings is function raw_format_slv_oct(slv : std_logic_vector) return string is variable Value : std_logic_vector(slv'length - 1 downto 0); variable Digit : std_logic_vector(2 downto 0); - variable Result : string(1 to div_ceil(slv'length, 3)); + variable Result : string(1 to div_ceil(slv'length, 3)); variable j : natural; begin -- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3 @@ -339,10 +336,10 @@ package body strings is function raw_format_slv_dec(slv : std_logic_vector) return string is variable Value : std_logic_vector(slv'length - 1 downto 0); - variable Result : string(1 to div_ceil(slv'length, 3)); + variable Result : string(1 to div_ceil(slv'length, 3)); subtype TT_BCD is integer range 0 to 31; - type TT_BCD_VECTOR is array(natural range <>) of TT_BCD; + type TT_BCD_VECTOR is array(natural range <>) of TT_BCD; variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0); variable Carry : T_UINT_8; @@ -358,7 +355,7 @@ package body strings is Carry := to_int(Value(i)); for j in Temp'reverse_range loop Temp(j) := Temp(j) * 2 + Carry; - Carry := to_int(Temp(j) > 9); + Carry := to_int( Temp(j) > 9); Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10); end loop; end loop; @@ -376,7 +373,7 @@ package body strings is function raw_format_slv_hex(slv : std_logic_vector) return string is variable Value : std_logic_vector(4*div_ceil(slv'length, 4) - 1 downto 0); variable Digit : std_logic_vector(3 downto 0); - variable Result : string(1 to div_ceil(slv'length, 4)); + variable Result : string(1 to div_ceil(slv'length, 4)); variable j : natural; begin Value := resize(slv, Value'length); @@ -414,12 +411,12 @@ package body strings is function str_format(Value : REAL; precision : natural := 3) return string is constant s : REAL := sign(Value); constant val : REAL := Value * s; - constant int : integer := integer(floor(val)); - constant frac : integer := integer(round((val - real(int)) * 10.0**precision)); + constant int : integer := integer(floor(val)); + constant frac : integer := integer(round((val - real(int)) * 10.0**precision)); constant overflow : boolean := frac >= 10**precision; constant int2 : integer := ite(overflow, int+1, int); constant frac2 : integer := ite(overflow, frac-10**precision, frac); - constant frac_str : string := integer'image(frac2); + constant frac_str : string := integer'image(frac2); constant res : string := integer'image(int2) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str; begin return ite ((s < 0.0), "-" & res, res); @@ -459,18 +456,18 @@ package body strings is -- QUESTION: rename to slv_format(..) ? function to_string(slv : std_logic_vector; format : character := 'h'; Length : natural := 0; fill : character := '0') return string is - constant int : integer := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0); + constant int : integer := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0); constant str : string := integer'image(int); constant bin_len : positive := slv'length; constant dec_len : positive := str'length;--log10ceilnz(int); constant hex_len : positive := ite(((bin_len mod 4) = 0), (bin_len / 4), (bin_len / 4) + 1); - constant len : natural := ite((format = 'b'), bin_len, + constant len : natural := ite((format = 'b'), bin_len, ite((format = 'd'), dec_len, ite((format = 'h'), hex_len, 0))); variable j : natural; - variable Result : string(1 to ite((Length = 0), len, imax(len, Length))); + variable Result : string(1 to ite((Length = 0), len, imax(len, Length))); begin - j := 0; + j := 0; Result := (others => fill); if (format = 'b') then @@ -480,12 +477,12 @@ package body strings is end loop; elsif (format = 'd') then -- TODO: enable big integer conversion --- if (slv'length < 32) then --- return INTEGER'image(int); --- else --- return raw_format_slv_dec(slv); --- end if; - Result(Result'length - str'length + 1 to Result'high) := str; +-- if (slv'length < 32) then +-- return INTEGER'image(int); +-- else +-- return raw_format_slv_dec(slv); +-- end if; + Result(Result'length - str'length + 1 to Result'high) := str; elsif (format = 'h') then for i in Result'reverse_range loop Result(i) := to_HexChar(unsigned(slv(imin((j * 4) + 3 + slv'low, slv'high) downto (j * 4) + slv'low))); @@ -538,8 +535,8 @@ package body strings is function to_digit_bin(chr : character) return T_DIGIT_BIN is begin case chr is - when '0' => return 0; - when '1' => return 1; + when '0' => return 0; + when '1' => return 1; when others => return -1; end case; end function; @@ -566,8 +563,8 @@ package body strings is function to_digit_hex(chr : character) return T_DIGIT_HEX is begin if chr_isDigit(chr) then return character'pos(chr) - CHARACTER'pos('0'); - elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('a') + 10; - elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('A') + 10; + elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('a') + 10; + elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('A') + 10; else return -1; end if; end function; @@ -576,10 +573,10 @@ package body strings is function to_digit(chr : character; base : character := 'd') return integer is begin case base is - when 'b' => return to_digit_bin(chr); - when 'o' => return to_digit_oct(chr); - when 'd' => return to_digit_dec(chr); - when 'h' => return to_digit_hex(chr); + when 'b' => return to_digit_bin(chr); + when 'o' => return to_digit_oct(chr); + when 'd' => return to_digit_dec(chr); + when 'h' => return to_digit_hex(chr); when others => report "Unknown base character: " & base & "." severity FAILURE; return -1; end case; @@ -589,7 +586,7 @@ package body strings is -- =========================================================================== -- convert a binary number given as STRING to a NATURAL; return -1 on error function to_natural_bin(str : string) return integer is - variable Result : natural; + variable Result : natural; variable Digit : integer; begin for i in str'range loop @@ -605,7 +602,7 @@ package body strings is -- convert an octal number given as STRING to a NATURAL; return -1 on error function to_natural_oct(str : string) return integer is - variable Result : natural; + variable Result : natural; variable Digit : integer; begin for i in str'range loop @@ -621,7 +618,7 @@ package body strings is -- convert a decimal number given as STRING to a NATURAL; return -1 on error function to_natural_dec(str : string) return integer is - variable Result : natural; + variable Result : natural; variable Digit : integer; begin -- WORKAROUND: Xilinx Vivado Synth @@ -643,7 +640,7 @@ package body strings is -- convert a hexadecimal number given as STRING to a NATURAL; return -1 on error function to_natural_hex(str : string) return integer is - variable Result : natural; + variable Result : natural; variable Digit : integer; begin for i in str'range loop @@ -804,9 +801,9 @@ package body strings is else return false; end if; --- return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal --- ((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len --- ((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len +-- return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal +-- ((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len +-- ((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len end function; -- compare two POC_NUL terminated STRINGs; case insentitve @@ -945,10 +942,10 @@ package body strings is -- input string: "Hello World." -- low=1; high=12; length=12 -- - -- str_substr("Hello World.", 0, 0) => "Hello World." - copy all - -- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string + -- str_substr("Hello World.", 0, 0) => "Hello World." - copy all + -- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string -- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters - -- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary + -- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary function str_substr(str : string; start : integer := 0; Length : integer := 0) return string is variable StartOfString : positive; variable EndOfString : positive; @@ -970,7 +967,7 @@ package body strings is end if; if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity FAILURE; end if; - if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity FAILURE; end if; + if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity FAILURE; end if; return str(StartOfString to EndOfString); end function; @@ -1006,7 +1003,7 @@ package body strings is -- center-align a STRING str in a FillChar filled STRING of length Length function str_calign(str : string; Length : natural; FillChar : character := ' ') return string is constant Start : positive := (Length - str'length) / 2; - variable Result : string(1 to Length); + variable Result : string(1 to Length); begin Result := (others => FillChar); Result(Start to (Start + str'length)) := str; diff --git a/src/common/utils.vhdl b/src/common/utils.vhdl index 323964add..d7dd927e6 100644 --- a/src/common/utils.vhdl +++ b/src/common/utils.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel @@ -15,7 +12,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/common/vectors.vhdl b/src/common/vectors.vhdl index 59f4a7c1f..07f900920 100644 --- a/src/common/vectors.vhdl +++ b/src/common/vectors.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel @@ -15,7 +12,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/dstruct/dstruct.pkg.vhdl b/src/dstruct/dstruct.pkg.vhdl index 4cf10013f..ac97d171c 100644 --- a/src/dstruct/dstruct.pkg.vhdl +++ b/src/dstruct/dstruct.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Jens Voss -- diff --git a/src/dstruct/dstruct.pro b/src/dstruct/dstruct.pro index 820205858..aff0f9992 100644 --- a/src/dstruct/dstruct.pro +++ b/src/dstruct/dstruct.pro @@ -4,5 +4,6 @@ # ============================================================================= analyze dstruct.pkg.vhdl -analyze dstruct_deque.vhdl +disabled dstruct_deque.vhdl +disabled dstruct_OutOfOrder_buffer.vhdl analyze dstruct_stack.vhdl diff --git a/src/dstruct/dstruct_deque.vhdl b/src/dstruct/dstruct_deque.vhdl index 4ad2e7a77..d67cdaa48 100644 --- a/src/dstruct/dstruct_deque.vhdl +++ b/src/dstruct/dstruct_deque.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Jens Voss -- diff --git a/src/dstruct/dstruct_stack.vhdl b/src/dstruct/dstruct_stack.vhdl index d3a907e9c..14a054971 100644 --- a/src/dstruct/dstruct_stack.vhdl +++ b/src/dstruct/dstruct_stack.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Jens Voss -- diff --git a/src/fifo/fifo.pkg.vhdl b/src/fifo/fifo.pkg.vhdl index ad7e31d57..0e7d866e9 100644 --- a/src/fifo/fifo.pkg.vhdl +++ b/src/fifo/fifo.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Steffen Koehler diff --git a/src/fifo/fifo.pro b/src/fifo/fifo.pro index 1b1922a67..2be3b9fbb 100644 --- a/src/fifo/fifo.pro +++ b/src/fifo/fifo.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -21,9 +21,12 @@ analyze fifo.pkg.vhdl analyze fifo_shift.vhdl +disabled fifo_stageFar.vhdl analyze fifo_stage.vhdl analyze fifo_ic_got.vhdl analyze fifo_ic_assembly.vhdl analyze fifo_cc_got.vhdl +disabled fifo_cc_got_commit.vhdl analyze fifo_cc_got_tempgot.vhdl analyze fifo_cc_got_tempput.vhdl +disabled fifo_cc_got_tempput_pipelined.vhdl diff --git a/src/fifo/fifo_cc_got.vhdl b/src/fifo/fifo_cc_got.vhdl index 76bccac66..425d43dae 100644 --- a/src/fifo/fifo_cc_got.vhdl +++ b/src/fifo/fifo_cc_got.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Steffen Koehler @@ -70,7 +67,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/fifo/fifo_cc_got_tempgot.vhdl b/src/fifo/fifo_cc_got_tempgot.vhdl index cc174cc71..1f00aac61 100644 --- a/src/fifo/fifo_cc_got_tempgot.vhdl +++ b/src/fifo/fifo_cc_got_tempgot.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Steffen Koehler @@ -57,7 +54,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2014 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/fifo/fifo_cc_got_tempput.vhdl b/src/fifo/fifo_cc_got_tempput.vhdl index 9d9a45d89..fd427f130 100644 --- a/src/fifo/fifo_cc_got_tempput.vhdl +++ b/src/fifo/fifo_cc_got_tempput.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Steffen Koehler @@ -57,7 +54,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2014 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- @@ -85,7 +82,7 @@ use work.ocram.ocram_sdp; entity fifo_cc_got_tempput is generic ( - RAM_TYPE : T_RAM_TYPE := RAM_TYPE_OPTIMIZED;--RAM_TYPE_AUTO; + RAM_TYPE : T_RAM_TYPE := RAM_TYPE_OPTIMIZED;--RAM_TYPE_AUTO; D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers @@ -165,21 +162,19 @@ begin OP0_slv <= std_logic_vector(OP0); incIP : entity work.arith_carrychain_inc - generic map( + generic map ( BITS => A_BITS ) - port map - ( + port map ( X => IP0_slv, Y => IP1_slv ); incOP : entity work.arith_carrychain_inc - generic map( + generic map ( BITS => A_BITS ) - port map - ( + port map ( X => OP0_slv, Y => OP1_slv ); @@ -318,13 +313,12 @@ begin -- Backing Memory ram : entity work.ocram_sdp_optimized - generic map( + generic map ( RAM_TYPE => RAM_TYPE, A_BITS => A_BITS, D_BITS => D_BITS ) - port map - ( + port map ( wclk => clk, rclk => clk, wce => '1', diff --git a/src/fifo/fifo_ic_assembly.vhdl b/src/fifo/fifo_ic_assembly.vhdl index d5dd7ad9a..d81aabf14 100644 --- a/src/fifo/fifo_ic_assembly.vhdl +++ b/src/fifo/fifo_ic_assembly.vhdl @@ -1,8 +1,5 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Thomas B. Preusser +-- Authors: Thomas B. Preusser -- -- Entity: Address-based FIFO stream assembly, independent clocks (ic) -- @@ -44,9 +41,9 @@ use IEEE.std_logic_1164.all; entity fifo_ic_assembly is generic ( - D_BITS : positive; -- Data Width - A_BITS : positive; -- Address Bits - G_BITS : positive -- Generation Guard Bits + D_BITS : positive; -- Data Width + A_BITS : positive; -- Address Bits + G_BITS : positive -- Generation Guard Bits ); port ( -- Write Interface diff --git a/src/fifo/fifo_ic_got.vhdl b/src/fifo/fifo_ic_got.vhdl index c96efee27..c04202c1e 100644 --- a/src/fifo/fifo_ic_got.vhdl +++ b/src/fifo/fifo_ic_got.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Steffen Koehler @@ -50,7 +47,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/fifo/fifo_shift.vhdl b/src/fifo/fifo_shift.vhdl index 216234763..0bf3d2d16 100644 --- a/src/fifo/fifo_shift.vhdl +++ b/src/fifo/fifo_shift.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Stefan Unrein @@ -19,7 +16,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/fifo/fifo_stage.vhdl b/src/fifo/fifo_stage.vhdl index dccb9b696..66acf19f0 100644 --- a/src/fifo/fifo_stage.vhdl +++ b/src/fifo/fifo_stage.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Stefan Unrein @@ -15,7 +12,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- @@ -33,7 +30,7 @@ -- ============================================================================= library IEEE; -use IEEE.std_logic_1164.all; +use IEEE.std_logic_1164.all; entity fifo_Stage is generic ( @@ -43,35 +40,36 @@ entity fifo_Stage is ); port ( -- Control - clk : in std_logic; -- Clock - rst : in std_logic; -- Synchronous Reset + clk : in std_logic; -- Clock + rst : in std_logic; -- Synchronous Reset -- Input - put : in std_logic; -- Put Value - di : in std_logic_vector(D_BITS - 1 downto 0); -- Data Input - ful : out std_logic; -- Full + put : in std_logic; -- Put Value + di : in std_logic_vector(D_BITS - 1 downto 0); -- Data Input + ful : out std_logic; -- Full -- Output vld : out std_logic; -- Data Available do : out std_logic_vector(D_BITS - 1 downto 0); -- Data Output - got : in std_logic -- Data Consumed + got : in std_logic -- Data Consumed ); end entity fifo_Stage; + architecture rtl of fifo_Stage is begin - + passthroughGen : if STAGES > 0 generate subtype T_slv_d is std_logic_vector(D_BITS - 1 downto 0); type T_slvv_d is array(natural range <>) of T_slv_d; - + signal di_v : T_slvv_d(0 to STAGES - 1);-- := (others => (others => '0')); signal do_v : T_slvv_d(0 to STAGES - 1);-- := (others => (others => '0')); - + signal Avail_v : std_logic_vector(0 to STAGES - 1); signal Full_v : std_logic_vector(0 to STAGES - 1); - - signal put_v : std_logic_vector(0 to STAGES - 1); - signal got_v : std_logic_vector(0 to STAGES - 1); + + signal put_v : std_logic_vector(0 to STAGES - 1); + signal got_v : std_logic_vector(0 to STAGES - 1); begin ful <= Full_v(0); vld <= Avail_v(Avail_v'high); @@ -126,40 +124,40 @@ begin do_v(i) <= B; end generate; else generate - genStage : for i in 0 to STAGES - 1 generate - signal A : T_slv_d := (others => '0'); - signal B : T_slv_d := (others => '0'); - - signal Avail : std_logic := '0'; - signal Full : std_logic := '0'; + genStage : for i in 0 to STAGES - 1 generate + signal A : T_slv_d := (others => '0'); + signal B : T_slv_d := (others => '0'); + + signal Avail : std_logic := '0'; + signal Full : std_logic := '0'; + begin + + process(clk) begin - - process (clk) - begin - if rising_edge(clk) then - if rst = '1' then - Avail <= '0'; + if rising_edge(clk) then + if rst = '1' then + Avail <= '0'; + else + if Avail = '1' then + Avail <= not got_v(i); else - if Avail = '1' then - Avail <= not got_v(i); - else - Avail <= put_v(i); - end if; + Avail <= put_v(i); end if; end if; - end process; - - B <= di_v(i) when rising_edge(clk) and Avail = '0'; - - Full_v(i) <= Avail; - Avail_v(i) <= Avail; - do_v(i) <= B; - end generate; - end generate; - else generate - ful <= not got; - vld <= put; - do <= di; + end if; + end process; + + B <= di_v(i) when rising_edge(clk) and Avail = '0'; + + Full_v(i) <= Avail; + Avail_v(i) <= Avail; + do_v(i) <= B; end generate; + end generate; + else generate + ful <= not got; + vld <= put; + do <= di; + end generate; - end architecture; +end architecture; diff --git a/src/io/ddrio/ddrio.pkg.vhdl b/src/io/ddrio/ddrio.pkg.vhdl index d00032ed6..3bb108d37 100644 --- a/src/io/ddrio/ddrio.pkg.vhdl +++ b/src/io/ddrio/ddrio.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/io/ddrio/ddrio_in.vhdl b/src/io/ddrio/ddrio_in.vhdl index 42b28bfa7..dd7b44e27 100644 --- a/src/io/ddrio/ddrio_in.vhdl +++ b/src/io/ddrio/ddrio_in.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/io/ddrio/ddrio_in_altera.vhdl b/src/io/ddrio/ddrio_in_altera.vhdl index 904eca15c..c61500f0d 100644 --- a/src/io/ddrio/ddrio_in_altera.vhdl +++ b/src/io/ddrio/ddrio_in_altera.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/io/ddrio/ddrio_in_xilinx.vhdl b/src/io/ddrio/ddrio_in_xilinx.vhdl index 484f65cfd..c2910f5da 100644 --- a/src/io/ddrio/ddrio_in_xilinx.vhdl +++ b/src/io/ddrio/ddrio_in_xilinx.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/io/ddrio/ddrio_inout.vhdl b/src/io/ddrio/ddrio_inout.vhdl index cf28d5f08..5f1977376 100644 --- a/src/io/ddrio/ddrio_inout.vhdl +++ b/src/io/ddrio/ddrio_inout.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/io/ddrio/ddrio_inout_altera.vhdl b/src/io/ddrio/ddrio_inout_altera.vhdl index 60814ea6c..3d7e51162 100644 --- a/src/io/ddrio/ddrio_inout_altera.vhdl +++ b/src/io/ddrio/ddrio_inout_altera.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/io/ddrio/ddrio_inout_xilinx.vhdl b/src/io/ddrio/ddrio_inout_xilinx.vhdl index 047c774c9..e77964477 100644 --- a/src/io/ddrio/ddrio_inout_xilinx.vhdl +++ b/src/io/ddrio/ddrio_inout_xilinx.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/io/ddrio/ddrio_out.vhdl b/src/io/ddrio/ddrio_out.vhdl index e428c2d7c..940f34732 100644 --- a/src/io/ddrio/ddrio_out.vhdl +++ b/src/io/ddrio/ddrio_out.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/io/ddrio/ddrio_out_altera.vhdl b/src/io/ddrio/ddrio_out_altera.vhdl index afa15635c..2702584e5 100644 --- a/src/io/ddrio/ddrio_out_altera.vhdl +++ b/src/io/ddrio/ddrio_out_altera.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/io/ddrio/ddrio_out_xilinx.vhdl b/src/io/ddrio/ddrio_out_xilinx.vhdl index f79d0c202..361a1a39b 100644 --- a/src/io/ddrio/ddrio_out_xilinx.vhdl +++ b/src/io/ddrio/ddrio_out_xilinx.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/io/fan/fan.pro b/src/io/fan/fan.pro new file mode 100644 index 000000000..f75c77dd9 --- /dev/null +++ b/src/io/fan/fan.pro @@ -0,0 +1,12 @@ +# ============================================================================= +# Authors: Adrian Weiland +# +# +# License: +# ============================================================================= +# Copyright (c) 2024 PLC2 Design GmbH - All Rights Reserved +# Unauthorized copying of this file, via any medium is strictly prohibited. +# Proprietary and confidential +# ============================================================================= + +analyze fan_TachoCalculator.vhdl diff --git a/src/io/iic/iic.pkg.vhdl b/src/io/iic/iic.pkg.vhdl index f8c7715f5..1493cd93d 100644 --- a/src/io/iic/iic.pkg.vhdl +++ b/src/io/iic/iic.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/io/iic/iic.pro b/src/io/iic/iic.pro index 4368215ff..617bd15e3 100644 --- a/src/io/iic/iic.pro +++ b/src/io/iic/iic.pro @@ -3,7 +3,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -19,3 +19,11 @@ # ============================================================================= analyze ./iic.pkg.vhdl +analyze ./iic_BusController.vhdl +analyze ./iic_Controller.vhdl +# analyze ./iic_Controller_SFF8431.vhdl # Curently not working +# analyze ./iic_IICSwitch_PCA9548A.vhdl # Curently not working +# analyze ./iic_IOB_Pad.vhdl # Curently not working +analyze ./iic_Passthrough.vhdl +analyze ./iic_RawDemux.vhdl +analyze ./iic_RawMux.vhdl diff --git a/src/io/io.pkg.vhdl b/src/io/io.pkg.vhdl index 12f2923ff..cf95b6798 100644 --- a/src/io/io.pkg.vhdl +++ b/src/io/io.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -13,7 +10,8 @@ -- -- License: -- ============================================================================= --- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- Copyright 2025-2026 The PoC-Library Authors +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -123,31 +121,31 @@ package io is type T_IO_7SEGMENT_CHAR_ENCODING is array(T_IO_7SEGMENT_CHAR) of std_logic_vector(6 downto 0); --constant C_IO_7SEGMENT_CHAR_ENCODING : T_IO_7SEGMENT_CHAR_ENCODING := ( - --IO_7SEGMENT_CHAR_0 - --IO_7SEGMENT_CHAR_1 - --IO_7SEGMENT_CHAR_2 - --IO_7SEGMENT_CHAR_3 - --IO_7SEGMENT_CHAR_4 - --IO_7SEGMENT_CHAR_5 - --IO_7SEGMENT_CHAR_6 - --IO_7SEGMENT_CHAR_7 - --IO_7SEGMENT_CHAR_8 - --IO_7SEGMENT_CHAR_9 - --IO_7SEGMENT_CHAR_A - --IO_7SEGMENT_CHAR_B - --IO_7SEGMENT_CHAR_C - --IO_7SEGMENT_CHAR_D - --IO_7SEGMENT_CHAR_E - --IO_7SEGMENT_CHAR_F - --IO_7SEGMENT_CHAR_H - --IO_7SEGMENT_CHAR_O - --IO_7SEGMENT_CHAR_U - --IO_7SEGMENT_CHAR_MINUS + --IO_7SEGMENT_CHAR_0 + --IO_7SEGMENT_CHAR_1 + --IO_7SEGMENT_CHAR_2 + --IO_7SEGMENT_CHAR_3 + --IO_7SEGMENT_CHAR_4 + --IO_7SEGMENT_CHAR_5 + --IO_7SEGMENT_CHAR_6 + --IO_7SEGMENT_CHAR_7 + --IO_7SEGMENT_CHAR_8 + --IO_7SEGMENT_CHAR_9 + --IO_7SEGMENT_CHAR_A + --IO_7SEGMENT_CHAR_B + --IO_7SEGMENT_CHAR_C + --IO_7SEGMENT_CHAR_D + --IO_7SEGMENT_CHAR_E + --IO_7SEGMENT_CHAR_F + --IO_7SEGMENT_CHAR_H + --IO_7SEGMENT_CHAR_O + --IO_7SEGMENT_CHAR_U + --IO_7SEGMENT_CHAR_MINUS --); function io_7SegmentDisplayEncoding(hex : std_logic_vector(3 downto 0); dot : std_logic := '0'; WITH_DOT : boolean := FALSE) return std_logic_vector; function io_7SegmentDisplayEncoding(digit : T_BCD; dot : std_logic := '0'; WITH_DOT : boolean := FALSE) return std_logic_vector; - + --------------------------------------------------------------------- -- MDIOController --------------------------------------------------------------------- @@ -226,10 +224,11 @@ package io is end component; end package; + package body io is function get_i_vector(vec : T_IO_TRISTATE_VECTOR) return std_logic_vector is - variable temp : std_logic_vector(vec'range); + variable temp : std_logic_vector(vec'range); begin for i in vec'range loop temp(i) := vec(i).i; @@ -237,8 +236,8 @@ package body io is return temp; end function; - function get_i_vector(vec : T_IO_TRISTATE_IN_VECTOR) return std_logic_vector is - variable temp : std_logic_vector(vec'range); + function get_i_vector(vec : T_IO_TRISTATE_IN_VECTOR) return std_logic_vector is + variable temp : std_logic_vector(vec'range); begin for i in vec'range loop temp(i) := vec(i).i; @@ -246,8 +245,8 @@ package body io is return temp; end function; - function get_o_vector(vec : T_IO_TRISTATE_VECTOR) return std_logic_vector is - variable temp : std_logic_vector(vec'range); + function get_o_vector(vec : T_IO_TRISTATE_VECTOR) return std_logic_vector is + variable temp : std_logic_vector(vec'range); begin for i in vec'range loop temp(i) := vec(i).o; @@ -256,7 +255,7 @@ package body io is end function; function get_o_vector(vec : T_IO_TRISTATE_OUT_VECTOR) return std_logic_vector is - variable temp : std_logic_vector(vec'range); + variable temp : std_logic_vector(vec'range); begin for i in vec'range loop temp(i) := vec(i).o; @@ -264,8 +263,8 @@ package body io is return temp; end function; - function get_t_vector(vec : T_IO_TRISTATE_VECTOR) return std_logic_vector is - variable temp : std_logic_vector(vec'range); + function get_t_vector(vec : T_IO_TRISTATE_VECTOR) return std_logic_vector is + variable temp : std_logic_vector(vec'range); begin for i in vec'range loop temp(i) := vec(i).t; @@ -274,7 +273,7 @@ package body io is end function; function get_t_vector(vec : T_IO_TRISTATE_OUT_VECTOR) return std_logic_vector is - variable temp : std_logic_vector(vec'range); + variable temp : std_logic_vector(vec'range); begin for i in vec'range loop temp(i) := vec(i).t; @@ -283,7 +282,7 @@ package body io is end function; function to_IO_TRISTATE_IN_VECTOR(i : std_logic_vector) return T_IO_TRISTATE_IN_VECTOR is - variable temp : T_IO_TRISTATE_IN_VECTOR(i'range); + variable temp : T_IO_TRISTATE_IN_VECTOR(i'range); begin for k in i'range loop temp(k).i := i(k); @@ -301,8 +300,9 @@ package body io is end loop; return temp; end function; + function get_p_vector(vec : T_IO_LVDS_VECTOR) return std_logic_vector is - variable temp : std_logic_vector(vec'range); + variable temp : std_logic_vector(vec'range); begin for i in vec'range loop temp(i) := vec(i).p; @@ -311,7 +311,7 @@ package body io is end function; function get_n_vector(vec : T_IO_LVDS_VECTOR) return std_logic_vector is - variable temp : std_logic_vector(vec'range); + variable temp : std_logic_vector(vec'range); begin for i in vec'range loop temp(i) := vec(i).n; @@ -400,4 +400,4 @@ package body io is end loop; return FALSE; end function; -end package body; \ No newline at end of file +end package body; diff --git a/src/io/io.pro b/src/io/io.pro index ddafc1822..c22e519f0 100644 --- a/src/io/io.pro +++ b/src/io/io.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -46,15 +46,18 @@ if { $::poc::vendor eq "Xilinx" } { analyze ./ddrio/ddrio_out_altera.vhdl } elseif { $::poc::vendor ne "GENERIC" } { - puts "Unknow vendor '$::poc::vendor' in arith!" + puts "Unknown vendor '$::poc::vendor'!" exit 1 } +disabled ./spi/spi.pro include ./uart/uart.pro -include ./iic/iic.pro +disabled ./iic/iic.pro +disabled ./fan/fan.pro analyze ./pmod/pmod.pkg.vhdl analyze ./pmod/pmod_KYPD.vhdl analyze ./pmod/pmod_SSD.vhdl -analyze ./pmod/pmod_USBUART.vhdl - +disabled ./pmod/pmod_USBUART.vhdl +disabled ./jtag/jtag.pkg.vhdl +disabled ./led/led.pkg.vhdl diff --git a/src/io/io_7SegmentMux_BCD.vhdl b/src/io/io_7SegmentMux_BCD.vhdl index 1f864d78e..46ed793f0 100644 --- a/src/io/io_7SegmentMux_BCD.vhdl +++ b/src/io/io_7SegmentMux_BCD.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -16,7 +13,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/io/io_7SegmentMux_HEX.vhdl b/src/io/io_7SegmentMux_HEX.vhdl index 2e92dc3fa..392bfb2ba 100644 --- a/src/io/io_7SegmentMux_HEX.vhdl +++ b/src/io/io_7SegmentMux_HEX.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/io/io_Debounce.vhdl b/src/io/io_Debounce.vhdl index 00a9260d4..5f481a6e3 100644 --- a/src/io/io_Debounce.vhdl +++ b/src/io/io_Debounce.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Thomas B. Preusser @@ -49,20 +46,20 @@ use work.physical.all; entity io_Debounce is - generic ( - CLOCK_FREQ : FREQ; - BOUNCE_TIME : t_time; - BITS : positive := 1; - INIT : std_logic_vector := x"00000000"; -- initial state of Output - ADD_INPUT_SYNCHRONIZERS : boolean := true; - COMMON_LOCK : boolean := false - ); - port ( - Clock : in std_logic; - Reset : in std_logic := '0'; - Input : in std_logic_vector(BITS-1 downto 0); - Output : out std_logic_vector(BITS-1 downto 0) := resize(descend(INIT), BITS) - ); + generic ( + CLOCK_FREQ : FREQ; + BOUNCE_TIME : t_time; + BITS : positive := 1; + INIT : std_logic_vector := x"00000000"; -- initial state of Output + ADD_INPUT_SYNCHRONIZERS : boolean := true; + COMMON_LOCK : boolean := false + ); + port ( + Clock : in std_logic; + Reset : in std_logic := '0'; + Input : in std_logic_vector(BITS - 1 downto 0); + Output : out std_logic_vector(BITS - 1 downto 0) := resize(descend(INIT), BITS) + ); end entity; @@ -71,28 +68,28 @@ architecture rtl of io_Debounce is constant LOCK_COUNT_X : integer := TimingToCycles(BOUNCE_TIME, CLOCK_FREQ) - 1; -- Input Refinements - signal sync : std_logic_vector(Input'range); -- Synchronized - signal prev : std_logic_vector(Input'range) := (others => '0'); -- Delayed - signal active : std_logic_vector(Input'range); -- Allow Output Updates + signal sync : std_logic_vector(Input'range); -- Synchronized + signal prev : std_logic_vector(Input'range) := (others => '0'); -- Delayed + signal active : std_logic_vector(Input'range); -- Allow Output Updates begin ----------------------------------------------------------------------------- - -- Input Synchronization - genNoSync: if not ADD_INPUT_SYNCHRONIZERS generate - sync <= Input; - end generate; - genSync: if ADD_INPUT_SYNCHRONIZERS generate - sync_i: entity work.sync_Bits - generic map ( - BITS => BITS, - INIT => INIT - ) - port map ( - Clock => Clock, -- Clock to be synchronized to - Input => Input, -- Data to be synchronized - Output => sync -- synchronised data - ); - end generate; + -- Input Synchronization + genNoSync: if not ADD_INPUT_SYNCHRONIZERS generate + sync <= Input; + end generate; + genSync: if ADD_INPUT_SYNCHRONIZERS generate + sync_i : entity work.sync_Bits + generic map ( + BITS => BITS, + INIT => INIT + ) + port map ( + Clock => Clock, -- Clock to be synchronized to + Input => Input, -- Data to be synchronized + Output => sync -- synchronised data + ); + end generate; ----------------------------------------------------------------------------- -- Bounce Filter @@ -116,23 +113,23 @@ begin active <= (others => '1'); end generate genNoLock; genLock: if LOCK_COUNT_X > 0 generate - constant LOCKS : positive := ite(COMMON_LOCK, 1, BITS); + constant LOCKS : positive := ite(COMMON_LOCK, 1, BITS); - signal toggle : std_logic_vector(LOCKS-1 downto 0); - signal locked : std_logic_vector(LOCKS-1 downto 0); + signal toggle : std_logic_vector(LOCKS-1 downto 0); + signal locked : std_logic_vector(LOCKS-1 downto 0); begin - genOneLock: if COMMON_LOCK generate - toggle(0) <= '1' when prev /= sync else '0'; - active <= (others => not locked(0)); - end generate genOneLock; - genManyLocks: if not COMMON_LOCK generate - toggle <= prev xor sync; - active <= not locked; - end generate genManyLocks; + genOneLock: if COMMON_LOCK generate + toggle(0) <= '1' when prev /= sync else '0'; + active <= (others => not locked(0)); + end generate genOneLock; + genManyLocks: if not COMMON_LOCK generate + toggle <= prev xor sync; + active <= not locked; + end generate genManyLocks; - genLocks: for i in 0 to LOCKS-1 generate - signal Lock : signed(log2ceil(LOCK_COUNT_X+1) downto 0) := (others => '0'); + genLocks: for i in 0 to LOCKS - 1 generate + signal Lock : signed(log2ceil(LOCK_COUNT_X + 1) downto 0) := (others => '0'); begin process(Clock) begin @@ -152,4 +149,4 @@ begin end generate genLocks; end generate genLock; -end; +end architecture; diff --git a/src/io/io_FanControl.vhdl b/src/io/io_FanControl.vhdl index bf1050948..363f1572d 100644 --- a/src/io/io_FanControl.vhdl +++ b/src/io/io_FanControl.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -49,6 +46,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; use work.config.all; use work.utils.all; @@ -87,7 +85,7 @@ architecture rtl of io_FanControl is constant TACHO_RESOLUTION : positive := 8; - signal PWM_PWMIn : std_logic_vector(PWM_RESOLUTION - 1 downto 0); + signal PWM_PWMIn : unsigned(PWM_RESOLUTION - 1 downto 0); signal PWM_PWMOut : std_logic := '0'; begin @@ -147,10 +145,10 @@ begin process(StartUp, UserTemperature_sync, OverTemperature_sync) begin - if (StartUp = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100%; start up - elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100% - elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50% - else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13% + if (StartUp = '1') then PWM_PWMIn <= to_unsigned(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100%; start up + elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_unsigned(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100% + elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_unsigned(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50% + else PWM_PWMIn <= to_unsigned(4, PWM_RESOLUTION); -- 13% end if; end process; end generate; @@ -188,10 +186,10 @@ begin process(StartUp, UserTemperature_sync, OverTemperature_sync) begin - if (StartUp = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100%; start up - elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100% - elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50% - else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13% + if (StartUp = '1') then PWM_PWMIn <= to_unsigned(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100%; start up + elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_unsigned(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100% + elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_unsigned(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50% + else PWM_PWMIn <= to_unsigned(4, PWM_RESOLUTION); -- 13% end if; end process; end generate; diff --git a/src/io/io_FrequencyCounter.vhdl b/src/io/io_FrequencyCounter.vhdl index 3f3503d3e..2873ca73a 100644 --- a/src/io/io_FrequencyCounter.vhdl +++ b/src/io/io_FrequencyCounter.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -32,67 +29,69 @@ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; -use work.utils.all; -use work.physical.all; + +use work.utils.all; +use work.physical.all; entity io_FrequencyCounter is generic ( - CLOCK_FREQ : FREQ := 100 MHz; - TIMEBASE : T_TIME := 1.0; - RESOLUTION : positive := 8 + CLOCK_FREQ : FREQ := 100 MHz; + TIMEBASE : T_TIME := 1.0; + RESOLUTION : positive := 8 ); port ( - Clock : in std_logic; - Reset : in std_logic; - FreqIn : in std_logic; - FreqOut : out std_logic_vector(RESOLUTION - 1 downto 0) + Clock : in std_logic; + Reset : in std_logic; + FreqIn : in std_logic; + FreqOut : out std_logic_vector(RESOLUTION - 1 downto 0); + FreqOut_Strobe : out std_logic ); end entity; architecture rtl of io_FrequencyCounter is - constant TIMEBASECOUNTER_MAX : positive := TimingToCycles(TIMEBASE, CLOCK_FREQ); - constant TIMEBASECOUNTER_BITS : positive := log2ceilnz(TIMEBASECOUNTER_MAX); - constant REQUENCYCOUNTER_MAX : positive := 2**RESOLUTION; - constant FREQUENCYCOUNTER_BITS : positive := RESOLUTION; + constant TIMEBASECOUNTER_MAX : positive := TimingToCycles(TIMEBASE, CLOCK_FREQ); + constant TIMEBASECOUNTER_BITS : positive := log2ceilnz(TIMEBASECOUNTER_MAX); + constant REQUENCYCOUNTER_MAX : positive := 2**RESOLUTION; + constant FREQUENCYCOUNTER_BITS : positive := RESOLUTION; - signal TimeBaseCounter_us : unsigned(TIMEBASECOUNTER_BITS - 1 downto 0) := (others => '0'); - signal TimeBaseCounter_ov : std_logic; - signal FrequencyCounter_us : unsigned(FREQUENCYCOUNTER_BITS downto 0) := (others => '0'); - signal FrequencyCounter_ov : std_logic; + signal TimeBaseCounter_us : unsigned(TIMEBASECOUNTER_BITS - 1 downto 0) := (others => '0'); + signal TimeBaseCounter_ov : std_logic; + signal FrequencyCounter_us : unsigned(FREQUENCYCOUNTER_BITS downto 0) := (others => '0'); + signal FrequencyCounter_ov : std_logic; - signal FreqIn_d : std_logic := '0'; - signal FreqIn_re : std_logic; + signal FreqIn_d : std_logic := '0'; + signal FreqIn_re : std_logic; - signal FreqOut_d : std_logic_vector(RESOLUTION - 1 downto 0) := (others => '0'); + signal FreqOut_d : std_logic_vector(RESOLUTION - 1 downto 0) := (others => '0'); begin - FreqIn_d <= FreqIn when rising_edge(Clock); - FreqIn_re <= not FreqIn_d and FreqIn; + FreqIn_d <= FreqIn when rising_edge(Clock); + FreqIn_re <= not FreqIn_d and FreqIn; -- timebase counter process(Clock) begin if rising_edge(Clock) then if ((Reset or TimeBaseCounter_ov) = '1') then - TimeBaseCounter_us <= (others => '0'); + TimeBaseCounter_us <= (others => '0'); else - TimeBaseCounter_us <= TimeBaseCounter_us + 1; + TimeBaseCounter_us <= TimeBaseCounter_us + 1; end if; end if; end process; - TimeBaseCounter_ov <= to_sl(TimeBaseCounter_us = TIMEBASECOUNTER_MAX); + TimeBaseCounter_ov <= to_sl(TimeBaseCounter_us = TIMEBASECOUNTER_MAX); -- frequency counter process(Clock) begin if rising_edge(Clock) then if ((Reset or TimeBaseCounter_ov) = '1') then - FrequencyCounter_us <= (others => '0'); + FrequencyCounter_us <= (others => '0'); elsif (FrequencyCounter_ov = '0') and (FreqIn_re = '1') then - FrequencyCounter_us <= FrequencyCounter_us + 1; + FrequencyCounter_us <= FrequencyCounter_us + 1; end if; end if; end process; @@ -103,17 +102,19 @@ begin process(Clock) begin if rising_edge(Clock) then + FreqOut_Strobe <= '0'; if (Reset = '1') then - FreqOut_d <= (others => '0'); + FreqOut_d <= (others => '0'); elsif (TimeBaseCounter_ov = '1') then + FreqOut_Strobe <= '1'; if (FrequencyCounter_ov = '1') then - FreqOut_d <= (others => '1'); + FreqOut_d <= (others => '1'); else - FreqOut_d <= std_logic_vector(FrequencyCounter_us(FreqOut_d'range)); + FreqOut_d <= std_logic_vector(FrequencyCounter_us(FreqOut_d'range)); end if; end if; end if; end process; - FreqOut <= FreqOut_d; + FreqOut <= FreqOut_d; end; diff --git a/src/io/io_GlitchFilter.vhdl b/src/io/io_GlitchFilter.vhdl index 0d78dd1d2..c29d9e718 100644 --- a/src/io/io_GlitchFilter.vhdl +++ b/src/io/io_GlitchFilter.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -124,7 +121,7 @@ begin end case; end process; - TC: entity work.io_TimingCounter + TC : entity work.io_TimingCounter generic map ( TIMING_TABLE => TIMING_TABLE -- timing table ) diff --git a/src/io/io_KeyPadScanner.vhdl b/src/io/io_KeyPadScanner.vhdl index a8a3c1d04..4978c2882 100644 --- a/src/io/io_KeyPadScanner.vhdl +++ b/src/io/io_KeyPadScanner.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -88,7 +85,7 @@ begin -- synchronize input signals genSync : if ADD_INPUT_SYNCHRONIZERS generate - sync: entity work.sync_Bits + sync : entity work.sync_Bits generic map ( BITS => ROWS ) diff --git a/src/io/io_PulseWidthModulation.vhdl b/src/io/io_PulseWidthModulation.vhdl index 7bbf80bda..41e912c7f 100644 --- a/src/io/io_PulseWidthModulation.vhdl +++ b/src/io/io_PulseWidthModulation.vhdl @@ -1,10 +1,8 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Patrick Lehmann +-- Authors: +-- Patrick Lehmann -- --- Entity: Pulse Width Modulated (PWM) signal generator +-- Entity: Pulse Width Modulated (PWM) signal generator -- -- Description: -- ------------------------------------- @@ -13,8 +11,9 @@ -- -- License: -- ============================================================================= --- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture +-- Copyright 2025-2026 The PoC-Library Authors +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. @@ -39,57 +38,57 @@ use work.physical.all; entity io_PulseWidthModulation is generic ( - CLOCK_FREQ : FREQ := 100 MHz; - PWM_FREQ : FREQ := 1 kHz; - PWM_RESOLUTION : positive := 8 + CLOCK_FREQ : FREQ := 100 MHz; + PWM_FREQ : FREQ := 1 kHz; + PWM_RESOLUTION : positive := 8 ); port ( - Clock : in std_logic; - Reset : in std_logic; - PWMIn : in std_logic_vector(PWM_RESOLUTION - 1 downto 0); - PWMOut : out std_logic + Clock : in std_logic; + Reset : in std_logic; + PWMIn : in unsigned(PWM_RESOLUTION - 1 downto 0); + PWMOut : out std_logic ); end entity; architecture rtl of io_PulseWidthModulation is - constant PWM_STEPS : positive := 2**PWM_RESOLUTION; - constant PWM_STEP_FREQ : FREQ := PWM_FREQ * (PWM_STEPS - 1); - constant PWM_FREQUENCYCOUNTER_MAX : positive := (CLOCK_FREQ+PWM_STEP_FREQ-1 Hz) / PWM_STEP_FREQ; -- division with round-up - constant PWM_FREQUENCYCOUNTER_BITS : positive := log2ceilnz(PWM_FREQUENCYCOUNTER_MAX); + constant PWM_STEPS : positive := 2**PWM_RESOLUTION; + constant PWM_STEP_FREQ : FREQ := PWM_FREQ * (PWM_STEPS - 1); + constant PWM_FREQUENCYCOUNTER_MAX : positive := (CLOCK_FREQ + PWM_STEP_FREQ - 1 Hz) / PWM_STEP_FREQ; -- division with round-up + constant PWM_FREQUENCYCOUNTER_BITS : positive := log2ceilnz(PWM_FREQUENCYCOUNTER_MAX); - signal PWM_FrequencyCounter_us : unsigned(PWM_FREQUENCYCOUNTER_BITS downto 0) := (others => '0'); - signal PWM_FrequencyCounter_ov : std_logic; - signal PWM_PulseCounter_us : unsigned(PWM_RESOLUTION - 1 downto 0) := (others => '0'); - signal PWM_PulseCounter_ov : std_logic; + signal PWM_FrequencyCounter_us : unsigned(PWM_FREQUENCYCOUNTER_BITS - 1 downto 0) := (others => '0'); + signal PWM_FrequencyCounter_ov : std_logic; + signal PWM_PulseCounter_us : unsigned(PWM_RESOLUTION - 1 downto 0) := (others => '0'); + signal PWM_PulseCounter_ov : std_logic; begin -- PWM frequency counter process(Clock) begin - if rising_edge(Clock) then - if ((Reset or PWM_FrequencyCounter_ov) = '1') then - PWM_FrequencyCounter_us <= (others => '0'); - else - PWM_FrequencyCounter_us <= PWM_FrequencyCounter_us + 1; - end if; + if rising_edge(Clock) then + if (Reset or PWM_FrequencyCounter_ov) = '1' then + PWM_FrequencyCounter_us <= (others => '0'); + else + PWM_FrequencyCounter_us <= PWM_FrequencyCounter_us + 1; end if; + end if; end process; - PWM_FrequencyCounter_ov <= to_sl(PWM_FrequencyCounter_us = PWM_FREQUENCYCOUNTER_MAX); + PWM_FrequencyCounter_ov <= to_sl(PWM_FrequencyCounter_us = PWM_FREQUENCYCOUNTER_MAX - 1); process(Clock) begin - if rising_edge(Clock) then - if ((Reset or PWM_PulseCounter_ov) = '1') then - PWM_PulseCounter_us <= (others => '0'); - elsif (PWM_FrequencyCounter_ov = '1') then - PWM_PulseCounter_us <= PWM_PulseCounter_us + 1; - end if; + if rising_edge(Clock) then + if (Reset or PWM_PulseCounter_ov) = '1' then + PWM_PulseCounter_us <= (others => '0'); + elsif PWM_FrequencyCounter_ov = '1' then + PWM_PulseCounter_us <= PWM_PulseCounter_us + 1; end if; + end if; end process; - PWM_PulseCounter_ov <= to_sl(PWM_PulseCounter_us = ((2**PWM_RESOLUTION) - 2)) and PWM_FrequencyCounter_ov; + PWM_PulseCounter_ov <= to_sl(PWM_PulseCounter_us = ((2**PWM_RESOLUTION) - 1)) and PWM_FrequencyCounter_ov; - PWMOut <= to_sl(PWM_PulseCounter_us < unsigned(PWMIn)); + PWMOut <= to_sl(PWM_PulseCounter_us < PWMIn); end; diff --git a/src/io/io_TimingCounter.vhdl b/src/io/io_TimingCounter.vhdl index 50b4b4bcb..ead99f39f 100644 --- a/src/io/io_TimingCounter.vhdl +++ b/src/io/io_TimingCounter.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -41,14 +38,14 @@ use work.utils.all; entity io_TimingCounter is generic ( - TIMING_TABLE : T_NATVEC -- timing table + TIMING_TABLE : T_NATVEC -- timing table ); port ( - Clock : in std_logic; -- clock - Enable : in std_logic; -- enable counter - Load : in std_logic; -- load Timing Value from TIMING_TABLE selected by slot - Slot : in natural range 0 to (TIMING_TABLE'length - 1); -- - Timeout : out std_logic -- timing reached + Clock : in std_logic; -- clock + Enable : in std_logic; -- enable counter + Load : in std_logic; -- load Timing Value from TIMING_TABLE selected by slot + Slot : in natural range 0 to (TIMING_TABLE'length - 1); -- + Timeout : out std_logic -- timing reached ); end entity; @@ -65,20 +62,20 @@ architecture rtl of io_TimingCounter is return Result; end; - constant TIMING_TABLE2 : T_INTVEC := transform(TIMING_TABLE); - constant TIMING_MAX : natural := imax(TIMING_TABLE2); - constant COUNTER_BITS : natural := log2ceilnz(TIMING_MAX + 1); + constant TIMING_TABLE2 : T_INTVEC := transform(TIMING_TABLE); + constant TIMING_MAX : natural := imax(TIMING_TABLE2); + constant COUNTER_BITS : natural := log2ceilnz(TIMING_MAX + 1); - signal Counter_s : signed(COUNTER_BITS downto 0) := to_signed(TIMING_TABLE2(0), COUNTER_BITS + 1); + signal Counter_s : signed(COUNTER_BITS downto 0) := to_signed(TIMING_TABLE2(0), COUNTER_BITS + 1); begin process(Clock) begin if rising_edge(Clock) then if (Load = '1') then - Counter_s <= to_signed(TIMING_TABLE2(Slot), Counter_s'length); + Counter_s <= to_signed(TIMING_TABLE2(Slot), Counter_s'length); elsif ((Enable = '1') and (Counter_s(Counter_s'high) = '0')) then - Counter_s <= Counter_s - 1; + Counter_s <= Counter_s - 1; end if; end if; end process; diff --git a/src/io/pmod/pmod.pkg.vhdl b/src/io/pmod/pmod.pkg.vhdl index bd779bd01..1b1ab917d 100644 --- a/src/io/pmod/pmod.pkg.vhdl +++ b/src/io/pmod/pmod.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/io/pmod/pmod_KYPD.vhdl b/src/io/pmod/pmod_KYPD.vhdl index 4bf9c3a80..a9ec59706 100644 --- a/src/io/pmod/pmod_KYPD.vhdl +++ b/src/io/pmod/pmod_KYPD.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/io/pmod/pmod_SSD.vhdl b/src/io/pmod/pmod_SSD.vhdl index d47b5f625..d2a342880 100644 --- a/src/io/pmod/pmod_SSD.vhdl +++ b/src/io/pmod/pmod_SSD.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/io/pmod/pmod_USBUART.vhdl b/src/io/pmod/pmod_USBUART.vhdl index ebc081a3c..089185b1a 100644 --- a/src/io/pmod/pmod_USBUART.vhdl +++ b/src/io/pmod/pmod_USBUART.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/io/spi/spi.pro b/src/io/spi/spi.pro new file mode 100644 index 000000000..e8f06567c --- /dev/null +++ b/src/io/spi/spi.pro @@ -0,0 +1,14 @@ +# ============================================================================= +# Authors: +# +# +# License: +# ============================================================================= +# Copyright (c) 2024 PLC2 Design GmbH - All Rights Reserved +# Unauthorized copying of this file, via any medium is strictly prohibited. +# Proprietary and confidential +# ============================================================================= + +analyze spi.pkg.vhdl +analyze spi_Slave.vhdl +analyze spi_Master.vhdl \ No newline at end of file diff --git a/src/io/uart/uart.pkg.vhdl b/src/io/uart/uart.pkg.vhdl index f3ac2aaf8..f195322e5 100644 --- a/src/io/uart/uart.pkg.vhdl +++ b/src/io/uart/uart.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Thomas B. Preusser @@ -10,7 +7,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- @@ -27,8 +24,8 @@ -- limitations under the License. -- ============================================================================= -library IEEE; -use IEEE.std_logic_1164.all; +library IEEE; +use IEEE.std_logic_1164.all; use work.utils.all; use work.physical.all; @@ -41,7 +38,16 @@ package uart is UART_FLOWCONTROL_RTS_CTS, UART_FLOWCONTROL_RTR_CTS ); - + type T_UART_PARITY_MODE is ( + PARITY_NONE, + PARITY_EVEN, + PARITY_ODD + ); + type T_UART_PARITY_ERROR_HANDLING is ( + REPLACE_ERROR_BYTE, + PASSTHROUGH_ERROR_BYTE, + DROP_ERROR_BYTE + ); constant C_IO_UART_TYPICAL_BAUDRATES : T_BAUDVEC := ( 0 => 300 Bd, 1 => 600 Bd, 2 => 1200 Bd, 3 => 1800 Bd, 4 => 2400 Bd, 5 => 4000 Bd, 6 => 4800 Bd, 7 => 7200 Bd, 8 => 9600 Bd, 9 => 14400 Bd, diff --git a/src/io/uart/uart.pro b/src/io/uart/uart.pro index 4e40e64e9..b2fc8b1a3 100644 --- a/src/io/uart/uart.pro +++ b/src/io/uart/uart.pro @@ -3,7 +3,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/io/uart/uart_bclk.vhdl b/src/io/uart/uart_bclk.vhdl index 04cd8d86d..7dbeb1553 100644 --- a/src/io/uart/uart_bclk.vhdl +++ b/src/io/uart/uart_bclk.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann @@ -48,41 +45,41 @@ use work.uart.all; entity uart_bclk is generic ( - CLOCK_FREQ : FREQ := 100 MHz; - BAUDRATE : BAUD := 115200 Bd + CLOCK_FREQ : FREQ := 100 MHz; + BAUDRATE : BAUD := 115200 Bd ); port ( - clk : in std_logic; - rst : in std_logic; - bclk : out std_logic; - bclk_x8 : out std_logic + clk : in std_logic; + rst : in std_logic; + bclk : out std_logic; + bclk_x8 : out std_logic ); end entity; architecture rtl of uart_bclk is - constant UART_OVERSAMPLING_RATE : positive := 8; - constant TIME_UNIT_INTERVAL : T_TIME := 1.0 / (to_real(BAUDRATE, 1 Bd) * real(UART_OVERSAMPLING_RATE)); - constant BAUDRATE_COUNTER_MAX : positive := TimingToCycles(TIME_UNIT_INTERVAL, CLOCK_FREQ); - constant BAUDRATE_COUNTER_BITS : positive := log2ceilnz(BAUDRATE_COUNTER_MAX + 1); + constant UART_OVERSAMPLING_RATE : positive := 8; + constant TIME_UNIT_INTERVAL : T_TIME := 1.0 / (to_real(BAUDRATE, 1 Bd) * real(UART_OVERSAMPLING_RATE)); + constant BAUDRATE_COUNTER_MAX : positive := TimingToCycles(TIME_UNIT_INTERVAL, CLOCK_FREQ); + constant BAUDRATE_COUNTER_BITS : positive := log2ceilnz(BAUDRATE_COUNTER_MAX + 1); -- registers signal x8_cnt : unsigned(BAUDRATE_COUNTER_BITS - 1 downto 0) := (others => '0'); - signal x1_cnt : unsigned(2 downto 0) := (others => '0'); + signal x1_cnt : unsigned(2 downto 0) := (others => '0'); -- control signals signal x8_cnt_done : std_logic; signal x1_cnt_done : std_logic; - signal bclk_r : std_logic := '0'; - signal bclk_x8_r : std_logic := '0'; + signal bclk_r : std_logic := '0'; + signal bclk_x8_r : std_logic := '0'; begin assert FALSE -- LF works in QuartusII report "uart_bclk:" & LF & " CLOCK_FREQ=" & to_string(CLOCK_FREQ, 3) & LF & " BAUDRATE=" & to_string(BAUDRATE, 3) & LF & " COUNTER_MAX=" & integer'image(BAUDRATE_COUNTER_MAX) & LF & - " COUNTER_BITS=" & integer'image(BAUDRATE_COUNTER_BITS) + " COUNTER_BITS=" & integer'image(BAUDRATE_COUNTER_BITS) severity NOTE; assert io_UART_IsTypicalBaudRate(BAUDRATE) @@ -90,17 +87,17 @@ begin severity WARNING; x8_cnt <= upcounter_next(cnt => x8_cnt, rst => (rst or x8_cnt_done)) when rising_edge(clk); - x8_cnt_done <= upcounter_equal(cnt => x8_cnt, value => BAUDRATE_COUNTER_MAX - 1); + x8_cnt_done <= upcounter_equal(cnt => x8_cnt, value => BAUDRATE_COUNTER_MAX - 1); - x1_cnt <= upcounter_next(cnt => x1_cnt, rst => rst, en => x8_cnt_done) when rising_edge(clk); - x1_cnt_done <= comp_allzero(x1_cnt); + x1_cnt <= upcounter_next(cnt => x1_cnt, rst => rst, en => x8_cnt_done) when rising_edge(clk); + x1_cnt_done <= comp_allzero(x1_cnt); -- outputs -- --------------------------------------------------------------------------- -- only x8_cnt_done is pulsed for one clock cycle! bclk_r <= (x1_cnt_done and x8_cnt_done) when rising_edge(clk); - bclk_x8_r <= x8_cnt_done when rising_edge(clk); + bclk_x8_r <= x8_cnt_done when rising_edge(clk); - bclk <= bclk_r; + bclk <= bclk_r; bclk_x8 <= bclk_x8_r; end; diff --git a/src/io/uart/uart_fifo.vhdl b/src/io/uart/uart_fifo.vhdl index ccacdfcd1..fdd2119b7 100644 --- a/src/io/uart/uart_fifo.vhdl +++ b/src/io/uart/uart_fifo.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann @@ -12,16 +9,19 @@ -- Small :abbr:`FIFO (first-in, first-out)` s are included in this module, if -- larger or asynchronous transmit / receive FIFOs are required, then they must -- be connected externally. --- --- old comments: --- :abbr:`UART (Universal Asynchronous Receiver Transmitter)` BAUD rate generator --- bclk = bit clock is rising --- bclk_x8 = bit clock times 8 is rising --- +-- Flow control: In this module flow control(SW flowcontrol and HW flow control) +-- are implemented for UART. Threshold limits can be set for flow control by using the generic +-- parameters FLOWCTRL_XON_THRESHOLD,FLOWCTRL_XOFF_THRESHOLD. +-- := For exmaple: +-- FLOWCTRL_XOFF_THRESHOLD is set to 0.75, if fifo filled upto = FIFO_DEPTH*0.75 +-- gives the backpressure based the flow control that being used. To know more about +-- TX_ESTATE_BITS,RX_FSTATE_BITS please refer 'fifo_cc_got' module. User can change the +-- SWFC_XON/XOFF_CHAR if needed. -- -- License: -- ============================================================================= --- Copyright 2008-2015 Technische Universitaet Dresden - Germany +-- Copyright 2025-2026 The PoC-Library Authors +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,7 @@ library IEEE; use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; use work.vectors.all; use work.physical.all; @@ -51,214 +52,256 @@ use work.uart.all; entity uart_fifo is generic ( -- Communication Parameters - CLOCK_FREQ : FREQ; - BAUDRATE : BAUD; - ADD_INPUT_SYNCHRONIZERS : boolean := TRUE; + CLOCK_FREQ : FREQ; + BAUDRATE : BAUD; + PARITY : T_UART_PARITY_MODE := PARITY_NONE; + PARITY_ERROR_HANDLING : T_UART_PARITY_ERROR_HANDLING := PASSTHROUGH_ERROR_BYTE; + PARITY_ERROR_IDENTIFIER : std_logic_vector(7 downto 0) := 8x"0"; + ADD_INPUT_SYNCHRONIZERS : boolean := TRUE; -- Buffer Dimensioning - TX_MIN_DEPTH : positive := 16; - TX_ESTATE_BITS : natural := 0; - RX_MIN_DEPTH : positive := 16; - RX_FSTATE_BITS : natural := 0; + TX_MIN_DEPTH : positive := 16; + TX_ESTATE_BITS : natural := 0; + RX_MIN_DEPTH : positive := 16; + RX_FSTATE_BITS : natural := 0; + + FLOWCTRL_XON_THRESHOLD : real := 0.0625; + FLOWCTRL_XOFF_THRESHOLD : real := 0.75; -- Flow Control - FLOWCONTROL : T_IO_UART_FLOWCONTROL_KIND := UART_FLOWCONTROL_NONE; - SWFC_XON_CHAR : std_logic_vector(7 downto 0) := x"11"; -- ^Q - SWFC_XON_TRIGGER : real := 0.0625; - SWFC_XOFF_CHAR : std_logic_vector(7 downto 0) := x"13"; -- ^S - SWFC_XOFF_TRIGGER : real := 0.75 + FLOWCONTROL : T_IO_UART_FLOWCONTROL_KIND := UART_FLOWCONTROL_NONE; + SWFC_XON_CHAR : std_logic_vector(7 downto 0) := x"11"; -- ^Q + + SWFC_XOFF_CHAR : std_logic_vector(7 downto 0) := x"13" -- ^S + ); port ( - Clock : in std_logic; - Reset : in std_logic; + Clock : in std_logic; + Reset : in std_logic; -- FIFO interface - TX_put : in std_logic; - TX_Data : in std_logic_vector(7 downto 0); - TX_Full : out std_logic; - TX_EmptyState : out std_logic_vector(imax(0, TX_ESTATE_BITS-1) downto 0); - - RX_Valid : out std_logic; - RX_Data : out std_logic_vector(7 downto 0); - RX_got : in std_logic; - RX_FullState : out std_logic_vector(imax(0, RX_FSTATE_BITS-1) downto 0); - RX_Overflow : out std_logic; + TX_put : in std_logic; + TX_Data : in std_logic_vector(7 downto 0); + TX_Full : out std_logic; + TX_EmptyState : out std_logic_vector(imax(0, TX_ESTATE_BITS-1) downto 0); + TXFIFO_Reset : in std_logic; + TXFIFO_Empty : out std_logic; + + RX_Valid : out std_logic; + RX_Data : out std_logic_vector(7 downto 0); + RX_got : in std_logic; + RX_FullState : out std_logic_vector(imax(0, RX_FSTATE_BITS-1) downto 0); + RX_Overflow : out std_logic; + RXFIFO_Full : out std_logic; + RXFIFO_Reset : in std_logic; -- External pins - UART_TX : out std_logic; - UART_RX : in std_logic; - UART_RTS : out std_logic; - UART_CTS : in std_logic + UART_TX : out std_logic; + UART_RX : in std_logic; + UART_RTS : out std_logic; + UART_CTS : in std_logic; + UART_parity_error : out std_logic ); end entity; architecture rtl of uart_fifo is - signal FC_TX_Strobe : std_logic; - signal FC_TX_Data : T_SLV_8; - signal FC_TX_got : std_logic; - signal FC_RX_put : std_logic; - signal FC_RX_Data : T_SLV_8; + signal FC_TX_Strobe : std_logic; + signal FC_TX_Data : T_SLV_8; + signal FC_TX_got : std_logic; + signal FC_RX_put : std_logic; + signal FC_RX_Data : T_SLV_8; + + signal TXFIFO_Valid : std_logic; + + signal TXFIFO_Data : T_SLV_8; + + signal RXFIFO_Full_int : std_logic; + signal RX_FullState_int : std_logic_vector(imax(0, RX_FSTATE_BITS-1) downto 0); - signal TXFIFO_Valid : std_logic; - signal TXFIFO_Data : T_SLV_8; + signal TXUART_Full : std_logic; + signal RXUART_Strobe : std_logic; + signal RXUART_Data : T_SLV_8; - signal RXFIFO_Full : std_logic; - signal TXUART_Full : std_logic; - signal RXUART_Strobe : std_logic; - signal RXUART_Data : T_SLV_8; - signal BitClock : std_logic; - signal BitClock_x8 : std_logic; + signal BitClock : std_logic; + signal BitClock_x8 : std_logic; - signal UART_RX_sync : std_logic; + signal UART_RX_sync : std_logic; begin - assert FALSE report "uart_fifo: BAUDRATE=: " & to_string(BAUDRATE, 3) severity NOTE; + assert FALSE report "uart_fifo: BAUDRATE=: " & to_string(BAUDRATE, 3) severity NOTE; + -- =========================================================================== -- Transmit and Receive FIFOs -- =========================================================================== - TXFIFO: entity work.fifo_cc_got + TXFIFO : entity work.fifo_cc_got generic map ( - D_BITS => 8, -- Data Width - MIN_DEPTH => TX_MIN_DEPTH, -- Minimum FIFO Depth - DATA_REG => TRUE, -- Store Data Content in Registers - STATE_REG => FALSE, -- Registered Full/Empty Indicators - OUTPUT_REG => FALSE, -- Registered FIFO Output - ESTATE_WR_BITS => TX_ESTATE_BITS, -- Empty State Bits - FSTATE_RD_BITS => 0 -- Full State Bits + D_BITS => 8, -- Data Width + MIN_DEPTH => TX_MIN_DEPTH, -- Minimum FIFO Depth + DATA_REG => TRUE, -- Store Data Content in Registers + STATE_REG => FALSE, -- Registered Full/Empty Indicators + OUTPUT_REG => FALSE, -- Registered FIFO Output + ESTATE_WR_BITS => TX_ESTATE_BITS, -- Empty State Bits + FSTATE_RD_BITS => 0 -- Full State Bits ) port map ( - rst => Reset, - clk => Clock, - put => TX_put, - din => TX_Data, - full => TX_Full, - estate_wr => TX_EmptyState, - - valid => TXFIFO_Valid, - dout => TXFIFO_Data, - got => FC_TX_got, - fstate_rd => open + rst => Reset or TXFIFO_Reset, + clk => Clock, + put => TX_put, + din => TX_Data, + full => TX_Full, + estate_wr => TX_EmptyState, + + valid => TXFIFO_Valid, + dout => TXFIFO_Data, + got => FC_TX_got, + fstate_rd => open ); - RXFIFO: entity work.fifo_cc_got + RXFIFO : entity work.fifo_cc_got generic map ( - D_BITS => 8, -- Data Width - MIN_DEPTH => RX_MIN_DEPTH, -- Minimum FIFO Depth - DATA_REG => TRUE, -- Store Data Content in Registers - STATE_REG => FALSE, -- Registered Full/Empty Indicators - OUTPUT_REG => FALSE, -- Registered FIFO Output - ESTATE_WR_BITS => 0, -- Empty State Bits - FSTATE_RD_BITS => RX_FSTATE_BITS -- Full State Bits + D_BITS => 8, -- Data Width + MIN_DEPTH => RX_MIN_DEPTH, -- Minimum FIFO Depth + DATA_REG => TRUE, -- Store Data Content in Registers + STATE_REG => FALSE, -- Registered Full/Empty Indicators + OUTPUT_REG => FALSE, -- Registered FIFO Output + ESTATE_WR_BITS => 0, -- Empty State Bits + FSTATE_RD_BITS => RX_FSTATE_BITS -- Full State Bits ) port map ( - rst => Reset, - clk => Clock, - put => FC_RX_put, - din => FC_RX_Data, - full => RXFIFO_Full, - estate_wr => open, - - valid => RX_Valid, - dout => RX_Data, - got => RX_got, - fstate_rd => RX_FullState + rst => Reset or RXFIFO_Reset, + clk => Clock, + put => FC_RX_put, + din => FC_RX_Data, + full => RXFIFO_Full_int, + estate_wr => open, + + valid => RX_Valid, + dout => RX_Data, + got => RX_got, + fstate_rd => RX_FullState_int ); + RXFIFO_Full <= RXFIFO_Full_int; + RX_FullState <= RX_FullState_int; + TXFIFO_Empty <= NOT TXFIFO_Valid; + + genNOFC : if FLOWCONTROL = UART_FLOWCONTROL_NONE generate - signal Overflow_r : std_logic := '0'; - begin - FC_TX_Strobe <= TXFIFO_Valid and not TXUART_Full; - FC_TX_Data <= TXFIFO_Data; - FC_TX_got <= FC_TX_Strobe; + begin - FC_RX_put <= RXUART_Strobe; - FC_RX_Data <= RXUART_Data; + FC_TX_Strobe <= TXFIFO_Valid and not TXUART_Full; + FC_TX_Data <= TXFIFO_Data; + FC_TX_got <= FC_TX_Strobe; - Overflow_r <= ffrs(q => Overflow_r, rst => Reset, set => (RXUART_Strobe and RXFIFO_Full)) when rising_edge(Clock); + FC_RX_put <= RXUART_Strobe; + FC_RX_Data <= RXUART_Data; - RX_Overflow <= Overflow_r; + RX_Overflow <= RXUART_Strobe and RXFIFO_Full_int; end generate; -- =========================================================================== -- Software Flow Control -- =========================================================================== genSWFC : if FLOWCONTROL = UART_FLOWCONTROL_XON_XOFF generate - constant XON : std_logic_vector(7 downto 0) := x"11"; -- ^Q - constant XOFF : std_logic_vector(7 downto 0) := x"13"; -- ^S - - constant XON_TRIG : integer := integer(SWFC_XON_TRIGGER * real(2**RX_FSTATE_BITS)); - constant XOFF_TRIG : integer := integer(SWFC_XOFF_TRIGGER * real(2**RX_FSTATE_BITS)); + constant XON_TRIG : integer := integer(FLOWCTRL_XON_THRESHOLD * real(2**RX_FSTATE_BITS)); + constant XOFF_TRIG : integer := integer(FLOWCTRL_XOFF_THRESHOLD * real(2**RX_FSTATE_BITS)); - signal send_xoff : std_logic; - signal send_xon : std_logic; + signal send_xoff : std_logic; + signal send_xon : std_logic; - signal set_xoff_transmitted : std_logic; - signal clr_xoff_transmitted : std_logic; - signal discard_user : std_logic; - - signal set_overflow : std_logic; + signal set_xoff_transmitted : std_logic; + signal clr_xoff_transmitted : std_logic; + signal discard_user_tx : std_logic; + signal discard_user_rx : std_logic; + signal RxFifo_FullState : integer := 0; -- receive fifo full_state -- registers - signal xoff_transmitted : std_logic; - + signal xoff_transmitted : std_logic := '0'; + signal transmit_enable : std_logic := '1'; begin --- -- send XOFF only once when fill state goes above trigger level --- send_xoff <= (not xoff_transmitted) when (rf_fs >= XOFF_TRIG) else '0'; --- set_xoff_transmitted <= tx_rdy when (rf_fs >= XOFF_TRIG) else '0'; --- --- -- send XON only once when receive FIFO is almost empty --- send_xon <= xoff_transmitted when (rf_fs = XON_TRIG) else '0'; --- clr_xoff_transmitted <= tx_rdy when (rf_fs = XON_TRIG) else '0'; --- --- -- discard any user supplied XON/XOFF --- discard_user <= '1' when (tf_dout = SWFC_XON_CHAR) or (tf_dout = SWFC_XOFF_CHAR) else '0'; --- --- -- tx / tf control --- tx_din <= SWFC_XOFF_CHAR when (send_xoff = '1') else --- SWFC_XON_CHAR when (send_xon = '1') else --- tf_dout; --- --- tx_stb <= send_xoff or send_xon or (tf_valid and (not discard_user)); --- tf_got <= (send_xoff nor send_xon) and --- tf_valid and tx_rdy; -- always check tf_valid --- --- -- rx / rf control --- rf_put <= (not rf_full) and rx_dos; -- always check rf_full --- rf_din <= rx_dout; --- --- set_overflow <= rf_full and rx_dos; --- --- -- registers --- process (Clock) --- begin -- process --- if rising_edge(Clock) then --- if (rst or set_xoff_transmitted) = '1' then --- -- send a XON after reset --- xoff_transmitted <= '1'; --- elsif clr_xoff_transmitted = '1' then --- xoff_transmitted <= '0'; --- end if; --- --- if rst = '1' then --- overflow <= '0'; --- elsif set_overflow = '1' then --- overflow <= '1'; --- end if; --- end if; --- end process; + RxFifo_FullState <= to_integer(unsigned(RX_FullState_int)); + --assert false report"FLOWCONTROL=" & T_IO_UART_FLOWCONTROL_KIND'image(FLOWCONTROL) & " is currently not supported!" severity failure; + -- send XOFF only once when fill state goes above trigger level + send_xoff <= not xoff_transmitted when (RxFifo_FullState >= XOFF_TRIG) else '0'; + set_xoff_transmitted <= (not TXUART_Full) when (RxFifo_FullState >= XOFF_TRIG) else '0'; + + -- send XON only once when receive FIFO is almost empty + send_xon <= xoff_transmitted when (RxFifo_FullState <= XON_TRIG) else '0'; + clr_xoff_transmitted <= (not TXUART_Full) when (RxFifo_FullState <= XON_TRIG) else '0'; + + -- discard any user supplied XON/XOFF + discard_user_tx <= '1' when (TXFIFO_Data = SWFC_XON_CHAR) or (TXFIFO_Data = SWFC_XOFF_CHAR) else '0'; + discard_user_rx <= '1' when (RXUART_Data = SWFC_XON_CHAR) or (RXUART_Data = SWFC_XOFF_CHAR) else '0'; + -- tx / tf control + FC_TX_Data <= SWFC_XOFF_CHAR when (send_xoff = '1') else + SWFC_XON_CHAR when (send_xon = '1') else + TXFIFO_Data; + + FC_TX_Strobe <= send_xoff or send_xon or (TXFIFO_Valid and transmit_enable and (not discard_user_tx)) ; + FC_TX_got <= (send_xoff nor send_xon) and TXFIFO_Valid and (not TXUART_Full); -- always check TXFIFO_Valid + -- rx / rf control + FC_RX_put <= (RXUART_Strobe and (not discard_user_rx)); -- always check RXFIFO_Full_int + FC_RX_Data <= RXUART_Data; + + + RX_Overflow <= RXUART_Strobe and RXFIFO_Full_int; + -- registers + process (Clock) + begin -- process + if rising_edge(Clock) then + if (reset or set_xoff_transmitted) = '1' then + xoff_transmitted <= '1'; + elsif clr_xoff_transmitted = '1' then + xoff_transmitted <= '0'; + end if; + if reset = '1' then + transmit_enable <= '1'; + elsif RXUART_Strobe = '1' then + if RXUART_Data = SWFC_XOFF_CHAR then + transmit_enable <= '0'; + elsif RXUART_Data = SWFC_XON_CHAR then + transmit_enable <= '1'; + end if; + end if; + end if; + end process; end generate; -- =========================================================================== -- Hardware Flow Control -- =========================================================================== genHWFC1 : if FLOWCONTROL = UART_FLOWCONTROL_RTS_CTS generate - + constant RX_FSTATE_UPPER_LIMIT : integer := integer(FLOWCTRL_XOFF_THRESHOLD * real(2**RX_FSTATE_BITS)); + constant RX_FSTATE_LOWER_LIMIT : integer := integer(FLOWCTRL_XON_THRESHOLD * real(2**RX_FSTATE_BITS)); begin - + --assert false report"FLOWCONTROL=" & T_IO_UART_FLOWCONTROL_KIND'image(FLOWCONTROL) & " is currently not supported!" severity failure; + + FC_TX_Strobe <= TXFIFO_Valid and not TXUART_Full and UART_CTS; + FC_TX_Data <= TXFIFO_Data; + FC_TX_got <= FC_TX_Strobe; + + FC_RX_put <= RXUART_Strobe; + FC_RX_Data <= RXUART_Data; + RX_Overflow <= RXUART_Strobe and RXFIFO_Full_int; + + RTS_process: process(Clock) + begin + if rising_edge(Clock) then + if TXUART_Full = '0' then + if Reset = '1' then + UART_RTS<='1'; + elsif (to_integer(unsigned(RX_FullState_int)) >= RX_FSTATE_UPPER_LIMIT) then + UART_RTS<='0'; + elsif (to_integer(unsigned(RX_FullState_int)) <= RX_FSTATE_LOWER_LIMIT) then + UART_RTS<='1'; + end if; + end if; + end if; + end process; end generate; -- =========================================================================== -- Hardware Flow Control @@ -266,7 +309,7 @@ begin genHWFC2 : if FLOWCONTROL = UART_FLOWCONTROL_RTR_CTS generate begin - + assert false report"FLOWCONTROL=" & T_IO_UART_FLOWCONTROL_KIND'image(FLOWCONTROL) & " is currently not supported!" severity failure; end generate; -- =========================================================================== @@ -276,17 +319,17 @@ begin UART_RX_sync <= UART_RX; end generate; genSync : if ADD_INPUT_SYNCHRONIZERS generate - sync_i: entity work.sync_Bits + sync_i : entity work.sync_Bits port map ( - Clock => Clock, -- Clock to be synchronized to - Input(0) => UART_RX, -- Data to be synchronized - Output(0) => UART_RX_sync -- synchronised data + Clock => Clock, -- Clock to be synchronized to + Input(0) => UART_RX, -- Data to be synchronized + Output(0) => UART_RX_sync -- synchronised data ); end generate; -- =========================================================================== -- BitClock, Transmitter, Receiver -- =========================================================================== - bclk: entity work.uart_bclk + bclk : entity work.uart_bclk generic map ( CLOCK_FREQ => CLOCK_FREQ, BAUDRATE => BAUDRATE @@ -298,7 +341,10 @@ begin bclk_x8 => BitClock_x8 ); - TX: entity work.uart_tx + TX : entity work.uart_tx + generic map ( + PARITY => PARITY + ) port map ( clk => Clock, rst => Reset, @@ -309,14 +355,20 @@ begin ful => TXUART_Full ); - RX: entity work.uart_rx + RX : entity work.uart_rx + generic map ( + PARITY => PARITY, + PARITY_ERROR_HANDLING => PARITY_ERROR_HANDLING, + PARITY_ERROR_IDENTIFIER => PARITY_ERROR_IDENTIFIER + ) port map ( clk => Clock, rst => Reset, bclk_x8 => BitClock_x8, rx => UART_RX_sync, do => RXUART_Data, - stb => RXUART_Strobe + stb => RXUART_Strobe, + parity_error => UART_parity_error ); end architecture; diff --git a/src/io/uart/uart_ft245.vhdl b/src/io/uart/uart_ft245.vhdl index b83b7993a..8b8d0c0f2 100644 --- a/src/io/uart/uart_ft245.vhdl +++ b/src/io/uart/uart_ft245.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Peter Reichel -- Jan Schirok @@ -64,9 +61,9 @@ end entity; library IEEE; -use IEEE.numeric_std.all; +use IEEE.numeric_std.all; -use work.utils.all; +use work.utils.all; architecture rtl of uart_ft245 is diff --git a/src/io/uart/uart_rx.vhdl b/src/io/uart/uart_rx.vhdl index fc605b7f3..1756e86eb 100644 --- a/src/io/uart/uart_rx.vhdl +++ b/src/io/uart/uart_rx.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- @@ -8,9 +5,21 @@ -- -- Description: -- ------------------------------------- --- :abbr:`UART (Universal Asynchronous Receiver Transmitter)` Receiver: --- 1 Start + 8 Data + 1 Stop --- +-- 1 Start + 8 Data + [1 parity] + 1 Stop +-- if data is "01000110" and with even parity the frame will be 0 + 01100010 + 1 + 1 +-- with odd parity the frame will be 0 + 01100010 + 0 + 1 +-- with no parity the frame will be 0 + 01100010 + 1 +-- 8 bits of data |(count of 1-bits)| 8 bits including parity +-- | | even odd +-- 00000000 | 0 | 000000000 000000001 +-- 10100010 | 3 | 101000101 101000100 +-- 11010010 | 4 | 110100100 110100101 +-- 11111110 | 7 | 111111101 111111100 +-- When parity error occured, +-- if PARITY_ERROR_HANDLING = PASSTHROUGH_ERROR_BYTE then error byte passed to FIFO +-- = REPLACE_ERROR_BYTE then error byte will replaced with PARITY_ERROR_IDENTIFIER which is generic +-- = DROP_ERROR_BYTE then error byte will be dropped +-- and all three scenarios, error flag will be raised. -- License: -- ============================================================================= -- Copyright 2008-2016 Technische Universitaet Dresden - Germany @@ -33,49 +42,56 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -library PoC; - +use work.uart.all; entity uart_rx is - generic ( - SYNC_DEPTH : natural := 2 -- use zero for already clock-synchronous rx + generic ( + SYNC_DEPTH : natural := 2; -- use zero for already clock-synchronous rx + PARITY : T_UART_PARITY_MODE := PARITY_NONE; --PARITY_EVEN, PARITY_ODD, PARITY_NONE + PARITY_ERROR_HANDLING : T_UART_PARITY_ERROR_HANDLING := PASSTHROUGH_ERROR_BYTE; --PASSTHROUGH_ERROR_BYTE,REPLACE_ERROR_BYTE + PARITY_ERROR_IDENTIFIER : std_logic_vector(7 downto 0) := x"15" -- ^NAK ); - port ( - -- Global Control - clk : in std_logic; - rst : in std_logic; + port ( + -- Global Control + clk : in std_logic; + rst : in std_logic; - -- Bit Clock and RX Line - bclk_x8 : in std_logic; -- bit clock, eight strobes per bit length - rx : in std_logic; + -- Bit Clock and RX Line + bclk_x8 : in std_logic; -- bit clock, eight strobes per bit length + rx : in std_logic; - -- Byte Stream Output - do : out std_logic_vector(7 downto 0); - stb : out std_logic - ); + -- Byte Stream Output + do : out std_logic_vector(7 downto 0); + stb : out std_logic; + parity_error : out std_logic + ); end entity; architecture rtl of uart_rx is - -- RX Synchronization - signal rxs : std_logic; + -- RX Synchronization + signal rxs : std_logic; - -- Buf Cnt Vld - -- Idle "---------0" X 0 - -- Start "0111111111" 5->16 0 -- 1.5 bit length after start of start bit - -- Recv "dcba011111" 9->16 0 -- shifting left to right (LSB first) - -- Done "1hgfedcba0" X 1 -- Output strobe + -- Buf Cnt Vld + -- Idle "----------0" X 0 + -- Start "01111111111" 5->16 0 -- 1.5 bit length after start of start bit + -- Recv "dcba0111111" 9->16 0 -- shifting left to right (LSB first) + -- Done "11hgfedcba0" X 1 -- Output strobe, without parity -- Data buffer - signal Buf : std_logic_vector(9 downto 0) := (0 => '0', others => '-'); + signal Buf : std_logic_vector(10 downto 0) := (0 => '0', others => '-'); -- Bit clock counter: 8 ticks per bit - signal Cnt : unsigned(4 downto 0) := (others => '-'); + signal Cnt : unsigned(4 downto 0) := (others => '-'); -- Output strobe - signal Vld : std_logic := '0'; + signal Vld : std_logic := '0'; + signal parity_bit_cal : std_logic := '0'; + signal parity_bit : std_logic := '0'; + signal parity_error_flag : std_logic := '0'; + begin -- Input synchronization - sync: entity work.sync_Bits + sync : entity work.sync_Bits generic map ( INIT => (SYNC_DEPTH - 1 downto 0 => '1'), -- initialitation bits SYNC_DEPTH => SYNC_DEPTH -- generate SYNC_DEPTH many stages, at least 2 @@ -85,17 +101,31 @@ begin Input(0) => rx, -- @async: input bits Output(0) => rxs -- @Clock: output bits ); - - -- Reception state - process(clk) - begin - if rising_edge(clk) then + paritycal: process(Buf) + begin + case PARITY is + when PARITY_EVEN => + -- Even parity: parity_bit_cal is '1' if the number of '1's in data is odd (to make total even) + parity_bit_cal <= xor(Buf(9 downto 2)); + when PARITY_ODD => + -- Odd parity: parity_bit_cal is '1' if the number of '1's in data is even (to make total odd) + parity_bit_cal <= not (xor(Buf(9 downto 2))); + when others => + -- No parity (PARITY = "NONE"): parity_bit_cal not used + parity_bit_cal <= '0'; + end case; + end process; + -- Reception state + process(clk) + begin + if rising_edge(clk) then Vld <= '0'; - if rst = '1' then - Buf <= (0 => '0', others => '-'); - Cnt <= (others => '-'); - else - if Buf(0) = '0' then + parity_error_flag <= '0'; + if rst = '1' then + Buf <= (0 => '0', others => '-'); + Cnt <= (others => '-'); + else + if Buf(0) = '0' or Vld ='1' then -- Idle if rxs = '0' then -- Start bit -> receive byte @@ -106,18 +136,46 @@ begin Cnt <= (others => '-'); end if; elsif bclk_x8 = '1' then - if Cnt(Cnt'left) = '1' then - Buf <= rxs & Buf(Buf'left downto 1); - Vld <= rxs and not Buf(1); + parity_bit <= Buf(10); + if Cnt(Cnt'left) = '1' then + Buf <= rxs & Buf(Buf'left downto 1); + if PARITY = PARITY_NONE then + Vld <= rxs and not Buf(2); + elsif Buf(1) = '0' then + if parity_bit /= parity_bit_cal then + parity_error_flag <= '1'; + end if; + Vld <= rxs; + end if; end if; Cnt <= Cnt + (Cnt(4) & Cnt(4) & "001"); end if; - end if; - end if; - end process; + end if; + end if; + end process; - -- Outputs - do <= Buf(8 downto 1); - stb <= Vld; + -- Outputs + ouput:process(all) + begin + if PARITY = PARITY_NONE then + do <= Buf(9 downto 2); + stb <= Vld; + elsif parity_error_flag = '1' then + if PARITY_ERROR_HANDLING = DROP_ERROR_BYTE then + do <= Buf(8 downto 1); + stb <= '0'; + elsif PARITY_ERROR_HANDLING = PASSTHROUGH_ERROR_BYTE then + do <= Buf(8 downto 1); + stb <= Vld; + elsif PARITY_ERROR_HANDLING = REPLACE_ERROR_BYTE then + do <= PARITY_ERROR_IDENTIFIER; + stb <= Vld; + end if; + else + do <= Buf(8 downto 1); + stb <= Vld and not parity_error_flag; + end if; + end process; + parity_error <= parity_error_flag; end architecture; diff --git a/src/io/uart/uart_tx.vhdl b/src/io/uart/uart_tx.vhdl index 27445dc0c..1ea1f53e4 100644 --- a/src/io/uart/uart_tx.vhdl +++ b/src/io/uart/uart_tx.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- @@ -9,7 +6,16 @@ -- Description: -- ------------------------------------- -- :abbr:`UART (Universal Asynchronous Receiver Transmitter)` Transmitter: --- 1 Start + 8 Data + 1 Stop +-- 1 Start + 8 Data + [1 parity] + 1 Stop +-- if data is "01000110" and with even parity the frame will be 0 + 01100010 + 1 + 1 +-- with odd parity the frame will be 0 + 01100010 + 0 + 1 +-- with no parity the frame will be 0 + 01100010 + 1 +-- 8 bits of data |(count of 1-bits)| 8 bits including parity +-- | | even odd +-- 00000000 | 0 | 000000000 000000001 +-- 10100010 | 3 | 101000101 101000100 +-- 11010010 | 4 | 110100100 110100101 +-- 11111110 | 7 | 111111101 111111100 -- -- License: -- ============================================================================= @@ -32,21 +38,26 @@ library IEEE; use IEEE.std_logic_1164.all; -entity uart_tx is - port ( - -- Global Control - clk : in std_logic; - rst : in std_logic; - - -- Bit Clock and TX Line - bclk : in std_logic; -- bit clock, one strobe each bit length - tx : out std_logic; +use work.uart.all; - -- Byte Stream Input - di : in std_logic_vector(7 downto 0); - put : in std_logic; - ful : out std_logic - ); +entity uart_tx is + generic( + PARITY : T_UART_PARITY_MODE := PARITY_NONE --PARITY_EVEN, PARITY_ODD,PARITY_NONE + ); + port ( + -- Global Control + clk : in std_logic; + rst : in std_logic; + + -- Bit Clock and TX Line + bclk : in std_logic; -- bit clock, one strobe each bit length + tx : out std_logic; + + -- Byte Stream Input + di : in std_logic_vector(7 downto 0); + put : in std_logic; + ful : out std_logic + ); end entity; @@ -55,44 +66,61 @@ use IEEE.numeric_std.all; architecture rtl of uart_tx is - -- Buf Cnt - -- Idle "---------1" "0----" - -- Start "hgfedcba01" -10 - -- Send "1111hgfedc" -10 -> -1 - -- Done "1111111111" 0 - - signal Buf : std_logic_vector(9 downto 0) := (0 => '1', others => '-'); - signal Cnt : signed(4 downto 0) := "0----"; + -- Buf Cnt + -- Idle "----------1" "0----" + -- Start "1hgfedcba01" -10 + -- Send "11111hgfedc" -10 -> -1 + -- Done "11111111111" 0 + + signal Buf : std_logic_vector(10 downto 0) := (0 => '1', others => '-'); + signal Cnt : signed(4 downto 0) := "0----"; + signal parity_bit : std_logic; begin - - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - Buf <= (0 => '1', others => '-'); - Cnt <= "0----"; - else - if Cnt(Cnt'left) = '0' then - -- Idle - if put = '1' then - -- Start Transmission - Buf <= di & "01"; - Cnt <= to_signed(-10, Cnt'length); - else - Buf <= (0 => '1', others => '-'); - Cnt <= "0----"; - end if; - else - -- Transmitting - if bclk = '1' then - Buf <= '1' & Buf(Buf'left downto 1); - Cnt <= Cnt + 1; - end if; - end if; - end if; - end if; - end process; + paritycal:process(di) + begin + case PARITY is + when PARITY_EVEN => + -- Even parity: parity_bit is '1' if the number of '1's in di is odd (to make total even) + parity_bit <= xor(di); + when PARITY_ODD => + -- Odd parity: parity_bit is '1' if the number of '1's in di is even (to make total odd) + parity_bit <= not (xor(di)); + when others => + -- No parity (PARITY = "NONE"): parity_bit not used + parity_bit <= '0'; + end case; + end process; + + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + Buf <= (0 => '1', others => '-'); + Cnt <= "0----"; + else + if Cnt(Cnt'left) = '0' then -- Idle + if put = '1' then -- Start Transmission + if PARITY = PARITY_NONE then + Buf <= "1" & di & "01"; + Cnt <= to_signed(-10, Cnt'length); + else + Buf <= parity_bit & di & "01"; + Cnt <= to_signed(-11, Cnt'length); + end if; + else + Buf <= (0 => '1', others => '-'); + Cnt <= "0----"; + end if; + else -- Transmitting + if bclk = '1' then + Buf <= '1' & Buf(Buf'left downto 1); + Cnt <= Cnt + 1; + end if; + end if; + end if; + end if; + end process; tx <= Buf(0); ful <= Cnt(Cnt'left); end; diff --git a/src/mem/lut/lut_Sine.vhdl b/src/mem/lut/lut_Sine.vhdl index 9fa76d2c4..be3f0bd56 100644 --- a/src/mem/lut/lut_Sine.vhdl +++ b/src/mem/lut/lut_Sine.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -80,7 +77,7 @@ begin constant LUT : T_LUT := generateLUT; begin - assert (OFFSET_DEG = 0.0) report "Offset > 0.0° is only supported in 4 quadrant mode." severity FAILURE; + assert (OFFSET_DEG = 0.0) report "Offset > 0.0� is only supported in 4 quadrant mode." severity FAILURE; Output_nxt <= std_logic_vector(to_unsigned(LUT(to_index(Input, LUT'length)), Output_nxt'length)); end generate; @@ -107,7 +104,7 @@ begin constant LUT : T_LUT := generateLUT; begin - assert (OFFSET_DEG = 0.0) report "Offset > 0.0° is only supported in 4 quadrant mode." severity FAILURE; + assert (OFFSET_DEG = 0.0) report "Offset > 0.0� is only supported in 4 quadrant mode." severity FAILURE; Output_nxt <= std_logic_vector(to_unsigned(LUT(to_index(Input, LUT'length)), Output_nxt'length)); end generate; diff --git a/src/mem/mem.pkg.vhdl b/src/mem/mem.pkg.vhdl index 41b561276..7a0fb9a1a 100644 --- a/src/mem/mem.pkg.vhdl +++ b/src/mem/mem.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann @@ -29,7 +26,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- @@ -111,10 +108,10 @@ package body mem is end function; procedure ReadHex(L : inout LINE; Value : out std_logic_vector; Good : out boolean) is - variable ok : boolean; - variable Char : character; + variable ok : boolean; + variable Char : character; variable Digit : T_DIGIT_HEX; - constant DigitCount : positive := div_ceil(Value'length, 4); + constant DigitCount : positive := div_ceil(Value'length, 4); variable slv : std_logic_vector((DigitCount * 4) - 1 downto 0); variable Swapped : std_logic_vector((DigitCount * 4) - 1 downto 0); begin @@ -145,11 +142,11 @@ package body mem is FORMAT : T_MEM_FILEFORMAT; CONTENT : T_MEM_CONTENT := MEM_CONTENT_HEX ) return T_SLM is - file FileHandle : TEXT open READ_MODE is FileName; + file FileHandle : TEXT open READ_MODE is FileName; variable CurrentLine : LINE; - variable Good : boolean; - variable TempWord : std_logic_vector((div_ceil(BitsPerMemoryLine, 4) * 4) - 1 downto 0); - variable Result : T_SLM(MemoryLines - 1 downto 0, BitsPerMemoryLine - 1 downto 0); + variable Good : boolean; + variable TempWord : std_logic_vector((div_ceil(BitsPerMemoryLine, 4) * 4) - 1 downto 0); + variable Result : T_SLM(MemoryLines - 1 downto 0, BitsPerMemoryLine - 1 downto 0); begin Result := (others => (others => ite(SIMULATION, 'U', '0'))); @@ -162,8 +159,8 @@ package body mem is exit when endfile(FileHandle); readline(FileHandle, CurrentLine); --- report CurrentLine.all severity NOTE; --- ReadHex(CurrentLine, TempWord, Good); +-- report CurrentLine.all severity NOTE; +-- ReadHex(CurrentLine, TempWord, Good); -- WORKAROUND: for Xilinx Vivado (tested with 2018.3) -- Version: All versions -- Issue: User defined procedures using access types like line are not supported (synthesizable). @@ -208,8 +205,8 @@ package body mem is function get_ram_type(a : positive; d : positive) return T_INTVEC is constant URAM : natural := 0; constant BRAM : natural := 1; --- constant LRAM : natural := 2; - +-- constant LRAM : natural := 2; + variable reminder : natural := d; variable result : T_INTVEC(0 to 1) := (others => 0); @@ -217,7 +214,7 @@ package body mem is --================================================================== --***********depth smaler than 512, everithing in LUT_RAM*********** if a <= 8 then --- LRAM := d; +-- LRAM := d; return result; --================================================================== @@ -227,8 +224,8 @@ package body mem is reminder := reminder - (result(BRAM) * 36); if reminder > 28 then result(BRAM) := result(BRAM) +1; --- else --- LRAM := (d - reminder); +-- else +-- LRAM := (d - reminder); end if; --================================================================== @@ -238,8 +235,8 @@ package body mem is reminder := reminder - (result(BRAM) * 18); if reminder > 14 then result(BRAM) := result(BRAM) +1; --- else --- LRAM := (d - reminder); +-- else +-- LRAM := (d - reminder); end if; --================================================================== @@ -249,8 +246,8 @@ package body mem is reminder := reminder - (result(BRAM) * 9); if reminder > 6 then result(BRAM) := result(BRAM) +1; --- else --- LRAM := (d - reminder); +-- else +-- LRAM := (d - reminder); end if; --================================================================== @@ -267,8 +264,8 @@ package body mem is reminder := reminder - (result(BRAM) * 4); if reminder > 2 then result(BRAM) := result(BRAM) +1; --- else --- LRAM := (d - reminder); +-- else +-- LRAM := (d - reminder); end if; end if; diff --git a/src/mem/mem.pro b/src/mem/mem.pro index 4d373be98..bb4b8336b 100644 --- a/src/mem/mem.pro +++ b/src/mem/mem.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -38,7 +38,7 @@ if { $::poc::vendor eq "Xilinx" } { analyze ./ocram/altera/ocram_tdp_altera.vhdl } elseif { $::poc::vendor ne "GENERIC" } { - puts "Unknow vendor '$::poc::vendor' in arith!" + puts "Unknown vendor '$::poc::vendor'!" exit 1 } @@ -48,6 +48,7 @@ analyze ./ocrom/ocrom_sp.vhdl analyze ./sdram/sdram_ctrl_fsm.vhdl +# TODO: Remove Spartan 3 and Cyclone 3 files if { $::poc::vendor eq "Xilinx" } { analyze ./sdram/sdram_ctrl_phy_s3esk.vhdl analyze ./sdram/sdram_ctrl_s3esk.vhdl @@ -57,7 +58,7 @@ if { $::poc::vendor eq "Xilinx" } { analyze ./sdram/sdram_ctrl_de0.vhdl } elseif { $::poc::vendor ne "GENERIC" } { - puts "Unknow vendor '$::poc::vendor' in arith!" + puts "Unknown vendor '$::poc::vendor'!" exit 1 } diff --git a/src/mem/mem_GitVersionRegister.pkg.vhdl b/src/mem/mem_GitVersionRegister.pkg.vhdl index b4dd33a8f..2e296a563 100644 --- a/src/mem/mem_GitVersionRegister.pkg.vhdl +++ b/src/mem/mem_GitVersionRegister.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Stefan Unrein -- Max Kraft-Kugler @@ -16,7 +13,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ocram/altera/ocram_sp_altera.vhdl b/src/mem/ocram/altera/ocram_sp_altera.vhdl index e99ebb153..47f65ffac 100644 --- a/src/mem/ocram/altera/ocram_sp_altera.vhdl +++ b/src/mem/ocram/altera/ocram_sp_altera.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/mem/ocram/altera/ocram_tdp_altera.vhdl b/src/mem/ocram/altera/ocram_tdp_altera.vhdl index b54e62451..5cf4181a0 100644 --- a/src/mem/ocram/altera/ocram_tdp_altera.vhdl +++ b/src/mem/ocram/altera/ocram_tdp_altera.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/mem/ocram/ocram.pkg.vhdl b/src/mem/ocram/ocram.pkg.vhdl index f4e40cae8..1e436fa0d 100644 --- a/src/mem/ocram/ocram.pkg.vhdl +++ b/src/mem/ocram/ocram.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/mem/ocram/ocram_esdp.vhdl b/src/mem/ocram/ocram_esdp.vhdl index 03ba47472..c5b760b88 100644 --- a/src/mem/ocram/ocram_esdp.vhdl +++ b/src/mem/ocram/ocram_esdp.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/mem/ocram/ocram_sdp.vhdl b/src/mem/ocram/ocram_sdp.vhdl index 3065caa35..f387e4326 100644 --- a/src/mem/ocram/ocram_sdp.vhdl +++ b/src/mem/ocram/ocram_sdp.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Thomas B. Preusser @@ -35,7 +32,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2008-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/mem/ocram/ocram_sdp_optimized.vhdl b/src/mem/ocram/ocram_sdp_optimized.vhdl index da6b018ea..5a3dd05e4 100644 --- a/src/mem/ocram/ocram_sdp_optimized.vhdl +++ b/src/mem/ocram/ocram_sdp_optimized.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -33,7 +30,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/mem/ocram/ocram_sdp_wf.vhdl b/src/mem/ocram/ocram_sdp_wf.vhdl index ce79906b4..dae5a1ea6 100644 --- a/src/mem/ocram/ocram_sdp_wf.vhdl +++ b/src/mem/ocram/ocram_sdp_wf.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/src/mem/ocram/ocram_sp.vhdl b/src/mem/ocram/ocram_sp.vhdl index 53111f96c..27d2f76af 100644 --- a/src/mem/ocram/ocram_sp.vhdl +++ b/src/mem/ocram/ocram_sp.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/mem/ocram/ocram_tdp.vhdl b/src/mem/ocram/ocram_tdp.vhdl index 11aebc390..bb3fd2752 100644 --- a/src/mem/ocram/ocram_tdp.vhdl +++ b/src/mem/ocram/ocram_tdp.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/mem/ocram/ocram_tdp_sim.vhdl b/src/mem/ocram/ocram_tdp_sim.vhdl index e4d02029d..91f53db23 100644 --- a/src/mem/ocram/ocram_tdp_sim.vhdl +++ b/src/mem/ocram/ocram_tdp_sim.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/src/mem/ocram/ocram_tdp_wf.vhdl b/src/mem/ocram/ocram_tdp_wf.vhdl index 12d1d8c5a..e062adf6a 100644 --- a/src/mem/ocram/ocram_tdp_wf.vhdl +++ b/src/mem/ocram/ocram_tdp_wf.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/mem/ocrom/ocrom.pkg.vhdl b/src/mem/ocrom/ocrom.pkg.vhdl index db192c1e1..6096df4c4 100644 --- a/src/mem/ocrom/ocrom.pkg.vhdl +++ b/src/mem/ocrom/ocrom.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/mem/ocrom/ocrom_dp.vhdl b/src/mem/ocrom/ocrom_dp.vhdl index 228e1fae7..dbfddabc7 100644 --- a/src/mem/ocrom/ocrom_dp.vhdl +++ b/src/mem/ocrom/ocrom_dp.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/mem/ocrom/ocrom_sp.vhdl b/src/mem/ocrom/ocrom_sp.vhdl index 74cbb74c3..7609e2a0b 100644 --- a/src/mem/ocrom/ocrom_sp.vhdl +++ b/src/mem/ocrom/ocrom_sp.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/src/mem/sdram/sdram_ctrl_de0.vhdl b/src/mem/sdram/sdram_ctrl_de0.vhdl index 0044aa9e3..c18d5953a 100644 --- a/src/mem/sdram/sdram_ctrl_de0.vhdl +++ b/src/mem/sdram/sdram_ctrl_de0.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/src/mem/sdram/sdram_ctrl_fsm.vhdl b/src/mem/sdram/sdram_ctrl_fsm.vhdl index 150c561f5..989fc540d 100644 --- a/src/mem/sdram/sdram_ctrl_fsm.vhdl +++ b/src/mem/sdram/sdram_ctrl_fsm.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/src/mem/sdram/sdram_ctrl_phy_de0.vhdl b/src/mem/sdram/sdram_ctrl_phy_de0.vhdl index 5d8b8c75d..1cb3d7fe1 100644 --- a/src/mem/sdram/sdram_ctrl_phy_de0.vhdl +++ b/src/mem/sdram/sdram_ctrl_phy_de0.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl b/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl index 2a2287f21..620d3fb44 100644 --- a/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl +++ b/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/src/mem/sdram/sdram_ctrl_s3esk.vhdl b/src/mem/sdram/sdram_ctrl_s3esk.vhdl index 38e56a326..1d49b6189 100644 --- a/src/mem/sdram/sdram_ctrl_s3esk.vhdl +++ b/src/mem/sdram/sdram_ctrl_s3esk.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- diff --git a/src/misc/clock/clock.pkg.vhdl b/src/misc/clock/clock.pkg.vhdl new file mode 100644 index 000000000..98e36ac40 --- /dev/null +++ b/src/misc/clock/clock.pkg.vhdl @@ -0,0 +1,103 @@ +-- ============================================================================= +-- Authors: +-- Patrick Lehmann +-- Adrian Weiland +-- +-- Entity: +-- +-- Description: +-- ------------------------------------- +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.physical.all; +use work.utils.all; + + +package clock is + type T_TIME_VEC is array (natural range <>) of T_TIME; + constant RESOLUTION_TIMES : T_TIME_VEC(0 to 2) := (1.0e-9, 1.0e-6, 1.0e-3); + + attribute Count : natural; + attribute Bits : natural; + + type T_SECOND_RESOLUTION is (NANOSECONDS, MICROSECONDS, MILLISECONDS); + attribute Count of T_SECOND_RESOLUTION : type is T_SECOND_RESOLUTION'pos(T_SECOND_RESOLUTION'high) + 1; -- to find the num of registers available + attribute Bits of T_SECOND_RESOLUTION : type is log2ceil(T_SECOND_RESOLUTION'Count); -- no of bits required to represent the num of registers constant RESOLUTION_TIMES : T_TIME_VEC(0 to 2) := (1.0e-9, 1.0e-6, 1.0e-3); + + function to_enum(value : std_logic_vector) return T_SECOND_RESOLUTION; + function to_timebase(resolution : T_SECOND_RESOLUTION) return T_TIME; + + type T_CLOCK_DATETIME is record + secondsResolution : unsigned(31 downto 0); -- time in ns, us or ms + seconds : unsigned( 5 downto 0); + minutes : unsigned( 5 downto 0); + hours : unsigned( 4 downto 0); + day : unsigned( 4 downto 0); + month : unsigned( 3 downto 0); + year : unsigned(12 downto 0); + end record; + + function slv_to_datetime(value_HMS: std_logic_vector(31 downto 0); value_Ymd: std_logic_vector(31 downto 0)) return T_CLOCK_DATETIME; + function datetime_to_slv(value_slv: T_CLOCK_DATETIME) return std_logic_vector; +end package; + +package body clock is + + function to_enum(value : std_logic_vector) return T_SECOND_RESOLUTION is + constant pos : natural := to_integer(unsigned(value(T_SECOND_RESOLUTION'Bits - 1 downto 0))); + begin + return T_SECOND_RESOLUTION'val(minimum(pos, T_SECOND_RESOLUTION'Count - 1)); + end function; + + function to_timebase(resolution : T_SECOND_RESOLUTION) return T_TIME is + begin + return RESOLUTION_TIMES(T_SECOND_RESOLUTION'pos(resolution)); + end function; + + function slv_to_datetime(value_HMS: std_logic_vector(31 downto 0); value_Ymd: std_logic_vector(31 downto 0)) return T_CLOCK_DATETIME is + variable datetime : T_CLOCK_DATETIME; + begin + datetime.secondsResolution := (others => '0'); + datetime.seconds := unsigned(value_HMS( 5 downto 0)); + datetime.minutes := unsigned(value_HMS(11 downto 6)); + datetime.hours := unsigned(value_HMS(16 downto 12)); + datetime.day := unsigned(value_Ymd( 4 downto 0)); + datetime.month := unsigned(value_Ymd( 8 downto 5)); + datetime.year := unsigned(value_Ymd(21 downto 9)); + return datetime; + end function; + + function datetime_to_slv(value_slv: T_CLOCK_DATETIME) return std_logic_vector is + variable value_Ymd: std_logic_vector(31 downto 0) := (others => '0'); + variable value_HMS: std_logic_vector(31 downto 0) := (others => '0'); + begin + value_HMS( 5 downto 0) := std_logic_vector(value_slv.seconds); + value_HMS(11 downto 6) := std_logic_vector(value_slv.minutes); + value_HMS(16 downto 12) := std_logic_vector(value_slv.hours); + value_Ymd( 4 downto 0) := std_logic_vector(value_slv.day); + value_Ymd( 8 downto 5) := std_logic_vector(value_slv.month); + value_Ymd(21 downto 9) := std_logic_vector(value_slv.year); + return value_Ymd & value_HMS; + end function; + +end package body; diff --git a/src/misc/clock/clock_Counter.vhdl b/src/misc/clock/clock_Counter.vhdl new file mode 100644 index 000000000..58f867217 --- /dev/null +++ b/src/misc/clock/clock_Counter.vhdl @@ -0,0 +1,77 @@ +-- ============================================================================= +-- Authors: +-- +-- +-- Entity: +-- +-- Description: +-- ------------------------------------- +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.utils.all; + + +entity clock_Counter is + generic ( + MODULO : positive; + BITS : natural := log2ceilnz(MODULO) + ); + port ( + Clock : in std_logic; + Reset : in std_logic := '0'; + Enable : in std_logic := '1'; + Load : in std_logic := '0'; + + LoadValue : in unsigned(BITS - 1 downto 0); + Value : out unsigned(BITS - 1 downto 0); + WrapAround : out std_logic + ); +end entity; + + +architecture rtl of clock_Counter is + + signal Load_d : std_logic := '0'; + signal Load_re : std_logic; + signal CounterValue : unsigned(log2ceilnz(MODULO) - 1 downto 0) := (others => '0'); + +begin + Load_d <= Load when rising_edge(Clock); + Load_re <= not Load_d and Load; + + process (Clock) + begin + if rising_edge(Clock) then + if ((Reset or WrapAround) = '1') then + CounterValue <= (others => '0'); + elsif Load_re = '1' then + CounterValue <= LoadValue; + elsif Enable = '1' then + CounterValue <= CounterValue + 1; + end if; + end if; + end process; + + Value <= resize(CounterValue, BITS); + WrapAround <= Enable when (CounterValue = MODULO - 1) else '0'; +end architecture; diff --git a/src/misc/clock/clock_HighResolution.vhdl b/src/misc/clock/clock_HighResolution.vhdl new file mode 100644 index 000000000..c00b42753 --- /dev/null +++ b/src/misc/clock/clock_HighResolution.vhdl @@ -0,0 +1,202 @@ +-- ============================================================================= +-- Authors: +-- +-- +-- Entity: +-- +-- Description: +-- ------------------------------------- +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.physical.all; +use work.utils.all; +use work.clock.all; + + +entity clock_HighResolution is + generic ( + SECOND_RESOLUTION : T_SECOND_RESOLUTION := MILLISECONDS; + CLOCK_FREQUENCY : FREQ + ); + port ( + Clock : in std_logic; + Reset : in std_logic; + + Load_nanoseconds : in std_logic; + Load_datetime : in std_logic; + Nanoseconds_to_load : in unsigned(63 downto 0); + Datetime_to_load : in T_CLOCK_Datetime; + Ns_inc : in std_logic; + Ns_dec : in std_logic; + + Nanoseconds : out unsigned(63 downto 0); + Datetime : out T_CLOCK_Datetime + ); +end entity; + + +architecture rtl of clock_HighResolution is + + signal counter_ns : Nanoseconds'subtype := (others => '0'); + signal secTick : std_logic; + signal minTick : std_logic; + signal hourTick : std_logic; + signal dayTick : std_logic; + signal monthTick : std_logic; + signal yearTick : std_logic; + +begin + nanoSecTimer: entity work.clock_Timer + generic map ( + CLOCK_FREQ => CLOCK_FREQUENCY, + TIME_BASE => 1.0e-9, + WRAP_TIME => 0.0, + CLOCK_BITS => Nanoseconds_to_load'length + ) + port map ( + Clock => Clock, + Reset => Reset, + Increment => Ns_inc, + Decrement => Ns_dec, + Load => Load_nanoseconds, + Time_to_load => Nanoseconds_to_load, + Current_time => counter_ns, + Overflow => open + ); + + Nanoseconds <= counter_ns; + + secTimer: entity work.clock_Timer + generic map ( + CLOCK_FREQ => CLOCK_FREQUENCY, + TIME_BASE => to_timebase(SECOND_RESOLUTION), + WRAP_TIME => 1.0, + CLOCK_BITS => 32 + ) + port map ( + Clock => Clock, + Reset => Reset, + Increment => '0', -- not connected + Decrement => '0', -- not connected + Load => Load_datetime, + Time_to_load => (31 downto 0 => '0'), + Current_time => Datetime.secondsResolution, + Overflow => secTick + ); + + secTime: entity work.clock_Counter + generic map ( + MODULO => 60, + BITS => Datetime.seconds'length + ) + port map ( + Clock => Clock, + Reset => Reset, + Enable => secTick, + Load => Load_datetime, + + LoadValue => Datetime_to_load.seconds, + Value => Datetime.seconds, + WrapAround => minTick + ); + + minTime: entity work.clock_Counter + generic map ( + MODULO => 60, + BITS => Datetime.minutes'length + ) + port map ( + Clock => Clock, + Reset => Reset, + Enable => minTick, + Load => Load_datetime, + + LoadValue => Datetime_to_load.minutes, + Value => Datetime.minutes, + WrapAround => hourTick + ); + + hourTime: entity work.clock_Counter + generic map ( + MODULO => 24, + BITS => Datetime.hours'length + ) + port map ( + Clock => Clock, + Reset => Reset, + Enable => hourTick, + Load => Load_datetime, + + LoadValue => Datetime_to_load.hours, + Value => Datetime.hours, + WrapAround => dayTick + ); + + dayTime: entity work.clock_Counter + generic map ( + MODULO => 31, + BITS => Datetime.day'length + ) + port map ( + Clock => Clock, + Reset => Reset, + Enable => dayTick, + Load => Load_datetime, + + LoadValue => Datetime_to_load.day, + Value => Datetime.day, + WrapAround => monthTick + ); + + monthTime: entity work.clock_Counter + generic map ( + MODULO => 12, + BITS => Datetime.month'length + ) + port map ( + Clock => Clock, + Reset => Reset, + Enable => monthTick, + Load => Load_datetime, + + LoadValue => Datetime_to_load.month, + Value => Datetime.month, + WrapAround => yearTick + ); + + yearTime: entity work.clock_Counter + generic map ( + MODULO => 8192, + BITS => Datetime.year'length + ) + port map ( + Clock => Clock, + Reset => Reset, + Enable => yearTick, + Load => Load_datetime, + + LoadValue => Datetime_to_load.year, + Value => Datetime.year, + WrapAround => open + ); +end architecture; diff --git a/src/misc/clock/clock_Timer.vhdl b/src/misc/clock/clock_Timer.vhdl new file mode 100644 index 000000000..de32264de --- /dev/null +++ b/src/misc/clock/clock_Timer.vhdl @@ -0,0 +1,154 @@ +-- ============================================================================= +-- Authors: +-- Stefan Unrein +-- Adrian Weiland +-- +-- Entity: +-- +-- Description: +-- ------------------------------------- +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.ALL; +use IEEE.numeric_std.ALL; +use IEEE.math_real.all; + +use work.math.all; +use work.utils.all; +use work.physical.all; + + +entity clock_Timer is + generic ( + DEBUG : boolean := false; + CLOCK_FREQ : Freq := 186 MHz; + TIME_BASE : T_TIME := 1.0e-9; + WRAP_TIME : T_TIME := 1.0e-6; -- 0.0 to disable wrap + CLOCK_BITS : natural := 64 + ); + port ( + Clock : in std_logic; + Reset : in std_logic; + Increment : in std_logic; + Decrement : in std_logic; + Load : in std_logic; + Time_to_load : in unsigned (CLOCK_BITS - 1 downto 0); + Current_time : out unsigned (CLOCK_BITS - 1 downto 0); + Overflow : out std_logic + ); +end entity; + +architecture rtl of clock_Timer is + + function "-" (left : t_natvec; right : integer) return t_natvec is + variable result : t_natvec(left'range) := (others => 0); + begin + for i in left'range loop + if left(i) > right then + result(i) := left(i) - right; + end if; + end loop; + return result; + end function; + + constant PERIOD : T_TIME := to_time(CLOCK_FREQ); + constant PERIOD_FRACT : t_fractional := fract(PERIOD / TIME_BASE, 1000000, 1.0e-12); + constant INCREMENT_FULL : natural := PERIOD_FRACT.whole; + constant INCREMENT_VEC : t_natvec := fract2timing(PERIOD_FRACT); + + constant WRAP_VALUE : integer := ite(WRAP_TIME /= 0.0, to_int(WRAP_TIME / TIME_BASE, 1.0), 0); + + signal wrap_around : std_logic; + signal counter : unsigned(CLOCK_BITS - 1 downto 0) := (others => '0'); + + signal Load_d : std_logic := '0'; + signal Load_re : std_logic; + signal correct : std_logic; + signal to_Increment : unsigned(log2ceilnz(INCREMENT_FULL + 3) - 1 downto 0); + +begin + assert not DEBUG report "periodic_fract for " & real'image(PERIOD) & "is: " & integer'image(INCREMENT_FULL) & ", " & integer'image(PERIOD_FRACT.numerator) & ", " & integer'image(PERIOD_FRACT.denominator) & "." severity note; + + Load_d <= Load when rising_edge(Clock); + Load_re <= not Load_d and Load; + + Current_time <= counter; + + correction_counter_gen: if INCREMENT_VEC'length = 1 and INCREMENT_VEC(0) = 0 generate + correct <= '0'; + else generate + signal correction_counter : unsigned(log2ceilnz(PERIOD_FRACT.denominator) - 1 downto 0) := (others => '0'); + begin + correct <= '1' when indexof(INCREMENT_VEC - 1, to_integer(correction_counter)) >= 0 else '0'; + + correction_counter_proc : process(Clock) + begin + if rising_edge(Clock) then + if Reset = '1' or Load_re = '1' or (correction_counter >= PERIOD_FRACT.denominator - 1 and PERIOD_FRACT.numerator > 0) then + correction_counter <= (others => '0'); + else + correction_counter <= correction_counter + 1; + end if; + end if; + end process; + end generate; + + wrap_gen : if WRAP_VALUE /= 0 and INCREMENT_FULL > 0 generate + wrap_around <= to_sl(counter >= WRAP_VALUE - 1); + elsif WRAP_VALUE /= 0 and INCREMENT_FULL = 0 generate + wrap_around <= to_sl(counter >= WRAP_VALUE - 1) and correct; + else generate + wrap_around <= '0'; + end generate; + + Overflow <= wrap_around; + + counter_proc : process(Clock) + begin + if rising_edge(Clock) then + if Reset = '1' then + counter <= (others => '0'); + elsif Load_re = '1' then + counter <= Time_to_load + INCREMENT_FULL; + elsif wrap_around = '1' then + counter <= counter - to_unsigned(WRAP_VALUE, CLOCK_BITS) + to_Increment; + else + counter <= counter + to_Increment; + end if; + end if; + end process; + + Increment_proc : process(Increment, Decrement, correct) + variable temp : unsigned(to_Increment'range); + begin + temp := to_unsigned(INCREMENT_FULL, temp'length); + if Increment = '1' then + temp := temp + 1; + end if; + if correct = '1' then + temp := temp + 1; + end if; + if Decrement = '1' then + temp := temp - 1; + end if; + to_Increment <= temp; + end process; + +end architecture; diff --git a/src/misc/filter/filter_and.vhdl b/src/misc/filter/filter_and.vhdl index 78c39b107..e6b182901 100644 --- a/src/misc/filter/filter_and.vhdl +++ b/src/misc/filter/filter_and.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/misc/filter/filter_mean.vhdl b/src/misc/filter/filter_mean.vhdl index cde9cd851..da0584892 100644 --- a/src/misc/filter/filter_mean.vhdl +++ b/src/misc/filter/filter_mean.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/misc/filter/filter_or.vhdl b/src/misc/filter/filter_or.vhdl index ea46d74a0..3554efeac 100644 --- a/src/misc/filter/filter_or.vhdl +++ b/src/misc/filter/filter_or.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/misc/gearbox/gearbox.pro b/src/misc/gearbox/gearbox.pro index 8e973d7ae..71df4b9e1 100644 --- a/src/misc/gearbox/gearbox.pro +++ b/src/misc/gearbox/gearbox.pro @@ -3,7 +3,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/misc/gearbox/gearbox_down_cc.vhdl b/src/misc/gearbox/gearbox_down_cc.vhdl index 3faca1dd1..885dbdd4d 100644 --- a/src/misc/gearbox/gearbox_down_cc.vhdl +++ b/src/misc/gearbox/gearbox_down_cc.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/misc/gearbox/gearbox_down_dc.vhdl b/src/misc/gearbox/gearbox_down_dc.vhdl index adae0c8f6..c84136097 100644 --- a/src/misc/gearbox/gearbox_down_dc.vhdl +++ b/src/misc/gearbox/gearbox_down_dc.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/misc/gearbox/gearbox_up_cc.vhdl b/src/misc/gearbox/gearbox_up_cc.vhdl index 8567ee848..53ddc35cd 100644 --- a/src/misc/gearbox/gearbox_up_cc.vhdl +++ b/src/misc/gearbox/gearbox_up_cc.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/misc/gearbox/gearbox_up_dc.vhdl b/src/misc/gearbox/gearbox_up_dc.vhdl index 49f7fddd1..27a4fe706 100644 --- a/src/misc/gearbox/gearbox_up_dc.vhdl +++ b/src/misc/gearbox/gearbox_up_dc.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/misc/misc.pro b/src/misc/misc.pro index d961e1e14..d51ad9dcf 100644 --- a/src/misc/misc.pro +++ b/src/misc/misc.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -19,16 +19,23 @@ # limitations under the License. # ============================================================================= +# ./misc_ClockBuffer.vhdl ; # Already analyzed in PoC.pro +disabled ./misc_ConditionCounter.vhdl +disabled ./misc_Data_Swapper.vhdl analyze ./misc_Delay.vhdl +analyze ./misc_FrequencyMeasurement.vhdl analyze ./misc_Sequencer.vhdl analyze ./misc_StrobeGenerator.vhdl analyze ./misc_StrobeLimiter.vhdl analyze ./misc_StrobeStretcher.vhdl -analyze ./misc_FrequencyMeasurement.vhdl analyze ./misc_bit_lz.vhdl +analyze ./clock/clock.pkg.vhdl +analyze ./clock/clock_Counter.vhdl +analyze ./clock/clock_Timer.vhdl +analyze ./clock/clock_HighResolution.vhdl + include ./filter/filter.pro include ./stat/stat.pro -# Included in PoC.pro for cross-dependency include ./gearbox/gearbox.pro diff --git a/src/misc/misc_Delay.vhdl b/src/misc/misc_Delay.vhdl index dd2c89432..0fa21a2d2 100644 --- a/src/misc/misc_Delay.vhdl +++ b/src/misc/misc_Delay.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/misc/misc_FrequencyMeasurement.vhdl b/src/misc/misc_FrequencyMeasurement.vhdl index 42bfd2572..393086bfa 100644 --- a/src/misc/misc_FrequencyMeasurement.vhdl +++ b/src/misc/misc_FrequencyMeasurement.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/misc/misc_StrobeGenerator.vhdl b/src/misc/misc_StrobeGenerator.vhdl index b36d4ac6d..5a5f3cc44 100644 --- a/src/misc/misc_StrobeGenerator.vhdl +++ b/src/misc/misc_StrobeGenerator.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/misc_StrobeLimiter.vhdl b/src/misc/misc_StrobeLimiter.vhdl index 599200e55..1d0dbc608 100644 --- a/src/misc/misc_StrobeLimiter.vhdl +++ b/src/misc/misc_StrobeLimiter.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/misc_StrobeStretcher.vhdl b/src/misc/misc_StrobeStretcher.vhdl index a2fe8f788..ed544e38d 100644 --- a/src/misc/misc_StrobeStretcher.vhdl +++ b/src/misc/misc_StrobeStretcher.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/misc/misc_bit_lz.vhdl b/src/misc/misc_bit_lz.vhdl index c76e68249..bf26496d1 100644 --- a/src/misc/misc_bit_lz.vhdl +++ b/src/misc/misc_bit_lz.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Description: -- diff --git a/src/misc/stat/stat.pro b/src/misc/stat/stat.pro index 751931132..579491188 100644 --- a/src/misc/stat/stat.pro +++ b/src/misc/stat/stat.pro @@ -3,7 +3,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/misc/stat/stat_Average.vhdl b/src/misc/stat/stat_Average.vhdl index e095a34a7..6c834403b 100644 --- a/src/misc/stat/stat_Average.vhdl +++ b/src/misc/stat/stat_Average.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/misc/stat/stat_Histogram.vhdl b/src/misc/stat/stat_Histogram.vhdl index ca699576e..91b6a2e69 100644 --- a/src/misc/stat/stat_Histogram.vhdl +++ b/src/misc/stat/stat_Histogram.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/misc/stat/stat_Maximum.vhdl b/src/misc/stat/stat_Maximum.vhdl index f21e42fb5..3da41e74b 100644 --- a/src/misc/stat/stat_Maximum.vhdl +++ b/src/misc/stat/stat_Maximum.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/misc/stat/stat_Minimum.vhdl b/src/misc/stat/stat_Minimum.vhdl index a4a3a9249..3f2bbafe3 100644 --- a/src/misc/stat/stat_Minimum.vhdl +++ b/src/misc/stat/stat_Minimum.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/arp/arp.pro b/src/net/arp/arp.pro index 280b72d31..bc26b351a 100644 --- a/src/net/arp/arp.pro +++ b/src/net/arp/arp.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/net/arp/arp_BroadCast_Receiver.vhdl b/src/net/arp/arp_BroadCast_Receiver.vhdl index cd2612861..c34c79057 100644 --- a/src/net/arp/arp_BroadCast_Receiver.vhdl +++ b/src/net/arp/arp_BroadCast_Receiver.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/arp/arp_BroadCast_Requester.vhdl b/src/net/arp/arp_BroadCast_Requester.vhdl index f5cfb3aee..4653ac5f7 100644 --- a/src/net/arp/arp_BroadCast_Requester.vhdl +++ b/src/net/arp/arp_BroadCast_Requester.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/arp/arp_Cache.vhdl b/src/net/arp/arp_Cache.vhdl index 76f01493e..18b4b3b03 100644 --- a/src/net/arp/arp_Cache.vhdl +++ b/src/net/arp/arp_Cache.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/arp/arp_IPPool.vhdl b/src/net/arp/arp_IPPool.vhdl index 6f6c9d364..f179058c1 100644 --- a/src/net/arp/arp_IPPool.vhdl +++ b/src/net/arp/arp_IPPool.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/arp/arp_UniCast_Receiver.vhdl b/src/net/arp/arp_UniCast_Receiver.vhdl index 9658b8820..40dbec925 100644 --- a/src/net/arp/arp_UniCast_Receiver.vhdl +++ b/src/net/arp/arp_UniCast_Receiver.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/arp/arp_UniCast_Responder.vhdl b/src/net/arp/arp_UniCast_Responder.vhdl index a98d606ac..216af6948 100644 --- a/src/net/arp/arp_UniCast_Responder.vhdl +++ b/src/net/arp/arp_UniCast_Responder.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/arp/arp_Wrapper.vhdl b/src/net/arp/arp_Wrapper.vhdl index e2f708fa6..4901cb7f7 100644 --- a/src/net/arp/arp_Wrapper.vhdl +++ b/src/net/arp/arp_Wrapper.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/icmpv4/icmpv4.pro b/src/net/icmpv4/icmpv4.pro index 7b0107bf3..88bec60f5 100644 --- a/src/net/icmpv4/icmpv4.pro +++ b/src/net/icmpv4/icmpv4.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/net/icmpv4/icmpv4_RX.vhdl b/src/net/icmpv4/icmpv4_RX.vhdl index d4d69807e..b7928c16e 100644 --- a/src/net/icmpv4/icmpv4_RX.vhdl +++ b/src/net/icmpv4/icmpv4_RX.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/icmpv4/icmpv4_TX.vhdl b/src/net/icmpv4/icmpv4_TX.vhdl index d5c3474dd..c19bd253c 100644 --- a/src/net/icmpv4/icmpv4_TX.vhdl +++ b/src/net/icmpv4/icmpv4_TX.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/icmpv4/icmpv4_Wrapper.vhdl b/src/net/icmpv4/icmpv4_Wrapper.vhdl index c9cf691bf..cb88e8a1d 100644 --- a/src/net/icmpv4/icmpv4_Wrapper.vhdl +++ b/src/net/icmpv4/icmpv4_Wrapper.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/ipv4/ipv4.pro b/src/net/ipv4/ipv4.pro index 9d766a742..c5ebf612d 100644 --- a/src/net/ipv4/ipv4.pro +++ b/src/net/ipv4/ipv4.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/net/ipv4/ipv4_FrameLoopback.vhdl b/src/net/ipv4/ipv4_FrameLoopback.vhdl index cb4637190..0a30280e2 100644 --- a/src/net/ipv4/ipv4_FrameLoopback.vhdl +++ b/src/net/ipv4/ipv4_FrameLoopback.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/ipv4/ipv4_RX.vhdl b/src/net/ipv4/ipv4_RX.vhdl index 4afbbc519..f7a7792a8 100644 --- a/src/net/ipv4/ipv4_RX.vhdl +++ b/src/net/ipv4/ipv4_RX.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/ipv4/ipv4_TX.vhdl b/src/net/ipv4/ipv4_TX.vhdl index 51db768a3..a0d2b9714 100644 --- a/src/net/ipv4/ipv4_TX.vhdl +++ b/src/net/ipv4/ipv4_TX.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/ipv4/ipv4_Wrapper.vhdl b/src/net/ipv4/ipv4_Wrapper.vhdl index 6a3b99296..e09c7e451 100644 --- a/src/net/ipv4/ipv4_Wrapper.vhdl +++ b/src/net/ipv4/ipv4_Wrapper.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/ipv6/ipv6.pro b/src/net/ipv6/ipv6.pro index 3b0cf205e..516bb917a 100644 --- a/src/net/ipv6/ipv6.pro +++ b/src/net/ipv6/ipv6.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/net/ipv6/ipv6_FrameLoopback.vhdl b/src/net/ipv6/ipv6_FrameLoopback.vhdl index fae5da1ae..c8a47c4c3 100644 --- a/src/net/ipv6/ipv6_FrameLoopback.vhdl +++ b/src/net/ipv6/ipv6_FrameLoopback.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/ipv6/ipv6_RX.vhdl b/src/net/ipv6/ipv6_RX.vhdl index 19dba83e1..56006de44 100644 --- a/src/net/ipv6/ipv6_RX.vhdl +++ b/src/net/ipv6/ipv6_RX.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/ipv6/ipv6_TX.vhdl b/src/net/ipv6/ipv6_TX.vhdl index 313906eb9..40abadecd 100644 --- a/src/net/ipv6/ipv6_TX.vhdl +++ b/src/net/ipv6/ipv6_TX.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/ipv6/ipv6_Wrapper.vhdl b/src/net/ipv6/ipv6_Wrapper.vhdl index f0235c697..4a10fb33a 100644 --- a/src/net/ipv6/ipv6_Wrapper.vhdl +++ b/src/net/ipv6/ipv6_Wrapper.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/mac/mac.pro b/src/net/mac/mac.pro index ad92b39a7..f52e33163 100644 --- a/src/net/mac/mac.pro +++ b/src/net/mac/mac.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/net/mac/mac_FrameLoopback.vhdl b/src/net/mac/mac_FrameLoopback.vhdl index 4a2b8e455..6bd2b2adb 100644 --- a/src/net/mac/mac_FrameLoopback.vhdl +++ b/src/net/mac/mac_FrameLoopback.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/mac/mac_RX_DestMAC_Switch.vhdl b/src/net/mac/mac_RX_DestMAC_Switch.vhdl index 5c08b61bd..9eace7812 100644 --- a/src/net/mac/mac_RX_DestMAC_Switch.vhdl +++ b/src/net/mac/mac_RX_DestMAC_Switch.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/mac/mac_RX_SrcMAC_Filter.vhdl b/src/net/mac/mac_RX_SrcMAC_Filter.vhdl index b32ffc332..46b8837f5 100644 --- a/src/net/mac/mac_RX_SrcMAC_Filter.vhdl +++ b/src/net/mac/mac_RX_SrcMAC_Filter.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/mac/mac_RX_Type_Switch.vhdl b/src/net/mac/mac_RX_Type_Switch.vhdl index 72ba6c4f8..67cc490ac 100644 --- a/src/net/mac/mac_RX_Type_Switch.vhdl +++ b/src/net/mac/mac_RX_Type_Switch.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/mac/mac_TX_DestMAC_Prepender.vhdl b/src/net/mac/mac_TX_DestMAC_Prepender.vhdl index 77f557945..77c8f9d13 100644 --- a/src/net/mac/mac_TX_DestMAC_Prepender.vhdl +++ b/src/net/mac/mac_TX_DestMAC_Prepender.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl b/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl index ab3382e00..cf280b16c 100644 --- a/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl +++ b/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/mac/mac_TX_Type_Prepender.vhdl b/src/net/mac/mac_TX_Type_Prepender.vhdl index 1a3165d8e..3f7f165b7 100644 --- a/src/net/mac/mac_TX_Type_Prepender.vhdl +++ b/src/net/mac/mac_TX_Type_Prepender.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/net/mac/mac_Wrapper.vhdl b/src/net/mac/mac_Wrapper.vhdl index bc35d74c4..b0551745d 100644 --- a/src/net/mac/mac_Wrapper.vhdl +++ b/src/net/mac/mac_Wrapper.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/net.pkg.vhdl b/src/net/net.pkg.vhdl index c6b4ee65e..285f08e37 100644 --- a/src/net/net.pkg.vhdl +++ b/src/net/net.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/net/net.pro b/src/net/net.pro index 93bd70584..4a103dcf5 100644 --- a/src/net/net.pro +++ b/src/net/net.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/net/net_FrameChecksum.vhdl b/src/net/net_FrameChecksum.vhdl index 9a9a371e4..2feccf1ee 100644 --- a/src/net/net_FrameChecksum.vhdl +++ b/src/net/net_FrameChecksum.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/udp/udp.pro b/src/net/udp/udp.pro index 6d697c324..7bbda38a0 100644 --- a/src/net/udp/udp.pro +++ b/src/net/udp/udp.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/net/udp/udp_FrameLoopback.vhdl b/src/net/udp/udp_FrameLoopback.vhdl index 6cf0ed984..7f360c294 100644 --- a/src/net/udp/udp_FrameLoopback.vhdl +++ b/src/net/udp/udp_FrameLoopback.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/udp/udp_RX.vhdl b/src/net/udp/udp_RX.vhdl index 537794212..be79cebc0 100644 --- a/src/net/udp/udp_RX.vhdl +++ b/src/net/udp/udp_RX.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/udp/udp_TX.vhdl b/src/net/udp/udp_TX.vhdl index 18887f792..776d9324a 100644 --- a/src/net/udp/udp_TX.vhdl +++ b/src/net/udp/udp_TX.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/net/udp/udp_Wrapper.vhdl b/src/net/udp/udp_Wrapper.vhdl index 64ff36730..c74681b43 100644 --- a/src/net/udp/udp_Wrapper.vhdl +++ b/src/net/udp/udp_Wrapper.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sim/README.md b/src/sim/README.md index 96c99bce1..5b0c50ad7 100644 --- a/src/sim/README.md +++ b/src/sim/README.md @@ -49,15 +49,15 @@ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; -library PoC; -use PoC.utils.all; -use PoC.vectors.all; -use PoC.strings.all; -use PoC.physical.all; + +use work.utils.all; +use work.vectors.all; +use work.strings.all; +use work.physical.all; -- simulation only packages -use PoC.sim_global.all; -use PoC.sim_types.all; -use PoC.simulation.all; +use work.sim_global.all; +use work.sim_types.all; +use work.simulation.all; entity my_frist_tb is end entity; @@ -86,7 +86,7 @@ begin end process; -- Unit under test - UUT : entity PoC.my_first + UUT : entity work.my_first generic map ( BITS => BITS -- diff --git a/src/sim/sim.pro b/src/sim/sim.pro index dead02a9c..fa6f56b67 100644 --- a/src/sim/sim.pro +++ b/src/sim/sim.pro @@ -5,7 +5,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/sim/sim_VCDParser.vhdl b/src/sim/sim_VCDParser.vhdl index 035361587..61bf0b8e3 100644 --- a/src/sim/sim_VCDParser.vhdl +++ b/src/sim/sim_VCDParser.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sort/sort.pro b/src/sort/sort.pro index 9470a842b..250a60794 100644 --- a/src/sort/sort.pro +++ b/src/sort/sort.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/sort/sort_lru_list.vhdl b/src/sort/sort_lru_list.vhdl index 500b82f6f..9707976db 100644 --- a/src/sort/sort_lru_list.vhdl +++ b/src/sort/sort_lru_list.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Martin Zabel diff --git a/src/sort/sortnet/sortnet.pkg.vhdl b/src/sort/sortnet/sortnet.pkg.vhdl index d5fd7726e..a93f4f565 100644 --- a/src/sort/sortnet/sortnet.pkg.vhdl +++ b/src/sort/sortnet/sortnet.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sort/sortnet/sortnet.pro b/src/sort/sortnet/sortnet.pro index 28d96f881..b1869e252 100644 --- a/src/sort/sortnet/sortnet.pro +++ b/src/sort/sortnet/sortnet.pro @@ -3,7 +3,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/sort/sortnet/sortnet_BitonicSort.vhdl b/src/sort/sortnet/sortnet_BitonicSort.vhdl index 6b78c59c8..07138cf08 100644 --- a/src/sort/sortnet/sortnet_BitonicSort.vhdl +++ b/src/sort/sortnet/sortnet_BitonicSort.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl b/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl index ecea83467..52f6ada5f 100644 --- a/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl +++ b/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl b/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl index 4f6864326..8b73a0a5f 100644 --- a/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl +++ b/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sort/sortnet/sortnet_OddEvenSort.vhdl b/src/sort/sortnet/sortnet_OddEvenSort.vhdl index 73f943b1f..660514d2e 100644 --- a/src/sort/sortnet/sortnet_OddEvenSort.vhdl +++ b/src/sort/sortnet/sortnet_OddEvenSort.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sort/sortnet/sortnet_Stream_Adapter.vhdl b/src/sort/sortnet/sortnet_Stream_Adapter.vhdl index d1daff45a..7f542c40a 100644 --- a/src/sort/sortnet/sortnet_Stream_Adapter.vhdl +++ b/src/sort/sortnet/sortnet_Stream_Adapter.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl b/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl index 1eb6cdb86..117da0ec9 100644 --- a/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl +++ b/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sort/sortnet/sortnet_Transform.vhdl b/src/sort/sortnet/sortnet_Transform.vhdl index 710d15117..a6dde01cb 100644 --- a/src/sort/sortnet/sortnet_Transform.vhdl +++ b/src/sort/sortnet/sortnet_Transform.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sync/sync.pkg.vhdl b/src/sync/sync.pkg.vhdl index dec0742ef..4d230fb7c 100644 --- a/src/sync/sync.pkg.vhdl +++ b/src/sync/sync.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/sync/sync.pro b/src/sync/sync.pro index e567827a1..a6b6bfc0f 100644 --- a/src/sync/sync.pro +++ b/src/sync/sync.pro @@ -3,7 +3,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -31,7 +31,7 @@ if { $::poc::vendor eq "Xilinx" } { analyze ./sync_Pulse_Altera.vhdl } elseif { $::poc::vendor ne "GENERIC" } { - puts "Unknow vendor '$::poc::vendor' in arith!" + puts "Unknown vendor '$::poc::vendor'!" exit 1 } diff --git a/src/sync/sync_Bits.vhdl b/src/sync/sync_Bits.vhdl index ce4727ac8..5734309bd 100644 --- a/src/sync/sync_Bits.vhdl +++ b/src/sync/sync_Bits.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -40,7 +37,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/sync/sync_Bits_Altera.vhdl b/src/sync/sync_Bits_Altera.vhdl index 0a6c09109..8637cd8d3 100644 --- a/src/sync/sync_Bits_Altera.vhdl +++ b/src/sync/sync_Bits_Altera.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sync/sync_Bits_Xilinx.vhdl b/src/sync/sync_Bits_Xilinx.vhdl index 17d9964af..123396f57 100644 --- a/src/sync/sync_Bits_Xilinx.vhdl +++ b/src/sync/sync_Bits_Xilinx.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -43,7 +40,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/sync/sync_Command.vhdl b/src/sync/sync_Command.vhdl index 0189630ec..a3aeb503c 100644 --- a/src/sync/sync_Command.vhdl +++ b/src/sync/sync_Command.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Steffen Koehler @@ -23,7 +20,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/sync/sync_Pulse.vhdl b/src/sync/sync_Pulse.vhdl index 45247b3c6..f44fab903 100644 --- a/src/sync/sync_Pulse.vhdl +++ b/src/sync/sync_Pulse.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sync/sync_Pulse_Altera.vhdl b/src/sync/sync_Pulse_Altera.vhdl index 471dd418d..1aac60964 100644 --- a/src/sync/sync_Pulse_Altera.vhdl +++ b/src/sync/sync_Pulse_Altera.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sync/sync_Pulse_Xilinx.vhdl b/src/sync/sync_Pulse_Xilinx.vhdl index 6005fb629..4c66ab938 100644 --- a/src/sync/sync_Pulse_Xilinx.vhdl +++ b/src/sync/sync_Pulse_Xilinx.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/sync/sync_Reset.vhdl b/src/sync/sync_Reset.vhdl index 06cf78448..66468da79 100644 --- a/src/sync/sync_Reset.vhdl +++ b/src/sync/sync_Reset.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -33,7 +30,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/sync/sync_Reset_Altera.vhdl b/src/sync/sync_Reset_Altera.vhdl index beccab9f0..508d1ef44 100644 --- a/src/sync/sync_Reset_Altera.vhdl +++ b/src/sync/sync_Reset_Altera.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/sync/sync_Reset_Xilinx.vhdl b/src/sync/sync_Reset_Xilinx.vhdl index 6f565995d..d224a707b 100644 --- a/src/sync/sync_Reset_Xilinx.vhdl +++ b/src/sync/sync_Reset_Xilinx.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -26,7 +23,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/sync/sync_Strobe.vhdl b/src/sync/sync_Strobe.vhdl index c96b1fc5a..121c7dcaa 100644 --- a/src/sync/sync_Strobe.vhdl +++ b/src/sync/sync_Strobe.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Steffen Koehler @@ -28,7 +25,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/sync/sync_Vector.vhdl b/src/sync/sync_Vector.vhdl index 7562a1ff5..24bcd4b15 100644 --- a/src/sync/sync_Vector.vhdl +++ b/src/sync/sync_Vector.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Steffen Koehler -- Patrick Lehmann @@ -22,9 +19,9 @@ -- -- License: -- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture --- Copyright 2025-2025 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/xil/xil.pkg.vhdl b/src/xil/xil.pkg.vhdl index 9b7933f25..49e716e7d 100644 --- a/src/xil/xil.pkg.vhdl +++ b/src/xil/xil.pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- @@ -17,7 +14,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/src/xil/xil.pro b/src/xil/xil.pro index a6685007b..28a472055 100644 --- a/src/xil/xil.pro +++ b/src/xil/xil.pro @@ -5,7 +5,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/xil/xil_BSCAN.vhdl b/src/xil/xil_BSCAN.vhdl index 7a6bbea2e..265fe73bd 100644 --- a/src/xil/xil_BSCAN.vhdl +++ b/src/xil/xil_BSCAN.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/xil/xil_DNAPort.vhdl b/src/xil/xil_DNAPort.vhdl index 2a76630ac..0cbda1690 100644 --- a/src/xil/xil_DNAPort.vhdl +++ b/src/xil/xil_DNAPort.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Stefan Unrein @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/src/xil/xil_Reconfigurator.vhdl b/src/xil/xil_Reconfigurator.vhdl index 0b359c31e..0af76604f 100644 --- a/src/xil/xil_Reconfigurator.vhdl +++ b/src/xil/xil_Reconfigurator.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/src/xil/xil_SystemMonitor.vhdl b/src/xil/xil_SystemMonitor.vhdl index 8607427fc..0e0b64c3a 100644 --- a/src/xil/xil_SystemMonitor.vhdl +++ b/src/xil/xil_SystemMonitor.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/OsvvmCommon.pkg.vhdl b/tb/OsvvmCommon.pkg.vhdl new file mode 100644 index 000000000..79992af99 --- /dev/null +++ b/tb/OsvvmCommon.pkg.vhdl @@ -0,0 +1,28 @@ +-- ============================================================================= +-- Brief +-- Package to set the OSVVM result directory +-- +-- Author(s) +-- Jonas Schreiner +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +package OsvvmTestCommonPkg is + -- FIXME: check if this is still needed. The constant was used by OSVVM in tranings, but is not relevant for normal testbenches. + constant OSVVM_RESULTS_DIR : string := ""; +end OsvvmTestCommonPkg; diff --git a/tb/RunAllTests.pro b/tb/RunAllTests.pro index b7614f379..db05a3075 100644 --- a/tb/RunAllTests.pro +++ b/tb/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -19,15 +19,17 @@ # limitations under the License. # ============================================================================= +library tb_common +include ./common.pro + include ./arith/RunAllTests.pro include ./bus/RunAllTests.pro -include ./sync/RunAllTests.pro #include ./cache/RunAllTests.pro #include ./common/RunAllTests.pro -#include ./dstruct/RunAllTests.pro +disabled ./dstruct/RunAllTests.pro #include ./fifo/RunAllTests.pro -#include ./io/RunAllTests.pro +disabled ./io/RunAllTests.pro #include ./mem/RunAllTests.pro -#include ./misc/RunAllTests.pro +include ./misc/RunAllTests.pro #include ./sim/RunAllTests.pro #include ./sort/RunAllTests.pro diff --git a/tb/arith/RunAllTests.pro b/tb/arith/RunAllTests.pro index d9d6cba56..b668dca0d 100644 --- a/tb/arith/RunAllTests.pro +++ b/tb/arith/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -19,7 +19,8 @@ # limitations under the License. # ============================================================================= -TestSuite PoC.arith +# TestSuite PoC.arith +# Deactivated to avoid failure on non-existing testcases library tb_arith diff --git a/tb/arith/addw/RunAllTests.pro b/tb/arith/addw/RunAllTests.pro index 2c2084151..c5b2b6cfd 100644 --- a/tb/arith/addw/RunAllTests.pro +++ b/tb/arith/addw/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/addw/arith_addw_Simple.vhdl b/tb/arith/addw/arith_addw_Simple.vhdl index 4abcdacfd..f03a6b482 100644 --- a/tb/arith/addw/arith_addw_Simple.vhdl +++ b/tb/arith/addw/arith_addw_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/addw/arith_addw_TestController.vhdl b/tb/arith/addw/arith_addw_TestController.vhdl index 463c60471..25ecff82c 100644 --- a/tb/arith/addw/arith_addw_TestController.vhdl +++ b/tb/arith/addw/arith_addw_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/addw/arith_addw_TestController_pkg.vhdl b/tb/arith/addw/arith_addw_TestController_pkg.vhdl index 61b245bea..2eae3ccd2 100644 --- a/tb/arith/addw/arith_addw_TestController_pkg.vhdl +++ b/tb/arith/addw/arith_addw_TestController_pkg.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/addw/arith_addw_TestHarness.vhdl b/tb/arith/addw/arith_addw_TestHarness.vhdl index 55ffcea67..26c4fdd61 100644 --- a/tb/arith/addw/arith_addw_TestHarness.vhdl +++ b/tb/arith/addw/arith_addw_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/carrychain_inc/RunAllTests.pro b/tb/arith/carrychain_inc/RunAllTests.pro index 5ee2b52bf..04fe5b68f 100644 --- a/tb/arith/carrychain_inc/RunAllTests.pro +++ b/tb/arith/carrychain_inc/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/carrychain_inc/arith_carrychain_inc_Simple.vhdl b/tb/arith/carrychain_inc/arith_carrychain_inc_Simple.vhdl index 4efa5b821..4d1789434 100644 --- a/tb/arith/carrychain_inc/arith_carrychain_inc_Simple.vhdl +++ b/tb/arith/carrychain_inc/arith_carrychain_inc_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/carrychain_inc/arith_carrychain_inc_TestController.vhdl b/tb/arith/carrychain_inc/arith_carrychain_inc_TestController.vhdl index d8fe683ea..9d54ca4e8 100644 --- a/tb/arith/carrychain_inc/arith_carrychain_inc_TestController.vhdl +++ b/tb/arith/carrychain_inc/arith_carrychain_inc_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/carrychain_inc/arith_carrychain_inc_TestHarness.vhdl b/tb/arith/carrychain_inc/arith_carrychain_inc_TestHarness.vhdl index 2b63e064f..b21688609 100644 --- a/tb/arith/carrychain_inc/arith_carrychain_inc_TestHarness.vhdl +++ b/tb/arith/carrychain_inc/arith_carrychain_inc_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/cca/RunAllTests.pro b/tb/arith/cca/RunAllTests.pro index affe130c6..2b598476c 100644 --- a/tb/arith/cca/RunAllTests.pro +++ b/tb/arith/cca/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/cca/arith_cca_Simple.vhdl b/tb/arith/cca/arith_cca_Simple.vhdl index 64c0d2e16..fe332f227 100644 --- a/tb/arith/cca/arith_cca_Simple.vhdl +++ b/tb/arith/cca/arith_cca_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/cca/arith_cca_TestController.vhdl b/tb/arith/cca/arith_cca_TestController.vhdl index 0b4306796..701df5b53 100644 --- a/tb/arith/cca/arith_cca_TestController.vhdl +++ b/tb/arith/cca/arith_cca_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/cca/arith_cca_TestHarness.vhdl b/tb/arith/cca/arith_cca_TestHarness.vhdl index abf73ec13..29858c9f2 100644 --- a/tb/arith/cca/arith_cca_TestHarness.vhdl +++ b/tb/arith/cca/arith_cca_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/convert_bin2bcd/RunAllTests.pro b/tb/arith/convert_bin2bcd/RunAllTests.pro index af83c6403..405c0b8eb 100644 --- a/tb/arith/convert_bin2bcd/RunAllTests.pro +++ b/tb/arith/convert_bin2bcd/RunAllTests.pro @@ -3,7 +3,7 @@ # Gustavo Martin # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/convert_bin2bcd/arith_convert_bin2bcd_Simple.vhdl b/tb/arith/convert_bin2bcd/arith_convert_bin2bcd_Simple.vhdl index 1833d865a..04cb0ed94 100644 --- a/tb/arith/convert_bin2bcd/arith_convert_bin2bcd_Simple.vhdl +++ b/tb/arith/convert_bin2bcd/arith_convert_bin2bcd_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/arith/convert_bin2bcd/arith_convert_bin2bcd_TestController.vhdl b/tb/arith/convert_bin2bcd/arith_convert_bin2bcd_TestController.vhdl index 310d9dfc3..29b00f8c3 100644 --- a/tb/arith/convert_bin2bcd/arith_convert_bin2bcd_TestController.vhdl +++ b/tb/arith/convert_bin2bcd/arith_convert_bin2bcd_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/arith/convert_bin2bcd/arith_convert_bin2bcd_TestHarness.vhdl b/tb/arith/convert_bin2bcd/arith_convert_bin2bcd_TestHarness.vhdl index d6ad57d08..883ee3924 100644 --- a/tb/arith/convert_bin2bcd/arith_convert_bin2bcd_TestHarness.vhdl +++ b/tb/arith/convert_bin2bcd/arith_convert_bin2bcd_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/arith/counter_bcd/RunAllTests.pro b/tb/arith/counter_bcd/RunAllTests.pro index acad4d983..de881d3d5 100644 --- a/tb/arith/counter_bcd/RunAllTests.pro +++ b/tb/arith/counter_bcd/RunAllTests.pro @@ -3,7 +3,7 @@ # Gustavo Martin # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_bcd/arith_counter_bcd_Simple.vhdl b/tb/arith/counter_bcd/arith_counter_bcd_Simple.vhdl index 42eb43cc9..91cfe01a2 100644 --- a/tb/arith/counter_bcd/arith_counter_bcd_Simple.vhdl +++ b/tb/arith/counter_bcd/arith_counter_bcd_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Thomas B. Preusser @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_bcd/arith_counter_bcd_TestController.vhdl b/tb/arith/counter_bcd/arith_counter_bcd_TestController.vhdl index d5c5c8c87..184f57ec8 100644 --- a/tb/arith/counter_bcd/arith_counter_bcd_TestController.vhdl +++ b/tb/arith/counter_bcd/arith_counter_bcd_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Thomas B. Preusser @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_bcd/arith_counter_bcd_TestHarness.vhdl b/tb/arith/counter_bcd/arith_counter_bcd_TestHarness.vhdl index 56df882e5..254b0f0a7 100644 --- a/tb/arith/counter_bcd/arith_counter_bcd_TestHarness.vhdl +++ b/tb/arith/counter_bcd/arith_counter_bcd_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Thomas B. Preusser @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_free/RunAllTests.pro b/tb/arith/counter_free/RunAllTests.pro index fb83a4696..a2e5300d4 100644 --- a/tb/arith/counter_free/RunAllTests.pro +++ b/tb/arith/counter_free/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_free/arith_counter_free_Simple.vhdl b/tb/arith/counter_free/arith_counter_free_Simple.vhdl index 84f258d47..c97a35632 100644 --- a/tb/arith/counter_free/arith_counter_free_Simple.vhdl +++ b/tb/arith/counter_free/arith_counter_free_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_free/arith_counter_free_TestController.vhdl b/tb/arith/counter_free/arith_counter_free_TestController.vhdl index 7383531e6..7f9c4291b 100644 --- a/tb/arith/counter_free/arith_counter_free_TestController.vhdl +++ b/tb/arith/counter_free/arith_counter_free_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_free/arith_counter_free_TestHarness.vhdl b/tb/arith/counter_free/arith_counter_free_TestHarness.vhdl index 58f303f89..318532d21 100644 --- a/tb/arith/counter_free/arith_counter_free_TestHarness.vhdl +++ b/tb/arith/counter_free/arith_counter_free_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_gray/RunAllTests.pro b/tb/arith/counter_gray/RunAllTests.pro index 4a971408e..348d07a5b 100644 --- a/tb/arith/counter_gray/RunAllTests.pro +++ b/tb/arith/counter_gray/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_gray/arith_counter_gray_Simple.vhdl b/tb/arith/counter_gray/arith_counter_gray_Simple.vhdl index d1f922fad..3cad0d3c9 100644 --- a/tb/arith/counter_gray/arith_counter_gray_Simple.vhdl +++ b/tb/arith/counter_gray/arith_counter_gray_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_gray/arith_counter_gray_TestController.vhdl b/tb/arith/counter_gray/arith_counter_gray_TestController.vhdl index 75780160e..599199d1f 100644 --- a/tb/arith/counter_gray/arith_counter_gray_TestController.vhdl +++ b/tb/arith/counter_gray/arith_counter_gray_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_gray/arith_counter_gray_TestHarness.vhdl b/tb/arith/counter_gray/arith_counter_gray_TestHarness.vhdl index 2d4951323..6cfd22a96 100644 --- a/tb/arith/counter_gray/arith_counter_gray_TestHarness.vhdl +++ b/tb/arith/counter_gray/arith_counter_gray_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_ring/RunAllTests.pro b/tb/arith/counter_ring/RunAllTests.pro index 3bee535ad..78ca9e2d9 100644 --- a/tb/arith/counter_ring/RunAllTests.pro +++ b/tb/arith/counter_ring/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_ring/arith_counter_ring_Simple.vhdl b/tb/arith/counter_ring/arith_counter_ring_Simple.vhdl index acef3348d..667b0715d 100644 --- a/tb/arith/counter_ring/arith_counter_ring_Simple.vhdl +++ b/tb/arith/counter_ring/arith_counter_ring_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_ring/arith_counter_ring_TestController.vhdl b/tb/arith/counter_ring/arith_counter_ring_TestController.vhdl index 65f656ae4..7a854a043 100644 --- a/tb/arith/counter_ring/arith_counter_ring_TestController.vhdl +++ b/tb/arith/counter_ring/arith_counter_ring_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/counter_ring/arith_counter_ring_TestHarness.vhdl b/tb/arith/counter_ring/arith_counter_ring_TestHarness.vhdl index 9f7e9acf6..0b0a130b6 100644 --- a/tb/arith/counter_ring/arith_counter_ring_TestHarness.vhdl +++ b/tb/arith/counter_ring/arith_counter_ring_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/div/RunAllTests.pro b/tb/arith/div/RunAllTests.pro index 3b50f3a1b..8bcb90b5f 100644 --- a/tb/arith/div/RunAllTests.pro +++ b/tb/arith/div/RunAllTests.pro @@ -3,7 +3,7 @@ # Gustavo Martin # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/div/arith_div_Simple.vhdl b/tb/arith/div/arith_div_Simple.vhdl index 9badc6fe7..bf17a1471 100644 --- a/tb/arith/div/arith_div_Simple.vhdl +++ b/tb/arith/div/arith_div_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/arith/div/arith_div_TestController.vhdl b/tb/arith/div/arith_div_TestController.vhdl index 55328032e..209a92014 100644 --- a/tb/arith/div/arith_div_TestController.vhdl +++ b/tb/arith/div/arith_div_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/arith/div/arith_div_TestHarness.vhdl b/tb/arith/div/arith_div_TestHarness.vhdl index 7398ba99d..54c05da62 100644 --- a/tb/arith/div/arith_div_TestHarness.vhdl +++ b/tb/arith/div/arith_div_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/arith/firstone/RunAllTests.pro b/tb/arith/firstone/RunAllTests.pro index e9e25a69a..5d17252b8 100644 --- a/tb/arith/firstone/RunAllTests.pro +++ b/tb/arith/firstone/RunAllTests.pro @@ -3,7 +3,7 @@ # Gustavo Martin # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/firstone/arith_firstone_Simple.vhdl b/tb/arith/firstone/arith_firstone_Simple.vhdl index 0a4ab4be3..46de6e78c 100644 --- a/tb/arith/firstone/arith_firstone_Simple.vhdl +++ b/tb/arith/firstone/arith_firstone_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/arith/firstone/arith_firstone_TestController.vhdl b/tb/arith/firstone/arith_firstone_TestController.vhdl index 19cf876a8..ea648576f 100644 --- a/tb/arith/firstone/arith_firstone_TestController.vhdl +++ b/tb/arith/firstone/arith_firstone_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/firstone/arith_firstone_TestHarness.vhdl b/tb/arith/firstone/arith_firstone_TestHarness.vhdl index 67c355357..8b1806a8e 100644 --- a/tb/arith/firstone/arith_firstone_TestHarness.vhdl +++ b/tb/arith/firstone/arith_firstone_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/prefix_and/RunAllTests.pro b/tb/arith/prefix_and/RunAllTests.pro index ccb2d5466..58a472a57 100644 --- a/tb/arith/prefix_and/RunAllTests.pro +++ b/tb/arith/prefix_and/RunAllTests.pro @@ -4,7 +4,7 @@ # Patrick Lehmann # Gustavo Martin # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/prefix_and/arith_prefix_and_Exhaustive.vhdl b/tb/arith/prefix_and/arith_prefix_and_Exhaustive.vhdl index 80eb3fbaa..cceff640c 100644 --- a/tb/arith/prefix_and/arith_prefix_and_Exhaustive.vhdl +++ b/tb/arith/prefix_and/arith_prefix_and_Exhaustive.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Patrick Lehmann @@ -15,7 +12,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/prefix_and/arith_prefix_and_Simple.vhdl b/tb/arith/prefix_and/arith_prefix_and_Simple.vhdl index eada5be63..622d2e420 100644 --- a/tb/arith/prefix_and/arith_prefix_and_Simple.vhdl +++ b/tb/arith/prefix_and/arith_prefix_and_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Patrick Lehmann @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/prefix_and/arith_prefix_and_TestController.vhdl b/tb/arith/prefix_and/arith_prefix_and_TestController.vhdl index 84132d05a..5004574e7 100644 --- a/tb/arith/prefix_and/arith_prefix_and_TestController.vhdl +++ b/tb/arith/prefix_and/arith_prefix_and_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Patrick Lehmann @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/prefix_and/arith_prefix_and_TestHarness.vhdl b/tb/arith/prefix_and/arith_prefix_and_TestHarness.vhdl index 1103f050b..389971f2d 100644 --- a/tb/arith/prefix_and/arith_prefix_and_TestHarness.vhdl +++ b/tb/arith/prefix_and/arith_prefix_and_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Patrick Lehmann @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/prefix_or/RunAllTests.pro b/tb/arith/prefix_or/RunAllTests.pro index c9e4e76e0..7047e6f89 100644 --- a/tb/arith/prefix_or/RunAllTests.pro +++ b/tb/arith/prefix_or/RunAllTests.pro @@ -4,7 +4,7 @@ # Patrick Lehmann # Gustavo Martin # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/prefix_or/arith_prefix_or_Exhaustive.vhdl b/tb/arith/prefix_or/arith_prefix_or_Exhaustive.vhdl index f17f69b96..aa76f09d8 100644 --- a/tb/arith/prefix_or/arith_prefix_or_Exhaustive.vhdl +++ b/tb/arith/prefix_or/arith_prefix_or_Exhaustive.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/prefix_or/arith_prefix_or_Simple.vhdl b/tb/arith/prefix_or/arith_prefix_or_Simple.vhdl index 5356c024a..a23d6b6d6 100644 --- a/tb/arith/prefix_or/arith_prefix_or_Simple.vhdl +++ b/tb/arith/prefix_or/arith_prefix_or_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/prefix_or/arith_prefix_or_TestController.vhdl b/tb/arith/prefix_or/arith_prefix_or_TestController.vhdl index 45c7f2a7e..c945ffe27 100644 --- a/tb/arith/prefix_or/arith_prefix_or_TestController.vhdl +++ b/tb/arith/prefix_or/arith_prefix_or_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/prefix_or/arith_prefix_or_TestHarness.vhdl b/tb/arith/prefix_or/arith_prefix_or_TestHarness.vhdl index 45730e7f6..27d0bfeed 100644 --- a/tb/arith/prefix_or/arith_prefix_or_TestHarness.vhdl +++ b/tb/arith/prefix_or/arith_prefix_or_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/prng/arith_prng_Simple.vhdl b/tb/arith/prng/arith_prng_Simple.vhdl index 98738ae69..4c2f93c95 100644 --- a/tb/arith/prng/arith_prng_Simple.vhdl +++ b/tb/arith/prng/arith_prng_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Jonas Schreiner -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/prng/arith_prng_TestController.vhdl b/tb/arith/prng/arith_prng_TestController.vhdl index d27fd2851..2e122eac1 100644 --- a/tb/arith/prng/arith_prng_TestController.vhdl +++ b/tb/arith/prng/arith_prng_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Jonas Schreiner -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/prng/arith_prng_TestHarness.vhdl b/tb/arith/prng/arith_prng_TestHarness.vhdl index c17e79efe..48d346210 100644 --- a/tb/arith/prng/arith_prng_TestHarness.vhdl +++ b/tb/arith/prng/arith_prng_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Jonas Schreiner -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/same/RunAllTests.pro b/tb/arith/same/RunAllTests.pro index 2e07f2c21..9e5e1eeb0 100644 --- a/tb/arith/same/RunAllTests.pro +++ b/tb/arith/same/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/same/arith_same_Simple.vhdl b/tb/arith/same/arith_same_Simple.vhdl index decb419bd..b61afd5aa 100644 --- a/tb/arith/same/arith_same_Simple.vhdl +++ b/tb/arith/same/arith_same_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/same/arith_same_TestController.vhdl b/tb/arith/same/arith_same_TestController.vhdl index 985b1eb64..7aaaf0fd8 100644 --- a/tb/arith/same/arith_same_TestController.vhdl +++ b/tb/arith/same/arith_same_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/same/arith_same_TestHarness.vhdl b/tb/arith/same/arith_same_TestHarness.vhdl index 391e09af4..e0381ab0d 100644 --- a/tb/arith/same/arith_same_TestHarness.vhdl +++ b/tb/arith/same/arith_same_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/scaler/RunAllTests.pro b/tb/arith/scaler/RunAllTests.pro index 143b2850a..b6ac5d573 100644 --- a/tb/arith/scaler/RunAllTests.pro +++ b/tb/arith/scaler/RunAllTests.pro @@ -3,7 +3,7 @@ # Gustavo Martin # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/scaler/arith_scaler_Simple.vhdl b/tb/arith/scaler/arith_scaler_Simple.vhdl index 14dbbaa04..2b7a4d9e7 100644 --- a/tb/arith/scaler/arith_scaler_Simple.vhdl +++ b/tb/arith/scaler/arith_scaler_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universität Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/arith/scaler/arith_scaler_TestController.vhdl b/tb/arith/scaler/arith_scaler_TestController.vhdl index 267326a85..dd5e0872b 100644 --- a/tb/arith/scaler/arith_scaler_TestController.vhdl +++ b/tb/arith/scaler/arith_scaler_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/scaler/arith_scaler_TestHarness.vhdl b/tb/arith/scaler/arith_scaler_TestHarness.vhdl index 335b5ae2a..b99a343c1 100644 --- a/tb/arith/scaler/arith_scaler_TestHarness.vhdl +++ b/tb/arith/scaler/arith_scaler_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universität Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/arith/shifter_barrel/RunAllTests.pro b/tb/arith/shifter_barrel/RunAllTests.pro index 0f3bf3993..b47cfb1b3 100644 --- a/tb/arith/shifter_barrel/RunAllTests.pro +++ b/tb/arith/shifter_barrel/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/shifter_barrel/arith_shifter_barrel_Simple.vhdl b/tb/arith/shifter_barrel/arith_shifter_barrel_Simple.vhdl index ef10830bb..76e4ad16e 100644 --- a/tb/arith/shifter_barrel/arith_shifter_barrel_Simple.vhdl +++ b/tb/arith/shifter_barrel/arith_shifter_barrel_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/shifter_barrel/arith_shifter_barrel_TestController.vhdl b/tb/arith/shifter_barrel/arith_shifter_barrel_TestController.vhdl index 042410493..cc0e72f80 100644 --- a/tb/arith/shifter_barrel/arith_shifter_barrel_TestController.vhdl +++ b/tb/arith/shifter_barrel/arith_shifter_barrel_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/shifter_barrel/arith_shifter_barrel_TestHarness.vhdl b/tb/arith/shifter_barrel/arith_shifter_barrel_TestHarness.vhdl index 50507e3b5..0bfbb87b2 100644 --- a/tb/arith/shifter_barrel/arith_shifter_barrel_TestHarness.vhdl +++ b/tb/arith/shifter_barrel/arith_shifter_barrel_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/sqrt/RunAllTests.pro b/tb/arith/sqrt/RunAllTests.pro index 002e64884..c93c75b0d 100644 --- a/tb/arith/sqrt/RunAllTests.pro +++ b/tb/arith/sqrt/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/sqrt/arith_sqrt_Simple.vhdl b/tb/arith/sqrt/arith_sqrt_Simple.vhdl index 56d62487b..770c49599 100644 --- a/tb/arith/sqrt/arith_sqrt_Simple.vhdl +++ b/tb/arith/sqrt/arith_sqrt_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/sqrt/arith_sqrt_TestController.vhdl b/tb/arith/sqrt/arith_sqrt_TestController.vhdl index cca960cc9..e6ce4d86d 100644 --- a/tb/arith/sqrt/arith_sqrt_TestController.vhdl +++ b/tb/arith/sqrt/arith_sqrt_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/sqrt/arith_sqrt_TestHarness.vhdl b/tb/arith/sqrt/arith_sqrt_TestHarness.vhdl index 8f5e034e2..7c945a465 100644 --- a/tb/arith/sqrt/arith_sqrt_TestHarness.vhdl +++ b/tb/arith/sqrt/arith_sqrt_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/trng/RunAllTests.pro b/tb/arith/trng/RunAllTests.pro index 691d2466c..ff915dcf2 100644 --- a/tb/arith/trng/RunAllTests.pro +++ b/tb/arith/trng/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/arith/trng/arith_trng_Simple.vhdl b/tb/arith/trng/arith_trng_Simple.vhdl index 28e0ec292..fcefa03af 100644 --- a/tb/arith/trng/arith_trng_Simple.vhdl +++ b/tb/arith/trng/arith_trng_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/trng/arith_trng_TestController.vhdl b/tb/arith/trng/arith_trng_TestController.vhdl index 7a228bb81..a6752ee16 100644 --- a/tb/arith/trng/arith_trng_TestController.vhdl +++ b/tb/arith/trng/arith_trng_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/arith/trng/arith_trng_TestHarness.vhdl b/tb/arith/trng/arith_trng_TestHarness.vhdl index 6020a8e4f..5085d77ad 100644 --- a/tb/arith/trng/arith_trng_TestHarness.vhdl +++ b/tb/arith/trng/arith_trng_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/bus/RunAllTests.pro b/tb/bus/RunAllTests.pro index 8577a86a1..9a22bc232 100644 --- a/tb/bus/RunAllTests.pro +++ b/tb/bus/RunAllTests.pro @@ -5,7 +5,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -26,4 +26,4 @@ library tb_bus include ./axi4/RunAllTests.pro -# include ./stream/RunAllTests.pro +disabled ./stream/RunAllTests.pro diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/RunAllTests.pro b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/RunAllTests.pro new file mode 100644 index 000000000..f38b4003a --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/RunAllTests.pro @@ -0,0 +1,32 @@ +# ============================================================================= +# Authors: +# Adrian Weiland (PLC2 Design GmbH) +# +# License: +# ============================================================================= +# Copyright 2025-2026 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +TestSuite PoC.bus.axi4.axi4lite.HighResolutionClock + +library tb_axi4lite_HighResolutionClock + +analyze axi4lite_HighResolutionClock_tb_pkg.vhdl +analyze axi4lite_HighResolutionClock_th.vhdl +analyze axi4lite_HighResolutionClock_tc.vhdl + +# Test Cases +RunTest axi4lite_HighResolutionClock_load_times.vhdl +RunTest axi4lite_HighResolutionClock_correction.vhdl diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_correction.tcl b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_correction.tcl new file mode 100644 index 000000000..cf52f7f2a --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_correction.tcl @@ -0,0 +1,5 @@ +log /axi4lite_HighResolutionClock_th/* +log /axi4lite_HighResolutionClock_th/dut/* +log /axi4lite_HighResolutionClock_th/dut/reg/Reg_ReadPort +log /axi4lite_HighResolutionClock_th/dut/reg/Reg_WritePort +log /axi4lite_HighResolutionClock_th/dut/ClockRegister/* diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_correction.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_correction.vhdl new file mode 100644 index 000000000..6f65ef6b7 --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_correction.vhdl @@ -0,0 +1,156 @@ +-- ============================================================================= +-- Authors: +-- Adrian Weiland +-- +-- Testcase: Test functionality of the correction counter. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +architecture correction of axi4lite_HighResolutionClock_tc is + + signal TestDone : integer_barrier := 1; + +begin + -- Testbench control process + ControlProc : process + constant TIMEOUT : time := 1 ms; + begin + -- Initialization of test + SetTestName("axi4lite_HighResolutionClock_correction"); + SetLogEnable(PASSED, TRUE); --Enable PASSED Logs + SetLogEnable(INFO, TRUE); --Enable INFO Logs + + -- Wait for testbench Initialization + wait for 0 ns; + wait for 0 ns; + TranscriptOpen; + SetTranscriptMirror(TRUE); + + -- wait for design reset + wait until Reset = '0'; + ClearAlerts; + + WaitForBarrier(TestDone, TIMEOUT); + EndOfTestReports(ReportAll => TRUE, Timeout => now >= TIMEOUT); + std.env.finish; + wait; + end process ControlProc; + + -- Generate transaction for AXI manager + ManagerProc : process + procedure LoadNanoseconds ( + signal manager : inout AddressBusRecType; + constant Nanoseconds_to_load : natural + ) is + variable ns_value_slv : std_logic_vector(63 downto 0) := to_slv(Nanoseconds_to_load, 64); + begin + log(""); + log("Writing Nanoseconds to register"); + Write(AXI_Manager, Reg_Nanoseconds_to_load_lower, ns_value_slv(31 downto 0)); + Write(AXI_Manager, Reg_Nanoseconds_to_load_upper, ns_value_slv(63 downto 32)); + end procedure; + + procedure CheckCorrection ( + signal manager : inout AddressBusRecType; + constant config : in std_logic_vector(1 downto 0); + constant correction_threshold : natural; + constant correction_time : time + ) is + variable ReadData : AXIDataType; + variable time_now_a : time; + variable time_now_b : time; + variable time_now_delta : time; + variable time_now_delta_val : natural; + variable time_ns_a_l : natural; + variable time_ns_b_l : natural; + variable time_ns_delta : natural; + variable delta_expected : natural; + begin + log(""); + log("Setting defined config"); + Write(AXI_Manager, Reg_Config_reg, config & to_slv(correction_threshold, 30)); + WaitForClock(AXI_Manager, 8); + ReadCheck(AXI_Manager, Reg_Config_reg, config & to_slv(correction_threshold, 30)); + + Read(AXI_Manager, Reg_Nanoseconds_lower, ReadData); + time_now_a := now; + time_ns_a_l := to_integer(unsigned(ReadData)); + + wait for correction_time; + + Read(AXI_Manager, Reg_Nanoseconds_lower, ReadData); + time_now_b := now; + time_now_delta := time_now_b - time_now_a; + time_now_delta_val := time_now_delta / 1000 ps; + + case config is + when "11" => -- increment + if correction_threshold = 0 then + delta_expected := time_now_delta_val; + else + delta_expected := time_now_delta_val + time_now_delta_val / (INCREMENT_FULL * correction_threshold); + end if; + when "10" => -- decrement + if correction_threshold = 0 then + delta_expected := time_now_delta_val; + else + delta_expected := time_now_delta_val - time_now_delta_val / (INCREMENT_FULL * correction_threshold); + end if; + when others => -- no correction + delta_expected := time_now_delta_val; + end case; + + time_ns_b_l := to_integer(unsigned(ReadData)); + time_ns_delta := time_ns_b_l - time_ns_a_l; + AffirmIf ( -- check if delta is in range + time_ns_delta = delta_expected or (time_ns_delta = delta_expected + 1) or (time_ns_delta = delta_expected - 1), + "Delta: " & to_string(time_ns_delta) & " (" & to_string(delta_expected - 1) & " to " & to_string(delta_expected + 1) & ")", + "Delta: /= " & to_string(delta_expected - 1) & " to " & to_string(delta_expected + 1) & " (expected)" + ); + end procedure; + + begin + wait until Reset = '0'; + WaitForClock(AXI_Manager, 2); + + LoadNanoseconds(AXI_Manager, 1000); + CheckCorrection(AXI_Manager, "11", 10, 600 ns); + CheckCorrection(AXI_Manager, "10", 10, 600 ns); + CheckCorrection(AXI_Manager, "01", 10, 600 ns); -- enable not set + CheckCorrection(AXI_Manager, "11", 53, 600 ns); + LoadNanoseconds(AXI_Manager, 1764); + CheckCorrection(AXI_Manager, "11", 1000, 600 ns); + CheckCorrection(AXI_Manager, "11", 2, 477 ns); + CheckCorrection(AXI_Manager, "10", 2, 352 ns); + CheckCorrection(AXI_Manager, "10", 1, 352 ns); + CheckCorrection(AXI_Manager, "11", 0, 444 ns); + + WaitForClock(AXI_Manager); + WaitForBarrier(TestDone); + wait; + end process ManagerProc; + +end architecture; + +configuration axi4lite_HighResolutionClock_correction of axi4lite_HighResolutionClock_th is + for TestHarness + for TestCtrl : axi4lite_HighResolutionClock_tc + use entity work.axi4lite_HighResolutionClock_tc(correction); + end for; + end for; +end configuration; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_load_times.tcl b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_load_times.tcl new file mode 100644 index 000000000..f11d7c185 --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_load_times.tcl @@ -0,0 +1,5 @@ +log /axi4lite_HighResolutionClock_th/* +log /axi4lite_HighResolutionClock_th/dut/* +log /axi4lite_HighResolutionClock_th/dut/reg/Reg_ReadPort +log /axi4lite_HighResolutionClock_th/dut/reg/Reg_WritePort +log /axi4lite_HighResolutionClock_th/dut/ClockRegister/* \ No newline at end of file diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_load_times.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_load_times.vhdl new file mode 100644 index 000000000..80ae29928 --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_load_times.vhdl @@ -0,0 +1,170 @@ +-- ============================================================================= +-- Authors: +-- Adrian Weiland +-- +-- Testcase: Load times into register. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +architecture load_times of axi4lite_HighResolutionClock_tc is + + signal TestDone : integer_barrier := 1; + +begin + -- Testbench control process + ControlProc : process + constant TIMEOUT : time := 1 ms; + begin + -- Initialization of test + SetTestName("axi4lite_HighResolutionClock_load_times"); + -- SetLogEnable(PASSED, TRUE); --Enable PASSED Logs + -- SetLogEnable(INFO, TRUE); --Enable INFO Logs + + -- Wait for testbench Initialization + wait for 0 ns; + wait for 0 ns; + TranscriptOpen; + SetTranscriptMirror(TRUE); + + -- wait for design reset + wait until Reset = '0'; + ClearAlerts; + + WaitForBarrier(TestDone, TIMEOUT); + EndOfTestReports(ReportAll => TRUE, Timeout => now >= TIMEOUT); + std.env.finish; + wait; + end process; + + -- Generate transaction for AXI manager + ManagerProc : process + variable ReadData : AXIDataType; + + variable comp_time : time := 200 ns; + variable comp_time_val : natural := 200; + + variable Nanoseconds_to_load : std_logic_vector(63 downto 0) := to_slv(1000, 64); + variable Nanosecond_value : natural; + variable Nanoseconds_updated_min : natural := to_integer(unsigned(Nanoseconds_to_load)) + comp_time_val; + variable Nanoseconds_updated_max : natural := to_integer(unsigned(Nanoseconds_to_load)) + comp_time_val + 100; + -- each Write need 8 CC until the value is available in the register. Therefore the updated value will be: + -- Nanoseconds_updated_min + 4 * 8 but it can differ depending on other operations in the network (in a real scenario with more op.) + variable Datetime_to_load : T_CLOCK_DATETIME := ( + secondsResolution => to_unsigned(0, 32), + seconds => to_unsigned(42, 6), + minutes => to_unsigned(7, 6), + hours => to_unsigned(16, 5), + day => to_unsigned(13, 5), + month => to_unsigned(1, 4), + year => to_unsigned(2025, 13) + ); + variable Datetime_to_load_slv : std_logic_vector(63 downto 0) := datetime_to_slv(Datetime_to_load); + + procedure LoadNanoseconds ( + signal manager : inout AddressBusRecType; + constant Nanoseconds_to_load : natural; + constant waitTime : time + ) is + variable ReadData : AXIDataType; + variable ns_value_slv : std_logic_vector(63 downto 0) := to_slv(Nanoseconds_to_load, 64); + variable time_now_a : time; + variable time_now_b : time; + variable time_now_delta : time; + variable time_total : natural; + variable time_ns_a_l : natural; + variable time_ns_b_l : natural; + variable time_ns_delta : natural; + variable delta_expected : natural; + begin + log(""); + log("Writing Nanoseconds to register"); + Write(AXI_Manager, Reg_Nanoseconds_to_load_lower, ns_value_slv(31 downto 0)); + time_now_a := now; + time_ns_a_l := to_integer(unsigned(ReadData)); + Write(AXI_Manager, Reg_Nanoseconds_to_load_upper, ns_value_slv(63 downto 32)); + + wait for waitTime; + + Read(AXI_Manager, Reg_Nanoseconds_lower, ReadData); + time_now_b := now; + time_ns_b_l := to_integer(unsigned(ReadData)); + time_now_delta := time_now_b - time_now_a; + time_total := Nanoseconds_to_load + time_now_delta / 1000 ps; + + time_ns_b_l := to_integer(unsigned(ReadData)); + time_ns_delta := time_ns_b_l - time_ns_a_l; + AffirmIfEqual(time_ns_delta, time_ns_b_l); + ReadCheck(AXI_Manager, Reg_Nanoseconds_upper, std_logic_vector(ns_value_slv(63 downto 32))); -- value should not have changed + end procedure; + + procedure LoadDatetime ( + signal manager : inout AddressBusRecType; + constant s : natural; -- second + constant m : natural; -- minute + constant h : natural; -- hour + constant d : natural; -- day + constant mo : natural; -- month + constant y : natural; -- year + constant waitTime : time + ) is + variable ReadData : AXIDataType; + variable Datetime_to_load : T_CLOCK_DATETIME := ( + secondsResolution => to_unsigned(0, 32), -- gets written to different register + seconds => to_unsigned(s, 6), + minutes => to_unsigned(m, 6), + hours => to_unsigned(h, 5), + day => to_unsigned(d, 5), + month => to_unsigned(mo, 4), + year => to_unsigned(y, 13) + ); + variable Datetime_to_load_slv : std_logic_vector(63 downto 0) := datetime_to_slv(Datetime_to_load); + variable time_now_a : time; + begin + log(""); + log("Writing Datetime to register"); + Write(AXI_Manager, Reg_Datetime_to_load_HMS, Datetime_to_load_slv(31 downto 0)); + Write(AXI_Manager, Reg_Datetime_to_load_Ymd, Datetime_to_load_slv(63 downto 32)); + + wait for waitTime; + + ReadCheck(AXI_Manager, Reg_Time_HMS, std_logic_vector(Datetime_to_load_slv(31 downto 0))); -- value should not have changed + ReadCheck(AXI_Manager, Reg_Date_Ymd, std_logic_vector(Datetime_to_load_slv(63 downto 32))); -- value should not have changed + + end procedure; + begin + wait until Reset = '0'; + WaitForClock(AXI_Manager, 2); + + log("Writing load values to register"); + LoadNanoseconds(AXI_Manager, 1000, 400 ns); + LoadDatetime(AXI_Manager, 42, 7, 16, 13, 1, 2025, 500 ns); + + WaitForClock(AXI_Manager); + WaitForBarrier(TestDone); + wait; + end process ManagerProc; + +end architecture; + +configuration axi4lite_HighResolutionClock_load_times of axi4lite_HighResolutionClock_th is + for TestHarness + for TestCtrl : axi4lite_HighResolutionClock_tc + use entity work.axi4lite_HighResolutionClock_tc(load_times); + end for; + end for; +end configuration; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_tb_pkg.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_tb_pkg.vhdl new file mode 100644 index 000000000..e704b81b7 --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_tb_pkg.vhdl @@ -0,0 +1,58 @@ +-- ============================================================================= +-- Authors: +-- Adrian Weiland +-- +-- Package: Variables and types needed for testing. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.utils.all; +use PoC.physical.all; +use PoC.vectors.all; + + +package axi4lite_HighResolutionClock_tb_pkg is + constant AXI_ADDR_WIDTH : integer := 32; + constant AXI_DATA_WIDTH : integer := 32; + constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH / 8; + + subtype AXIAddressType is std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0); + subtype AXIDataType is std_logic_vector(AXI_DATA_WIDTH - 1 downto 0); + + -- Register addresses + constant Reg_reserved : AXIAddressType := 32x"00"; + constant Reg_Config_reg : AXIAddressType := 32x"04"; + constant Reg_Nanoseconds_lower : AXIAddressType := 32x"08"; + constant Reg_Nanoseconds_upper : AXIAddressType := 32x"0C"; + constant Reg_Time_HMS : AXIAddressType := 32x"10"; + constant Reg_Date_Ymd : AXIAddressType := 32x"14"; + constant Reg_Time_sec_res : AXIAddressType := 32x"18"; + constant Reg_Nanoseconds_to_load_lower : AXIAddressType := 32x"20"; + constant Reg_Nanoseconds_to_load_upper : AXIAddressType := 32x"24"; + constant Reg_Datetime_to_load_HMS : AXIAddressType := 32x"28"; + constant Reg_Datetime_to_load_Ymd : AXIAddressType := 32x"2C"; + +end package; + +package body axi4lite_HighResolutionClock_tb_pkg is +end package body; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_tc.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_tc.vhdl new file mode 100644 index 000000000..d95290f3a --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_tc.vhdl @@ -0,0 +1,56 @@ +-- ============================================================================= +-- Authors: +-- Adrian Weiland +-- +-- Entity: Test controller. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.AXI4Lite_OSVVM.all; +use PoC.utils.all; +use PoC.physical.all; +use PoC.vectors.all; +use PoC.axi4lite.all; +use PoC.uart.all; +use PoC.math.all; +use PoC.clock.all; + +library OSVVM; +context OSVVM.OsvvmContext; + +library osvvm_Axi4; +context osvvm_Axi4.Axi4LiteContext; + +use work.axi4Lite_HighResolutionClock_tb_pkg.all; + + +entity axi4lite_HighResolutionClock_tc is + generic ( + CLOCK_FREQ : FREQ; + INCREMENT_FULL : natural + ); + port ( + Reset : in std_logic; + AXI_Manager : inout AddressBusRecType + ); +end entity; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_th.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_th.vhdl new file mode 100644 index 000000000..648ac690b --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_HighResolutionClock/axi4lite_HighResolutionClock_th.vhdl @@ -0,0 +1,178 @@ +-- ============================================================================= +-- Authors: +-- Adrian Weiland +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.AXI4Lite_OSVVM.all; +use PoC.utils.all; +use PoC.physical.all; +use PoC.vectors.all; +use PoC.axi4lite.all; +use PoC.uart.all; +use PoC.math.all; +use PoC.clock.all; + +library OSVVM; +context OSVVM.OsvvmContext; + +library OSVVM_Axi4; +context OSVVM_Axi4.Axi4LiteContext; + +use work.axi4lite_HighResolutionClock_tb_pkg.all; + + +entity axi4lite_HighResolutionClock_th is +end entity; + + +architecture TestHarness of axi4lite_HighResolutionClock_th is + -- DUT + constant CLOCK_FREQ : FREQ := 200 MHz; + constant PERIOD : T_TIME := to_time(CLOCK_FREQ); + constant PERIOD_FRACT : t_fractional := fract(PERIOD / 1.0e-9, 1000000, 1.0e-12); + constant INCREMENT_FULL : natural := PERIOD_FRACT.whole; + + constant SECOND_RESOLUTION : T_SECOND_RESOLUTION := MICROSECONDS; + + signal Nanoseconds : unsigned(63 downto 0) := (others => '0'); + signal Datetime : T_CLOCK_Datetime := (others => (others => '0')); + + signal Clock : std_logic := '1'; + signal AXI_clock : std_logic := '1'; + signal Reset : std_logic := '1'; + signal AXI_reset : std_logic := '1'; + + signal AXI_m2s : T_AXI4Lite_BUS_M2S( + AWAddr(AXI_ADDR_WIDTH - 1 downto 0), + WData(AXI_DATA_WIDTH - 1 downto 0), + WStrb(AXI_STRB_WIDTH-1 downto 0), + ARAddr(AXI_ADDR_WIDTH - 1 downto 0) + ); + signal AXI_s2m : T_AXI4Lite_BUS_S2M( + RData(AXI_DATA_WIDTH - 1 downto 0) + ); + + -- Clock, reset generation + constant tperiod_Clk : time := to_time(CLOCK_FREQ); + constant tpd : time := 0 ns; + + -- Transaction interfaces + signal AXI_Manager : AddressBusRecType( + Address (AXI_ADDR_WIDTH - 1 downto 0), + DataToModel (AXI_DATA_WIDTH - 1 downto 0), + DataFromModel(AXI_DATA_WIDTH - 1 downto 0) + ); + + -- AXI Manager physical Interface + signal AxiLiteBus : Axi4LiteRecType( + WriteAddress(Addr(AXI_ADDR_WIDTH - 1 downto 0)), + WriteData (Data(AXI_DATA_WIDTH - 1 downto 0), Strb(AXI_STRB_WIDTH - 1 downto 0)), + ReadAddress (Addr(AXI_ADDR_WIDTH - 1 downto 0)), + ReadData (Data(AXI_DATA_WIDTH - 1 downto 0)) + ); + + component axi4Lite_HighResolutionClock_tc + generic ( + CLOCK_FREQ : FREQ; + INCREMENT_FULL : natural + ); + port ( + Reset : in std_logic; + AXI_Manager : inout AddressBusRecType + ); + end component; + +begin + -- Create system clock + clk: Osvvm.ClockResetPkg.CreateClock( + Clk => Clock, + Period => tperiod_Clk + ); + + -- Create system reset + rst: Osvvm.ClockResetPkg.CreateReset ( + Reset => Reset, + ResetActive => '1', + Clk => Clock, + Period => 7 * tperiod_Clk, + tpd => tpd + ); + + -- AXI4Lite configuration manager + manager: entity OSVVM_AXI4.Axi4LiteManager + generic map ( + tperiod_Clk => tperiod_Clk, + DEFAULT_DELAY => tpd + ) + port map ( + Clk => Clock, + nReset => not Reset, + + -- Transaction interface from TestController + TransRec => AXI_Manager, + + -- AXI manager physical interface + AxiBus => AxiLiteBus + ); + + -- mapping between PoC and OSVVM AXI bus types + to_PoC_AXI4Lite_Bus_Master(AXI_m2s, AXI_s2m, AxiLiteBus); + + -- todo: check frequency + AXI_clock <= Clock; + AXI_reset <= Reset; + dut: entity PoC.axi4lite_HighResolutionClock + generic map ( + CLOCK_FREQUENCY => 200 MHz, + USE_CDC => True, + REGISTER_NANOSECONDS => 4, -- num pipelining stages + SECOND_RESOLUTION => SECOND_RESOLUTION + ) + port map ( + Clock => Clock, + Reset => Reset, + + AXI_clock => AXI_clock, + AXI_reset => AXI_reset, + + AXI_m2s => AXI_m2s, + AXI_s2m => AXI_s2m, + + Nanoseconds => Nanoseconds, + Datetime => Datetime + ); + + TestCtrl: component axi4lite_HighResolutionClock_tc + generic map ( + CLOCK_FREQ => CLOCK_FREQ, + INCREMENT_FULL => INCREMENT_FULL + ) + port map ( + Reset => Reset, + AXI_Manager => AXI_Manager + ); + +end architecture; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/AXI4Lite_Ocram_Adapter_TestController.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/AXI4Lite_Ocram_Adapter_TestController.vhdl new file mode 100644 index 000000000..bca622cb2 --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/AXI4Lite_Ocram_Adapter_TestController.vhdl @@ -0,0 +1,51 @@ +-- ============================================================================= +-- Authors: +-- Iqbal Asif (PLC2 Design GmbH) +-- Patrick Lehmann (PLC2 Design GmbH) +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library ieee ; + use ieee.std_logic_1164.all ; + use ieee.numeric_std.all ; + use ieee.numeric_std_unsigned.all ; + +library OSVVM ; + context OSVVM.OsvvmContext ; + +--library osvvm_Axi4; +-- context osvvm_Axi4.Axi4Context ; + +library osvvm_Axi4; + context osvvm_Axi4.Axi4LiteContext ; + +entity AXI4Lite_Ocram_Adapter_TestController is + port ( + -- Global Signal Interface + Clk : in std_logic ; + nReset : in std_logic ; + -- Transaction Interfaces + MasterRec : inout AddressBusRecType + ) ; + constant AXI_ADDR_WIDTH : integer := MasterRec.Address'length ; + constant AXI_DATA_WIDTH : integer := MasterRec.DataToModel'length ; + +-- Not currently used in the Axi4Lite model - future use for Axi4Lite Burst Emulation modes +-- alias WriteBurstFifo is <> ; +-- alias ReadBurstFifo is <> ; +end entity; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/AXI4Lite_Ocram_Adapter_TestHarness.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/AXI4Lite_Ocram_Adapter_TestHarness.vhdl new file mode 100644 index 000000000..735c46da8 --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/AXI4Lite_Ocram_Adapter_TestHarness.vhdl @@ -0,0 +1,204 @@ +-- ============================================================================= +-- Authors: +-- Iqbal Asif (PLC2 Design GmbH) +-- Patrick Lehmann (PLC2 Design GmbH) +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library PoC; +use PoC.utils.all; +use PoC.axi4.all; +use PoC.vectors.all; + +library osvvm; +context osvvm.OsvvmContext ; + +library OSVVM_AXI4; +--context OSVVM_AXI4.Axi4Context ; +context OSVVM_AXI4.Axi4LiteContext ; + +entity AXI4Lite_Ocram_Adapter_TestHarness is +end AXI4Lite_Ocram_Adapter_TestHarness; + +architecture sim of AXI4Lite_Ocram_Adapter_TestHarness is + + constant AXI_ADDR_WIDTH : integer := 32 ; + constant AXI_DATA_WIDTH : integer := 32 ; + constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH/8 ; + constant OCRAM_ADDRESS_BITS : positive := 8; + constant OCRAM_DATA_BITS : positive := 32; + constant PREFFERED_READ_ACCESS : boolean := TRUE; + + constant tperiod_Clk : time := 10 ns ; + constant tperiod_Clk_SPI : time := 100 ns ; + constant tpd : time := 2 ns ; + + signal Clk : std_logic := '1'; + signal Reset : std_logic := '1'; + + signal write_en : std_logic; + signal address : unsigned(OCRAM_ADDRESS_BITS-1 downto 0); + signal data_in : std_logic_vector(OCRAM_DATA_BITS-1 downto 0) := (others => '0'); + signal data_out : std_logic_vector(OCRAM_DATA_BITS-1 downto 0); + + signal PortB_address : unsigned(OCRAM_ADDRESS_BITS-1 downto 0); + signal PortB_data : std_logic_vector(OCRAM_DATA_BITS-1 downto 0) := (others => '0'); + + -- Testbench Transaction Interface + subtype MasterTransactionRecType is AddressBusTransactionRecType( + Address((AXI_ADDR_WIDTH)-1 downto 0), + DataToModel((AXI_DATA_WIDTH)-1 downto 0), + DataFromModel((AXI_DATA_WIDTH)-1 downto 0) + ) ; + + signal AxiMasterTransRec : MasterTransactionRecType ; + +-- AXI Master Functional Interface + signal AxiBus : Axi4LiteRecType( + WriteAddress( Addr(AXI_ADDR_WIDTH-1 downto 0) ), + WriteData ( Data (AXI_DATA_WIDTH-1 downto 0), Strb(AXI_STRB_WIDTH-1 downto 0) ), + ReadAddress ( Addr(AXI_ADDR_WIDTH-1 downto 0) ), + ReadData ( Data (AXI_DATA_WIDTH-1 downto 0) ) + ) ; + + component AXI4Lite_Ocram_Adapter_TestController is + port ( + -- Global Signal Interface + Clk : in std_logic ; + nReset : in std_logic ; + + MasterRec : inout AddressBusRecType + ) ; + end component; + +begin + + -- create Clock for TB and 100 Mhz + Osvvm.ClockResetPkg.CreateClock ( + Clk => Clk, + Period => Tperiod_Clk + ) ; + + -- create nReset + Osvvm.ClockResetPkg.CreateReset ( + Reset => Reset, + ResetActive => '0', + Clk => Clk, + Period => 7 * tperiod_Clk, + tpd => tpd + ) ; + + AXI4_Config : entity OSVVM_AXI4.Axi4LiteManager + generic map ( + tperiod_Clk => 5 ns, + tpd_Clk_AWValid => 0 ns, + tpd_Clk_AWProt => 0 ns, + tpd_Clk_AWAddr => 0 ns, + tpd_Clk_WValid => 0 ns, + tpd_Clk_WData => 0 ns, + tpd_Clk_WStrb => 0 ns, + tpd_Clk_BReady => 0 ns, + tpd_Clk_ARValid => 0 ns, + tpd_Clk_ARProt => 0 ns, + tpd_Clk_ARAddr => 0 ns, + tpd_Clk_RReady => 0 ns + ) + port map ( + Clk => Clk, + nReset => not Reset, + + TransRec => AxiMasterTransRec, -- Testbench Transaction Interface + AxiBus => AxiBus -- AXI Master Functional Interface + ) ; + + --------------------------------------------------------------------------- + -- axi4_slave_rb_interface + --------------------------------------------------------------------------- + AXI4Lite_Ocram_Adaptar : entity PoC.AXI4Lite_Ocram_Adapter + generic map ( + OCRAM_ADDRESS_BITS => OCRAM_ADDRESS_BITS, + OCRAM_DATA_BITS => OCRAM_DATA_BITS, + PREFFERED_READ_ACCESS => PREFFERED_READ_ACCESS + ) + port map ( + -- AXI4lite slave interface + Clock => Clk, + Reset => Reset, + + AXI4Lite_m2s.AWValid => AxiBus.WriteAddress.Valid, + AXI4Lite_m2s.AWAddr => AxiBus.WriteAddress.Addr, + AXI4Lite_m2s.AWCache => (others => '0'), + AXI4Lite_m2s.AWProt => AxiBus.WriteAddress.Prot, + AXI4Lite_m2s.WValid => AxiBus.WriteData.Valid, + AXI4Lite_m2s.WData => AxiBus.WriteData.Data, + AXI4Lite_m2s.WStrb => AxiBus.WriteData.Strb, + AXI4Lite_m2s.BReady => AxiBus.WriteResponse.Ready, + AXI4Lite_m2s.ARValid => AxiBus.ReadAddress.Valid, + AXI4Lite_m2s.ARAddr => AxiBus.ReadAddress.Addr, + AXI4Lite_m2s.ARCache => (others => '0'), + AXI4Lite_m2s.ARProt => AxiBus.ReadAddress.Prot, + AXI4Lite_m2s.RReady => AxiBus.ReadData.Ready, + + AXI4Lite_s2m.WReady => AxiBus.WriteData.Ready, + AXI4Lite_s2m.BValid => AxiBus.WriteResponse.Valid, + AXI4Lite_s2m.BResp => AxiBus.WriteResponse.Resp, + AXI4Lite_s2m.ARReady => AxiBus.ReadAddress.Ready, + AXI4Lite_s2m.AWReady => AxiBus.WriteAddress.Ready, + AXI4Lite_s2m.RValid => AxiBus.ReadData.Valid, + AXI4Lite_s2m.RData => AxiBus.ReadData.Data, + AXI4Lite_s2m.RResp => AxiBus.ReadData.Resp, + + Write_En => write_en, + Address => address, + Data_In => data_in, + Data_Out => data_out + ) ; + + ocram : entity PoC.ocram_tdp + generic map ( + A_BITS => OCRAM_ADDRESS_BITS, + D_BITS => OCRAM_DATA_BITS + ) + port map ( + clk1 => Clk, + clk2 => Clk, + ce1 => '1', + ce2 => '1', + we1 => write_en, + we2 => '0', + a1 => address, + a2 => PortB_address, + d1 => data_out, + d2 => (others => '0'), + q1 => data_in, + q2 => PortB_data + ) ; + + TestCtrl : AXI4Lite_Ocram_Adapter_TestController + port map( + Clk => Clk, + nReset => not Reset, + + MasterRec => AxiMasterTransRec + ); + +end architecture; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/RunAllTests.pro b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/RunAllTests.pro new file mode 100644 index 000000000..b50b5d34e --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/RunAllTests.pro @@ -0,0 +1,31 @@ +# ============================================================================= +# Authors: +# Iqbal Asif (PLC2 Design GmbH) +# Patrick Lehmann (PLC2 Design GmbH) +# +# License: +# ============================================================================= +# Copyright 2025-2026 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +TestSuite PoC.bus.axi4.axi4lite.AXI4LiteOcram_Adapter + +library tb_axi4lite_OCRAMAdapter + +analyze AXI4Lite_Ocram_Adapter_TestController.vhdl +analyze AXI4Lite_Ocram_Adapter_TestHarness.vhdl + +RunTest TC_AsyncReadWrite.vhdl +RunTest TC_SimpleReadWrite.vhdl diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/TC_AsyncReadWrite.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/TC_AsyncReadWrite.vhdl new file mode 100644 index 000000000..3c1602d6d --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/TC_AsyncReadWrite.vhdl @@ -0,0 +1,151 @@ +-- ============================================================================= +-- Authors: +-- Iqbal Asif (PLC2 Design GmbH) +-- Patrick Lehmann (PLC2 Design GmbH) +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +architecture AsyncReadWrite of AXI4Lite_Ocram_Adapter_TestController is + signal TestDone : integer_barrier := 1; + +begin + + ------------------------------------------------------------ + -- ControlProc + -- Set up AlertLog and wait for end of test + ------------------------------------------------------------ + ControlProc : process + constant TestName : string := "TC_AsyncReadWrite"; + constant TIMEOUT : time := 30 ms; + begin + -- Initialization of test + SetAlertLogName(TestName) ; + -- SetLogEnable(PASSED, TRUE) ; -- Enable PASSED logs + -- SetLogEnable(INFO, TRUE) ; -- Enable INFO logs + + -- Wait for testbench initialization + wait for 0 ns ; + SetTranscriptMirror(TRUE) ; + + -- Wait for Design Reset + wait until nReset = '1' ; + ClearAlerts ; + + WaitForBarrier(TestDone, TIMEOUT); + EndOfTestReports(ReportAll => TRUE, Timeout => now >= TIMEOUT); + std.env.finish; + wait; + end process ControlProc ; + + ------------------------------------------------------------ + -- MasterProc + -- Generate transactions for AxiMaster + ------------------------------------------------------------ + MasterProc : process + variable Address : std_logic_vector(AXI_ADDR_WIDTH-1 downto 0); + variable Data : std_logic_vector(AXI_DATA_WIDTH-1 downto 0); + variable ReadData : std_logic_vector(AXI_DATA_WIDTH-1 downto 0); + + begin + ------------------------------------- + -- Normal Rread and Wirte + ------------------------------------- + wait until nReset = '1' ; + WaitForClock(MasterRec, 2); + + Write(MasterRec, 32x"04", 32x"F" ); + WaitForClock(MasterRec, 2); + + Write(MasterRec, 32x"08", 32x"FF" ); + WaitForClock(MasterRec, 2); + + Write(MasterRec, 32x"14", 32x"AFAF" ); + WaitForClock(MasterRec, 2); + + Read(MasterRec, 32x"14", ReadData ); + WaitForClock(MasterRec, 2) ; + + ------------------------------------- + -- Async. Wirte + ------------------------------------- + WriteAsync(MasterRec, 32x"0C", 32x"0C" ); + WriteAsync(MasterRec, 32x"10", 32x"CC" ); + WaitForClock(MasterRec, 1) ; + + ------------------------------------- + -- Async. Address and Wirte Data + ------------------------------------- + WriteAddressAsync(MasterRec, 32x"1C"); + WaitForClock(MasterRec, 3) ; + WriteDataAsync(MasterRec,x"0",32x"1C"); + WaitForClock(MasterRec, 3) ; + + WriteAddressAsync(MasterRec, 32x"2C"); + WaitForClock(MasterRec, 3) ; + WriteDataAsync(MasterRec,x"0",32x"2C"); + WaitForClock(MasterRec, 3) ; + + WriteAddressAsync(MasterRec, 32x"3C"); + WaitForClock(MasterRec, 3) ; + WriteDataAsync(MasterRec,x"0",32x"3C"); + WaitForClock(MasterRec, 3) ; + + WriteAddressAsync(MasterRec, 32x"4C"); + WaitForClock(MasterRec, 3) ; + WriteDataAsync(MasterRec,x"0",32x"4C"); + WaitForClock(MasterRec, 3) ; + + ------------------------------------- + -- Async. Address and Read Data + ------------------------------------- + ReadAddressAsync(MasterRec, 32x"04"); + ReadAddressAsync(MasterRec, 32x"08"); + ReadCheckData(MasterRec, 32x"F"); + ReadCheckData(MasterRec, 32x"FF"); + + ------------------------------------- + -- Async. Data first and Address later + ------------------------------------- + WriteDataAsync(MasterRec,x"0",32x"1C"); + WriteDataAsync(MasterRec,x"0",32x"2C"); + WriteDataAsync(MasterRec,x"0",32x"3C"); + WriteDataAsync(MasterRec,x"0",32x"4C"); + + WaitForClock(MasterRec, 1) ; + + WriteAddressAsync(MasterRec, 32x"1C"); + WriteAddressAsync(MasterRec, 32x"2C"); + WriteAddressAsync(MasterRec, 32x"3C"); + WriteAddressAsync(MasterRec, 32x"4C"); + + WaitForClock(MasterRec, 1) ; + + wait for 200 ns; + WaitForBarrier(TestDone) ; + wait; + end process MasterProc ; + +end architecture; + +configuration TC_AsyncReadWrite of AXI4Lite_Ocram_Adapter_TestHarness is + for sim + for TestCtrl : AXI4Lite_Ocram_Adapter_TestController + use entity work.AXI4Lite_Ocram_Adapter_TestController(AsyncReadWrite) ; + end for ; + end for ; +end configuration ; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/TC_SimpleReadWrite.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/TC_SimpleReadWrite.vhdl new file mode 100644 index 000000000..f4faffe9e --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/TC_SimpleReadWrite.vhdl @@ -0,0 +1,95 @@ +-- ============================================================================= +-- Authors: +-- Iqbal Asif (PLC2 Design GmbH) +-- Patrick Lehmann (PLC2 Design GmbH) +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +architecture SimpleReadWrite of AXI4Lite_Ocram_Adapter_TestController is + signal TestDone : integer_barrier := 1; + +begin + + ------------------------------------------------------------ + -- ControlProc + -- Set up AlertLog and wait for end of test + ------------------------------------------------------------ + ControlProc : process + constant TestName : string := "TC_SimpleReadWrite"; + constant TIMEOUT : time := 30 ms; + begin + -- Initialization of test + SetAlertLogName(TestName) ; + -- SetLogEnable(PASSED, TRUE) ; -- Enable PASSED logs + -- SetLogEnable(INFO, TRUE) ; -- Enable INFO logs + + -- Wait for testbench initialization + wait for 0 ns ; + SetTranscriptMirror(TRUE) ; + + -- Wait for Design Reset + wait until nReset = '1' ; + ClearAlerts ; + + WaitForBarrier(TestDone, TIMEOUT); + EndOfTestReports(ReportAll => TRUE, Timeout => now >= TIMEOUT); + std.env.finish; + wait; + end process ControlProc ; + + ------------------------------------------------------------ + -- MasterProc + -- Generate transactions for AxiMaster + ------------------------------------------------------------ + MasterProc : process + variable Address : std_logic_vector(AXI_ADDR_WIDTH-1 downto 0); + variable Data : std_logic_vector(AXI_DATA_WIDTH-1 downto 0); + variable ReadData : std_logic_vector(AXI_DATA_WIDTH-1 downto 0); + + begin + ------------------------------------- + -- Normal Rread and Wirte + ------------------------------------- + wait until nReset = '1' ; + WaitForClock(MasterRec, 2); + + Write(MasterRec, 32x"04", 32x"F" ); + WaitForClock(MasterRec, 2); + + Write(MasterRec, 32x"08", 32x"FF" ); + WaitForClock(MasterRec, 2); + + Write(MasterRec, 32x"14", 32x"AFAF" ); + WaitForClock(MasterRec, 2); + + Read(MasterRec, 32x"14", ReadData ); + WaitForClock(MasterRec, 2) ; + + wait for 100 ns; + WaitForBarrier(TestDone) ; + wait; + end process MasterProc ; +end architecture ; + +configuration TC_SimpleReadWrite of AXI4Lite_Ocram_Adapter_TestHarness is + for sim + for TestCtrl : AXI4Lite_Ocram_Adapter_TestController + use entity work.AXI4Lite_Ocram_Adapter_TestController(SimpleReadWrite) ; + end for ; + end for ; +end configuration ; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_initial.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_Initial.vhdl similarity index 91% rename from tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_initial.vhdl rename to tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_Initial.vhdl index f49c5c994..bc814c799 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_initial.vhdl +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_Initial.vhdl @@ -1,11 +1,8 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: --- Adrian Weiland (PLC2 Design GmbH) +-- Adrian Weiland (PLC2 Design GmbH) -- --- Entity: Initial +-- Testcase: Initial -- -- Description: -- ------------------------------------- @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. @@ -46,7 +43,7 @@ begin constant TIMEOUT : time := 10 ms; begin -- Initialization of test - SetAlertLogName("AXI4Lite_Register_initial"); + SetAlertLogName("AXI4Lite_Register_Initial"); SetLogEnable(PASSED, FALSE); SetLogEnable(INFO, FALSE); SetLogEnable(osvvm.AlertLogPkg.DEBUG, FALSE); @@ -147,7 +144,7 @@ begin end architecture; -configuration AXI4Lite_Register_initial of AXI4Lite_Register_TestHarness is +configuration AXI4Lite_Register_Initial of AXI4Lite_Register_TestHarness is for sim for TestCtrl : AXI4Lite_Register_TestController use entity work.AXI4Lite_Register_TestController(Initial); diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_ReadWrite.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_ReadWrite.vhdl index 5ad23a1eb..ab4b814f3 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_ReadWrite.vhdl +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_ReadWrite.vhdl @@ -1,19 +1,12 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: --- Adrian Weiland (PLC2 Design GmbH) +-- Adrian Weiland (PLC2 Design GmbH) -- --- Entity: ReadWrite --- --- Description: --- ------------------------------------- --- Test-Case ReadWrite +-- Testcase: ReadWrite -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestController.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestController.vhdl index 5e9229399..865929bdd 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestController.vhdl +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestController.vhdl @@ -1,13 +1,10 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: --- Iqbal Asif (PLC2 Design GmbH) --- Patrick Lehmann (PLC2 Design GmbH) --- Adrian Weiland (PLC2 Design GmbH) +-- Iqbal Asif (PLC2 Design GmbH) +-- Patrick Lehmann (PLC2 Design GmbH) +-- Adrian Weiland (PLC2 Design GmbH) -- --- Entity: AXI4Lite_Register_TestController +-- Entity: AXI4Lite_Register_TestController -- -- Description: -- ------------------------------------- @@ -15,7 +12,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestHarness.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestHarness.vhdl index b6076d915..3fe477e9b 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestHarness.vhdl +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestHarness.vhdl @@ -1,13 +1,10 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: --- Iqbal Asif (PLC2 Design GmbH) --- Patrick Lehmann (PLC2 Design GmbH) --- Adrian Weiland (PLC2 Design GmbH) +-- Iqbal Asif (PLC2 Design GmbH) +-- Patrick Lehmann (PLC2 Design GmbH) +-- Adrian Weiland (PLC2 Design GmbH) -- --- Entity: AXI4Lite_Register_TestHarness +-- Entity: AXI4Lite_Register_TestHarness -- -- Description: -- ------------------------------------- @@ -15,7 +12,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_pkg.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_pkg.vhdl index aa0abe012..beb18fec9 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_pkg.vhdl +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_pkg.vhdl @@ -1,19 +1,12 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: --- Adrian Weiland (PLC2 Design GmbH) +-- Adrian Weiland (PLC2 Design GmbH) -- --- Entity: AXI4Lite_Register_pkg --- --- Description: --- ------------------------------------- --- AXI4Lite Register package of OSVVM Testbench +-- Package: AXI4Lite Register package of OSVVM Testbench -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/RunAllTests.pro b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/RunAllTests.pro index ad32fdb3d..5d0472431 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/RunAllTests.pro +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -19,12 +19,13 @@ # limitations under the License. # ============================================================================= -library tb_axi4liteRegister +TestSuite PoC.bus.axi4.axi4Lite.Register +library tb_axi4lite_Register analyze AXI4Lite_Register_pkg.vhdl analyze AXI4Lite_Register_TestController.vhdl analyze AXI4Lite_Register_TestHarness.vhdl # Test cases -RunTest AXI4Lite_Register_initial.vhdl +RunTest AXI4Lite_Register_Initial.vhdl RunTest AXI4Lite_Register_ReadWrite.vhdl diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/RunAllTests.pro b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/RunAllTests.pro new file mode 100644 index 000000000..7411d5d54 --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/RunAllTests.pro @@ -0,0 +1,33 @@ +# ============================================================================= +# Authors: +# Srikanth Boppudi (PLC2 Design GmbH) +# +# License: +# ============================================================================= +# Copyright 2025-2026 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +TestSuite PoC.bus.axi4.axi4Lite.Uart + +library tb_axi4lite_UART + +analyze axi4lite_UART_tc.vhdl +analyze axi4lite_UART_th.vhdl + +RunTest axi4lite_UART_receive.vhdl +RunTest axi4lite_UART_transmit_burst.vhdl +# RunTest axi4lite_UART_receive_burst.vhdl +# RunTest axi4lite_UART_receive_parity.vhdl +# RunTest axi4lite_UART_SWFC.vhdl diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_SWFC.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_SWFC.vhdl new file mode 100644 index 000000000..3113eed6b --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_SWFC.vhdl @@ -0,0 +1,256 @@ +architecture Software_flowcontrol of axi4lite_UART_tc is + subtype UARTDataType is std_logic_vector(7 downto 0); + alias UARTSequenceType is T_SLVV_8; + + alias SB_IDType is OSVVM.ScoreBoardPkg_slv.ScoreboardIdType; + signal UART_receive_SB : SB_IDType; + signal UART_transmit_SB : SB_IDType; + + constant TestCtrlID : AlertLogIDType := NewID("TestController"); + + constant TestData : UARTSequenceType := (x"5A", -- 1B + x"CA",x"FE",x"AF",x"FE", -- 4B + x"DE",x"AD",x"BE",x"EF",x"DE",x"AD",x"BE",x"EF", -- 8B + x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"10", -- 16B + x"DA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE", x"BA", -- 17B + x"EA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE", x"BA",x"CA"); -- 18B + + type SequenceDescriptionType is record + TransmitLength : positive; + ReadoutLength : positive; + IsFull : boolean; + IsOverrun : boolean; + end record; + type SequencesType is array(natural range <>) of SequenceDescriptionType; + + constant Sequences : SequencesType := ( + 0 => ( 4, 4, FALSE, FALSE), + 1 => ( 8, 8, FALSE, FALSE), + 2 => ( 11, 11, FALSE, FALSE), + 3 => (12, 12, FALSE, FALSE), + 4 => (16, 16, TRUE, FALSE) + ); + + function toTransmitLengths(sequences : SequencesType) return T_POSVEC is + variable lengths : T_POSVEC(sequences'range); + begin + for i in sequences'range loop + lengths(i) := sequences(i).TransmitLength; + end loop; + return lengths; + end function; + + function toReadoutLengths(sequences : SequencesType) return T_POSVEC is + variable lengths : T_POSVEC(sequences'range); + begin + for i in sequences'range loop + lengths(i) := sequences(i).ReadoutLength; + end loop; + return lengths; + end function; + + constant TransmitLengths : T_POSVEC := toTransmitLengths(Sequences); + constant ReadoutLengths : T_POSVEC := toReadoutLengths(Sequences); + + signal TestDone : integer_barrier := 1; + signal ReadByteTrigger : natural := 0; + signal Read_Enable : std_logic:= '0'; + signal SWFC_TRigger : integer:= 0; --software flow control trigger + signal latch_xon : std_logic:= '0'; + signal check_FC_Char : std_logic:= '0'; + + constant XON : std_logic_vector(7 downto 0) := x"11"; -- ^Q + constant XOFF : std_logic_vector(7 downto 0) := x"13"; -- ^S +begin + -- Testbench control process + ControlProc : process + constant TIMEOUT : time := 10 ms; + begin + -- Initialization of test + SetTestName("axi4lite_UART_SWFC"); + SetLogEnable(PASSED, FALSE); --Enable PASSED Logs + SetLogEnable(INFO, FALSE); --Enable INFO Logs + UART_receive_SB <= OSVVM.ScoreBoardPkg_slv.NewID("UART_receive_SB"); + UART_transmit_SB <= OSVVM.ScoreBoardPkg_slv.NewID("UART_transmit_SB"); + + -- Wait for testbench Initialization + wait for 0 ns; + wait for 0 ns; + TranscriptOpen; + SetTranscriptMirror(TRUE); + + -- wait for design reset + wait until Reset = '0'; + ClearAlerts; + + WaitForBarrier(TestDone, TIMEOUT); + EndOfTestReports(ReportAll => TRUE, Timeout => now >= TIMEOUT); + std.env.finish; + end process ControlProc; + + -- Generate transaction for AXI manager + ManagerProc : process + constant ProcLogID : AlertLogIDType := NewID("ManagerProc", TestCtrlID); + variable AxiManagerLogID : AlertLogIDType; + + constant RX_REG : AXIAddressType := 32x"00"; + constant TX_REG : AXIAddressType := 32x"04"; + constant STATUS_REG : AXIAddressType := 32x"08"; + constant CONTROL_REG : AXIAddressType := 32x"0C"; + + variable ReceivedData : AXIDataType; + variable isFull : boolean := true; + variable isEmpty : boolean := true; + + -- status reg for rx, bit 5 checks for the Status_RX_Overrun + procedure CheckIsEmpty_RX( + signal manager : inout AddressBusRecType; + constant expected : in boolean + ) is + variable Data : AXIDataType; + variable isEmpty : boolean; + begin + Read(manager, STATUS_REG, Data); + isEmpty := Data(0) = '0'; + AffirmIf(isEmpty = expected, "EmptyBit: Received: " & to_string(isEmpty), " /= Expected: " & to_string(expected)); + end procedure; + + procedure CheckIsFull_RX( + signal manager : inout AddressBusRecType; + constant expected : in boolean + ) is + variable Data : AXIDataType; + variable isFull : boolean; + begin + Read(manager, STATUS_REG, Data); + isFull := Data(1) = '1'; + AffirmIf(isFull = expected, "FullBit: Received: " & to_string(isFull), " /= Expected: " & to_string(expected)); + end procedure; + + procedure CheckIsOverrun_RX( + signal manager : inout AddressBusRecType; + constant expected : in boolean + ) is + variable Data : AXIDataType; + variable isOverrun : boolean; + begin + Read(manager, STATUS_REG, Data); + isOverrun := Data(5) = '1'; + AffirmIf(isOverrun = expected, "OverrunBit: Received: " & to_string(isOverrun), " /= Expected: " & to_string(expected)); + end procedure; + + begin + wait until Reset = '0'; + + GetAlertLogID(AXI_Manager, AxiManagerLogID); + SetLogEnable(AxiManagerLogID, INFO, False); + OSVVM.ScoreBoardPkg_slv.Push(UART_transmit_SB, XON); + OSVVM.ScoreBoardPkg_slv.Push(UART_transmit_SB, XOFF); + OSVVM.ScoreBoardPkg_slv.Push(UART_transmit_SB, XON); + OSVVM.ScoreBoardPkg_slv.Push(UART_transmit_SB, XOFF); + OSVVM.ScoreBoardPkg_slv.Push(UART_transmit_SB, XON); + + for i in ReadoutLengths'range loop + + WaitForToggle(Read_Enable); + + CheckIsEmpty_RX(AXI_Manager, FALSE); + CheckIsFull_RX(AXI_Manager, Sequences(i).IsFull); + CheckIsOverrun_RX(AXI_Manager, Sequences(i).IsOverrun); + + log(ProcLogID, "Reading received data sequence " & to_string(i) & " of " & to_string(ReadoutLengths(i)) & " bytes from UART register"); + for j in 0 to ReadoutLengths(i) - 1 loop + Read(AXI_Manager, RX_REG, ReceivedData); + OSVVM.ScoreBoardPkg_slv.Check(UART_receive_SB, ReceivedData(7 downto 0)); + end loop; + toggle(latch_xon); + CheckIsEmpty_RX(AXI_Manager, TRUE); + CheckIsFull_RX(AXI_Manager, FALSE); + CheckIsOverrun_RX(AXI_Manager, FALSE); + end loop; + + + wait for 500 us; + WaitForBarrier(TestDone); + wait; + end process ManagerProc; + + -- Generate transactions for UART transmitter + UartTxProc : process + constant ProcLogID : AlertLogIDType := NewID("UartTxProc", TestCtrlID); + + procedure UARTSendBurst( + signal uartRec : inout UartRecType; + constant data_array : in UARTSequenceType + ) is + begin + for i in data_array'range loop + OSVVM.ScoreBoardPkg_slv.Push(UART_receive_SB, data_array(i)); + log(ProcLogID, "Sending data of " & to_string(i) & "th byte to AXI RX register"); + Send(uartRec, data_array(i)); + end loop; + end procedure; + begin + wait until Reset = '0'; + WaitForClock(UartTxRec, 1); + + for i in TransmitLengths'range loop + log("Send test sequence " & to_string(i) & " of " & to_string(TransmitLengths(i)) & " bytes to AXI RX register ..."); + UARTSendBurst(UartTxRec, TestData(low(TransmitLengths, i) to high(TransmitLengths, i))); + if TransmitLengths(i) >= 12 then -- 12=(16*0.75) is the set upper limit for RX Fifo flow control. + check_FC_Char <= '1'; + Increment(SWFC_TRigger); + else + check_FC_Char <= '0'; + Increment(SWFC_TRigger); + end if; + --Increment(SWFC_TRigger); + end loop; + + WaitForBarrier(TestDone); + wait; + end process; + + -- Generate transactions for UART receiver + UartRxProc : process + constant ProcLogID : AlertLogIDType := NewID("UartRxProc", TestCtrlID); + variable ReceivedData : UARTDataType; + + begin + wait until Reset = '0'; + for i in sequences'range loop + if check_FC_Char = '1' then + + WaitForToggle(SWFC_TRigger); + + Get(UartRxRec, ReceivedData); + OSVVM.ScoreBoardPkg_slv.Check(UART_transmit_SB, ReceivedData); + log(ProcLogID, "received XOFF character"); + + toggle(Read_Enable); + + WaitForToggle(latch_xon); + + Get(UartRxRec, ReceivedData); + OSVVM.ScoreBoardPkg_slv.Check(UART_transmit_SB, ReceivedData); + + log(ProcLogID, "received XON character"); + else + WaitForToggle(SWFC_TRigger); + toggle(Read_Enable); + end if; + end loop; + + WaitForBarrier(TestDone); + wait; + end process; +end architecture; + + +configuration axi4lite_UART_SWFC of uart_AXILite_th is + for TestHarness + for TestCtrl : axi4lite_UART_tc + use entity work.axi4lite_UART_tc(Software_flowcontrol); + end for; + end for; +end configuration; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_receive.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_receive.vhdl new file mode 100644 index 000000000..4c525b617 --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_receive.vhdl @@ -0,0 +1,95 @@ +architecture receive of axi4lite_UART_tc is + subtype UARTDataType is std_logic_vector(7 downto 0); + + constant TestData : UARTDataType := x"45"; + + signal TestDone : integer_barrier := 1; + signal ReadByteTrigger : bit := '0'; +begin + -- Testbench control process + ControlProc : process + constant TIMEOUT : time := 10 ms; + begin + -- Initialization of test + SetTestName("axi4lite_UART_receive"); + SetLogEnable(PASSED, FALSE); --Enable PASSED Logs + SetLogEnable(INFO, FALSE); --Enable INFO Logs + + -- Wait for testbench Initialization + wait for 0 ns; + wait for 0 ns; + TranscriptOpen; + SetTranscriptMirror(TRUE); + + -- wait for design reset + wait until Reset = '0'; + ClearAlerts; + + WaitForBarrier(TestDone, TIMEOUT); + EndOfTestReports(ReportAll => TRUE, Timeout => now >= TIMEOUT); + std.env.finish; + end process ControlProc; + + -- Generate transaction for AXI manager + ManagerProc : process + constant RX_REG : AXIAddressType := 32x"00"; + constant TX_REG : AXIAddressType := 32x"04"; + constant STATUS_REG : AXIAddressType := 32x"08"; + constant CONTROL_REG : AXIAddressType := 32x"0C"; + + function toAXIData(data : UARTDataType) return AXIDataType is + begin + return 24x"00" & data; + end function; + + variable ReceivedData : AXIDataType; + begin + wait until Reset = '0'; + + WaitForToggle(ReadByteTrigger); + + log("Reading received data byte from UART register ..."); + Read(AXI_Manager, RX_REG, ReceivedData); + AffirmIf( + ReceivedData = toAXIData(TestData), + "Received: " & to_hstring(ReceivedData), + " /= Expected: " & to_hstring(TestData) + ); + + wait for 500 us; -- this delay is added because the uart implementation in OSVVM is providing half a stop bit and due to this there will be a error. + WaitForBarrier(TestDone); + wait; + end process ManagerProc; + + -- Generate transactions for UART transmitter + UartTxProc : process + begin + wait until Reset = '0'; + + WaitForClock(UartTxRec, 1); + Send(UartTxRec, TestData); + Toggle(ReadByteTrigger); + + WaitForBarrier(TestDone); + wait; + end process; + + + -- Generate transactions for UART receiver + UartRxProc : process + begin + wait until Reset = '0'; + + WaitForBarrier(TestDone); + wait; + end process; +end architecture; + + +configuration axi4lite_UART_receive of axi4lite_UART_th is + for TestHarness + for TestCtrl : axi4lite_UART_tc + use entity work.axi4lite_UART_tc(receive); + end for; + end for; +end configuration; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_receive_burst.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_receive_burst.vhdl new file mode 100644 index 000000000..e7451f258 --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_receive_burst.vhdl @@ -0,0 +1,225 @@ +architecture receive_burst of axi4lite_UART_tc is + subtype UARTDataType is std_logic_vector(7 downto 0); + alias UARTSequenceType is T_SLVV_8; + + alias SB_IDType is OSVVM.ScoreBoardPkg_slv.ScoreboardIdType; + signal UART_receive_SB : SB_IDType; + + constant TestCtrlID : AlertLogIDType := NewID("TestController"); + + constant TestData : UARTSequenceType := (x"5A", -- 1B + x"CA",x"FE",x"AF",x"FE", -- 4B + x"DE",x"AD",x"BE",x"EF",x"DE",x"AD",x"BE",x"EF", -- 8B + x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE", -- 16B + x"DA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE", x"BA", -- 17B + x"EA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE",x"CA",x"FE",x"AF",x"FE", x"BA",x"CA"); -- 18B + + type SequenceDescriptionType is record + TransmitLength : positive; + ReadoutLength : positive; + IsFull : boolean; + IsOverrun : boolean; + end record; + type SequencesType is array(natural range <>) of SequenceDescriptionType; + + constant Sequences : SequencesType := ( + 0 => ( 1, 1, FALSE, FALSE), + 1 => ( 4, 4, FALSE, FALSE), + 2 => ( 8, 8, FALSE, FALSE), + 3 => (16, 16, TRUE, FALSE), + 4 => (17, 16, TRUE, TRUE) + ); + + function toTransmitLengths(sequences : SequencesType) return T_POSVEC is + variable lengths : T_POSVEC(sequences'range); + begin + for i in sequences'range loop + lengths(i) := sequences(i).TransmitLength; + end loop; + return lengths; + end function; + + function toReadoutLengths(sequences : SequencesType) return T_POSVEC is + variable lengths : T_POSVEC(sequences'range); + begin + for i in sequences'range loop + lengths(i) := sequences(i).ReadoutLength; + end loop; + return lengths; + end function; + + constant TransmitLengths : T_POSVEC := toTransmitLengths(Sequences); + constant ReadoutLengths : T_POSVEC := toReadoutLengths(Sequences); + + signal TestDone : integer_barrier := 1; + signal ReadByteTrigger : natural := 0; +begin + -- Testbench control process + ControlProc : process + constant TIMEOUT : time := 10 ms; + begin + -- Initialization of test + SetTestName("axi4lite_UART_receive_burst"); + SetLogEnable(PASSED, TRUE); --Enable PASSED Logs + SetLogEnable(INFO, TRUE); --Enable INFO Logs + UART_receive_SB <= OSVVM.ScoreBoardPkg_slv.NewID("UART_receive_SB"); + + -- Wait for testbench Initialization + wait for 0 ns; + wait for 0 ns; + TranscriptOpen; + SetTranscriptMirror(TRUE); + + -- wait for design reset + wait until Reset = '0'; + ClearAlerts; + + WaitForBarrier(TestDone, TIMEOUT); + EndOfTestReports(ReportAll => TRUE, Timeout => now >= TIMEOUT); + std.env.finish;.stop; + wait; + end process ControlProc; + + -- Generate transaction for AXI manager + ManagerProc : process + constant ProcLogID : AlertLogIDType := NewID("ManagerProc", TestCtrlID); + variable AxiManagerLogID : AlertLogIDType; + + constant RX_REG : AXIAddressType := 32x"00"; + constant TX_REG : AXIAddressType := 32x"04"; + constant STATUS_REG : AXIAddressType := 32x"08"; + constant CONTROL_REG : AXIAddressType := 32x"0C"; + + variable ReceivedData : AXIDataType; + variable isFull : boolean := true; + variable isEmpty : boolean := true; + + -- status reg for rx, bit 5 checks for the Status_RX_Overrun + procedure CheckIsEmpty_RX( + signal manager : inout AddressBusRecType; + constant expected : in boolean + ) is + variable Data : AXIDataType; + variable isEmpty : boolean; + begin + Read(manager, STATUS_REG, Data); + isEmpty := Data(0) = '0'; + AffirmIf(isEmpty = expected, "EmptyBit: Received: " & to_string(isEmpty), " /= Expected: " & to_string(expected)); + end procedure; + + procedure CheckIsFull_RX( + signal manager : inout AddressBusRecType; + constant expected : in boolean + ) is + variable Data : AXIDataType; + variable isFull : boolean; + begin + Read(manager, STATUS_REG, Data); + isFull := Data(1) = '1'; + AffirmIf(isFull = expected, "FullBit: Received: " & to_string(isFull), " /= Expected: " & to_string(expected)); + end procedure; + + procedure CheckIsOverrun_RX( + signal manager : inout AddressBusRecType; + constant expected : in boolean + ) is + variable Data : AXIDataType; + variable isOverrun : boolean; + begin + Read(manager, STATUS_REG, Data); + isOverrun := Data(5) = '1'; + AffirmIf(isOverrun = expected, "OverrunBit: Received: " & to_string(isOverrun), " /= Expected: " & to_string(expected)); + end procedure; + + procedure CheckIsParity_flag( + signal manager : inout AddressBusRecType; + constant expected : in boolean + ) is + variable Data : AXIDataType; + variable parity_error : boolean; + begin + Read(manager, STATUS_REG, Data); + parity_error := Data(7) = '1'; + AffirmIf(parity_error = expected, "EmptyBit: Received: " & to_string(parity_error), " /= Expected: " & to_string(expected)); + end procedure; + + begin + wait until Reset = '0'; + + GetAlertLogID(AXI_Manager, AxiManagerLogID); + SetLogEnable(AxiManagerLogID, INFO, False); + + for i in ReadoutLengths'range loop + WaitForToggle(ReadByteTrigger); + + CheckIsEmpty_RX(AXI_Manager, FALSE); + CheckIsParity_flag(AXI_Manager, FALSE); + CheckIsFull_RX(AXI_Manager, Sequences(i).IsFull); + CheckIsOverrun_RX(AXI_Manager, Sequences(i).IsOverrun); + + log(ProcLogID, "Reading received data sequence " & to_string(i) & " of " & to_string(ReadoutLengths(i)) & " bytes from UART register"); + for j in 0 to ReadoutLengths(i) - 1 loop + Read(AXI_Manager, RX_REG, ReceivedData); + OSVVM.ScoreBoardPkg_slv.Check(UART_receive_SB, ReceivedData(7 downto 0)); + end loop; + + CheckIsEmpty_RX(AXI_Manager, TRUE); + CheckIsFull_RX(AXI_Manager, FALSE); + CheckIsOverrun_RX(AXI_Manager, FALSE); + end loop; + + wait for 500 us; + WaitForBarrier(TestDone); + wait; + end process ManagerProc; + + -- Generate transactions for UART transmitter + UartTxProc : process + constant ProcLogID : AlertLogIDType := NewID("UartTxProc", TestCtrlID); + + procedure UARTSendBurst( + signal uartRec : inout UartRecType; + constant data_array : in UARTSequenceType + ) is + begin + for i in data_array'range loop + OSVVM.ScoreBoardPkg_slv.Push(UART_receive_SB, data_array(i)); + log(ProcLogID, "Sending data of " & to_string(i) & "th byte to AXI RX register"); + Send(uartRec, data_array(i)); + end loop; + end procedure; + begin + wait until Reset = '0'; + WaitForClock(UartTxRec, 1); + + for i in TransmitLengths'range loop + log("Send test sequence " & to_string(i) & " of " & to_string(TransmitLengths(i)) & " bytes to AXI RX register ..."); + UARTSendBurst(UartTxRec, TestData(low(TransmitLengths, i) to high(TransmitLengths, i))); + Increment(ReadByteTrigger); + end loop; + + WaitForBarrier(TestDone); + wait; + end process; + + -- Generate transactions for UART receiver + UartRxProc : process + constant ProcLogID : AlertLogIDType := NewID("UartRxProc", TestCtrlID); + begin + wait until Reset = '0'; + + log(ProcLogID, "Transmit verification model isn't used in this testcase"); + + WaitForBarrier(TestDone); + wait; + end process; +end architecture; + + +configuration axi4lite_UART_receive_burst of axi4lite_UART_th is + for TestHarness + for TestCtrl : axi4lite_UART_tc + use entity work.axi4lite_UART_tc(receive_burst); + end for; + end for; +end configuration; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_receive_parity.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_receive_parity.vhdl new file mode 100644 index 000000000..1e259d58c --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_receive_parity.vhdl @@ -0,0 +1,118 @@ +architecture receive_parity of axi4lite_UART_tc is + subtype UARTDataType is std_logic_vector(7 downto 0); + alias UARTSequenceType is T_SLVV_8; + constant TestData : UARTSequenceType := (x"5A", x"CA", x"FE", x"AF", x"FE", x"5A", x"CA", x"FE", x"AF", x"FE"); -- to PASSTHROUGH_ERROR_BYTE + constant TestData_replacebyte : UARTSequenceType := (x"5A", x"15", x"FE", x"15", x"FE", x"5A", x"15", x"FE", x"15", x"FE"); --to REPLACE_ERROR_BYTE + + constant parityerror : boolean_vector := (FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, TRUE, FALSE, TRUE, FALSE); + --constant TestData : UARTDataType := x"27"; + + signal TestDone : integer_barrier := 1; + signal ReadByteTrigger : bit := '0'; +begin + -- Testbench control process + ControlProc : process + constant TIMEOUT : time := 10 ms; + begin + -- Initialization of test + SetTestName("axi4lite_UART_receive_parity"); + SetLogEnable(PASSED, TRUE); --Enable PASSED Logs + SetLogEnable(INFO, TRUE); --Enable INFO Logs + + -- Wait for testbench Initialization + wait for 0 ns; + wait for 0 ns; + TranscriptOpen; + SetTranscriptMirror(TRUE); + + -- wait for design reset + wait until Reset = '0'; + ClearAlerts; + + WaitForBarrier(TestDone, TIMEOUT); + EndOfTestReports(ReportAll => TRUE, Timeout => now >= TIMEOUT); + std.env.finish; + end process ControlProc; + + -- Generate transaction for AXI manager + ManagerProc : process + constant RX_REG : AXIAddressType := 32x"00"; + constant TX_REG : AXIAddressType := 32x"04"; + constant STATUS_REG : AXIAddressType := 32x"08"; + constant CONTROL_REG : AXIAddressType := 32x"0C"; + + function toAXIData(data : UARTDataType) return AXIDataType is + begin + return 24x"00" & data; + end function; + + variable ReceivedData : AXIDataType; + + procedure CheckIsParity_flag( + signal manager : inout AddressBusRecType; + constant expected : in boolean + ) is + variable Data : AXIDataType; + variable parity_error : boolean; + begin + Read(manager, STATUS_REG, Data); + parity_error := Data(7) = '1'; + AffirmIf(parity_error = expected, "EmptyBit: Received: " & to_string(parity_error), " /= Expected: " & to_string(expected)); + end procedure; + + begin + wait until Reset = '0'; + for j in parityerror'range loop + WaitForToggle(ReadByteTrigger); + CheckIsParity_flag(AXI_Manager, parityerror(j)); + + log("Reading received data byte from UART register ..."); + Read(AXI_Manager, RX_REG, ReceivedData); + AffirmIf( + ReceivedData = toAXIData(TestData(j)), + "Received: " & to_string(ReceivedData), + " /= Expected: " & to_string(TestData) + ); + end loop; + wait for 500 us; -- this delay is added because the uart implementation in OSVVM is providing half a stop bit and due to this there will be a error. + WaitForBarrier(TestDone); + wait; + end process ManagerProc; + + -- Generate transactions for UART transmitter + UartTxProc : process + begin + wait until Reset = '0'; + + WaitForClock(UartTxRec, 1); + for i in TestData'range loop + if parityerror(i) then + Send(UartTxRec, TestData(i),UARTTB_PARITY_ERROR); + else + Send(UartTxRec, TestData(i)); + end if; + Toggle(ReadByteTrigger); + end loop; + WaitForBarrier(TestDone); + wait; + end process; + + + -- Generate transactions for UART receiver + UartRxProc : process + begin + wait until Reset = '0'; + + WaitForBarrier(TestDone); + wait; + end process; +end architecture; + + +configuration axi4lite_UART_receive_parity of axi4lite_UART_th is + for TestHarness + for TestCtrl : axi4lite_UART_tc + use entity work.axi4lite_UART_tc(receive_parity); + end for; + end for; +end configuration; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_tc.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_tc.vhdl new file mode 100644 index 000000000..e72fba7dc --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_tc.vhdl @@ -0,0 +1,74 @@ +-- ============================================================================= +-- Authors: +-- Stefan Unrein +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE ; +use IEEE.std_logic_1164.all ; +use IEEE.numeric_std.all ; + +library std; +use std.env.all; + +library PoC; +use PoC.stream.all; +use PoC.utils.all; +use PoC.vectors.all; +use PoC.physical.all; +use PoC.net.all; + +library OSVVM ; +context OSVVM.OsvvmContext ; + +-- use OSVVM.ScoreBoardPkg_slv.all; + +library osvvm_uart ; +context osvvm_uart.UartContext ; + +library osvvm_Axi4 ; +context osvvm_Axi4.Axi4LiteContext ; + +-- use work.OsvvmTestCommonPkg.all ; +-- use work.AlertLogPkg.all; +-- use work.UartTbPkg.all ; + + +entity axi4lite_UART_tc is + port ( + --Global signal Interface + -- Clock : in std_logic; + Reset : in std_logic; + + -- axi transaction record + AXI_Manager : inout AddressBusRecType ; + + -- tx transaction record + UartTxRec : inout UartRecType ; + + -- rx transaction record + UartRxRec : inout UartRecType + ); + + constant AXI_ADDR_WIDTH : integer := AXi_Manager.Address'length ; + constant AXI_DATA_WIDTH : integer := AXi_Manager.DataToModel'length ; + + subtype AXIAddressType is std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0); + subtype AXIDataType is std_logic_vector(AXI_DATA_WIDTH - 1 downto 0); + +end entity; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_th.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_th.vhdl new file mode 100644 index 000000000..eb757a4f8 --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_th.vhdl @@ -0,0 +1,186 @@ +-- ============================================================================= +-- Authors: +-- Stefan Unrein +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.AXI4Lite_OSVVM.all; +use PoC.physical.all; +use PoC.vectors.all; +use PoC.utils.all; +use PoC.axi4lite.all; +use PoC.uart.all; + +library OSVVM; +context OSVVM.OsvvmContext; + +library OSVVM_Axi4; +context OSVVM_Axi4.Axi4LiteContext; + +library OSVVM_uart; +context OSVVM_uart.UartContext; + + +entity axi4lite_UART_th is +end entity; + + +architecture TestHarness of axi4lite_UART_th is + constant CLOCK_FREQ : FREQ := 100 MHz; + constant BAUDRATE : BAUD := 115.200 kBd; + + constant AXI_ADDR_WIDTH : integer := 32; + constant AXI_DATA_WIDTH : integer := 32; + constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH / 8; + + constant tperiod_Clk : time := to_time(CLOCK_FREQ); + constant tpd : time := 0 ns; + + signal Clock : std_logic := '1'; + signal Reset : std_logic := '1'; + + -- Transaction interfaces + signal AXI_Manager : AddressBusRecType( + Address(AXI_ADDR_WIDTH - 1 downto 0), + DataToModel(AXI_DATA_WIDTH - 1 downto 0), + DataFromModel(AXI_DATA_WIDTH - 1 downto 0) + ); + signal UartTxRec : UartRecType; + signal UartRxRec : UartRecType; + + -- AXI Manager physical Interface + signal AxiBus : Axi4LiteRecType( + WriteAddress(Addr(AXI_ADDR_WIDTH - 1 downto 0)), + WriteData(Data(AXI_DATA_WIDTH - 1 downto 0), Strb(AXI_STRB_WIDTH-1 downto 0)), + ReadAddress (Addr(AXI_ADDR_WIDTH-1 downto 0)), + ReadData (Data(AXI_DATA_WIDTH-1 downto 0)) + ); + + signal UART_AXI4Lite_m2s : T_AXI4LITE_BUS_M2S( + AWAddr(AXI_ADDR_WIDTH - 1 downto 0), + WData(AXI_DATA_WIDTH - 1 downto 0), + WStrb(AXI_STRB_WIDTH-1 downto 0), + ARAddr(AXI_ADDR_WIDTH - 1 downto 0) + ); + signal UART_AXI4Lite_s2m : T_AXI4LITE_BUS_S2M( + RData(AXI_DATA_WIDTH - 1 downto 0) + ); + + -- Uart Interface + signal UART_TX : std_logic := 'H'; + signal UART_RX : std_logic := 'H'; + + component axi4lite_UART_tc + port( + Reset : in std_logic; + + AXI_Manager : inout AddressBusRecType; + + UartTxRec : inout UartRecType; + UartRxRec : inout UartRecType + ); + end component; + +begin + -- Create system clock + clk: Osvvm.ClockResetPkg.CreateClock( + Clk => Clock, + Period => tperiod_Clk + ); + + -- Create system reset + rst: Osvvm.ClockResetPkg.CreateReset ( + Reset => Reset, + ResetActive => '1', + Clk => Clock, + Period => 7 * tperiod_Clk, + tpd => tpd + ); + + -- AXI4Lite configuration manager + manager: entity OSVVM_AXI4.Axi4LiteManager + generic map ( + DEFAULT_DELAY => tpd + ) + port map ( + Clk => Clock, + nReset => not Reset, + + -- Transaction interface from TestController + TransRec => AXI_Manager, + + -- AXI manager physical interface + AxiBus => AxiBus + ); + + -- mapping between PoC and OSVVM AXI bus types + to_PoC_AXI4Lite_Bus_Master(UART_AXI4Lite_m2s, UART_AXI4Lite_s2m, AXIBus); + + dut: entity PoC.AXI4Lite_Uart + generic map ( + CLOCK_FREQ => CLOCK_FREQ, + BAUDRATE => BAUDRATE, + FLOWCONTROL => UART_FLOWCONTROL_NONE + ) + port map ( + Clock => Clock, + Reset => Reset, + + AXI4Lite_m2s => UART_AXI4Lite_m2s, + AXI4Lite_s2m => UART_AXI4Lite_s2m, + AXI4Lite_irq => open, + + UART_TX => UART_TX, + UART_RX => UART_RX, + UART_RTS => open, + UART_CTS => 'U' + ); + + rx: entity OSVVM_UART.UartRx + generic map ( + DEFAULT_BAUD => UART_BAUD_PERIOD_115200, + DEFAULT_PARITY_MODE => UARTTB_PARITY_NONE --UARTTB_PARITY_EVEN,UARTTB_PARITY_NONE,UARTTB_PARITY_ODD + ) + port map ( + TransRec => UartRxRec, + SerialDataIn => UART_TX + ); + + tx: entity OSVVM_UART.UartTx + generic map ( + DEFAULT_BAUD => UART_BAUD_PERIOD_115200, + DEFAULT_PARITY_MODE => UARTTB_PARITY_NONE + ) + port map ( + TransRec => UartTxRec, + SerialDataOut => UART_RX + ); + + TestCtrl: component axi4lite_UART_tc + port map ( + Reset => Reset, + AXI_Manager => AXI_Manager, + UartTxRec => UartTxRec, + UartRxRec => UartRxRec + ); +end architecture; diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_transmit_burst.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_transmit_burst.vhdl new file mode 100644 index 000000000..0aafeb912 --- /dev/null +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Uart/axi4lite_UART_transmit_burst.vhdl @@ -0,0 +1,184 @@ +architecture transmit_burst of axi4lite_UART_tc is + subtype UARTDataType is std_logic_vector(7 downto 0); + alias UARTSequenceType is T_SLVV_8; + + alias SB_IDType is OSVVM.ScoreBoardPkg_slv.ScoreboardIdType; + -- alias SB_NewID is OSVVM.ScoreBoardPkg_slv.NewID[string, AlertLogIDType, AlertLogReportModeType, NameSearchType, AlertLogPrintParentType return ScoreboardIDType]; + -- alias SB_Push is OSVVM.ScoreBoardPkg_slv.Push; + -- alias SB_Check is OSVVM.ScoreBoardPkg_slv.Check; + + constant TestCtrlID : AlertLogIDType := NewID("TestController"); + signal UART_transmit_SB : SB_IDType; + + constant TestData : UARTSequenceType := (x"5A", -- 1B + x"CA",x"FE",x"AF",x"FE", -- 4B + x"DE",x"AD",x"BE",x"EF",x"DE",x"AD",x"BE",x"EF", -- 8B + x"BE",x"EF",x"DE",x"AD",x"BE",x"EF",x"DE",x"AD",x"BE",x"EF",x"DE",x"AD",x"BE",x"EF",x"DE",x"AD", -- 16B + x"CA",x"BE",x"EF",x"DE",x"AD",x"BE",x"EF",x"DE",x"AD",x"BE",x"EF",x"DE",x"AD",x"BE",x"EF",x"DE",x"AD", -- 17B + x"DA",x"CA",x"BE",x"EF",x"DE",x"AD",x"BE",x"EF",x"DE",x"AD",x"BE",x"EF",x"DE",x"AD",x"BE",x"EF",x"DE",x"AD"); -- 18B + constant SequenceLengths : T_POSVEC := (1, 4, 8, 16); + + signal TestDone : integer_barrier := 1; + signal WriteDone : bit := '0'; -- barrier for triggering uart rx process + signal ReadDone : bit := '0'; -- barrier for triggering manager after uart rx process is done. + +begin + -- Testbench control process + ControlProc : process + constant TIMEOUT : time := 10 ms; + begin + -- Initialization of test + SetTestName("axi4lite_UART_transmit_burst"); + SetLogEnable(PASSED, FALSE); --Enable PASSED Logs + SetLogEnable(INFO, FALSE); --Enable INFO Logs + UART_transmit_SB <= OSVVM.ScoreBoardPkg_slv.NewID("UART_transmit_SB"); + + -- Wait for testbench Initialization + wait for 0 ns; + wait for 0 ns; + TranscriptOpen; + SetTranscriptMirror(TRUE); + + -- wait for design reset + wait until Reset = '0'; + ClearAlerts; + + WaitForBarrier(TestDone, TIMEOUT); + EndOfTestReports(ReportAll => TRUE, Timeout => now >= TIMEOUT); + std.env.finish; + wait; + end process ControlProc; + + -- Generate transaction for AXI manager + ManagerProc : process + constant ProcLogID : AlertLogIDType := NewID("ManagerProc", TestCtrlID); + variable AxiManagerLogID : AlertLogIDType; + + constant RX_REG : AXIAddressType := 32x"00"; + constant TX_REG : AXIAddressType := 32x"04"; + constant STATUS_REG : AXIAddressType := 32x"08"; + constant CONTROL_REG : AXIAddressType := 32x"0C"; + + variable result1 : boolean := true; + variable result2 : boolean := true; + variable isFull : boolean := true; + variable isEmpty : boolean := true; + + --status reg for tx + procedure StatusIsFull_TX( + signal manager : inout AddressBusRecType; + variable result : out boolean + ) is + variable Data : AXIDataType; + begin + Read(manager, STATUS_REG, Data); + result := Data(3) = '1'; + end procedure; + + procedure WaitOnNotFull( + signal manager : inout AddressBusRecType + ) is + variable isFull : boolean := true; + begin + while isFull loop + StatusIsFull_TX(manager, isFull); + end loop; + end procedure; + + procedure UARTSendBurst( + signal manager : inout AddressBusRecType; + constant data_array : in UARTSequenceType + ) is + begin + for i in data_array'range loop + WaitOnNotFull(manager); + OSVVM.ScoreBoardPkg_slv.Push(UART_transmit_SB, data_array(i)); + Write(manager, TX_REG, data_array(i)); + end loop; + end procedure; + begin + wait until Reset = '0'; + + WaitForClock(AXI_Manager, 2); + + GetAlertLogID(AXI_Manager, AxiManagerLogID); + SetLogEnable(AxiManagerLogID, INFO, False); + + for i in SequenceLengths'range loop + log(ProcLogID, "Send test sequence " & to_string(i) & " of " & to_string(SequenceLengths(i)) & " bytes by writing multiple bytes to UART TX register ..."); + UARTSendBurst(AXI_Manager, TestData(low(SequenceLengths, i) to high(SequenceLengths, i))); + + + + + -- create a barrier here to notify UART RX process + Toggle(WriteDone); + + -- read status, full should be 1 + StatusIsFull_TX(AXI_Manager, isFull); + log(ProcLogID, "TX status reg is filled: " & to_string(isFull)); + + + -- wait for barriers from RX proces + WaitForToggle(ReadDone); + + -- read status, empty should be 1 + StatusIsFull_TX(AXI_Manager, isEmpty); + log(ProcLogID, "TX status reg is empty: " & to_string(not isEmpty)); + end loop; + + -- End of Test + wait for 16 * 10 * UART_BAUD_PERIOD_115200; + -- wait; + WaitForBarrier(TestDone); + wait; + end process; + + -- Generate transactions for UART transmitter + UartTxProc : process + constant ProcLogID : AlertLogIDType := NewID("UartTxProc", TestCtrlID); + begin + wait until Reset = '0'; + + log(ProcLogID, "Transmit verification model isn't used in this testcase"); + + WaitForBarrier(TestDone); + wait; + end process; + + + -- Generate transactions for UART receiver + UartRxProc : process + constant ProcLogID : AlertLogIDType := NewID("UartRxProc", TestCtrlID); + variable ReceivedData : UARTDataType; + begin + wait until Reset = '0'; + + for i in SequenceLengths'range loop + -- barrier from manager process that all 17 bytes are written to fifo + WaitForToggle(WriteDone); + + log(ProcLogID, "Receive sequence " & to_string(i) & " ..."); + + -- Receive sequence length many bytes. + for j in 0 to SequenceLengths(i) - 1 loop + Get(UartRxRec, ReceivedData); -- Read out the data. + OSVVM.ScoreBoardPkg_slv.Check(UART_transmit_SB, ReceivedData); + end loop; + + -- send barrier to manager + Toggle(ReadDone); + end loop; + + WaitForBarrier(TestDone); + wait; + end process; +end architecture; + +configuration axi4lite_UART_transmit_burst of axi4lite_UART_th is + for TestHarness + for TestCtrl : axi4lite_UART_tc + use entity work.axi4lite_UART_tc(transmit_burst); + end for; + end for; +end configuration; diff --git a/tb/bus/axi4/AXI4Lite/RunAllTests.pro b/tb/bus/axi4/AXI4Lite/RunAllTests.pro index 3c84686d7..21b2fe63c 100644 --- a/tb/bus/axi4/AXI4Lite/RunAllTests.pro +++ b/tb/bus/axi4/AXI4Lite/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -19,8 +19,14 @@ # limitations under the License. # ============================================================================= -TestSuite PoC.bus.axi4.axi4Lite +# TestSuite PoC.bus.axi4.axi4Lite +# Deactivated to avoid failure on non-existing testcases library tb_axi4Lite +disabled ./AXI4Lite_Demux/RunAllTests.pro include ./AXI4Lite_Register/RunAllTests.pro +include ./AXI4Lite_Ocram_Adapter/RunAllTests.pro +# include ./AXI4Lite_InterruptController/RunAllTests.pro # Currently not working +include ./AXI4Lite_Uart/RunAllTests.pro +# include ./AXI4Lite_HighResolutionClock/RunAllTests.pro # Currently not working diff --git a/tb/bus/axi4/RunAllTests.pro b/tb/bus/axi4/RunAllTests.pro index 0b6fa26f5..9acadf52a 100644 --- a/tb/bus/axi4/RunAllTests.pro +++ b/tb/bus/axi4/RunAllTests.pro @@ -7,7 +7,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/common.pro b/tb/common.pro new file mode 100644 index 000000000..111ee1888 --- /dev/null +++ b/tb/common.pro @@ -0,0 +1,24 @@ +# ============================================================================= +# Authors: +# Jonas Schreiner +# +# License: +# ============================================================================= +# Copyright 2025-2026 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +library tb_common + +analyze ./OsvvmCommon.pkg.vhdl diff --git a/tb/mem/ocram/ocram_sp_tb.vhdl b/tb/mem/ocram/ocram_sp_tb.vhdl index cf9ed9797..c96b768b2 100644 --- a/tb/mem/ocram/ocram_sp_tb.vhdl +++ b/tb/mem/ocram/ocram_sp_tb.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann diff --git a/tb/misc/RunAllTests.pro b/tb/misc/RunAllTests.pro new file mode 100644 index 000000000..aae64fa91 --- /dev/null +++ b/tb/misc/RunAllTests.pro @@ -0,0 +1,28 @@ +# ============================================================================= +# Authors: +# Jonas Schreiner +# +# License: +# ============================================================================= +# Copyright 2025-2026 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +# TestSuite PoC.misc +# Deactivated to avoid failure on non-existing testcases + +library tb_misc + +#include ./gearbox/RunAllTests.pro +include ./clock/RunAllTests.pro diff --git a/tb/misc/clock/RunAllTests.pro b/tb/misc/clock/RunAllTests.pro new file mode 100644 index 000000000..896762e32 --- /dev/null +++ b/tb/misc/clock/RunAllTests.pro @@ -0,0 +1,31 @@ +# ============================================================================= +# Authors: +# Adrian Weiland +# +# License: +# ============================================================================= +# Copyright 2025-2026 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +TestSuite PoC.misc.HighResolutionClock + +library tb_HighResolutionClock + +# analyze clock_HighResolution_tb_pkg.vhdl +analyze clock_HighResolution_th.vhdl +analyze clock_HighResolution_tc.vhdl + +# Test Cases +RunTest clock_HighResolution_load.vhdl diff --git a/tb/misc/clock/clock_HighResolution_load.tcl b/tb/misc/clock/clock_HighResolution_load.tcl new file mode 100644 index 000000000..5bab90efe --- /dev/null +++ b/tb/misc/clock/clock_HighResolution_load.tcl @@ -0,0 +1,2 @@ +log /clock_HighResolution_th/* +log /clock_HighResolution_th/dut/* diff --git a/tb/misc/clock/clock_HighResolution_load.vhdl b/tb/misc/clock/clock_HighResolution_load.vhdl new file mode 100644 index 000000000..a0da9bfb9 --- /dev/null +++ b/tb/misc/clock/clock_HighResolution_load.vhdl @@ -0,0 +1,187 @@ +-- ============================================================================ +-- Author(s) +-- Adrian Weiland +-- +-- Test Case: Test functionality of the correction counter. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +architecture load of clock_HighResolution_tc is + + signal TestDone : integer_barrier := 1; + +begin + -- Testbench control process + ControlProc : process + constant TIMEOUT : time := 1100 ms; + begin + -- Initialization of test + SetTestName("clock_HighResolution_load"); + SetLogEnable(PASSED, FALSE); --Enable PASSED Logs + SetLogEnable(INFO, FALSE); --Enable INFO Logs + + -- Wait for testbench Initialization + wait for 0 ns; + wait for 0 ns; + TranscriptOpen; + SetTranscriptMirror(TRUE); + + -- wait for design reset + wait until Reset = '0'; + ClearAlerts; + + -- wait for test to finish + WaitForBarrier(TestDone, TIMEOUT); + AlertIf(now >= TIMEOUT, "Test finished due to timeout"); + --AlertIf(GetAffirmCount < 1, "Test is not Self-Checking"); + + print(""); + EndOfTestReports; + TranscriptClose; + std.env.stop; + wait; + end process ControlProc; + + -- Generate transaction for AXI manager + ManagerProc : process + + procedure LoadNanoseconds ( + signal manager : inout AddressBusRecType; + constant ns_load_value : natural; + constant waitTime : time + ) is + variable ns_value_slv : std_logic_vector(63 downto 0) := to_slv(ns_load_value, 64); + variable time_now_a : time; + variable time_now_b : time; + variable time_elapsed : time; + variable time_elapsed_nat : natural; + variable ns_elapsed : natural; + begin + Nanoseconds_to_load <= unsigned(ns_value_slv); + Load_nanoseconds <= '1'; + WaitForClock(AXI_Manager, 1); + Load_nanoseconds <= '0'; + time_now_a := now; + + wait for waitTime; + + ns_elapsed := to_integer(Nanoseconds - unsigned(ns_value_slv) + 1); -- + 1 because of WaitForClock + time_now_b := now; + time_elapsed := time_now_b - time_now_a; + time_elapsed_nat := time_elapsed / 1 ns; + AffirmIfEqual(ns_elapsed, time_elapsed_nat); + end procedure; + + procedure LoadDatetime ( + signal manager : inout AddressBusRecType; + constant s : natural; -- second + constant m : natural; -- minute + constant h : natural; -- hour + constant d : natural; -- day + constant mo : natural; -- month + constant y : natural; -- year + constant waitTime : time + ) is + variable Datetime_to_load_i : T_CLOCK_DATETIME := ( + secondsResolution => to_unsigned(0, 32), + seconds => to_unsigned(s, 6), + minutes => to_unsigned(m, 6), + hours => to_unsigned(h, 5), + day => to_unsigned(d, 5), + month => to_unsigned(mo, 4), + year => to_unsigned(y, 13) + ); + variable Datetime_read : T_CLOCK_DATETIME := (others => (others => '0')); + variable Datetime_to_load_slv : std_logic_vector(63 downto 0) := datetime_to_slv(Datetime_to_load_i); + variable time_now_a : time; + variable time_now_b : time; + begin + Datetime_to_load <= Datetime_to_load_i; + Load_datetime <= '1'; + WaitForClock(AXI_Manager, 1); + Load_datetime <= '0'; + time_now_a := now; + + wait for waitTime; + + time_now_b := now; + Datetime_read := Datetime; + + AffirmIfEqual(Datetime_read.secondsResolution, Datetime_to_load.secondsResolution); + AffirmIfEqual(Datetime_read.seconds, Datetime_to_load.seconds); + AffirmIfEqual(Datetime_read.minutes, Datetime_to_load.minutes); + AffirmIfEqual(Datetime_read.hours, Datetime_to_load.hours); + AffirmIfEqual(Datetime_read.day, Datetime_to_load.day); + AffirmIfEqual(Datetime_read.month, Datetime_to_load.month); + AffirmIfEqual(Datetime_read.year, Datetime_to_load.year); + end procedure; + + variable RV : RandomPType; + variable randTime : time := 0 ns; + type T_RandTimes is record + randNs : positive; + randT : positive; + randSec : positive; + randMin : positive; + randHour : positive; + randDay : positive; + randMonth : positive; + randYear : positive; + end record; + variable RandTimes : T_RandTimes := (others => 1); + + begin + RV.InitSeed(RV'instance_name); + + Load_nanoseconds <= '0'; + Load_datetime <= '0'; + wait until Reset = '0'; + WaitForClock(AXI_Manager, 2); + + log("Checking nanosecond load"); + for i in 0 to 5 loop + randTime := RV.RandTime(1 ns, 500 ns); -- in ns + RandTimes.randNs := RV.RandInt(1, 999); + LoadNanoseconds(AXI_Manager, RandTimes.randNs, randTime); + + RandTimes.randT := RV.RandInt(1, 1000); + RandTimes.randSec := RV.RandInt(1, 59); + RandTimes.randMin := RV.RandInt(1, 59); + RandTimes.randHour := RV.RandInt(1, 24); + RandTimes.randDay := RV.RandInt(1, 12); + RandTimes.randMonth := RV.RandInt(1, 12); + RandTimes.randYear := RV.RandInt(2000, 4000); + LoadDatetime(AXI_Manager, RandTimes.randT, RandTimes.randSec, RandTimes.randMin, RandTimes.randHour, RandTimes.randDay, RandTimes.randYear, randTime); + end loop; + -- todo: check for changes in datetime + + wait for 1 ms; + WaitForClock(AXI_Manager); + WaitForBarrier(TestDone); + wait; + end process; + +end architecture; + +configuration clock_HighResolution_load of clock_HighResolution_th is + for TestHarness + for TestCtrl : clock_HighResolution_tc + use entity work.clock_HighResolution_tc(load); + end for; + end for; +end configuration; diff --git a/tb/misc/clock/clock_HighResolution_tc.vhdl b/tb/misc/clock/clock_HighResolution_tc.vhdl new file mode 100644 index 000000000..c9fec0d7a --- /dev/null +++ b/tb/misc/clock/clock_HighResolution_tc.vhdl @@ -0,0 +1,58 @@ +-- ============================================================================= +-- Authors: +-- Adrian Weiland +-- +-- Entity: Test controller. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.utils.all; +use PoC.physical.all; +use PoC.math.all; +use PoC.clock.all; + +library OSVVM; +context OSVVM.OsvvmContext; + +library osvvm_Axi4; +context osvvm_Axi4.Axi4LiteContext; + + +entity clock_HighResolution_tc is + generic ( + CLOCK_FREQ : FREQ + ); + port ( + Clock : in std_logic; + Reset : in std_logic; + AXI_Manager : inout AddressBusRecType; + + Load_nanoseconds : out std_logic; + Load_datetime : out std_logic; + Nanoseconds_to_load : out unsigned(63 downto 0); + Datetime_to_load : out T_CLOCK_Datetime; + + Nanoseconds : in unsigned(63 downto 0); + Datetime : in T_CLOCK_Datetime + ); +end entity; diff --git a/tb/misc/clock/clock_HighResolution_th.vhdl b/tb/misc/clock/clock_HighResolution_th.vhdl new file mode 100644 index 000000000..eaad1b7da --- /dev/null +++ b/tb/misc/clock/clock_HighResolution_th.vhdl @@ -0,0 +1,193 @@ +-- ============================================================================= +-- Authors: +-- Adrian Weiland +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2026 The PoC-Library Authors +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.AXI4Lite_OSVVM.all; +use PoC.physical.all; +use PoC.vectors.all; +use PoC.axi4lite.all; +use PoC.uart.all; +use PoC.clock.all; + +library OSVVM; +context OSVVM.OsvvmContext; + +library OSVVM_Axi4; +context OSVVM_Axi4.Axi4LiteContext; + + +entity clock_HighResolution_th is +end entity; + + +architecture TestHarness of clock_HighResolution_th is + + constant AXI_ADDR_WIDTH : integer := 32; + constant AXI_DATA_WIDTH : integer := 32; + constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH / 8; + + -- DUT + constant SECOND_RESOLUTION : T_SECOND_RESOLUTION := MILLISECONDS; + constant CLOCK_FREQ : FREQ := 1000 MHz; + + signal Load_nanoseconds : std_logic := '0'; + signal Load_datetime : std_logic := '0'; + signal Nanoseconds_to_load : unsigned(63 downto 0) := (others => '0'); + signal Datetime_to_load : T_CLOCK_Datetime := (others => (others => '0')); + signal Ns_inc : std_logic := '0'; + signal Ns_dec : std_logic := '0'; + signal Nanoseconds : unsigned(63 downto 0) := (others => '0'); + signal Nanoseconds_i : unsigned(63 downto 0) := (others => '0'); + signal Datetime : T_CLOCK_Datetime := (others => (others => '0')); + signal Datetime_i : T_CLOCK_Datetime := (others => (others => '0')); + + -- Clock, reset generation + signal Clock : std_logic := '1'; + signal Reset : std_logic := '1'; + + constant tperiod_Clk : time := to_time(CLOCK_FREQ); + constant tpd : time := 0 ns; + + signal AXI_m2s : T_AXI4Lite_BUS_M2S( + AWAddr(AXI_ADDR_WIDTH - 1 downto 0), + WData(AXI_DATA_WIDTH - 1 downto 0), + WStrb(AXI_STRB_WIDTH-1 downto 0), + ARAddr(AXI_ADDR_WIDTH - 1 downto 0) + ); + signal AXI_s2m : T_AXI4Lite_BUS_S2M( + RData(AXI_DATA_WIDTH - 1 downto 0) + ); + + -- Transaction interfaces + signal AXI_Manager : AddressBusRecType( + Address (AXI_ADDR_WIDTH - 1 downto 0), + DataToModel (AXI_DATA_WIDTH - 1 downto 0), + DataFromModel(AXI_DATA_WIDTH - 1 downto 0) + ); + + -- AXI Manager physical Interface + signal AxiBus : Axi4LiteRecType( + WriteAddress(Addr(AXI_ADDR_WIDTH - 1 downto 0)), + WriteData (Data(AXI_DATA_WIDTH - 1 downto 0), Strb(AXI_STRB_WIDTH - 1 downto 0)), + ReadAddress (Addr(AXI_ADDR_WIDTH - 1 downto 0)), + ReadData (Data(AXI_DATA_WIDTH - 1 downto 0)) + ); + + component clock_HighResolution_tc + generic ( + CLOCK_FREQ : FREQ + ); + port ( + Clock : in std_logic; + Reset : in std_logic; + AXI_Manager : inout AddressBusRecType; + + Load_nanoseconds : out std_logic; + Load_datetime : out std_logic; + Nanoseconds_to_load : out unsigned(63 downto 0); + Datetime_to_load : out T_CLOCK_Datetime; + + Nanoseconds : in unsigned(63 downto 0); + Datetime : in T_CLOCK_Datetime + ); + end component; + +begin + -- Create system clock + clk: Osvvm.ClockResetPkg.CreateClock( + Clk => Clock, + Period => tperiod_Clk + ); + + -- Create system reset + rst: Osvvm.ClockResetPkg.CreateReset ( + Reset => Reset, + ResetActive => '1', + Clk => Clock, + Period => 7 * tperiod_Clk, + tpd => tpd + ); + + -- AXI4Lite configuration manager + manager: entity OSVVM_AXI4.Axi4LiteManager + generic map ( + tperiod_Clk => tperiod_Clk, + DEFAULT_DELAY => tpd + ) + port map ( + Clk => Clock, + nReset => not Reset, + + -- Transaction interface from TestController + TransRec => AXI_Manager, + + -- AXI manager physical interface + AxiBus => AxiBus + ); + + dut: entity PoC.clock_HighResolution + generic map ( + SECOND_RESOLUTION => SECOND_RESOLUTION, + CLOCK_FREQUENCY => 1000 MHz + ) + port map ( + Clock => Clock, + Reset => Reset, + + Load_nanoseconds => Load_nanoseconds, + Load_datetime => Load_datetime, + Nanoseconds_to_load => Nanoseconds_to_load, + Datetime_to_load => Datetime_to_load, + Ns_inc => Ns_inc, + Ns_dec => Ns_dec, + + Nanoseconds => Nanoseconds_i, + Datetime => Datetime_i + ); + + Nanoseconds <= Nanoseconds_i when rising_edge(Clock); + Datetime <= Datetime_i when rising_edge(Clock); + + TestCtrl: component clock_HighResolution_tc + generic map ( + CLOCK_FREQ => CLOCK_FREQ + ) + port map ( + Clock => Clock, + Reset => Reset, + AXI_Manager => AXI_Manager, + + Load_nanoseconds => Load_nanoseconds, + Load_datetime => Load_datetime, + Nanoseconds_to_load => Nanoseconds_to_load, + Datetime_to_load => Datetime_to_load, + + Nanoseconds => Nanoseconds, + Datetime => Datetime + ); + +end architecture; diff --git a/tb/sim/sim_VCDParser_tb.vhdl b/tb/sim/sim_VCDParser_tb.vhdl index c15a71d0d..ac4e18e35 100644 --- a/tb/sim/sim_VCDParser_tb.vhdl +++ b/tb/sim/sim_VCDParser_tb.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- diff --git a/tb/sync/Bits/RunAllTests.pro b/tb/sync/Bits/RunAllTests.pro index d52c7f2bd..fa8746609 100644 --- a/tb/sync/Bits/RunAllTests.pro +++ b/tb/sync/Bits/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/sync/Bits/sync_Bits_Simple.vhdl b/tb/sync/Bits/sync_Bits_Simple.vhdl index b4ff77817..ebab1e964 100644 --- a/tb/sync/Bits/sync_Bits_Simple.vhdl +++ b/tb/sync/Bits/sync_Bits_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/sync/Bits/sync_Bits_TestController.vhdl b/tb/sync/Bits/sync_Bits_TestController.vhdl index 40f92b9c8..61e973cc2 100644 --- a/tb/sync/Bits/sync_Bits_TestController.vhdl +++ b/tb/sync/Bits/sync_Bits_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/sync/Bits/sync_Bits_TestHarness.vhdl b/tb/sync/Bits/sync_Bits_TestHarness.vhdl index b01334976..f81d54072 100644 --- a/tb/sync/Bits/sync_Bits_TestHarness.vhdl +++ b/tb/sync/Bits/sync_Bits_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/sync/Command/RunAllTests.pro b/tb/sync/Command/RunAllTests.pro index d16eb699b..94ecb982c 100644 --- a/tb/sync/Command/RunAllTests.pro +++ b/tb/sync/Command/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/sync/Command/sync_Command_Simple.vhdl b/tb/sync/Command/sync_Command_Simple.vhdl index ada247783..ccec64b8f 100644 --- a/tb/sync/Command/sync_Command_Simple.vhdl +++ b/tb/sync/Command/sync_Command_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/sync/Command/sync_Command_TestController.vhdl b/tb/sync/Command/sync_Command_TestController.vhdl index 0950d4133..97065ec2d 100644 --- a/tb/sync/Command/sync_Command_TestController.vhdl +++ b/tb/sync/Command/sync_Command_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/sync/Command/sync_Command_TestHarness.vhdl b/tb/sync/Command/sync_Command_TestHarness.vhdl index 3f4e677a8..8609327f7 100644 --- a/tb/sync/Command/sync_Command_TestHarness.vhdl +++ b/tb/sync/Command/sync_Command_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/sync/Reset/RunAllTests.pro b/tb/sync/Reset/RunAllTests.pro index 708ab45bb..6c98c2eff 100644 --- a/tb/sync/Reset/RunAllTests.pro +++ b/tb/sync/Reset/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/sync/Reset/sync_Reset_Simple.vhdl b/tb/sync/Reset/sync_Reset_Simple.vhdl index 629a00da4..5602f31a6 100644 --- a/tb/sync/Reset/sync_Reset_Simple.vhdl +++ b/tb/sync/Reset/sync_Reset_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/sync/Reset/sync_Reset_TestController.vhdl b/tb/sync/Reset/sync_Reset_TestController.vhdl index 16ed843b5..4b08393ac 100644 --- a/tb/sync/Reset/sync_Reset_TestController.vhdl +++ b/tb/sync/Reset/sync_Reset_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/sync/Reset/sync_Reset_TestHarness.vhdl b/tb/sync/Reset/sync_Reset_TestHarness.vhdl index 1076ca162..270b475d7 100644 --- a/tb/sync/Reset/sync_Reset_TestHarness.vhdl +++ b/tb/sync/Reset/sync_Reset_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/sync/RunAllTests.pro b/tb/sync/RunAllTests.pro index b1a978deb..337dd05b1 100644 --- a/tb/sync/RunAllTests.pro +++ b/tb/sync/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/sync/Strobe/RunAllTests.pro b/tb/sync/Strobe/RunAllTests.pro index ef9fafd49..adfeeebc0 100644 --- a/tb/sync/Strobe/RunAllTests.pro +++ b/tb/sync/Strobe/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/sync/Strobe/sync_Strobe_Simple.vhdl b/tb/sync/Strobe/sync_Strobe_Simple.vhdl index 38992996f..daebb36ac 100644 --- a/tb/sync/Strobe/sync_Strobe_Simple.vhdl +++ b/tb/sync/Strobe/sync_Strobe_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/sync/Strobe/sync_Strobe_TestController.vhdl b/tb/sync/Strobe/sync_Strobe_TestController.vhdl index 41fcafce7..cd0583672 100644 --- a/tb/sync/Strobe/sync_Strobe_TestController.vhdl +++ b/tb/sync/Strobe/sync_Strobe_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/sync/Strobe/sync_Strobe_TestHarness.vhdl b/tb/sync/Strobe/sync_Strobe_TestHarness.vhdl index 09aee584a..6e60a693e 100644 --- a/tb/sync/Strobe/sync_Strobe_TestHarness.vhdl +++ b/tb/sync/Strobe/sync_Strobe_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/sync/Vector/RunAllTests.pro b/tb/sync/Vector/RunAllTests.pro index e89409187..cbe35032a 100644 --- a/tb/sync/Vector/RunAllTests.pro +++ b/tb/sync/Vector/RunAllTests.pro @@ -4,7 +4,7 @@ # # License: # ============================================================================= -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/tb/sync/Vector/sync_Vector_Simple.vhdl b/tb/sync/Vector/sync_Vector_Simple.vhdl index cdc66c050..e39aaf375 100644 --- a/tb/sync/Vector/sync_Vector_Simple.vhdl +++ b/tb/sync/Vector/sync_Vector_Simple.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -14,7 +11,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/sync/Vector/sync_Vector_TestController.vhdl b/tb/sync/Vector/sync_Vector_TestController.vhdl index 04637031e..aaa6723d5 100644 --- a/tb/sync/Vector/sync_Vector_TestController.vhdl +++ b/tb/sync/Vector/sync_Vector_TestController.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Gustavo Martin @@ -13,7 +10,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- diff --git a/tb/sync/Vector/sync_Vector_TestHarness.vhdl b/tb/sync/Vector/sync_Vector_TestHarness.vhdl index 5f58076bf..b4b7fa481 100644 --- a/tb/sync/Vector/sync_Vector_TestHarness.vhdl +++ b/tb/sync/Vector/sync_Vector_TestHarness.vhdl @@ -1,6 +1,3 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Gustavo Martin -- @@ -12,7 +9,7 @@ -- -- License: -- ============================================================================= --- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2025-2026 The PoC-Library Authors -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/temp/README.md b/temp/README.md index 8c1c5fcac..6e67128c1 100644 --- a/temp/README.md +++ b/temp/README.md @@ -1,5 +1,5 @@ # Temporary directory This folder and its sub-folders are used by several external tools as working -directories. All sub-folders can be removed to cleanup intermediat steps or to +directories. All sub-folders can be removed to clean-up intermediate steps or to free disk space. diff --git a/tools/git/preSynth_GitVersionRegister_Vivado.tcl b/tools/git/preSynth_GitVersionRegister_Vivado.tcl index aded16ea3..a5ece410c 100644 --- a/tools/git/preSynth_GitVersionRegister_Vivado.tcl +++ b/tools/git/preSynth_GitVersionRegister_Vivado.tcl @@ -18,7 +18,7 @@ ## ## License: ## ============================================================================= -## Copyright 2025-2025 The PoC-Library Authors +## Copyright 2025-2026 The PoC-Library Authors ## ## Licensed under the Apache License, Version 2.0 (the "License"); ## you may not use this file except in compliance with the License. diff --git a/tools/precompile/compile-altera.sh b/tools/precompile/compile-altera.sh index 9007a544a..c28ca590a 100755 --- a/tools/precompile/compile-altera.sh +++ b/tools/precompile/compile-altera.sh @@ -16,7 +16,7 @@ # # License: # ============================================================================== -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # Copyright 2007-2016 Technische Universität Dresden - Germany # Chair of VLSI-Design, Diagnostics and Architecture # diff --git a/tools/precompile/compile-lattice.sh b/tools/precompile/compile-lattice.sh index 5fce48c37..84c6a4e9d 100755 --- a/tools/precompile/compile-lattice.sh +++ b/tools/precompile/compile-lattice.sh @@ -17,7 +17,7 @@ # # License: # ============================================================================== -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # Copyright 2007-2016 Technische Universität Dresden - Germany # Chair of VLSI-Design, Diagnostics and Architecture # diff --git a/tools/precompile/compile-osvvm.sh b/tools/precompile/compile-osvvm.sh index d20e555d3..e28c2e373 100755 --- a/tools/precompile/compile-osvvm.sh +++ b/tools/precompile/compile-osvvm.sh @@ -17,7 +17,7 @@ # # License: # ============================================================================== -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # Copyright 2007-2016 Technische Universität Dresden - Germany # Chair of VLSI-Design, Diagnostics and Architecture # diff --git a/tools/precompile/compile-xilinx-vivado.sh b/tools/precompile/compile-xilinx-vivado.sh index b3c943cda..b9a24733b 100755 --- a/tools/precompile/compile-xilinx-vivado.sh +++ b/tools/precompile/compile-xilinx-vivado.sh @@ -17,7 +17,7 @@ # # License: # ============================================================================== -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # Copyright 2007-2016 Technische Universität Dresden - Germany # Chair of VLSI-Design, Diagnostics and Architecture # diff --git a/tools/precompile/precompile.sh b/tools/precompile/precompile.sh index b6525c16b..08113f542 100644 --- a/tools/precompile/precompile.sh +++ b/tools/precompile/precompile.sh @@ -14,7 +14,7 @@ # # License: # ============================================================================== -# Copyright 2025-2025 The PoC-Library Authors +# Copyright 2025-2026 The PoC-Library Authors # Copyright 2007-2016 Technische Universität Dresden - Germany # Chair of VLSI-Design, Diagnostics and Architecture # diff --git a/ucf/sync/sync_Reset.xdc b/ucf/sync/sync_Reset.xdc new file mode 100644 index 000000000..e2aef575b --- /dev/null +++ b/ucf/sync/sync_Reset.xdc @@ -0,0 +1,11 @@ +# This XDC file must be directly applied to all instances of sync_Reset. +# To achieve this, set property SCOPED_TO_REF to sync_Reset within the Vivado project. +# Load XDC file defining the clocks before this XDC file by using the property PROCESSING_ORDER. +set_property ASYNC_REG true [ get_cells {Data_meta_reg} ] +set_property ASYNC_REG true [ get_cells {Data_sync_reg[0]} ] + +set_max_delay -to [ get_pins {Data_meta_reg/D} ] -datapath_only [ get_property PERIOD [ get_clocks -of_objects [ get_pins {Data_meta_reg/C} ] ] ] +set_false_path -hold -to [ get_pins {Data_meta_reg/D} ] + +set_false_path -to [ get_pins {Data_meta_reg/PRE} ] +set_false_path -to [ get_pins {Data_sync_reg*/PRE} ] diff --git a/ucf/sync/sync_Reset_Xilinx.xdc b/ucf/sync/sync_Reset_Xilinx.xdc index 816967e38..4680b14a5 100644 --- a/ucf/sync/sync_Reset_Xilinx.xdc +++ b/ucf/sync/sync_Reset_Xilinx.xdc @@ -1,6 +1,11 @@ # This XDC file must be directly applied to all instances of sync_Reset_Xilinx. # To achieve this, set property SCOPED_TO_REF to sync_Reset_Xilinx within the Vivado project. # Load XDC file defining the clocks before this XDC file by using the property PROCESSING_ORDER. -set_property ASYNC_REG true [get_cells {FF2_METASTABILITY_FFS FF3_METASTABILITY_FFS}] -set_false_path -from [all_clocks] -to [get_pins FF2_METASTABILITY_FFS/PRE] -set_false_path -from [all_clocks] -to [get_pins FF3_METASTABILITY_FFS/PRE] + +set_property ASYNC_REG true [ get_cells {FF2_METASTABILITY_FFS} ] +set_property ASYNC_REG true [ get_cells {FF3_METASTABILITY_FFS} ] + +set_max_delay -from [all_clocks] -to [ get_pins {FF2_METASTABILITY_FFS/D} ] -datapath_only [ get_property PERIOD [ get_clocks -of_objects [ get_pins {FF2_METASTABILITY_FFS/C} ] ] ] + +set_false_path -to [ get_pins {FF2_METASTABILITY_FFS/PRE} ] +set_false_path -to [ get_pins {FF3_METASTABILITY_FFS/PRE} ] diff --git a/ucf/sync/sync_Vector.xdc b/ucf/sync/sync_Vector.xdc index 5d61b91e7..369f89fae 100644 --- a/ucf/sync/sync_Vector.xdc +++ b/ucf/sync/sync_Vector.xdc @@ -6,4 +6,4 @@ # set max delay between data register D0 and D4 to lower clock period set_max_delay -from [get_cells -regexp {D0_reg\[\d+\]}] \ -to [get_cells -regexp {D4_reg\[\d+\]}] \ - -datapath_only [expr "min([get_property period [get_clocks -of_objects [get_pins {D0_reg[0]/C}]]], [get_property period [get_clocks -of_objects [get_pins {D4_reg[0]/C}]]])"] + -datapath_only [expr "min([get_property period [get_clocks -of_objects [get_pins {D0_reg[*]/C}]]], [get_property period [get_clocks -of_objects [get_pins {D4_reg[*]/C}]]])"] diff --git a/vhdl_coding.md b/vhdl_coding.md index 352ee772c..c88dadca8 100644 --- a/vhdl_coding.md +++ b/vhdl_coding.md @@ -16,6 +16,16 @@ this license. package, to which `_tb` is appended. Its implementing architecture is named `tb`. +## Conventions for OSVVM Testbenches + +1. An OSVVM testbench generally consists of three parts: the Test Harness, +Test Controller and one or more Test Cases. +2. All three parts shall be in one subdirectory which shall be named after the DUT. +For example, the testbench files for the `arith_addw` shall be in the directory `tb/arith/addw`. +3. The Test Controller's and Test Harness' names shall be prefixed with the DUT's name, e.g. +`addw_TestController.vhdl` and `addw_TestHarness.vhdl`. +4. All testcases shall have the prefix `TC_` followed by a meaningfull name. + ## Formatting ### Header @@ -49,7 +59,7 @@ this license. -- limitations under the License. -- =========================================================================== ``` - + ### Whitespace * Indent with one tab character per indentation level. * Assume a tab width of two spaces. diff --git a/xst/README.md b/xst/README.md deleted file mode 100644 index 7ed2cd983..000000000 --- a/xst/README.md +++ /dev/null @@ -1,3 +0,0 @@ -# Files required by Xilinx XST - -*No documentation available.* \ No newline at end of file diff --git a/xst/Series-7.xst b/xst/Series-7.xst deleted file mode 100644 index 2c0e79d05..000000000 --- a/xst/Series-7.xst +++ /dev/null @@ -1,55 +0,0 @@ -set -xsthdpdir "xst" -run --ifn {prjFile} --use_new_parser {UseNewParser} --ifmt {InputFormat} --ofn {OutputName} --ofmt {OutputFormat} --p {Part} --top {TopModuleName} --opt_mode {OptimizationMode} --opt_level {OptimizationLevel} --power {PowerReduction} --iuc {IgnoreSynthesisConstraintsFile} --uc {SynthesisConstraintsFile} --keep_hierarchy {KeepHierarchy} --netlist_hierarchy {NetListHierarchy} --rtlview {GenerateRTLView} --glob_opt {GlobalOptimization} --read_cores {ReadCores} --sd {SearchDirectories} --write_timing_constraints {WriteTimingConstraints} --cross_clock_analysis {CrossClockAnalysis} --hierarchy_separator {HierarchySeparator} --bus_delimiter {BusDelimiter} --case {Case} --slice_utilization_ratio {SliceUtilizationRatio} --bram_utilization_ratio {BRAMUtilizationRatio} --dsp_utilization_ratio {DSPUtilizationRatio} --lc {LUTCombining} --reduce_control_sets {ReduceControlSets} --fsm_extract {FSMExtract} --fsm_encoding {FSMEncoding} --safe_implementation {FSMSafeImplementation} --fsm_style {FSMStyle} --ram_extract {RAMExtract} --ram_style {RAMStyle} --rom_extract {ROMExtract} --shreg_extract {ShRegExtract} --rom_style {ROMStyle} --auto_bram_packing {AutoBRAMPacking} --resource_sharing {ResourceSharing} --async_to_sync {ASyncToSync} --use_dsp48 {UseDSP48} --iobuf {IOBuf} --max_fanout {MaxFanOut} --bufg {BufG} --register_duplication {RegisterDuplication} --register_balancing {RegisterBalancing} --optimize_primitives {OptimizePrimitives} --use_clock_enable {UseClockEnable} --use_sync_set {UseSyncSet} --use_sync_reset {UseSyncReset} --iob {PackIORegistersIntoIOBs} --equivalent_register_removal {EquivalentRegisterRemoval} --slice_utilization_ratio_maxmargin {SliceUtilizationRatioMaxMargin} diff --git a/xst/Spartan-3.xst b/xst/Spartan-3.xst deleted file mode 100644 index be56374a6..000000000 --- a/xst/Spartan-3.xst +++ /dev/null @@ -1,58 +0,0 @@ -set -xsthdpdir "xst" -run --ifn {prjFile} --use_new_parser {UseNewParser} --ifmt {InputFormat} --ofn {OutputName} --ofmt {OutputFormat} --p {Part} --top {TopModuleName} --opt_mode {OptimizationMode} --opt_level {OptimizationLevel} --iuc {IgnoreSynthesisConstraintsFile} --uc {SynthesisConstraintsFile} --keep_hierarchy {KeepHierarchy} --netlist_hierarchy {NetListHierarchy} --rtlview {GenerateRTLView} --glob_opt {GlobalOptimization} --read_cores {ReadCores} --sd {SearchDirectories} --write_timing_constraints {WriteTimingConstraints} --cross_clock_analysis {CrossClockAnalysis} --hierarchy_separator {HierarchySeparator} --bus_delimiter {BusDelimiter} --case {Case} --slice_utilization_ratio {SliceUtilizationRatio} --bram_utilization_ratio {BRAMUtilizationRatio} --verilog2001 {Verilog2001} --fsm_extract {FSMExtract} --fsm_encoding {FSMEncoding} --safe_implementation {FSMSafeImplementation} --fsm_style {FSMStyle} --ram_extract {RAMExtract} --ram_style {RAMStyle} --rom_extract {ROMExtract} --mux_style {MUXStyle} --decoder_extract {DecoderExtract} --priority_extract {PriorityExtract} --shreg_extract {ShRegExtract} --shift_extract {ShiftExtract} --xor_collapse {XorCollapse} --rom_style {ROMStyle} --auto_bram_packing {AutoBRAMPacking} --mux_extract {MUXExtract} --resource_sharing {ResourceSharing} --async_to_sync {ASyncToSync} --iobuf {IOBuf} --max_fanout {MaxFanOut} --bufg {BufG} --register_duplication {RegisterDuplication} --register_balancing {RegisterBalancing} --slice_packing {SlicePacking} --optimize_primitives {OptimizePrimitives} --use_clock_enable {UseClockEnable} --use_sync_set {UseSyncSet} --use_sync_reset {UseSyncReset} --iob {PackIORegistersIntoIOBs} --equivalent_register_removal {EquivalentRegisterRemoval} --slice_utilization_ratio_maxmargin {SliceUtilizationRatioMaxMargin} diff --git a/xst/Spartan-6.xst b/xst/Spartan-6.xst deleted file mode 100644 index 2c0e79d05..000000000 --- a/xst/Spartan-6.xst +++ /dev/null @@ -1,55 +0,0 @@ -set -xsthdpdir "xst" -run --ifn {prjFile} --use_new_parser {UseNewParser} --ifmt {InputFormat} --ofn {OutputName} --ofmt {OutputFormat} --p {Part} --top {TopModuleName} --opt_mode {OptimizationMode} --opt_level {OptimizationLevel} --power {PowerReduction} --iuc {IgnoreSynthesisConstraintsFile} --uc {SynthesisConstraintsFile} --keep_hierarchy {KeepHierarchy} --netlist_hierarchy {NetListHierarchy} --rtlview {GenerateRTLView} --glob_opt {GlobalOptimization} --read_cores {ReadCores} --sd {SearchDirectories} --write_timing_constraints {WriteTimingConstraints} --cross_clock_analysis {CrossClockAnalysis} --hierarchy_separator {HierarchySeparator} --bus_delimiter {BusDelimiter} --case {Case} --slice_utilization_ratio {SliceUtilizationRatio} --bram_utilization_ratio {BRAMUtilizationRatio} --dsp_utilization_ratio {DSPUtilizationRatio} --lc {LUTCombining} --reduce_control_sets {ReduceControlSets} --fsm_extract {FSMExtract} --fsm_encoding {FSMEncoding} --safe_implementation {FSMSafeImplementation} --fsm_style {FSMStyle} --ram_extract {RAMExtract} --ram_style {RAMStyle} --rom_extract {ROMExtract} --shreg_extract {ShRegExtract} --rom_style {ROMStyle} --auto_bram_packing {AutoBRAMPacking} --resource_sharing {ResourceSharing} --async_to_sync {ASyncToSync} --use_dsp48 {UseDSP48} --iobuf {IOBuf} --max_fanout {MaxFanOut} --bufg {BufG} --register_duplication {RegisterDuplication} --register_balancing {RegisterBalancing} --optimize_primitives {OptimizePrimitives} --use_clock_enable {UseClockEnable} --use_sync_set {UseSyncSet} --use_sync_reset {UseSyncReset} --iob {PackIORegistersIntoIOBs} --equivalent_register_removal {EquivalentRegisterRemoval} --slice_utilization_ratio_maxmargin {SliceUtilizationRatioMaxMargin} diff --git a/xst/default.filter b/xst/default.filter deleted file mode 100644 index e69de29bb..000000000 diff --git a/xst/empty.xcf b/xst/empty.xcf deleted file mode 100644 index e69de29bb..000000000 diff --git a/xst/xil/mig/mig_Atlys_1x128.rules b/xst/xil/mig/mig_Atlys_1x128.rules deleted file mode 100644 index 4a5248314..000000000 --- a/xst/xil/mig/mig_Atlys_1x128.rules +++ /dev/null @@ -1,36 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -PreProcessRules - # Empty -End PreProcessRules - -PostProcessRules - # copy output files into netlist directory - Copy "${SPECIAL:OutputDir}/${TopLevel}.ngc" To "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ngc" - Copy "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}_top.vhd" To "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl" - - # patch top-level according to the generic values used while synthesis - File "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl" - Replace "(architecture arc of ${TopLevel} is).*(end arc;)" With "\\1\\nbegin\\n\\2" Options DotAll - Replace "generic.*port" With "port" Options DotAll - Replace "C3_NUM_DQ_PINS" With "16" - Replace "C3_MEM_ADDR_WIDTH" With "13" - Replace "C3_MEM_BANKADDR_WIDTH" With "3" - Replace "C3_P0_MASK_SIZE" With "16" - Replace "C3_P0_DATA_PORT_SIZE" With "128" - End File - - # delete intermediate files from CoreGen step - Delete "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/iodrp_controller.vhd" - Delete "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/iodrp_mcb_controller.vhd" - Delete "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/mcb_raw_wrapper.vhd" - Delete "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/mcb_soft_calibration_top.vhd" - Delete "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/mcb_soft_calibration.vhd" - Delete "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/memc3_infrastructure.vhd" - Delete "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/memc3_wrapper.vhd" - Delete "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}_top.vhd" -End PostProcessRules diff --git a/xst/xil/mig/mig_Atlys_1x128.xcf b/xst/xil/mig/mig_Atlys_1x128.xcf deleted file mode 100644 index 758c600c5..000000000 --- a/xst/xil/mig/mig_Atlys_1x128.xcf +++ /dev/null @@ -1,3 +0,0 @@ - -NET "c3_sys_clk" TNM_NET = "NET_mig_Atlys_1x128_c3_sys_clk"; -TIMESPEC "TS_mig_Atlys_1x128_c3_sys_clk" = PERIOD "NET_mig_Atlys_1x128_c3_sys_clk" 100 MHz HIGH 50 %; ## 100 MHz board clock (50%/50% duty-cycle) diff --git a/xst/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rules b/xst/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rules deleted file mode 100644 index f80461719..000000000 --- a/xst/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rules +++ /dev/null @@ -1,88 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Notes: -# - all files are relative to PoCRoot directory -# - ${section:option} expressions refer to the section, wherein this rule file was referenced -# -# Section [XST.xil.mig.KC705_MT8JTF12864HZ_1G6.nl] defines `netlistDir` -# -PreProcessRules - # Empty -End PreProcessRules - -PostProcessRules - Copy "${SPECIAL:OutputDir}/${TopLevel}.ngc" To "${netlistDir}/${TopLevel}.ngc" - Copy "${netlistDir}/${TopLevel}_top.vhd" To "${netlistDir}/${TopLevel}.vhdl" - - File "${netlistDir}/${TopLevel}.vhdl" - Replace "(architecture arch_mig.* of ${TopLevel} is).*(end architecture arch_mig.*;)" With "\\1\\nbegin\\n\\2" Options DotAll - Replace "generic.*port\\s+\\(" With "port (" Options DotAll - Replace "DQ_WIDTH" With "64" - Replace "DQS_WIDTH" With "8" - Replace "ROW_WIDTH" With "14" - Replace "BANK_WIDTH" With "3" - Replace "CK_WIDTH" With "1" - Replace "CKE_WIDTH" With "1" - Replace "CS_WIDTH" With "1" - Replace "nCS_PER_RANK" With "1" - Replace "DM_WIDTH" With "8" - Replace "ODT_WIDTH" With "1" - Replace "ADDR_WIDTH" With "28" - Replace "nCK_PER_CLK" With "4" - Replace "PAYLOAD_WIDTH" With "64" - End File - - Delete "${netlistDir}/mig_7series_v1_9_ecc_buf.v" - Delete "${netlistDir}/mig_7series_v1_9_ecc_gen.v" - Delete "${netlistDir}/mig_7series_v1_9_ecc_merge_enc.v" - Delete "${netlistDir}/mig_7series_v1_9_ecc_dec_fix.v" - Delete "${netlistDir}/mig_7series_v1_9_tempmon.v" - Delete "${netlistDir}/mig_7series_v1_9_clk_ibuf.v" - Delete "${netlistDir}/mig_7series_v1_9_iodelay_ctrl.v" - Delete "${netlistDir}/mig_7series_v1_9_infrastructure.v" - Delete "${netlistDir}/mig_7series_v1_9_bank_queue.v" - Delete "${netlistDir}/mig_7series_v1_9_bank_compare.v" - Delete "${netlistDir}/mig_7series_v1_9_arb_select.v" - Delete "${netlistDir}/mig_7series_v1_9_arb_mux.v" - Delete "${netlistDir}/mig_7series_v1_9_col_mach.v" - Delete "${netlistDir}/mig_7series_v1_9_bank_common.v" - Delete "${netlistDir}/mig_7series_v1_9_bank_state.v" - Delete "${netlistDir}/mig_7series_v1_9_mc.v" - Delete "${netlistDir}/mig_7series_v1_9_bank_cntrl.v" - Delete "${netlistDir}/mig_7series_v1_9_rank_cntrl.v" - Delete "${netlistDir}/mig_7series_v1_9_bank_mach.v" - Delete "${netlistDir}/mig_7series_v1_9_rank_mach.v" - Delete "${netlistDir}/mig_7series_v1_9_arb_row_col.v" - Delete "${netlistDir}/mig_7series_v1_9_rank_common.v" - Delete "${netlistDir}/mig_7series_v1_9_round_robin_arb.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_wrlvl.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_init.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_dqs_found_cal_hr.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_mc_phy_wrapper.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_mc_phy.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_tempmon.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_prbs_rdlvl.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_ck_addr_cmd_delay.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_4lanes.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_wrcal.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_calib_top.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_if_post_fifo.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_rdlvl.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_dqs_found_cal.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_prbs_gen.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_wrlvl_off_delay.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_oclkdelay_cal.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_of_pre_fifo.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_byte_lane.v" - Delete "${netlistDir}/mig_7series_v1_9_ddr_phy_top.vhd" - Delete "${netlistDir}/mig_7series_v1_9_ddr_byte_group_io.v" - Delete "${netlistDir}/mig_7series_v1_9_mem_intfc.v" - Delete "${netlistDir}/mig_7series_v1_9_memc_ui_top_std.v" - Delete "${netlistDir}/mig_7series_v1_9_ui_top.v" - Delete "${netlistDir}/mig_7series_v1_9_ui_rd_data.v" - Delete "${netlistDir}/mig_7series_v1_9_ui_wr_data.v" - Delete "${netlistDir}/mig_7series_v1_9_ui_cmd.v" - Delete "${netlistDir}/${TopLevel}_top.vhd" -End PostProcessRules From 85d13ee19b9a4a71ba3fc9d38c8ad09ba76568cf Mon Sep 17 00:00:00 2001 From: "adrian.weiland" Date: Fri, 20 Feb 2026 16:42:16 +0100 Subject: [PATCH 2/2] TCL code cleanup. made pipeline stageless, merge junit reports fix naming test simple pages job fix reset Oram adapter added Miktex job, enabled pages for NVC Edit AXI4Lite_Register_initial.vhdl added Sphinx job Co-authored-by: Patrick Lehmann Co-authored-by: Patrick Lehmann --- .github/workflows/Simulate.yml | 2 +- .gitlab-ci.yml | 152 +++++++++++------- .sigasi/project.sigasi | 2 +- docs/conf.py | 2 +- lib/OSVVM-Scripts | 2 +- regression.tcl | 86 ++++------ src/arith/arith.pro | 8 +- src/io/io.pro | 8 +- src/mem/mem.pro | 16 +- src/sync/sync.pro | 8 +- src/xil/xil.pro | 8 +- .../AXI4Lite_Ocram_Adapter_TestHarness.vhdl | 2 +- .../TC_AsyncReadWrite.vhdl | 2 +- tools/OSVVM/poc.tcl | 100 ++++++++++++ 14 files changed, 252 insertions(+), 146 deletions(-) create mode 100644 tools/OSVVM/poc.tcl diff --git a/.github/workflows/Simulate.yml b/.github/workflows/Simulate.yml index f1620c083..2ef9f1212 100644 --- a/.github/workflows/Simulate.yml +++ b/.github/workflows/Simulate.yml @@ -14,7 +14,7 @@ on: default: false type: boolean simulator: - description: 'simualtor name' + description: 'simulator name' required: true type: string ghdl-backend: diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 1d68b9a9f..fe96438cf 100755 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,13 +1,6 @@ -stages: - - prepare - - build_osvvm - - build_poc - - test - - pages - variables: GIT_SUBMODULE_STRATEGY: recursive - SIMULATOR_PAGES: "GHDL" # simulator from which the results should be published on GitLab pages (GHDL, Riviera-PRO) + SIMULATOR_PAGES: "NVC" # simulator from which the results should be published on GitLab pages (GHDL, Riviera-PRO) #pyIPCMI-Selftest: # stage: Selftest @@ -21,7 +14,6 @@ variables: # - ./tools/GitLab-CI/poc.run.sh "PoC.*" Scripts: - stage: prepare image: ${CI_REGISTRY}/docker-images/base-image:alpine script: - cp src/common/my_project.vhdl.template tb/common/my_project.vhdl # use CopyFile when its supporting renaming @@ -144,7 +136,7 @@ Scripts: paths: - temp/$SIMULATOR reports: - junit: "temp/$SIMULATOR/$RESULT_NAME/*.xml" + junit: "temp/junit/*.xml" expire_in: 1 week when: always @@ -171,6 +163,9 @@ Scripts: else echo "Error: Simulation for $RESULT_NAME did not pass!" && exit 1 fi + after_script: + - mkdir temp/junit + - CopyFile --rename "temp/$SIMULATOR/$RESULT_NAME/$RESULT_NAME.xml" "temp/junit/${SIMULATOR}_$RESULT_NAME.xml" allow_failure: true # if case the Riviera license is in use @@ -186,6 +181,9 @@ Scripts: else echo "Error: Simulation for $RESULT_NAME did not pass!" && exit 1 fi + after_script: + - mkdir temp/junit + - CopyFile --rename "temp/NVC/$RESULT_NAME/$RESULT_NAME.xml" "temp/junit/NVC_$RESULT_NAME.xml" # --------------- @@ -194,14 +192,12 @@ Scripts: .GHDL: parallel: matrix: - - GHDL_BACKEND: "llvm" - - GHDL_BACKEND: "mcode" + - GHDL_BACKEND: ["llvm", "mcode"] image: ${CI_REGISTRY}/docker-images/ghdl:${GHDL_BACKEND} variables: SIMULATOR: "GHDL" GHDL_OSVVM_compile: - stage: build_osvvm extends: - .GHDL - .compile @@ -212,7 +208,6 @@ GHDL_OSVVM_compile: TCL_FILE: "osvvm_compile.tcl" GHDL_PoC_compile: - stage: build_poc extends: - .GHDL - .compile @@ -225,7 +220,6 @@ GHDL_PoC_compile: TCL_FILE: "poc_compile.tcl" GHDL_OSVVM_sim: - stage: test extends: - .GHDL - .simulate @@ -243,7 +237,6 @@ GHDL_OSVVM_sim: RESULT_NAME: "lib_RunAllTests" GHDL_PoC_sim: - stage: test extends: - .GHDL - .simulate @@ -255,6 +248,9 @@ GHDL_PoC_sim: variables: TCL_FILE: "poc_sim.tcl" RESULT_NAME: "tb_RunAllTests" + artifacts: + paths: + - temp/junit # ------------------ # ---- Riviera ----- @@ -266,7 +262,6 @@ GHDL_PoC_sim: LM_LICENSE_FILE: "1717@flexlm.plc2.de:1718@flexlm.plc2.de:1719@flexlm.plc2.de" RIVIERA_OSVVM_compile: - stage: build_osvvm extends: - .RIVIERA-PRO - .compile @@ -277,7 +272,6 @@ RIVIERA_OSVVM_compile: TCL_FILE: "osvvm_compile.tcl" RIVIERA_PoC_compile: - stage: build_poc extends: - .RIVIERA-PRO - .compile @@ -290,7 +284,6 @@ RIVIERA_PoC_compile: TCL_FILE: "poc_compile.tcl" RIVIERA_OSVVM_sim: - stage: test extends: - .RIVIERA-PRO - .simulate @@ -311,7 +304,6 @@ RIVIERA_OSVVM_sim: RESULT_NAME: "lib_RunAllTests" RIVIERA_PoC_sim: - stage: test extends: - .RIVIERA-PRO - .simulate @@ -326,6 +318,9 @@ RIVIERA_PoC_sim: variables: TCL_FILE: "poc_sim.tcl" RESULT_NAME: "tb_RunAllTests" + artifacts: + paths: + - temp/junit # -------------- @@ -337,7 +332,6 @@ RIVIERA_PoC_sim: SIMULATOR: "NVC" NVC_OSVVM_compile: - stage: build_osvvm extends: - .NVC - .compileNVC @@ -348,7 +342,6 @@ NVC_OSVVM_compile: TCL_FILE: "osvvm_compile.tcl" NVC_PoC_compile: - stage: build_poc extends: - .NVC - .compileNVC @@ -359,8 +352,8 @@ NVC_PoC_compile: artifacts: true variables: TCL_FILE: "poc_compile.tcl" + NVC_OSVVM_sim: - stage: test extends: - .NVC - .simulateNVC @@ -378,7 +371,6 @@ NVC_OSVVM_sim: RESULT_NAME: "lib_RunAllTests" NVC_PoC_sim: - stage: test extends: - .NVC - .simulateNVC @@ -390,47 +382,85 @@ NVC_PoC_sim: variables: TCL_FILE: "poc_sim.tcl" RESULT_NAME: "tb_RunAllTests" + artifacts: + paths: + - temp/junit + + +# -------------------------- +# ----- Documentation ------ +# -------------------------- +MergeReports: + image: ${CI_REGISTRY}/docker-images/base-image:alpine + needs: + - job: GHDL_PoC_sim + artifacts: true + - job: RIVIERA_PoC_sim + artifacts: true + - job: NVC_PoC_sim + artifacts: true + before_script: + - pip install pyEDAA.Reports + - pip install colorama + script: + - mkdir temp/report/unit + - touch temp/report/unit/unittest.xml + - pyedaa-reports -v unittest "--merge=Any-JUnit:temp/junit/*.xml" "--output=pyTest-JUnit:temp/report/unit/unittest.xml" + artifacts: + paths: + - temp/report/unit/ + +Sphinx: + image: ${CI_REGISTRY}/docker-images/base-image:alpine + needs: + - job: MergeReports + artifacts: true + parallel: + matrix: + - SPHINX_BUILDER: ["html", "latex"] + before_script: + - apt-get update + - pip install -U -r docs/requirements.txt + script: + - cd docs + - sphinx-build --verbose --builder ${SPHINX_BUILDER} -d _build/doctrees --jobs 4 -w _build/${SPHINX_BUILDER}.log . _build/${SPHINX_BUILDER} + artifacts: + paths: + - docs/_build/${SPHINX_BUILDER} + +MikTeX: + needs: + - job: Sphinx + parallel: + matrix: + - SPHINX_BUILDER: "latex" + artifacts: true + image: ${CI_REGISTRY}/docker-images/miktex:sphinx + script: + - cd docs/_build/latex + - exec-LaTeX.sh --xelatex "PoC.tex" + after_script: + - CopyFile docs/_build/latex/PoC.pdf . + artifacts: + paths: + - ./*.pdf + allow_failure: true + # ------------------ # ----- Pages ------ # ------------------ .pages: - stage: pages image: ${CI_REGISTRY}/docker-images/base-image:alpine variables: GIT_SUBMODULE_STRATEGY: normal + pages: true before_script: - - apk add rsync + - apk update + - apk add tree script: - - mkdir -p public/static - - rsync -av --progress temp/$SIMULATOR_PAGES/ ./public --include="*/" --include="*.html" --include="*.log" --include="*.png" --include="*.css" --exclude="*" - - cp temp/$SIMULATOR_PAGES/reports/OsvvmLogo.png public/static/ - - | - echo "Chosen simulator: $SIMULATOR_PAGES" - echo "Write an 'index.html' ..." - tee public/index.html < - - PoC Simulation Results - - -
-

PoC Simulation Results

- -

OSVVM Analysis Reports

- OSVVM-Libaries
- -

OSVVM Simulation Reports

- OSVVM-Libaries-tests
- -

PoC Analysis Reports

- PoC-analysis
- -

Simulation Reports

- PoC-tests
- - - EOF + - CopyDir docs/_build/html public + #- CopyFile PoC.pdf public - tree public after_script: - echo "Pages accessible at ${CI_PAGES_URL}" @@ -438,6 +468,7 @@ NVC_PoC_sim: paths: - public + pagesGHDL: rules: - if: > @@ -468,17 +499,18 @@ pagesRiviera: - .pages pagesNVC: + extends: + - .pages rules: - if: > $SIMULATOR_PAGES == "NVC" && - $CI_PIPELINE_SOURCE == "push" && - $CI_COMMIT_BRANCH =~ /^(main|master|dev)$/ + $CI_PIPELINE_SOURCE == "push" needs: - - job: NVC_OSVVM_sim # main only + - job: NVC_OSVVM_sim artifacts: true optional: true - job: NVC_PoC_sim artifacts: true optional: true - extends: - - .pages + - job: Sphinx + artifacts: true diff --git a/.sigasi/project.sigasi b/.sigasi/project.sigasi index da529cc2f..b88099dbb 100644 --- a/.sigasi/project.sigasi +++ b/.sigasi/project.sigasi @@ -26,7 +26,7 @@ ], "dependencies": [ { - "Quartus": [ + "Quartus25.3": [ "altera_mf" ] } diff --git a/docs/conf.py b/docs/conf.py index 7632355e8..792cbf0d2 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -31,7 +31,7 @@ # copyright = versionInformation.Copyright # version = ".".join(versionInformation.Version.split(".")[:2]) # e.g. 2.3 The short X.Y version. # release = versionInformation.Version -project = 'The PoC-Library' +# project = 'The PoC-Library' copyright = '2007-2016 Technische Universitaet Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture' author = 'The PoC-Library Authors' diff --git a/lib/OSVVM-Scripts b/lib/OSVVM-Scripts index d9cb9aebf..e53eaf6c6 160000 --- a/lib/OSVVM-Scripts +++ b/lib/OSVVM-Scripts @@ -1 +1 @@ -Subproject commit d9cb9aebf52b105900ca958f4d1ba53002f43e5b +Subproject commit e53eaf6c61ae95b52c31d2f15b0362fd12702613 diff --git a/regression.tcl b/regression.tcl index 87202d4fb..bcb092bd0 100644 --- a/regression.tcl +++ b/regression.tcl @@ -22,72 +22,46 @@ # limitations under the License. # ============================================================================= -namespace eval ::poc { - proc getEnv {var {default ""}} { - if {[info exists ::env($var)]} { - return $::env($var) - } - return $default - } - - variable vendorName [getEnv VENDOR "GENERIC"] - variable boardName [getEnv BOARD "GENERIC"] +source ../lib/OSVVM-Scripts/StartUp.tcl +source ../tools/OSVVM/poc.tcl - variable myConfigFile "../tb/common/my_config_$boardName.vhdl" - variable myProjectFile "../tb/common/my_project.vhdl" +namespace import ::poc::* - variable vendor $vendorName; # GENERIC for vendor-less build; Xilinx, Altera,... for vendor specific build +# Skip report generation if executed within Sigasi/VS Code +if {[info exists ::env(OSVVM_TOOL)] && $::env(OSVVM_TOOL) eq "Sigasi"} { + set ::osvvm::GenerateOsvvmReports "false" } - -if {[info exists nvc_dataDir]} { - source ../lib/OSVVM-Scripts/StartNVC.tcl +if {[info exists ::env(GITLAB_CI)]} { + set buildNamePrefix "" } else { - source ../lib/OSVVM-Scripts/StartUp.tcl + set buildNamePrefix "${::osvvm::ToolNameVersion}-" } -build ../lib/OsvvmLibraries.pro - -if {$::osvvm::ToolName eq "GHDL"} { - SetExtendedAnalyzeOptions {-frelaxed -Wno-specs -Wno-elaboration} - SetExtendedSimulateOptions {-frelaxed -Wno-specs -Wno-binding} - -} elseif {$::osvvm::ToolName eq "RivieraPRO"} { - set RivieraSimOptions {-unbounderror} - -} elseif {$::osvvm::ToolName eq "NVC"} { - SetExtendedAnalyzeOptions {--relaxed} - -} elseif {$::osvvm::ToolName eq "Sigasi"} { - -} else { - error [format { -====================================== -Unknown simulator selected: %s +namespace eval ::poc { + variable myConfigFile "../tb/common/my_config_${boardName}.vhdl" + variable myProjectFile "../tb/common/my_project.vhdl" +} -Supported simulators: - - GHDL - - RivieraPRO - - NVC -Other tools: - - Sigasi in VSCode -====================================== -} $::osvvm::ToolName] +build ../lib/OsvvmLibraries.pro [BuildName "${buildNamePrefix}OsvvmLibraries"] +if {$::osvvm::AnalyzeErrorCount > 0} { + puts "ERROR: While building OSVVM" + scriptExit } -set ::osvvm::AnalyzeErrorStopCount 1 -set ::osvvm::SimulateErrorStopCount 1 -set ::osvvm::TclDebug 1 -set ::osvvm::FailOnBuildErrors 1 +# -s -stop set the stop counts to +# -d -debug enable debugging +# -w -waves save waveforms +configureOSVVM -stop 1 ;# -debug -proc disabled {args} { - puts "Disabled from analysis: $args" -} -proc duplicate {args} { - puts "Duplicate file: $args" -} +build ../src/PoC.pro [BuildName "${buildNamePrefix}PoC"] +if {$::osvvm::AnalyzeErrorCount > 0} { + puts "ERROR: While building PoC Library" -build ../src/PoC.pro + puts $::errorInfo + puts "=====================================" + puts $::osvvm::BuildErrorInfo -# SetSaveWaves + scriptExit +} -build ../tb/RunAllTests.pro +build ../tb/RunAllTests.pro [BuildName "${buildNamePrefix}RunAllTests"] diff --git a/src/arith/arith.pro b/src/arith/arith.pro index aa33056b2..144c26640 100644 --- a/src/arith/arith.pro +++ b/src/arith/arith.pro @@ -22,7 +22,7 @@ analyze ./arith.pkg.vhdl -if { $::poc::vendor eq "Xilinx" } { +if { $::poc::vendorName eq "Xilinx" } { analyze ./xilinx/arith_carrychain_inc_xilinx.vhdl analyze ./xilinx/arith_cca_xilinx.vhdl analyze ./xilinx/arith_addw_xilinx.vhdl @@ -30,11 +30,11 @@ if { $::poc::vendor eq "Xilinx" } { analyze ./xilinx/arith_prefix_and_xilinx.vhdl analyze ./xilinx/arith_prefix_or_xilinx.vhdl -} elseif { $::poc::vendor eq "Altera" } { +} elseif { $::poc::vendorName eq "Altera" } { puts "No Altera files for arith." -} elseif { $::poc::vendor ne "GENERIC" } { - puts "Unknown vendor '$::poc::vendor'!" +} elseif { $::poc::vendorName ne "GENERIC" } { + puts "Unknown vendor '$::poc::vendorName' in arith!" exit 1 } diff --git a/src/io/io.pro b/src/io/io.pro index c22e519f0..912a18934 100644 --- a/src/io/io.pro +++ b/src/io/io.pro @@ -35,18 +35,18 @@ analyze ./ddrio/ddrio_in.vhdl analyze ./ddrio/ddrio_inout.vhdl analyze ./ddrio/ddrio_out.vhdl -if { $::poc::vendor eq "Xilinx" } { +if { $::poc::vendorName eq "Xilinx" } { analyze ./ddrio/ddrio_in_xilinx.vhdl analyze ./ddrio/ddrio_inout_xilinx.vhdl analyze ./ddrio/ddrio_out_xilinx.vhdl -} elseif { $::poc::vendor eq "Altera" } { +} elseif { $::poc::vendorName eq "Altera" } { analyze ./ddrio/ddrio_in_altera.vhdl analyze ./ddrio/ddrio_inout_altera.vhdl analyze ./ddrio/ddrio_out_altera.vhdl -} elseif { $::poc::vendor ne "GENERIC" } { - puts "Unknown vendor '$::poc::vendor'!" +} elseif { $::poc::vendorName ne "GENERIC" } { + puts "Unknown vendor '$::poc::vendorName' in io!" exit 1 } diff --git a/src/mem/mem.pro b/src/mem/mem.pro index bb4b8336b..d68ad319e 100644 --- a/src/mem/mem.pro +++ b/src/mem/mem.pro @@ -30,15 +30,15 @@ analyze ./ocram/ocram_sdp_wf.vhdl analyze ./ocram/ocram_sp.vhdl analyze ./ocram/ocram_tdp_wf.vhdl -if { $::poc::vendor eq "Xilinx" } { +if { $::poc::vendorName eq "Xilinx" } { puts "No files for Xilinx." -} elseif { $::poc::vendor eq "Altera" } { +} elseif { $::poc::vendorName eq "Altera" } { analyze ./ocram/altera/ocram_sp_altera.vhdl analyze ./ocram/altera/ocram_tdp_altera.vhdl -} elseif { $::poc::vendor ne "GENERIC" } { - puts "Unknown vendor '$::poc::vendor'!" +} elseif { $::poc::vendorName ne "GENERIC" } { + puts "Unknown vendor '$::poc::vendorName'!" exit 1 } @@ -49,16 +49,16 @@ analyze ./ocrom/ocrom_sp.vhdl analyze ./sdram/sdram_ctrl_fsm.vhdl # TODO: Remove Spartan 3 and Cyclone 3 files -if { $::poc::vendor eq "Xilinx" } { +if { $::poc::vendorName eq "Xilinx" } { analyze ./sdram/sdram_ctrl_phy_s3esk.vhdl analyze ./sdram/sdram_ctrl_s3esk.vhdl -} elseif { $::poc::vendor eq "Altera" } { +} elseif { $::poc::vendorName eq "Altera" } { analyze ./sdram/sdram_ctrl_phy_de0.vhdl analyze ./sdram/sdram_ctrl_de0.vhdl -} elseif { $::poc::vendor ne "GENERIC" } { - puts "Unknown vendor '$::poc::vendor'!" +} elseif { $::poc::vendorName ne "GENERIC" } { + puts "Unknown vendor '$::poc::vendorName' in mem!" exit 1 } diff --git a/src/sync/sync.pro b/src/sync/sync.pro index a6b6bfc0f..819153544 100644 --- a/src/sync/sync.pro +++ b/src/sync/sync.pro @@ -20,18 +20,18 @@ analyze ./sync.pkg.vhdl -if { $::poc::vendor eq "Xilinx" } { +if { $::poc::vendorName eq "Xilinx" } { analyze ./sync_Bits_Xilinx.vhdl analyze ./sync_Reset_Xilinx.vhdl analyze ./sync_Pulse_Xilinx.vhdl -} elseif { $::poc::vendor eq "Altera" } { +} elseif { $::poc::vendorName eq "Altera" } { analyze ./sync_Bits_Altera.vhdl analyze ./sync_Reset_Altera.vhdl analyze ./sync_Pulse_Altera.vhdl -} elseif { $::poc::vendor ne "GENERIC" } { - puts "Unknown vendor '$::poc::vendor'!" +} elseif { $::poc::vendorName ne "GENERIC" } { + puts "Unknown vendor '$::poc::vendorName' in sync!" exit 1 } diff --git a/src/xil/xil.pro b/src/xil/xil.pro index 28a472055..0ed607f17 100644 --- a/src/xil/xil.pro +++ b/src/xil/xil.pro @@ -21,7 +21,7 @@ # ============================================================================= analyze ./xil.pkg.vhdl -if { $::poc::vendor eq "Xilinx" } { +if { $::poc::vendorName eq "Xilinx" } { analyze ./xil_DNAPort.vhdl analyze ./xil_ICAP.vhdl analyze ./xil_BSCAN.vhdl @@ -30,11 +30,11 @@ if { $::poc::vendor eq "Xilinx" } { analyze ./reconfig/reconfig_icap_fsm.vhdl analyze ./reconfig/reconfig_icap_wrapper.vhdl -} elseif { $::poc::vendor eq "Altera" } { +} elseif { $::poc::vendorName eq "Altera" } { puts "No Altera files in this namespace." -} elseif { $::poc::vendor ne "GENERIC" } { - puts "Unknow vendor '$::poc::vendor' in arith!" +} elseif { $::poc::vendorName ne "GENERIC" } { + puts "Unknow vendor '$::poc::vendorName' in xil!" exit 1 } diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/AXI4Lite_Ocram_Adapter_TestHarness.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/AXI4Lite_Ocram_Adapter_TestHarness.vhdl index 735c46da8..bf6909222 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/AXI4Lite_Ocram_Adapter_TestHarness.vhdl +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/AXI4Lite_Ocram_Adapter_TestHarness.vhdl @@ -101,7 +101,7 @@ begin -- create nReset Osvvm.ClockResetPkg.CreateReset ( Reset => Reset, - ResetActive => '0', + ResetActive => '1', Clk => Clk, Period => 7 * tperiod_Clk, tpd => tpd diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/TC_AsyncReadWrite.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/TC_AsyncReadWrite.vhdl index 3c1602d6d..eed41b4a2 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/TC_AsyncReadWrite.vhdl +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Ocram_Adapter/TC_AsyncReadWrite.vhdl @@ -63,7 +63,7 @@ begin begin ------------------------------------- - -- Normal Rread and Wirte + -- Normal Rread and Write ------------------------------------- wait until nReset = '1' ; WaitForClock(MasterRec, 2); diff --git a/tools/OSVVM/poc.tcl b/tools/OSVVM/poc.tcl new file mode 100644 index 000000000..2ce659db8 --- /dev/null +++ b/tools/OSVVM/poc.tcl @@ -0,0 +1,100 @@ +namespace eval ::poc { + proc getEnv {var {default ""}} { + if {[info exists ::env($var)]} { + return $::env($var) + } + return $default + } + + variable vendorName [getEnv VENDOR "GENERIC"] + variable boardName [getEnv BOARD "GENERIC"] + + proc exitScript {{code 1}} { + if {$::osvvm::ToolName eq "RivieraPRO"} { + exit -code $code + } else { + exit $code + } + } + + proc configureOSVVM {args} { + set stopCount 0 + set debugMode 0 + + set i 0 + while {$i < [llength $args]} { + set arg [lindex $args $i] + switch -glob -- $arg { + "-stop" - + "-s" { + incr i + if {$i < [llength $args]} { + set stopCount [lindex $args $i] + } else { + puts "Option -stopCount requires an integer value." + exitScript + } + } + "-debug" - + "-d" { + set debugMode 1 + } + "-waves" - + "-w" { + SetSaveWaves + } + default { + puts "ERROR: Unknown option $arg" + exitScript + } + } + incr i + } + + set ::osvvm::AnalyzeErrorStopCount $stopCount + set ::osvvm::SimulateErrorStopCount $stopCount + set ::osvvm::TclDebug $debugMode + set ::osvvm::FailOnBuildErrors $debugMode + + if {$::osvvm::ToolName eq "GHDL"} { + SetExtendedAnalyzeOptions {-frelaxed -Wno-specs -Wno-elaboration} + SetExtendedSimulateOptions {-frelaxed -Wno-specs -Wno-binding} + + } elseif {$::osvvm::ToolName eq "RivieraPRO"} { + set RivieraSimOptions {-unbounderror} + + } elseif {$::osvvm::ToolName eq "NVC"} { + SetExtendedAnalyzeOptions {--relaxed} + + } elseif {$::osvvm::ToolName eq "Sigasi"} { + + } else { + puts [format { +====================================== +Unknown simulator selected: %s + +Supported simulators: + - GHDL + - NVC + - Riviera-PRO +Other tools: + - Sigasi in VSCode +====================================== +} $::osvvm::ToolName] + exitScript + } + } + + # New procedures for OSVVM's *.pro files + proc disabled {args} { + puts "Disabled from analysis: $args" + } + proc duplicate {args} { + puts "Duplicate file: $args" + } + + namespace export exitScript + namespace export configureOSVVM + namespace export disabled + namespace export duplicate +}