Behaviour: When a LD instruction is followed by an ADD instruction, if the rd of the load is source of the add, the load value wont be forwarded to the add instruction.
Trace: The instruction in the counter example is lw x13, 19(x7) followed by add x2, x13, x24. At cycle 10, when the add instruction is performed execution, the opA_i is 0 but not the value return from memory. Moreover, although load instruction has issued a dmem_req_o from cycle 9, only at cycle 11 that the value come back, at which point should the add instruction perform execution.
This is because, the lsu_r from ex_units for forwarding path is hardwired to 0 in lsu_r_o.
Behaviour: When a LD instruction is followed by an ADD instruction, if the rd of the load is source of the add, the load value wont be forwarded to the add instruction.
Trace: The instruction in the counter example is lw x13, 19(x7) followed by add x2, x13, x24. At cycle 10, when the add instruction is performed execution, the opA_i is 0 but not the value return from memory. Moreover, although load instruction has issued a dmem_req_o from cycle 9, only at cycle 11 that the value come back, at which point should the add instruction perform execution.
This is because, the lsu_r from ex_units for forwarding path is hardwired to 0 in lsu_r_o.