PC_MUX.v

module PC_add4(
	input [31:0] pc_in,
	output [31:0] pc_out
);
	assign pc_out = pc_in + 32'h00000004;
endmodule

module Mux2x1(
	input [31:0] inp_1,
	input [31:0] inp_2,
	input select,
	output reg [31:0] outp
);
	always @(select) begin
		if(select == 1'b0) begin
			outp = inp_1;
		end
		else begin
			outp = inp_2;
		end
	end
endmodule

module Mux4x2(
	input [31:0] inp_1,
	input [31:0] inp_2,
	input [31:0] inp_3,
	input [31:0] inp_4,
	input [1:0] select,
	output reg [31:0] outp
);
	always@ (select) begin
		case(select)
			2'b00: outp = inp_1;
			2'b01: outp = inp_2;
			2'b10: outp = inp_3;
			2'b11: outp = inp_4;
			default: outp = 32'hxxxxxxxx;
		endcase
	end
endmodule

// PC Mux 21BCE0289
module msrv32_pc(rst_in, pc_src_in, epc_in, trap_address_in, branch_taken_in, iaddr_in, ahb_ready_in, pc_in, iaddr_out, pc_plus_4_out, misaligned_instr_logic_out, pc_mux_out);
	
	parameter [31:0] BOOT_ADDRESS = 32'h00000000;

	input rst_in;
	input [1:0] pc_src_in;
	input [31:0] epc_in;
	input [31:0] trap_address_in;
	input branch_taken_in;
	input [30:0] iaddr_in;
	input ahb_ready_in;
	input [31:0] pc_in;

	wire [31:0] Mux3_in1;
	wire [31:0] iaddr_in_t;
	wire [31:0] pc_out;
	wire [31:0] next_pc;
	wire [31:0] Mux2_out;
	wire [31:0] Mux3_out;
	output reg [31:0] iaddr_out;
	output reg [31:0] pc_plus_4_out;
	output reg misaligned_instr_logic_out;
	output reg [31:0] pc_mux_out;

	PC_add4 PCplus(
		.pc_in(pc_in),
		.pc_out(pc_out)
	);
	Mux2x1 Mux1(
		.inp_1(pc_out),
		.inp_2(iaddr_in_t),
		.select(branch_taken_in),
		.outp(next_pc)
	);
	Mux4x2 Mux2(
		.inp_1(BOOT_ADDRESS),
		.inp_2(epc_in),
		.inp_3(trap_address_in),
		.inp_4(next_pc),
		.select(pc_src_in),
		.outp(Mux2_out)
	);
	Mux2x1 Mux3(
		.inp_1(Mux3_in1),
		.inp_2(iaddr_in_t),
		.select(ahb_ready_in),
		.outp(Mux3_out)
	);
	Mux2x1 Mux4(
		.inp_1(Mux3_out),
		.inp_2(BOOT_ADDRESS),
		.select(rst_in),
		.outp(Mux3_in1)
	);
	
	assign iaddr_in_t = {iaddr_in, 1'b0};
	always @(*) begin
		pc_plus_4_out = pc_out;
		pc_mux_out = Mux2_out;
		misaligned_instr_logic_out = next_pc[1] & branch_taken_in;
		iaddr_out = Mux3_in1;
	end
endmodule