Integer_File_tb.v.bak

// Testbench for msrv32_integer_file 21BCE0289
module Testbench_Integer_File;
	reg ms_riscv32_mp_clk_in;
	reg ms_riscv32_mp_rst_in;
	reg [4:0] rs_2_addr_in;
	reg [4:0] rd_addr_in;
	reg wr_en_in;
	reg [31:0] rd_in;
	reg [4:0] rs_1_addr_in;
	wire [31:0] rs_1_out;
	wire [31:0] rs_2_out;

	Integer_File msrv32_integer_file(
		.ms_riscv32_mp_clk_in(ms_riscv32_mp_clk_in),
		.ms_riscv32_mp_rst_in(ms_riscv32_mp_rst_in),
		.rs_2_addr_in(rs_2_addr_in),
		.rd_addr_in(rd_addr_in),
		.wr_en_in(wr_en_in),
		.rd_in(rd_in),
		.rs_1_addr_in(rs_1_addr_in),
		.rs_1_out(rs_1_out),
		.rs_2_out(rs_2_out)
	);

	always #5 ms_riscv32_mp_clk_in = ~ms_riscv32_mp_clk_in;

	initial begin
		ms_riscv32_mp_clk_in = 0;	// initializing
		ms_riscv32_mp_rst_in = 1;
		rs_2_addr_in = 5'b01010;
		rd_addr_in = 5'b11111;
		wr_en_in = 0;
		rd_in = 32'h23456789;
		rs_1_addr_in = 5'b10101;
		#5;

		ms_riscv32_mp_rst_in = 0;	// disabling reset
		#10;

		wr_en_in = 1;			// only writing to addr 11111
		#20;

		wr_en_in = 0;			// reading addr 11111
		rs_1_addr_in = 5'b11111;
		#20;

		wr_en_in = 1;			// writing and reading from 01010
		rs_2_addr_in = 5'b01010;	// hazard testing
		rd_addr_in = 5'b01010;
		#20;

		wr_en_in = 0;			// reading 01010
		#30;
		
		$stop;
	end

	always #10 $display($time, "ns: rs_1_out: %h, rs_2_out: %h", rs_1_out, rs_2_out);
endmodule