ALU.v

// msrv32_alu 21BCE0289
module msrv32_alu(
	input [31:0] op_1_in,
	input [31:0] op_2_in,
	input [3:0] opcode_in,
	output [31:0] result_out
);
	parameter ALU_ADD = 4'b0000,
		ALU_SUB = 4'b1000,
		ALU_SLT = 4'b0010,
		ALU_SLTU = 4'b0011,
		ALU_AND = 4'b0111,
		ALU_OR = 4'b0110,
		ALU_XOR = 4'b0100,
		ALU_SLL = 4'b0001,
		ALU_SRL = 4'b0101,
		ALU_SRA = 4'b1101;
	
	reg [31:0] result;

	always @(*) begin
		case (opcode_in)
			ALU_ADD: result = op_1_in + op_2_in;
			ALU_SUB: result = op_1_in - op_2_in;
			ALU_SLT: result = ($signed(op_1_in) < $signed(op_2_in)) ? 1 : 0;
			ALU_SLTU: result = (op_1_in < op_2_in) ? 1 : 0;
			ALU_AND: result = op_1_in & op_2_in;
			ALU_OR: result = op_1_in | op_2_in;
			ALU_XOR: result = op_1_in ^ op_2_in;
			ALU_SLL: result = op_1_in << op_2_in;
			ALU_SRL: result = op_1_in >> op_2_in;
			ALU_SRA: result = op_1_in >>> op_2_in;
			default: result = 32'b0;
		endcase
	end

	assign result_out = result;
endmodule