From 0b6eb00cf0d99f9b5dc6a913207ac1bca34c0b04 Mon Sep 17 00:00:00 2001 From: tmahatej_amdeng Date: Wed, 6 May 2026 22:29:02 +0530 Subject: [PATCH 1/3] XFAIL 11 tests failing with Dbg values not emitted in LDV --- .../CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll | 2 ++ llvm/test/CodeGen/AMDGPU/debug-value.ll | 1 + llvm/test/CodeGen/AMDGPU/debug-value2.ll | 1 + llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll | 1 + llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll | 1 + llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll | 2 +- llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll | 1 + .../AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll | 1 + llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll | 1 + llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll | 2 ++ llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll | 1 + 11 files changed, 13 insertions(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll b/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll index 0ea51b2b3e212..d071182cf099e 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll @@ -3,6 +3,8 @@ ; RUN: llc -mcpu=gfx1250 < %t.no_debug.ll -filetype=obj -o %t.no_debug.o ; RUN: llvm-strip %t.with_debug.o %t.no_debug.o ; RUN: cmp %t.with_debug.o %t.no_debug.o +; XFAIL: * + ; Ensure that compiling with and without debug generates identical code. ; Test that adjustSchedDependency does not count debug instructions in bundles. diff --git a/llvm/test/CodeGen/AMDGPU/debug-value.ll b/llvm/test/CodeGen/AMDGPU/debug-value.ll index 9d1f51e7e05ee..25734a1a02796 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-value.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s +; XFAIL: * %struct.wombat = type { [4 x i32], [4 x i32], [4 x i32] } diff --git a/llvm/test/CodeGen/AMDGPU/debug-value2.ll b/llvm/test/CodeGen/AMDGPU/debug-value2.ll index daf092f765495..220f3797d35ad 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value2.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-value2.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false < %s | FileCheck %s +; XFAIL: * %struct.ShapeData = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32, i64, <4 x float>, i32, i8, i8, i16, i32, i32 } diff --git a/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll b/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll index bc34ba07d2320..7018137d2e9c7 100644 --- a/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll +++ b/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: opt -passes=debugify < %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck %s +; XFAIL: * @lds = addrspace(3) global [512 x float] poison, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll index 884d712e93ebe..8ac76151ecce8 100644 --- a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck %s +; XFAIL: * ; Don't crash. diff --git a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll index 903bba8a4866f..debc39f28be95 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll @@ -1,6 +1,6 @@ ; RUN: llc -O0 -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,NOOPT %s ; RUN: llc -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,OPT %s - +; XFAIL: * ; GCN-LABEL: {{^}}test_debug_value: ; NOOPT: .loc 1 1 42 prologue_end ; /tmp/test_debug_value.cl:1:42 diff --git a/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll b/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll index ce2a9f6323834..afbda07d7356d 100644 --- a/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll +++ b/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+xnack -amdgpu-max-memory-clause=0 -experimental-debug-variable-locations=false < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; XFAIL: * ; Test the behavior of the post-RA soft clause bundler in the presence ; of debug info. The debug info should not interfere with the diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll index 6646f83baadaf..c4f935904cab2 100644 --- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll +++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s +; XFAIL: * define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg noundef %dst.coerce, ptr addrspace(1) inreg noundef %src.coerce, i64 inreg noundef %nElts, i64 inreg noundef %redOpArg, i1 inreg noundef %redOpArgIsPtr) #0 !dbg !4 { ; GFX942-LABEL: preload_block_count_x: diff --git a/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll b/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll index 54db72c802986..7f5f866bb86ae 100644 --- a/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll +++ b/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -experimental-debug-variable-locations=false < %s | FileCheck %s +; XFAIL: * %struct.A = type { [100 x i32] } diff --git a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll index bd1752d21507c..2b10a99620b70 100644 --- a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll +++ b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll @@ -8,6 +8,8 @@ ; FIXME: Asserts when using -O2 + -vgpr-regalloc=fast ; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -stress-regalloc=1 -O0 -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-FAST %s +; XFAIL: * + ; TODO: Should we fix emitting multiple errors sometimes in basic and fast? diff --git a/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll b/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll index 23f64b3353ba5..a1a3e988a53f5 100644 --- a/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll +++ b/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll @@ -1,5 +1,6 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -experimental-debug-variable-locations=false < %s | FileCheck -check-prefix=GCN %s ; Make sure dbg_value reports something for argument registers when they are split into multiple registers +; XFAIL: * define hidden <4 x float> @split_v4f32_arg(<4 x float> returned %arg) local_unnamed_addr #0 !dbg !7 { ; GCN-LABEL: split_v4f32_arg: From a2c19666e46301e449a525671b296551fce5c976 Mon Sep 17 00:00:00 2001 From: tmahatej_amdeng Date: Thu, 7 May 2026 11:44:32 +0530 Subject: [PATCH 2/3] Enable LWT --- .../debug-independence-adjustSchedDependency.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/debug-value.ll | 2 +- llvm/test/CodeGen/AMDGPU/debug-value2.ll | 2 +- .../CodeGen/AMDGPU/ds-read2-write2-debug-info.ll | 2 +- .../CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll | 4 ++-- .../CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll | 2 +- ...eload-implicit-kernargs-debug-info-multi-entry.ll | 2 +- llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll | 2 +- .../CodeGen/AMDGPU/ran-out-of-registers-errors.ll | 12 ++++++------ llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll | 2 +- 11 files changed, 18 insertions(+), 18 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll b/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll index d071182cf099e..0a849820fa826 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll @@ -1,6 +1,6 @@ ; RUN: opt %s -strip-debug -o %t.no_debug.ll -S -; RUN: llc -mcpu=gfx1250 < %s -filetype=obj -o %t.with_debug.o -; RUN: llc -mcpu=gfx1250 < %t.no_debug.ll -filetype=obj -o %t.no_debug.o +; RUN: llc -amdgpu-late-wave-transform=1 -mcpu=gfx1250 < %s -filetype=obj -o %t.with_debug.o +; RUN: llc -amdgpu-late-wave-transform=1 -mcpu=gfx1250 < %t.no_debug.ll -filetype=obj -o %t.no_debug.o ; RUN: llvm-strip %t.with_debug.o %t.no_debug.o ; RUN: cmp %t.with_debug.o %t.no_debug.o ; XFAIL: * diff --git a/llvm/test/CodeGen/AMDGPU/debug-value.ll b/llvm/test/CodeGen/AMDGPU/debug-value.ll index 25734a1a02796..b5fe3906f2cb2 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-value.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s +; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s ; XFAIL: * %struct.wombat = type { [4 x i32], [4 x i32], [4 x i32] } diff --git a/llvm/test/CodeGen/AMDGPU/debug-value2.ll b/llvm/test/CodeGen/AMDGPU/debug-value2.ll index 220f3797d35ad..e999d78712126 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value2.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-value2.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false < %s | FileCheck %s +; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false < %s | FileCheck %s ; XFAIL: * %struct.ShapeData = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32, i64, <4 x float>, i32, i8, i8, i16, i32, i32 } diff --git a/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll b/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll index 7018137d2e9c7..25bb57935b2c2 100644 --- a/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll +++ b/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -passes=debugify < %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck %s +; RUN: opt -passes=debugify < %s | llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck %s ; XFAIL: * @lds = addrspace(3) global [512 x float] poison, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll index 8ac76151ecce8..cd0fdaa57977a 100644 --- a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck %s +; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck %s ; XFAIL: * ; Don't crash. diff --git a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll index debc39f28be95..55a5fe0514ccd 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,NOOPT %s -; RUN: llc -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,OPT %s +; RUN: llc -amdgpu-late-wave-transform=1 -O0 -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,NOOPT %s +; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,OPT %s ; XFAIL: * ; GCN-LABEL: {{^}}test_debug_value: diff --git a/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll b/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll index afbda07d7356d..691539c82739f 100644 --- a/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll +++ b/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+xnack -amdgpu-max-memory-clause=0 -experimental-debug-variable-locations=false < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn -mcpu=gfx900 -mattr=+xnack -amdgpu-max-memory-clause=0 -experimental-debug-variable-locations=false < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; XFAIL: * ; Test the behavior of the post-RA soft clause bundler in the presence diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll index c4f935904cab2..597740e1861f7 100644 --- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll +++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s +; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s ; XFAIL: * define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg noundef %dst.coerce, ptr addrspace(1) inreg noundef %src.coerce, i64 inreg noundef %nElts, i64 inreg noundef %redOpArg, i1 inreg noundef %redOpArgIsPtr) #0 !dbg !4 { diff --git a/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll b/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll index 7f5f866bb86ae..fe711fd6e69f5 100644 --- a/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll +++ b/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -experimental-debug-variable-locations=false < %s | FileCheck %s +; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -experimental-debug-variable-locations=false < %s | FileCheck %s ; XFAIL: * %struct.A = type { [100 x i32] } diff --git a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll index 2b10a99620b70..6a4eceff2ac17 100644 --- a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll +++ b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll @@ -1,12 +1,12 @@ -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -check-prefixes=CHECK,GREEDY -implicit-check-not=error %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,BASIC %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,FAST %s +; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -check-prefixes=CHECK,GREEDY -implicit-check-not=error %s +; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,BASIC %s +; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,FAST %s ; RUN: opt -passes=debugify -o %t.bc %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-GREEDY %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-BASIC %s +; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-GREEDY %s +; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-BASIC %s ; FIXME: Asserts when using -O2 + -vgpr-regalloc=fast -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -stress-regalloc=1 -O0 -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-FAST %s +; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -stress-regalloc=1 -O0 -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-FAST %s ; XFAIL: * diff --git a/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll b/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll index a1a3e988a53f5..3d2d83c3a53f0 100644 --- a/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll +++ b/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -experimental-debug-variable-locations=false < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -experimental-debug-variable-locations=false < %s | FileCheck -check-prefix=GCN %s ; Make sure dbg_value reports something for argument registers when they are split into multiple registers ; XFAIL: * From 96a35d36cd3d60ed976659426567fccf465c0e75 Mon Sep 17 00:00:00 2001 From: tmahatej_amdeng Date: Thu, 7 May 2026 15:28:12 +0530 Subject: [PATCH 3/3] Move the XFAIL lines to the top --- .../CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll | 2 +- llvm/test/CodeGen/AMDGPU/debug-value.ll | 2 +- llvm/test/CodeGen/AMDGPU/debug-value2.ll | 2 +- llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll | 2 +- llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll | 2 +- llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll | 2 +- .../AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll | 2 +- llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll | 2 +- llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll | 3 +-- llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll | 2 +- 11 files changed, 11 insertions(+), 12 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll b/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll index 0a849820fa826..7e0d3ccbd081d 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll @@ -1,9 +1,9 @@ +; XFAIL: * ; RUN: opt %s -strip-debug -o %t.no_debug.ll -S ; RUN: llc -amdgpu-late-wave-transform=1 -mcpu=gfx1250 < %s -filetype=obj -o %t.with_debug.o ; RUN: llc -amdgpu-late-wave-transform=1 -mcpu=gfx1250 < %t.no_debug.ll -filetype=obj -o %t.no_debug.o ; RUN: llvm-strip %t.with_debug.o %t.no_debug.o ; RUN: cmp %t.with_debug.o %t.no_debug.o -; XFAIL: * ; Ensure that compiling with and without debug generates identical code. ; Test that adjustSchedDependency does not count debug instructions in bundles. diff --git a/llvm/test/CodeGen/AMDGPU/debug-value.ll b/llvm/test/CodeGen/AMDGPU/debug-value.ll index b5fe3906f2cb2..30beb7bb53871 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-value.ll @@ -1,5 +1,5 @@ -; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s ; XFAIL: * +; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s %struct.wombat = type { [4 x i32], [4 x i32], [4 x i32] } diff --git a/llvm/test/CodeGen/AMDGPU/debug-value2.ll b/llvm/test/CodeGen/AMDGPU/debug-value2.ll index e999d78712126..b6b680226110e 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value2.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-value2.ll @@ -1,5 +1,5 @@ -; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false < %s | FileCheck %s ; XFAIL: * +; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false < %s | FileCheck %s %struct.ShapeData = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32, i64, <4 x float>, i32, i8, i8, i16, i32, i32 } diff --git a/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll b/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll index 25bb57935b2c2..fcd70739d6dc7 100644 --- a/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll +++ b/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll @@ -1,6 +1,6 @@ +; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: opt -passes=debugify < %s | llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck %s -; XFAIL: * @lds = addrspace(3) global [512 x float] poison, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll index cd0fdaa57977a..32b19d83690fd 100644 --- a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll @@ -1,6 +1,6 @@ +; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck %s -; XFAIL: * ; Don't crash. diff --git a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll index 55a5fe0514ccd..3f319197bfd0b 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll @@ -1,6 +1,6 @@ +; XFAIL: * ; RUN: llc -amdgpu-late-wave-transform=1 -O0 -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,NOOPT %s ; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,OPT %s -; XFAIL: * ; GCN-LABEL: {{^}}test_debug_value: ; NOOPT: .loc 1 1 42 prologue_end ; /tmp/test_debug_value.cl:1:42 diff --git a/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll b/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll index 691539c82739f..28b25f6969372 100644 --- a/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll +++ b/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll @@ -1,6 +1,6 @@ +; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn -mcpu=gfx900 -mattr=+xnack -amdgpu-max-memory-clause=0 -experimental-debug-variable-locations=false < %s | FileCheck -enable-var-scope -check-prefix=GCN %s -; XFAIL: * ; Test the behavior of the post-RA soft clause bundler in the presence ; of debug info. The debug info should not interfere with the diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll index 597740e1861f7..2fce232e5fda7 100644 --- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll +++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll @@ -1,6 +1,6 @@ +; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s -; XFAIL: * define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg noundef %dst.coerce, ptr addrspace(1) inreg noundef %src.coerce, i64 inreg noundef %nElts, i64 inreg noundef %redOpArg, i1 inreg noundef %redOpArgIsPtr) #0 !dbg !4 { ; GFX942-LABEL: preload_block_count_x: diff --git a/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll b/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll index fe711fd6e69f5..ca96272b0f566 100644 --- a/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll +++ b/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll @@ -1,6 +1,6 @@ +; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -experimental-debug-variable-locations=false < %s | FileCheck %s -; XFAIL: * %struct.A = type { [100 x i32] } diff --git a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll index 6a4eceff2ac17..451b04cac406a 100644 --- a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll +++ b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -check-prefixes=CHECK,GREEDY -implicit-check-not=error %s ; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,BASIC %s ; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,FAST %s @@ -8,8 +9,6 @@ ; FIXME: Asserts when using -O2 + -vgpr-regalloc=fast ; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -stress-regalloc=1 -O0 -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-FAST %s -; XFAIL: * - ; TODO: Should we fix emitting multiple errors sometimes in basic and fast? diff --git a/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll b/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll index 3d2d83c3a53f0..e78df7af31d63 100644 --- a/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll +++ b/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll @@ -1,6 +1,6 @@ +; XFAIL: * ; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -experimental-debug-variable-locations=false < %s | FileCheck -check-prefix=GCN %s ; Make sure dbg_value reports something for argument registers when they are split into multiple registers -; XFAIL: * define hidden <4 x float> @split_v4f32_arg(<4 x float> returned %arg) local_unnamed_addr #0 !dbg !7 { ; GCN-LABEL: split_v4f32_arg: